1 /* 2 * Copyright (c) 2009 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * SATA port multiplier registers 37 */ 38 #define SATA_PMREG_SSTS 0 /* use SATA_PM_SSTS_ bit defs */ 39 #define SATA_PMREG_SERR 1 /* use SATA_PM_SERR_ bit defs */ 40 #define SATA_PMREG_SCTL 2 /* use SATA_PM_SCTL_ bit defs */ 41 #define SATA_PMREG_SACT 3 /* (not implemented on PM) */ 42 43 #define SATA_PM_SSTS_DET 0xf /* Device Detection */ 44 #define SATA_PM_SSTS_DET_NONE 0x0 45 #define SATA_PM_SSTS_DET_DEV_NE 0x1 46 #define SATA_PM_SSTS_DET_DEV 0x3 47 #define SATA_PM_SSTS_DET_PHYOFFLINE 0x4 48 #define SATA_PM_SSTS_SPD 0xf0 /* Current Interface Speed */ 49 #define SATA_PM_SSTS_SPD_NONE 0x00 50 #define SATA_PM_SSTS_SPD_GEN1 0x10 51 #define SATA_PM_SSTS_SPD_GEN2 0x20 52 #define SATA_PM_SSTS_SPD_GEN3 0x30 53 #define SATA_PM_SSTS_IPM 0xf00 /* Interface Power Management */ 54 #define SATA_PM_SSTS_IPM_NONE 0x000 55 #define SATA_PM_SSTS_IPM_ACTIVE 0x100 56 #define SATA_PM_SSTS_IPM_PARTIAL 0x200 57 #define SATA_PM_SSTS_IPM_SLUMBER 0x600 58 59 #define SATA_PM_SCTL_DET 0xf /* Device Detection */ 60 #define SATA_PM_SCTL_DET_NONE 0x0 61 #define SATA_PM_SCTL_DET_INIT 0x1 62 #define SATA_PM_SCTL_DET_DISABLE 0x4 63 #define SATA_PM_SCTL_SPD 0xf0 /* Speed Allowed */ 64 #define SATA_PM_SCTL_SPD_ANY 0x00 65 #define SATA_PM_SCTL_SPD_GEN1 0x10 66 #define SATA_PM_SCTL_SPD_GEN2 0x20 67 #define SATA_PM_SCTL_SPD_GEN3 0x30 68 #define SATA_PM_SCTL_IPM 0xf00 /* Interface Power Management */ 69 #define SATA_PM_SCTL_IPM_NONE 0x000 70 #define SATA_PM_SCTL_IPM_NOPARTIAL 0x100 71 #define SATA_PM_SCTL_IPM_NOSLUMBER 0x200 72 #define SATA_PM_SCTL_IPM_DISABLED 0x300 73 #define SATA_PM_SCTL_SPM 0xf000 /* Select Power Management */ 74 #define SATA_PM_SCTL_SPM_NONE 0x0000 75 #define SATA_PM_SCTL_SPM_NOPARTIAL 0x1000 76 #define SATA_PM_SCTL_SPM_NOSLUMBER 0x2000 77 #define SATA_PM_SCTL_SPM_DISABLED 0x3000 78 #define SATA_PM_SCTL_PMP 0xf0000 /* Set PM port for xmit FISes */ 79 #define SATA_PM_SCTL_PMP_SHIFT 16 80 81 #define SATA_PM_SERR_ERR_I (1<<0) /* Recovered Data Integrity */ 82 #define SATA_PM_SERR_ERR_M (1<<1) /* Recovered Communications */ 83 #define SATA_PM_SERR_ERR_T (1<<8) /* Transient Data Integrity */ 84 #define SATA_PM_SERR_ERR_C (1<<9) /* Persistent Comm/Data */ 85 #define SATA_PM_SERR_ERR_P (1<<10) /* Protocol */ 86 #define SATA_PM_SERR_ERR_E (1<<11) /* Internal */ 87 #define SATA_PM_SERR_DIAG_N (1<<16) /* PhyRdy Change */ 88 #define SATA_PM_SERR_DIAG_I (1<<17) /* Phy Internal Error */ 89 #define SATA_PM_SERR_DIAG_W (1<<18) /* Comm Wake */ 90 #define SATA_PM_SERR_DIAG_B (1<<19) /* 10B to 8B Decode Error */ 91 #define SATA_PM_SERR_DIAG_D (1<<20) /* Disparity Error */ 92 #define SATA_PM_SERR_DIAG_C (1<<21) /* CRC Error */ 93 #define SATA_PM_SERR_DIAG_H (1<<22) /* Handshake Error */ 94 #define SATA_PM_SERR_DIAG_S (1<<23) /* Link Sequence Error */ 95 #define SATA_PM_SERR_DIAG_T (1<<24) /* Transport State Trans Err */ 96 #define SATA_PM_SERR_DIAG_F (1<<25) /* Unknown FIS Type */ 97 #define SATA_PM_SERR_DIAG_X (1<<26) /* Exchanged */ 98 99 #define SATA_PFMT_SERR "\020" \ 100 "\033DIAG.X" "\032DIAG.F" "\031DIAG.T" "\030DIAG.S" \ 101 "\027DIAG.H" "\026DIAG.C" "\025DIAG.D" "\024DIAG.B" \ 102 "\023DIAG.W" "\022DIAG.I" "\021DIAG.N" \ 103 "\014ERR.E" "\013ERR.P" "\012ERR.C" "\011ERR.T" \ 104 "\002ERR.M" "\001ERR.I" 105 106 /* 107 * AHCI port multiplier revision information SCR[1] (see ahci_pm_read) 108 * 109 * Rev 1.1 is the one that should support async notification. 110 */ 111 #define SATA_PMREV_PM1_0 0x00000002 112 #define SATA_PMREV_PM1_1 0x00000004 113 #define SATA_PFMT_PM_REV "\20" "\003PM1.1" "\002PM1.0" 114 115 /* 116 * GSCR[64] and GSCR[96] - Port Multiplier features available and features 117 * enabled. 118 */ 119 #define SATA_PMREG_FEA 64 120 #define SATA_PMREG_FEAEN 96 /* (features enabled) */ 121 #define SATA_PMFEA_BIST 0x00000001 /* BIST Support */ 122 #define SATA_PMFEA_PMREQ 0x00000002 /* Can issue PMREQp to host */ 123 #define SATA_PMFEA_DYNSSC 0x00000004 /* Dynamic SSC transmit enab */ 124 #define SATA_PMFEA_ASYNCNOTIFY 0x00000008 /* Async notification */ 125 126 #define SATA_PFMT_PM_FEA "\20" \ 127 "\004AsyncNotify" \ 128 "\003DynamicSSC" \ 129 "\002PMREQ" \ 130 "\001BIST" 131 132 /* 133 * Enable generation of async notify events for individual targets 134 * via the PMEENA register. Each bit in PMEINFO is a wire-or of all 135 * SERROR bits for that target. To enable a new notification event 136 * the SERROR bits in PMSERROR_REGNO must be cleared. 137 */ 138 #define SATA_PMREG_EINFO 32 /* error info 16 ports */ 139 #define SATA_PMREG_EEENA 33 /* error info enable 16 ports */ 140