1 /* $FreeBSD: src/sys/dev/isp/ispreg.h,v 1.13.2.7 2002/02/22 19:56:23 mjacob Exp $ */ 2 /* 3 * Machine Independent (well, as best as possible) register 4 * definitions for Qlogic ISP SCSI adapters. 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice immediately at the beginning of the file, without modification, 14 * this list of conditions, and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 #ifndef _ISPREG_H 31 #define _ISPREG_H 32 33 /* 34 * Hardware definitions for the Qlogic ISP registers. 35 */ 36 37 /* 38 * This defines types of access to various registers. 39 * 40 * R: Read Only 41 * W: Write Only 42 * RW: Read/Write 43 * 44 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 45 * if RISC processor in ISP is paused. 46 */ 47 48 /* 49 * Offsets for various register blocks. 50 * 51 * Sad but true, different architectures have different offsets. 52 * 53 * Don't be alarmed if none of this makes sense. The original register 54 * layout set some defines in a certain pattern. Everything else has been 55 * grafted on since. For example, the ISP1080 manual will state that DMA 56 * registers start at 0x80 from the base of the register address space. 57 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 58 * to start at offset 0x60 because the DMA registers are all defined to 59 * be DMA_BLOCK+0x20 and so on. Clear? 60 */ 61 62 #define BIU_REGS_OFF 0x00 63 64 #define PCI_MBOX_REGS_OFF 0x70 65 #define PCI_MBOX_REGS2100_OFF 0x10 66 #define PCI_MBOX_REGS2300_OFF 0x40 67 #define SBUS_MBOX_REGS_OFF 0x80 68 69 #define PCI_SXP_REGS_OFF 0x80 70 #define SBUS_SXP_REGS_OFF 0x200 71 72 #define PCI_RISC_REGS_OFF 0x80 73 #define SBUS_RISC_REGS_OFF 0x400 74 75 /* Bless me! Chip designers have putzed it again! */ 76 #define ISP1080_DMA_REGS_OFF 0x60 77 #define DMA_REGS_OFF 0x00 /* same as BIU block */ 78 79 #define SBUS_REGSIZE 0x450 80 #define PCI_REGSIZE 0x100 81 82 /* 83 * NB: The *_BLOCK definitions have no specific hardware meaning. 84 * They serve simply to note to the MD layer which block of 85 * registers offsets are being accessed. 86 */ 87 #define _NREG_BLKS 5 88 #define _BLK_REG_SHFT 13 89 #define _BLK_REG_MASK (7 << _BLK_REG_SHFT) 90 #define BIU_BLOCK (0 << _BLK_REG_SHFT) 91 #define MBOX_BLOCK (1 << _BLK_REG_SHFT) 92 #define SXP_BLOCK (2 << _BLK_REG_SHFT) 93 #define RISC_BLOCK (3 << _BLK_REG_SHFT) 94 #define DMA_BLOCK (4 << _BLK_REG_SHFT) 95 96 /* 97 * Bus Interface Block Register Offsets 98 */ 99 100 #define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ 101 #define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) 102 #define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ 103 #define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) 104 #define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ 105 #define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ 106 #define BIU2100_CSR (BIU_BLOCK+0x6) 107 #define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ 108 #define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ 109 #define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ 110 #define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ 111 /* 112 * These are specific to the 2300. 113 * 114 * They *claim* you can read BIU_R2HSTSLO with a full 32 bit access 115 * and get both registers, but I'm a bit dubious about that. But the 116 * point here is that the top 16 bits are firmware defined bits that 117 * the RISC processor uses to inform the host about something- usually 118 * something which was nominally in a mailbox register. 119 */ 120 #define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */ 121 #define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */ 122 #define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */ 123 #define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */ 124 125 #define BIU_R2HSTSLO (BIU_BLOCK+0x18) 126 #define BIU_R2HSTSHI (BIU_BLOCK+0x1A) 127 128 #define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */ 129 #define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */ 130 #define BIU_R2HST_ISTAT_MASK 0x3f /* intr information && status */ 131 #define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 132 #define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 133 #define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 134 #define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 135 #define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */ 136 #define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 137 #define ISPR2HST_RQST_UPDATE 0x14 /* Resquest Queue Update */ 138 #define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */ 139 #define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ 140 #define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ 141 142 #define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ 143 #define RDMA2100_CONTROL DFIFO_COMMAND 144 #define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ 145 146 /* 147 * Putzed DMA register layouts. 148 */ 149 #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ 150 #define CDMA2100_CONTROL CDMA_CONF 151 #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ 152 #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ 153 #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ 154 #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ 155 #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ 156 #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ 157 #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ 158 #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ 159 160 #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ 161 #define TDMA2100_CONTROL DDMA_CONF 162 #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ 163 #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ 164 #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ 165 #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ 166 #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ 167 #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ 168 #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ 169 /* these are for the 1040A cards */ 170 #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ 171 #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ 172 173 174 /* 175 * Bus Interface Block Register Definitions 176 */ 177 /* BUS CONFIGURATION REGISTER #0 */ 178 #define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ 179 /* BUS CONFIGURATION REGISTER #1 */ 180 181 #define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ 182 #define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ 183 184 #define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ 185 #define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ 186 #define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ 187 #define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ 188 #define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ 189 #define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ 190 #define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ 191 #define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ 192 #define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ 193 #define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ 194 #define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ 195 196 #define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ 197 #define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ 198 #define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ 199 200 /* ISP2100 Bus Control/Status Register */ 201 202 #define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ 203 #define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ 204 #define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ 205 #define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ 206 #define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ 207 #define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ 208 #define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ 209 #define BIU2100_SOFT_RESET 0x01 210 /* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ 211 212 213 /* BUS CONTROL REGISTER */ 214 #define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ 215 #define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ 216 #define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ 217 #define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ 218 #define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ 219 #define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ 220 221 #define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 222 #define BIU2100_ICR_ENA_FPM_INT 0x0020 223 #define BIU2100_ICR_ENA_FB_INT 0x0010 224 #define BIU2100_ICR_ENA_RISC_INT 0x0008 225 #define BIU2100_ICR_ENA_CDMA_INT 0x0004 226 #define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 227 #define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 228 #define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 229 230 #define ENABLE_INTS(isp) (IS_SCSI(isp))? \ 231 ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ 232 ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) 233 234 #define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ 235 (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ 236 (ISP_READ(isp, BIU_ICR) & \ 237 (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) 238 239 #define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) 240 241 /* BUS STATUS REGISTER */ 242 #define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ 243 #define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ 244 #define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ 245 #define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ 246 #define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ 247 248 #define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ 249 #define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ 250 #define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ 251 #define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ 252 #define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ 253 #define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ 254 #define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ 255 256 #define INT_PENDING(isp, isr) (IS_FC(isp)? \ 257 ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) 258 259 #define INT_PENDING_MASK(isp) \ 260 (IS_FC(isp)? BIU2100_ISR_RISC_INT: BIU_ISR_RISC_INT) 261 262 /* BUS SEMAPHORE REGISTER */ 263 #define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ 264 #define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ 265 266 /* NVRAM SEMAPHORE REGISTER */ 267 #define BIU_NVRAM_CLOCK 0x0001 268 #define BIU_NVRAM_SELECT 0x0002 269 #define BIU_NVRAM_DATAOUT 0x0004 270 #define BIU_NVRAM_DATAIN 0x0008 271 #define ISP_NVRAM_READ 6 272 273 /* COMNMAND && DATA DMA CONFIGURATION REGISTER */ 274 #define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ 275 #define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ 276 #define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ 277 #define DMA_DMA_DIRECTION 0x0001 /* 278 * Set DMA direction: 279 * 0 - DMA FIFO to host 280 * 1 - Host to DMA FIFO 281 */ 282 283 /* COMMAND && DATA DMA CONTROL REGISTER */ 284 #define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ 285 #define DMA_CNTRL_CLEAR_CHAN 0x0008 /* 286 * Clear FIFO and DMA Channel, 287 * reset DMA registers 288 */ 289 #define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ 290 #define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ 291 #define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ 292 293 /* 294 * Variants of same for 2100 295 */ 296 #define DMA_CNTRL2100_CLEAR_CHAN 0x0004 297 #define DMA_CNTRL2100_RESET_INT 0x0002 298 299 300 301 /* DMA STATUS REGISTER */ 302 #define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ 303 #define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ 304 #define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ 305 #define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ 306 #define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ 307 #define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ 308 309 #define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ 310 #define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ 311 #define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ 312 #define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ 313 #define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ 314 #define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ 315 #define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ 316 #define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ 317 #define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ 318 #define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ 319 #define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ 320 321 /* DMA Status Register, pipeline status bits */ 322 #define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ 323 #define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ 324 #define DMA_SBUS_PIPE_STAGE1 0x0040 /* 325 * Pipeline stage 1 Loaded, 326 * stage 2 empty 327 */ 328 #define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ 329 #define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ 330 #define DMA_PCI_PIPE_STAGE1 0x0001 /* 331 * Pipeline stage 1 Loaded, 332 * stage 2 empty 333 */ 334 #define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ 335 336 /* DMA Status Register, channel status bits */ 337 #define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ 338 #define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ 339 #define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ 340 #define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ 341 #define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ 342 #define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ 343 #define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ 344 345 346 /* DMA FIFO STATUS REGISTER */ 347 #define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ 348 #define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ 349 #define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ 350 #define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ 351 352 /* 353 * Mailbox Block Register Offsets 354 */ 355 356 #define INMAILBOX0 (MBOX_BLOCK+0x0) 357 #define INMAILBOX1 (MBOX_BLOCK+0x2) 358 #define INMAILBOX2 (MBOX_BLOCK+0x4) 359 #define INMAILBOX3 (MBOX_BLOCK+0x6) 360 #define INMAILBOX4 (MBOX_BLOCK+0x8) 361 #define INMAILBOX5 (MBOX_BLOCK+0xA) 362 #define INMAILBOX6 (MBOX_BLOCK+0xC) 363 #define INMAILBOX7 (MBOX_BLOCK+0xE) 364 365 #define OUTMAILBOX0 (MBOX_BLOCK+0x0) 366 #define OUTMAILBOX1 (MBOX_BLOCK+0x2) 367 #define OUTMAILBOX2 (MBOX_BLOCK+0x4) 368 #define OUTMAILBOX3 (MBOX_BLOCK+0x6) 369 #define OUTMAILBOX4 (MBOX_BLOCK+0x8) 370 #define OUTMAILBOX5 (MBOX_BLOCK+0xA) 371 #define OUTMAILBOX6 (MBOX_BLOCK+0xC) 372 #define OUTMAILBOX7 (MBOX_BLOCK+0xE) 373 374 #define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 375 #define NMBOX(isp) \ 376 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 377 ((isp)->isp_type & ISP_HA_FC))? 8 : 6) 378 #define NMBOX_BMASK(isp) \ 379 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ 380 ((isp)->isp_type & ISP_HA_FC))? 0xff : 0x3f) 381 382 #define MAX_MAILBOX 8 383 384 /* 385 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). 386 * NB: The RISC processor must be paused and the appropriate register 387 * bank selected via BIU2100_CSR bits. 388 */ 389 390 #define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) 391 #define FPM_SOFT_RESET 0x0100 392 393 #define FBM_CMD (BIU_BLOCK + 0xB8) 394 #define FBMCMD_FIFO_RESET_ALL 0xA000 395 396 397 /* 398 * SXP Block Register Offsets 399 */ 400 #define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 401 #define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 402 #define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 403 #define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 404 #define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 405 #define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 406 #define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 407 #define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 408 #define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 409 #define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 410 #define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 411 #define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 412 #define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 413 #define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 414 #define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 415 #define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 416 #define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 417 #define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 418 #define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 419 #define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 420 #define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 421 #define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 422 #define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 423 #define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 424 #define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 425 #define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 426 #define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 427 #define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 428 #define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 429 #define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 430 #define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 431 #define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 432 #define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 433 #define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 434 #define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 435 #define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 436 #define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 437 #define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 438 #define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 439 440 /* for 1080/1280/1240 only */ 441 #define SXP_BANK1_SELECT 0x100 442 443 444 /* SXP CONF1 REGISTER */ 445 #define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 446 #define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 447 #define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 448 #define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 449 #define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 450 451 /* SXP CONF2 REGISTER */ 452 #define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 453 #define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 454 #define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 455 #define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 456 #define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 457 #define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 458 459 /* SXP INTERRUPT REGISTER */ 460 #define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 461 #define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 462 #define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 463 #define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 464 #define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 465 #define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 466 #define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 467 #define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 468 #define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 469 #define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 470 471 472 /* SXP GROSS ERROR REGISTER */ 473 #define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 474 #define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 475 #define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 476 #define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 477 #define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 478 #define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 479 #define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 480 481 /* SXP EXCEPTION REGISTER */ 482 #define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 483 #define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 484 #define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 485 #define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 486 #define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 487 #define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 488 #define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 489 #define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 490 #define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 491 #define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 492 493 /* SXP OVERRIDE REGISTER */ 494 #define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 495 #define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 496 #define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 497 #define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 498 #define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 499 #define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 500 #define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 501 #define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 502 #define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 503 #define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 504 #define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 505 #define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 506 #define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 507 508 /* SXP COMMANDS */ 509 #define SXP_RESET_BUS_CMD 0x300b 510 511 /* SXP SCSI ID REGISTER */ 512 #define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 513 #define SXP_SELECT_ID 0x000F /* Select id */ 514 515 /* SXP DEV CONFIG1 REGISTER */ 516 #define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 517 #define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 518 #define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 519 520 521 /* SXP DEV CONFIG2 REGISTER */ 522 #define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 523 #define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 524 #define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 525 #define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 526 #define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 527 528 529 /* SXP PHASE POINTER REGISTER */ 530 #define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 531 #define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 532 #define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 533 #define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 534 535 536 /* SXP FIFO STATUS REGISTER */ 537 #define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 538 #define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 539 #define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 540 #define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 541 542 543 /* SXP CONTROL PINS REGISTER */ 544 #define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 545 #define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 546 #define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 547 #define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 548 #define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 549 #define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 550 #define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 551 #define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 552 #define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 553 #define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 554 #define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 555 #define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 556 557 /* 558 * Set the hold time for the SCSI Bus Reset to be 250 ms 559 */ 560 #define SXP_SCSI_BUS_RESET_HOLD_TIME 250 561 562 /* SXP DIFF PINS REGISTER */ 563 #define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 564 #define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 565 #define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 566 #define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 567 #define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 568 #define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 569 570 /* Ultra2 only */ 571 #define SXP_PINS_LVD_MODE 0x1000 572 #define SXP_PINS_HVD_MODE 0x0800 573 #define SXP_PINS_SE_MODE 0x0400 574 575 /* The above have to be put together with the DIFFM pin to make sense */ 576 #define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 577 #define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 578 #define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 579 #define ISP1080_MODE_MASK \ 580 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) 581 582 /* 583 * RISC and Host Command and Control Block Register Offsets 584 */ 585 586 #define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 587 #define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 588 #define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 589 #define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 590 #define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 591 #define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 592 #define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 593 #define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 594 #define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 595 #define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 596 #define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 597 #define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 598 #define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 599 #define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 600 #define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 601 #define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 602 #define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 603 #define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 604 #define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 605 #define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 606 #define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 607 #define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 608 #define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 609 #define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 610 #define RISC_MTR2100 RISC_BLOCK+0x30 611 612 #define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 613 #define DUAL_BANK 8 614 #define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 615 #define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 616 #define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 617 #define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 618 #define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 619 #define TCR RISC_BLOCK+0x46 /* W : Test Control */ 620 #define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 621 622 623 /* PROCESSOR STATUS REGISTER */ 624 #define RISC_PSR_FORCE_TRUE 0x8000 625 #define RISC_PSR_LOOP_COUNT_DONE 0x4000 626 #define RISC_PSR_RISC_INT 0x2000 627 #define RISC_PSR_TIMER_ROLLOVER 0x1000 628 #define RISC_PSR_ALU_OVERFLOW 0x0800 629 #define RISC_PSR_ALU_MSB 0x0400 630 #define RISC_PSR_ALU_CARRY 0x0200 631 #define RISC_PSR_ALU_ZERO 0x0100 632 633 #define RISC_PSR_PCI_ULTRA 0x0080 634 #define RISC_PSR_SBUS_ULTRA 0x0020 635 636 #define RISC_PSR_DMA_INT 0x0010 637 #define RISC_PSR_SXP_INT 0x0008 638 #define RISC_PSR_HOST_INT 0x0004 639 #define RISC_PSR_INT_PENDING 0x0002 640 #define RISC_PSR_FORCE_FALSE 0x0001 641 642 643 /* Host Command and Control */ 644 #define HCCR_CMD_NOP 0x0000 /* NOP */ 645 #define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 646 #define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 647 #define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 648 #define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 649 #define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* 650 * Disable RISC pause on FPM 651 * parity error. 652 */ 653 #define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 654 #define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 655 #define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 656 #define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 657 #define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 658 #define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 659 #define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 660 #define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 661 662 #define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 663 #define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 664 #define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 665 #define ISP2100_HCCR_PARITY 0x0001 666 667 #define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 668 #define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 669 #define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 670 671 #define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 672 #define HCCR_RESET 0x0040 /* R : reset in progress */ 673 #define HCCR_PAUSE 0x0020 /* R : RISC paused */ 674 675 #define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 676 677 /* 678 * NVRAM Definitions (PCI cards only) 679 */ 680 681 #define ISPBSMX(c, byte, shift, mask) \ 682 (((c)[(byte)] >> (shift)) & (mask)) 683 /* 684 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 685 * 686 * Some portion of the front of this is for general host adapter properties 687 * This is followed by an array of per-target parameters, and is tailed off 688 * with a checksum xor byte at offset 127. For non-byte entities data is 689 * stored in Little Endian order. 690 */ 691 692 #define ISP_NVRAM_SIZE 128 693 694 #define ISP_NVRAM_VERSION(c) (c)[4] 695 #define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 696 #define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 697 #define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 698 #define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 699 #define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 700 #define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 701 #define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 702 #define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 703 #define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 704 #define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 705 #define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 706 #define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 707 #define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 708 #define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 709 #define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 710 #define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 711 #define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 712 #define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 713 #define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 714 #define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 715 #define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 716 #define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 717 #define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 718 #define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 719 #define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 720 #define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 721 #define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 722 #define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 723 #define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 724 725 #define ISP_NVRAM_TARGOFF 28 726 #define ISP_NVARM_TARGSIZE 6 727 #define _IxT(tgt, tidx) \ 728 (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) 729 #define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 730 #define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 731 #define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 732 #define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 733 #define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 734 #define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 735 #define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 736 #define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 737 #define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 738 #define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 739 #define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 740 #define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 741 #define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 742 743 /* 744 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 745 * 746 * Some portion of the front of this is for general host adapter properties 747 * This is followed by an array of per-target parameters, and is tailed off 748 * with a checksum xor byte at offset 256. For non-byte entities data is 749 * stored in Little Endian order. 750 */ 751 752 #define ISP1080_NVRAM_SIZE 256 753 754 #define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 755 756 /* Offset 5 */ 757 /* 758 u_int8_t bios_configuration_mode :2; 759 u_int8_t bios_disable :1; 760 u_int8_t selectable_scsi_boot_enable :1; 761 u_int8_t cd_rom_boot_enable :1; 762 u_int8_t disable_loading_risc_code :1; 763 u_int8_t enable_64bit_addressing :1; 764 u_int8_t unused_7 :1; 765 */ 766 767 /* Offsets 6, 7 */ 768 /* 769 u_int8_t boot_lun_number :5; 770 u_int8_t scsi_bus_number :1; 771 u_int8_t unused_6 :1; 772 u_int8_t unused_7 :1; 773 u_int8_t boot_target_number :4; 774 u_int8_t unused_12 :1; 775 u_int8_t unused_13 :1; 776 u_int8_t unused_14 :1; 777 u_int8_t unused_15 :1; 778 */ 779 780 #define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 781 782 #define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 783 #define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 784 785 #define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 786 #define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 787 #define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 788 789 #define ISP1080_ISP_PARAMETER(c) \ 790 (((c)[18]) | ((c)[19] << 8)) 791 792 #define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 793 #define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 794 795 #define ISP1080_BUS1_OFF 112 796 797 #define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 798 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 799 #define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 800 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 801 #define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 802 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 803 #define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 804 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 805 806 #define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 807 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 808 #define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 809 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 810 #define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 811 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 812 #define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 813 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 814 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 815 #define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 816 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 817 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 818 819 #define ISP1080_NVRAM_TARGOFF(b) \ 820 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 821 #define ISP1080_NVRAM_TARGSIZE 6 822 #define _IxT8(tgt, tidx, b) \ 823 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 824 825 #define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 826 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 827 #define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 828 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 829 #define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 830 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 831 #define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 832 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 833 #define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 834 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 835 #define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 836 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 837 #define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 838 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 839 #define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 840 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 841 #define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 842 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 843 #define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 844 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 845 #define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 846 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 847 #define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 848 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 849 #define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 850 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 851 852 #define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 853 #define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 854 #define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 855 #define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 856 #define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 857 #define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 858 #define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 859 #define ISP12160_FAST_POST ISP1080_FAST_POST 860 #define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 861 862 #define ISP12160_NVRAM_INITIATOR_ID \ 863 ISP1080_NVRAM_INITIATOR_ID 864 #define ISP12160_NVRAM_BUS_RESET_DELAY \ 865 ISP1080_NVRAM_BUS_RESET_DELAY 866 #define ISP12160_NVRAM_BUS_RETRY_COUNT \ 867 ISP1080_NVRAM_BUS_RETRY_COUNT 868 #define ISP12160_NVRAM_BUS_RETRY_DELAY \ 869 ISP1080_NVRAM_BUS_RETRY_DELAY 870 #define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 871 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 872 #define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 873 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 874 #define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 875 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 876 #define ISP12160_NVRAM_SELECTION_TIMEOUT \ 877 ISP1080_NVRAM_SELECTION_TIMEOUT 878 #define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 879 ISP1080_NVRAM_MAX_QUEUE_DEPTH 880 881 882 #define ISP12160_BUS0_OFF 24 883 #define ISP12160_BUS1_OFF 136 884 885 #define ISP12160_NVRAM_TARGOFF(b) \ 886 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 887 888 #define ISP12160_NVRAM_TARGSIZE 6 889 #define _IxT16(tgt, tidx, b) \ 890 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 891 892 #define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 893 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 894 #define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 895 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 896 #define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 897 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 898 #define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 899 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 900 #define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 901 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 902 #define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 903 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 904 #define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 905 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 906 #define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 907 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 908 909 #define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 910 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 911 #define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 912 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 913 914 #define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 915 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 916 #define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 917 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 918 919 #define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 920 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 921 #define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 922 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 923 #define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 924 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 925 926 /* 927 * Qlogic 2XXX NVRAM is an array of 256 bytes. 928 * 929 * Some portion of the front of this is for general RISC engine parameters, 930 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 931 * 932 * This is followed by some general host adapter parameters, and ends with 933 * a checksum xor byte at offset 255. For non-byte entities data is stored 934 * in Little Endian order. 935 */ 936 #define ISP2100_NVRAM_SIZE 256 937 /* ISP_NVRAM_VERSION is in same overall place */ 938 #define ISP2100_NVRAM_RISCVER(c) (c)[6] 939 #define ISP2100_NVRAM_OPTIONS(c) (c)[8] 940 #define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 941 #define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 942 #define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 943 #define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 944 #define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 945 946 #define ISP2100_NVRAM_PORT_NAME(c) (\ 947 (((u_int64_t)(c)[18]) << 56) | \ 948 (((u_int64_t)(c)[19]) << 48) | \ 949 (((u_int64_t)(c)[20]) << 40) | \ 950 (((u_int64_t)(c)[21]) << 32) | \ 951 (((u_int64_t)(c)[22]) << 24) | \ 952 (((u_int64_t)(c)[23]) << 16) | \ 953 (((u_int64_t)(c)[24]) << 8) | \ 954 (((u_int64_t)(c)[25]) << 0)) 955 956 #define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] 957 958 #define ISP2200_NVRAM_NODE_NAME(c) (\ 959 (((u_int64_t)(c)[30]) << 56) | \ 960 (((u_int64_t)(c)[31]) << 48) | \ 961 (((u_int64_t)(c)[32]) << 40) | \ 962 (((u_int64_t)(c)[33]) << 32) | \ 963 (((u_int64_t)(c)[34]) << 24) | \ 964 (((u_int64_t)(c)[35]) << 16) | \ 965 (((u_int64_t)(c)[36]) << 8) | \ 966 (((u_int64_t)(c)[37]) << 0)) 967 968 #define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] 969 #define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 970 #define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 971 #define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 972 #define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 973 #define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 974 #define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 975 976 #define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 977 (((u_int64_t)(c)[72]) << 56) | \ 978 (((u_int64_t)(c)[73]) << 48) | \ 979 (((u_int64_t)(c)[74]) << 40) | \ 980 (((u_int64_t)(c)[75]) << 32) | \ 981 (((u_int64_t)(c)[76]) << 24) | \ 982 (((u_int64_t)(c)[77]) << 16) | \ 983 (((u_int64_t)(c)[78]) << 8) | \ 984 (((u_int64_t)(c)[79]) << 0)) 985 986 #define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 987 988 #define ISP2200_HBA_FEATURES(c) (c)[232] | ((c)[233] << 8) 989 990 /* 991 * Firmware Crash Dump 992 * 993 * QLogic needs specific information format when they look at firmware crashes. 994 * 995 * This is incredibly kernel memory consumptive (to say the least), so this 996 * code is only compiled in when needed. 997 */ 998 999 #define QLA2200_RISC_IMAGE_DUMP_SIZE \ 1000 (1 * sizeof (u_int16_t)) + /* 'used' flag (also HBA type) */ \ 1001 (352 * sizeof (u_int16_t)) + /* RISC registers */ \ 1002 (61440 * sizeof (u_int16_t)) /* RISC SRAM (offset 0x1000..0xffff) */ 1003 #define QLA2300_RISC_IMAGE_DUMP_SIZE \ 1004 (1 * sizeof (u_int16_t)) + /* 'used' flag (also HBA type) */ \ 1005 (464 * sizeof (u_int16_t)) + /* RISC registers */ \ 1006 (63488 * sizeof (u_int16_t)) + /* RISC SRAM (0x0800..0xffff) */ \ 1007 (4096 * sizeof (u_int16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \ 1008 (61440 * sizeof (u_int16_t)) /* RISC SRAM (0x11000..0x1FFFF) */ 1009 /* the larger of the two */ 1010 #define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE 1011 #endif /* _ISPREG_H */ 1012