1 /* $FreeBSD: src/sys/dev/mpt/mpilib/mpi_cnfg.h,v 1.1.2.2 2002/09/01 23:08:06 mjacob Exp $ */ 2 /* 3 * Copyright (c) 2000, 2001 by LSI Logic Corporation 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * 27 * Name: MPI_CNFG.H 28 * Title: MPI Config message, structures, and Pages 29 * Creation Date: July 27, 2000 30 * 31 * MPI Version: 01.02.05 32 * 33 * Version History 34 * --------------- 35 * 36 * Date Version Description 37 * -------- -------- ------------------------------------------------------ 38 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 39 * 06-06-00 01.00.01 Update version number for 1.0 release. 40 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 41 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 42 * fields to FC_DEVICE_0 page, updated the page version. 43 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 44 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 45 * and updated the page versions. 46 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 47 * page and updated the page version. 48 * Added Information field and _INFO_PARAMS_NEGOTIATED 49 * definitionto SCSI_DEVICE_0 page. 50 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 51 * page version. 52 * Added BucketsRemaining to LAN_1 page, redefined the 53 * state values, and updated the page version. 54 * Revised bus width definitions in SCSI_PORT_0, 55 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 56 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 57 * version. 58 * Moved FC_DEVICE_0 PageAddress description to spec. 59 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 60 * widths in IOC_0 page and updated the page version. 61 * 11-02-00 01.01.01 Original release for post 1.0 work 62 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 63 * Port Page 2, FC Port Page 4, FC Port Page 5 64 * 11-15-00 01.01.02 Interim changes to match proposals 65 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 66 * 12-05-00 01.01.04 Modified config page actions. 67 * 01-09-01 01.01.05 Added defines for page address formats. 68 * Data size for Manufacturing pages 2 and 3 no longer 69 * defined here. 70 * Io Unit Page 2 size is fixed at 4 adapters and some 71 * flags were changed. 72 * SCSI Port Page 2 Device Settings modified. 73 * New fields added to FC Port Page 0 and some flags 74 * cleaned up. 75 * Removed impedance flash from FC Port Page 1. 76 * Added FC Port pages 6 and 7. 77 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 78 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 79 * Added some LinkType defines for FcPortPage0. 80 * 02-20-01 01.01.08 Started using MPI_POINTER. 81 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 82 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 83 * Added definitions and structures for IOC Page 2 and 84 * RAID Volume Page 2. 85 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 86 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 87 * Added VendorId and ProductRevLevel fields to 88 * RAIDVOL2_IM_PHYS_ID struct. 89 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 90 * defines to make them compatible to MPI version 1.0. 91 * Added structure offset comments. 92 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 93 * removed some obsolete ones. 94 * Added IO Unit Page 3. 95 * Modified defines for Scsi Port Page 2. 96 * Modified RAID Volume Pages. 97 * 08-08-01 01.02.01 Original release for v1.2 work. 98 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 99 * Added defines for the SEP bits in RVP2 VolumeSettings. 100 * Modified the DeviceSettings field in RVP2 to use the 101 * proper structure. 102 * Added defines for SES, SAF-TE, and cross channel for 103 * IOCPage2 CapabilitiesFlags. 104 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 105 * Removed define for 106 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 107 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 108 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 109 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 110 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 111 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 112 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 113 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 114 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 115 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 116 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 117 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 118 * Added rejected bits to SCSI Device Page 0 Information. 119 * Increased size of ALPA array in FC Port Page 2 by one 120 * and removed a one byte reserved field. 121 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 122 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 123 * Added structures for Manufacturing Page 4, IO Unit 124 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 125 * RAID PhysDisk Page 0. 126 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 127 * Modified some of the new defines to make them 32 128 * character unique. 129 * Modified how variable length pages (arrays) are defined. 130 * Added generic defines for hot spare pools and RAID 131 * volume types. 132 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 133 * -------------------------------------------------------------------------- 134 */ 135 136 #ifndef MPI_CNFG_H 137 #define MPI_CNFG_H 138 139 140 /***************************************************************************** 141 * 142 * C o n f i g M e s s a g e a n d S t r u c t u r e s 143 * 144 *****************************************************************************/ 145 146 typedef struct _CONFIG_PAGE_HEADER 147 { 148 U8 PageVersion; /* 00h */ 149 U8 PageLength; /* 01h */ 150 U8 PageNumber; /* 02h */ 151 U8 PageType; /* 03h */ 152 } fCONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 153 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 154 155 typedef union _CONFIG_PAGE_HEADER_UNION 156 { 157 ConfigPageHeader_t Struct; 158 U8 Bytes[4]; 159 U16 Word16[2]; 160 U32 Word32; 161 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 162 fCONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 163 164 165 /**************************************************************************** 166 * PageType field values 167 ****************************************************************************/ 168 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 169 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 170 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 171 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 172 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 173 174 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 175 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 176 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 177 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 178 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 179 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 180 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 181 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 182 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 183 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 184 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 185 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 186 187 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 188 189 190 /**************************************************************************** 191 * PageAddress field values 192 ****************************************************************************/ 193 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 194 195 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 196 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 197 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 198 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 199 200 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 201 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 202 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 203 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 204 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 205 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 206 207 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 208 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 209 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 210 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 211 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 212 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 213 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 214 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 215 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 216 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 217 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 218 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 219 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 220 221 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 222 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 223 224 225 226 /**************************************************************************** 227 * Config Request Message 228 ****************************************************************************/ 229 typedef struct _MSG_CONFIG 230 { 231 U8 Action; /* 00h */ 232 U8 Reserved; /* 01h */ 233 U8 ChainOffset; /* 02h */ 234 U8 Function; /* 03h */ 235 U8 Reserved1[3]; /* 04h */ 236 U8 MsgFlags; /* 07h */ 237 U32 MsgContext; /* 08h */ 238 U8 Reserved2[8]; /* 0Ch */ 239 fCONFIG_PAGE_HEADER Header; /* 14h */ 240 U32 PageAddress; /* 18h */ 241 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 242 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 243 Config_t, MPI_POINTER pConfig_t; 244 245 246 /**************************************************************************** 247 * Action field values 248 ****************************************************************************/ 249 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 250 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 251 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 252 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 253 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 254 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 255 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 256 257 258 /* Config Reply Message */ 259 typedef struct _MSG_CONFIG_REPLY 260 { 261 U8 Action; /* 00h */ 262 U8 Reserved; /* 01h */ 263 U8 MsgLength; /* 02h */ 264 U8 Function; /* 03h */ 265 U8 Reserved1[3]; /* 04h */ 266 U8 MsgFlags; /* 07h */ 267 U32 MsgContext; /* 08h */ 268 U8 Reserved2[2]; /* 0Ch */ 269 U16 IOCStatus; /* 0Eh */ 270 U32 IOCLogInfo; /* 10h */ 271 fCONFIG_PAGE_HEADER Header; /* 14h */ 272 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 273 ConfigReply_t, MPI_POINTER pConfigReply_t; 274 275 276 277 /***************************************************************************** 278 * 279 * C o n f i g u r a t i o n P a g e s 280 * 281 *****************************************************************************/ 282 283 /**************************************************************************** 284 * Manufacturing Config pages 285 ****************************************************************************/ 286 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 287 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 288 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 289 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 290 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 291 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 292 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 293 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 294 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 295 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 296 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 297 298 typedef struct _CONFIG_PAGE_MANUFACTURING_0 299 { 300 fCONFIG_PAGE_HEADER Header; /* 00h */ 301 U8 ChipName[16]; /* 04h */ 302 U8 ChipRevision[8]; /* 14h */ 303 U8 BoardName[16]; /* 1Ch */ 304 U8 BoardAssembly[16]; /* 2Ch */ 305 U8 BoardTracerNumber[16]; /* 3Ch */ 306 307 } fCONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 308 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 309 310 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 311 312 313 typedef struct _CONFIG_PAGE_MANUFACTURING_1 314 { 315 fCONFIG_PAGE_HEADER Header; /* 00h */ 316 U8 VPD[256]; /* 04h */ 317 } fCONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 318 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 319 320 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 321 322 323 typedef struct _MPI_CHIP_REVISION_ID 324 { 325 U16 DeviceID; /* 00h */ 326 U8 PCIRevisionID; /* 02h */ 327 U8 Reserved; /* 03h */ 328 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 329 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 330 331 332 /* 333 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 334 * one and check Header.PageLength at runtime. 335 */ 336 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 337 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 338 #endif 339 340 typedef struct _CONFIG_PAGE_MANUFACTURING_2 341 { 342 fCONFIG_PAGE_HEADER Header; /* 00h */ 343 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 344 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 345 } fCONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 346 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 347 348 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 349 350 351 /* 352 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 353 * one and check Header.PageLength at runtime. 354 */ 355 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 356 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 357 #endif 358 359 typedef struct _CONFIG_PAGE_MANUFACTURING_3 360 { 361 fCONFIG_PAGE_HEADER Header; /* 00h */ 362 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 363 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 364 } fCONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 365 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 366 367 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 368 369 370 typedef struct _CONFIG_PAGE_MANUFACTURING_4 371 { 372 fCONFIG_PAGE_HEADER Header; /* 00h */ 373 U32 Reserved1; /* 04h */ 374 U8 InfoOffset0; /* 08h */ 375 U8 InfoSize0; /* 09h */ 376 U8 InfoOffset1; /* 0Ah */ 377 U8 InfoSize1; /* 0Bh */ 378 U8 InquirySize; /* 0Ch */ 379 U8 Reserved2; /* 0Dh */ 380 U16 Reserved3; /* 0Eh */ 381 U8 InquiryData[56]; /* 10h */ 382 U32 ISVolumeSettings; /* 48h */ 383 U32 IMEVolumeSettings; /* 4Ch */ 384 U32 IMVolumeSettings; /* 50h */ 385 } fCONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 386 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 387 388 #define MPI_MANUFACTURING4_PAGEVERSION (0x00) 389 390 391 /**************************************************************************** 392 * IO Unit Config Pages 393 ****************************************************************************/ 394 395 typedef struct _CONFIG_PAGE_IO_UNIT_0 396 { 397 fCONFIG_PAGE_HEADER Header; /* 00h */ 398 U64 UniqueValue; /* 04h */ 399 } fCONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 400 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 401 402 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 403 404 405 typedef struct _CONFIG_PAGE_IO_UNIT_1 406 { 407 fCONFIG_PAGE_HEADER Header; /* 00h */ 408 U32 Flags; /* 04h */ 409 } fCONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 410 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 411 412 #define MPI_IOUNITPAGE1_PAGEVERSION (0x00) 413 414 /* IO Unit Page 1 Flags defines */ 415 416 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 417 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 418 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 419 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 420 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 421 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 422 423 424 typedef struct _MPI_ADAPTER_INFO 425 { 426 U8 PciBusNumber; /* 00h */ 427 U8 PciDeviceAndFunctionNumber; /* 01h */ 428 U16 AdapterFlags; /* 02h */ 429 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 430 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 431 432 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 433 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 434 435 typedef struct _CONFIG_PAGE_IO_UNIT_2 436 { 437 fCONFIG_PAGE_HEADER Header; /* 00h */ 438 U32 Flags; /* 04h */ 439 U32 BiosVersion; /* 08h */ 440 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 441 } fCONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 442 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 443 444 #define MPI_IOUNITPAGE2_PAGEVERSION (0x00) 445 446 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 447 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 448 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 449 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 450 451 452 /* 453 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 454 * one and check Header.PageLength at runtime. 455 */ 456 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 457 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 458 #endif 459 460 typedef struct _CONFIG_PAGE_IO_UNIT_3 461 { 462 fCONFIG_PAGE_HEADER Header; /* 00h */ 463 U8 GPIOCount; /* 04h */ 464 U8 Reserved1; /* 05h */ 465 U16 Reserved2; /* 06h */ 466 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 467 } fCONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 468 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 469 470 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 471 472 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 473 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 474 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 475 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 476 477 478 /**************************************************************************** 479 * IOC Config Pages 480 ****************************************************************************/ 481 482 typedef struct _CONFIG_PAGE_IOC_0 483 { 484 fCONFIG_PAGE_HEADER Header; /* 00h */ 485 U32 TotalNVStore; /* 04h */ 486 U32 FreeNVStore; /* 08h */ 487 U16 VendorID; /* 0Ch */ 488 U16 DeviceID; /* 0Eh */ 489 U8 RevisionID; /* 10h */ 490 U8 Reserved[3]; /* 11h */ 491 U32 ClassCode; /* 14h */ 492 U16 SubsystemVendorID; /* 18h */ 493 U16 SubsystemID; /* 1Ah */ 494 } fCONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 495 IOCPage0_t, MPI_POINTER pIOCPage0_t; 496 497 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 498 499 500 typedef struct _CONFIG_PAGE_IOC_1 501 { 502 fCONFIG_PAGE_HEADER Header; /* 00h */ 503 U32 Flags; /* 04h */ 504 U32 CoalescingTimeout; /* 08h */ 505 U8 CoalescingDepth; /* 0Ch */ 506 U8 Reserved[3]; /* 0Dh */ 507 } fCONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 508 IOCPage1_t, MPI_POINTER pIOCPage1_t; 509 510 #define MPI_IOCPAGE1_PAGEVERSION (0x00) 511 512 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 513 514 515 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 516 { 517 U8 VolumeID; /* 00h */ 518 U8 VolumeBus; /* 01h */ 519 U8 VolumeIOC; /* 02h */ 520 U8 VolumePageNumber; /* 03h */ 521 U8 VolumeType; /* 04h */ 522 U8 Reserved2; /* 05h */ 523 U16 Reserved3; /* 06h */ 524 } fCONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 525 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 526 527 /* 528 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 529 * one and check Header.PageLength at runtime. 530 */ 531 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 532 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 533 #endif 534 535 typedef struct _CONFIG_PAGE_IOC_2 536 { 537 fCONFIG_PAGE_HEADER Header; /* 00h */ 538 U32 CapabilitiesFlags; /* 04h */ 539 U8 NumActiveVolumes; /* 08h */ 540 U8 MaxVolumes; /* 09h */ 541 U8 NumActivePhysDisks; /* 0Ah */ 542 U8 MaxPhysDisks; /* 0Bh */ 543 fCONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 544 } fCONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 545 IOCPage2_t, MPI_POINTER pIOCPage2_t; 546 547 #define MPI_IOCPAGE2_PAGEVERSION (0x01) 548 549 /* IOC Page 2 Capabilities flags */ 550 551 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 552 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 553 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 554 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 555 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 556 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 557 558 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 559 560 #define MPI_RAID_VOL_TYPE_IS (0x00) 561 #define MPI_RAID_VOL_TYPE_IME (0x01) 562 #define MPI_RAID_VOL_TYPE_IM (0x02) 563 564 565 typedef struct _IOC_3_PHYS_DISK 566 { 567 U8 PhysDiskID; /* 00h */ 568 U8 PhysDiskBus; /* 01h */ 569 U8 PhysDiskIOC; /* 02h */ 570 U8 PhysDiskNum; /* 03h */ 571 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 572 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 573 574 /* 575 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 576 * one and check Header.PageLength at runtime. 577 */ 578 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 579 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 580 #endif 581 582 typedef struct _CONFIG_PAGE_IOC_3 583 { 584 fCONFIG_PAGE_HEADER Header; /* 00h */ 585 U8 NumPhysDisks; /* 04h */ 586 U8 Reserved1; /* 05h */ 587 U16 Reserved2; /* 06h */ 588 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 589 } fCONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 590 IOCPage3_t, MPI_POINTER pIOCPage3_t; 591 592 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 593 594 595 typedef struct _IOC_4_SEP 596 { 597 U8 SEPTargetID; /* 00h */ 598 U8 SEPBus; /* 01h */ 599 U16 Reserved; /* 02h */ 600 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 601 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 602 603 /* 604 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 605 * one and check Header.PageLength at runtime. 606 */ 607 #ifndef MPI_IOC_PAGE_4_SEP_MAX 608 #define MPI_IOC_PAGE_4_SEP_MAX (1) 609 #endif 610 611 typedef struct _CONFIG_PAGE_IOC_4 612 { 613 fCONFIG_PAGE_HEADER Header; /* 00h */ 614 U8 ActiveSEP; /* 04h */ 615 U8 MaxSEP; /* 05h */ 616 U16 Reserved1; /* 06h */ 617 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 618 } fCONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 619 IOCPage4_t, MPI_POINTER pIOCPage4_t; 620 621 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 622 623 624 /**************************************************************************** 625 * SCSI Port Config Pages 626 ****************************************************************************/ 627 628 typedef struct _CONFIG_PAGE_SCSI_PORT_0 629 { 630 fCONFIG_PAGE_HEADER Header; /* 00h */ 631 U32 Capabilities; /* 04h */ 632 U32 PhysicalInterface; /* 08h */ 633 } fCONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 634 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 635 636 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01) 637 638 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 639 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 640 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 641 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 642 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 643 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 644 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 645 646 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 647 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 648 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 649 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 650 651 652 typedef struct _CONFIG_PAGE_SCSI_PORT_1 653 { 654 fCONFIG_PAGE_HEADER Header; /* 00h */ 655 U32 Configuration; /* 04h */ 656 U32 OnBusTimerValue; /* 08h */ 657 } fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 658 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 659 660 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02) 661 662 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 663 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 664 665 666 typedef struct _MPI_DEVICE_INFO 667 { 668 U8 Timeout; /* 00h */ 669 U8 SyncFactor; /* 01h */ 670 U16 DeviceFlags; /* 02h */ 671 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 672 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 673 674 typedef struct _CONFIG_PAGE_SCSI_PORT_2 675 { 676 fCONFIG_PAGE_HEADER Header; /* 00h */ 677 U32 PortFlags; /* 04h */ 678 U32 PortSettings; /* 08h */ 679 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 680 } fCONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 681 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 682 683 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01) 684 685 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 686 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 687 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 688 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 689 690 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 691 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 692 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 693 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 694 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 695 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 696 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 697 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 698 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 699 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 700 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 701 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 702 703 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 704 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 705 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 706 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 707 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 708 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 709 710 711 /**************************************************************************** 712 * SCSI Target Device Config Pages 713 ****************************************************************************/ 714 715 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 716 { 717 fCONFIG_PAGE_HEADER Header; /* 00h */ 718 U32 NegotiatedParameters; /* 04h */ 719 U32 Information; /* 08h */ 720 } fCONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 721 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 722 723 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x02) 724 725 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 726 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 727 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 728 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 729 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 730 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 731 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 732 733 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 734 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 735 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 736 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 737 738 739 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 740 { 741 fCONFIG_PAGE_HEADER Header; /* 00h */ 742 U32 RequestedParameters; /* 04h */ 743 U32 Reserved; /* 08h */ 744 U32 Configuration; /* 0Ch */ 745 } fCONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 746 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 747 748 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x03) 749 750 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 751 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 752 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 753 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 754 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 755 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 756 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 757 758 #define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK (0x00000003) 759 #define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK (0x00000300) 760 761 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 762 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 763 764 765 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 766 { 767 fCONFIG_PAGE_HEADER Header; /* 00h */ 768 U32 DomainValidation; /* 04h */ 769 U32 ParityPipeSelect; /* 08h */ 770 U32 DataPipeSelect; /* 0Ch */ 771 } fCONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 772 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 773 774 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x00) 775 776 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 777 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 778 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 779 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 780 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 781 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 782 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 783 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 784 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 785 786 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 787 788 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 789 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 790 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 791 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 792 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 793 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 794 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 795 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 796 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 797 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 798 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 799 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 800 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 801 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 802 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 803 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 804 805 806 /**************************************************************************** 807 * FC Port Config Pages 808 ****************************************************************************/ 809 810 typedef struct _CONFIG_PAGE_FC_PORT_0 811 { 812 fCONFIG_PAGE_HEADER Header; /* 00h */ 813 U32 Flags; /* 04h */ 814 U8 MPIPortNumber; /* 08h */ 815 U8 LinkType; /* 09h */ 816 U8 PortState; /* 0Ah */ 817 U8 Reserved; /* 0Bh */ 818 U32 PortIdentifier; /* 0Ch */ 819 U64 WWNN; /* 10h */ 820 U64 WWPN; /* 18h */ 821 U32 SupportedServiceClass; /* 20h */ 822 U32 SupportedSpeeds; /* 24h */ 823 U32 CurrentSpeed; /* 28h */ 824 U32 MaxFrameSize; /* 2Ch */ 825 U64 FabricWWNN; /* 30h */ 826 U64 FabricWWPN; /* 38h */ 827 U32 DiscoveredPortsCount; /* 40h */ 828 U32 MaxInitiators; /* 44h */ 829 } fCONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 830 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 831 832 #define MPI_FCPORTPAGE0_PAGEVERSION (0x01) 833 834 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 835 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 836 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 837 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 838 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 839 840 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 841 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 842 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000030) 843 844 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 845 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 846 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 847 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 848 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 849 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 850 851 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 852 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 853 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 854 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 855 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 856 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 857 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 858 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 859 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 860 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 861 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 862 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 863 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 864 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 865 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 866 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 867 868 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 869 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 870 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 871 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 872 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 873 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 874 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 875 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 876 877 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 878 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 879 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 880 881 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 882 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 883 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 884 885 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 886 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 887 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 888 889 890 typedef struct _CONFIG_PAGE_FC_PORT_1 891 { 892 fCONFIG_PAGE_HEADER Header; /* 00h */ 893 U32 Flags; /* 04h */ 894 U64 NoSEEPROMWWNN; /* 08h */ 895 U64 NoSEEPROMWWPN; /* 10h */ 896 U8 HardALPA; /* 18h */ 897 U8 LinkConfig; /* 19h */ 898 U8 TopologyConfig; /* 1Ah */ 899 U8 Reserved; /* 1Bh */ 900 } fCONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 901 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 902 903 #define MPI_FCPORTPAGE1_PAGEVERSION (0x02) 904 905 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 906 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 907 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 908 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 909 910 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 911 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 912 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 913 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 914 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 915 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 916 917 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 918 919 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 920 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 921 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 922 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 923 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 924 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 925 926 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 927 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 928 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 929 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 930 931 932 typedef struct _CONFIG_PAGE_FC_PORT_2 933 { 934 fCONFIG_PAGE_HEADER Header; /* 00h */ 935 U8 NumberActive; /* 04h */ 936 U8 ALPA[127]; /* 05h */ 937 } fCONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 938 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 939 940 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 941 942 943 typedef struct _WWN_FORMAT 944 { 945 U64 WWNN; /* 00h */ 946 U64 WWPN; /* 08h */ 947 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 948 WWNFormat, MPI_POINTER pWWNFormat; 949 950 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 951 { 952 WWN_FORMAT WWN; 953 U32 Did; 954 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 955 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 956 957 typedef struct _FC_PORT_PERSISTENT 958 { 959 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 960 U8 TargetID; /* 10h */ 961 U8 Bus; /* 11h */ 962 U16 Flags; /* 12h */ 963 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 964 PersistentData_t, MPI_POINTER pPersistentData_t; 965 966 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 967 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 968 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 969 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 970 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 971 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 972 973 /* 974 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 975 * one and check Header.PageLength at runtime. 976 */ 977 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 978 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 979 #endif 980 981 typedef struct _CONFIG_PAGE_FC_PORT_3 982 { 983 fCONFIG_PAGE_HEADER Header; /* 00h */ 984 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 985 } fCONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 986 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 987 988 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 989 990 991 typedef struct _CONFIG_PAGE_FC_PORT_4 992 { 993 fCONFIG_PAGE_HEADER Header; /* 00h */ 994 U32 PortFlags; /* 04h */ 995 U32 PortSettings; /* 08h */ 996 } fCONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 997 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 998 999 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1000 1001 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1002 1003 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1004 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1005 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1006 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1007 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1008 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1009 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1010 1011 1012 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1013 { 1014 U8 Flags; /* 00h */ 1015 U8 AliasAlpa; /* 01h */ 1016 U16 Reserved; /* 02h */ 1017 U64 AliasWWNN; /* 04h */ 1018 U64 AliasWWPN; /* 0Ch */ 1019 } fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1020 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1021 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1022 1023 /* 1024 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1025 * one and check Header.PageLength at runtime. 1026 */ 1027 #ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX 1028 #define MPI_FC_PORT_PAGE_5_ALIAS_MAX (1) 1029 #endif 1030 1031 typedef struct _CONFIG_PAGE_FC_PORT_5 1032 { 1033 fCONFIG_PAGE_HEADER Header; /* 00h */ 1034 fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX];/* 04h */ 1035 } fCONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1036 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1037 1038 #define MPI_FCPORTPAGE5_PAGEVERSION (0x00) 1039 1040 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID (0x01) 1041 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID (0x02) 1042 1043 1044 typedef struct _CONFIG_PAGE_FC_PORT_6 1045 { 1046 fCONFIG_PAGE_HEADER Header; /* 00h */ 1047 U32 Reserved; /* 04h */ 1048 U64 TimeSinceReset; /* 08h */ 1049 U64 TxFrames; /* 10h */ 1050 U64 RxFrames; /* 18h */ 1051 U64 TxWords; /* 20h */ 1052 U64 RxWords; /* 28h */ 1053 U64 LipCount; /* 30h */ 1054 U64 NosCount; /* 38h */ 1055 U64 ErrorFrames; /* 40h */ 1056 U64 DumpedFrames; /* 48h */ 1057 U64 LinkFailureCount; /* 50h */ 1058 U64 LossOfSyncCount; /* 58h */ 1059 U64 LossOfSignalCount; /* 60h */ 1060 U64 PrimativeSeqErrCount; /* 68h */ 1061 U64 InvalidTxWordCount; /* 70h */ 1062 U64 InvalidCrcCount; /* 78h */ 1063 U64 FcpInitiatorIoCount; /* 80h */ 1064 } fCONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 1065 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 1066 1067 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 1068 1069 1070 typedef struct _CONFIG_PAGE_FC_PORT_7 1071 { 1072 fCONFIG_PAGE_HEADER Header; /* 00h */ 1073 U32 Reserved; /* 04h */ 1074 U8 PortSymbolicName[256]; /* 08h */ 1075 } fCONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 1076 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 1077 1078 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 1079 1080 1081 typedef struct _CONFIG_PAGE_FC_PORT_8 1082 { 1083 fCONFIG_PAGE_HEADER Header; /* 00h */ 1084 U32 BitVector[8]; /* 04h */ 1085 } fCONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 1086 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 1087 1088 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 1089 1090 1091 typedef struct _CONFIG_PAGE_FC_PORT_9 1092 { 1093 fCONFIG_PAGE_HEADER Header; /* 00h */ 1094 U32 Reserved; /* 04h */ 1095 U64 GlobalWWPN; /* 08h */ 1096 U64 GlobalWWNN; /* 10h */ 1097 U32 UnitType; /* 18h */ 1098 U32 PhysicalPortNumber; /* 1Ch */ 1099 U32 NumAttachedNodes; /* 20h */ 1100 U16 IPVersion; /* 24h */ 1101 U16 UDPPortNumber; /* 26h */ 1102 U8 IPAddress[16]; /* 28h */ 1103 U16 Reserved1; /* 38h */ 1104 U16 TopologyDiscoveryFlags; /* 3Ah */ 1105 } fCONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 1106 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 1107 1108 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 1109 1110 1111 /**************************************************************************** 1112 * FC Device Config Pages 1113 ****************************************************************************/ 1114 1115 typedef struct _CONFIG_PAGE_FC_DEVICE_0 1116 { 1117 fCONFIG_PAGE_HEADER Header; /* 00h */ 1118 U64 WWNN; /* 04h */ 1119 U64 WWPN; /* 0Ch */ 1120 U32 PortIdentifier; /* 14h */ 1121 U8 Protocol; /* 18h */ 1122 U8 Flags; /* 19h */ 1123 U16 BBCredit; /* 1Ah */ 1124 U16 MaxRxFrameSize; /* 1Ch */ 1125 U8 Reserved1; /* 1Eh */ 1126 U8 PortNumber; /* 1Fh */ 1127 U8 FcPhLowestVersion; /* 20h */ 1128 U8 FcPhHighestVersion; /* 21h */ 1129 U8 CurrentTargetID; /* 22h */ 1130 U8 CurrentBus; /* 23h */ 1131 } fCONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 1132 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 1133 1134 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02) 1135 1136 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 1137 1138 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 1139 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 1140 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 1141 1142 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 1143 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 1144 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 1145 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 1146 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 1147 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 1148 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 1149 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 1150 1151 1152 /**************************************************************************** 1153 * RAID Volume Config Pages 1154 ****************************************************************************/ 1155 1156 typedef struct _RAID_VOL0_PHYS_DISK 1157 { 1158 U16 Reserved; /* 00h */ 1159 U8 PhysDiskMap; /* 02h */ 1160 U8 PhysDiskNum; /* 03h */ 1161 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 1162 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 1163 1164 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1165 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1166 1167 typedef struct _RAID_VOL0_STATUS 1168 { 1169 U8 Flags; /* 00h */ 1170 U8 State; /* 01h */ 1171 U16 Reserved; /* 02h */ 1172 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 1173 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 1174 1175 /* RAID Volume Page 0 VolumeStatus defines */ 1176 1177 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 1178 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 1179 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 1180 1181 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 1182 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 1183 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 1184 1185 typedef struct _RAID_VOL0_SETTINGS 1186 { 1187 U16 Settings; /* 00h */ 1188 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1189 U8 Reserved; /* 02h */ 1190 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 1191 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 1192 1193 /* RAID Volume Page 0 VolumeSettings defines */ 1194 1195 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 1196 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 1197 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 1198 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 1199 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 1200 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 1201 1202 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1203 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 1204 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 1205 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 1206 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 1207 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 1208 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 1209 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 1210 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 1211 1212 /* 1213 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1214 * one and check Header.PageLength at runtime. 1215 */ 1216 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 1217 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1218 #endif 1219 1220 typedef struct _CONFIG_PAGE_RAID_VOL_0 1221 { 1222 fCONFIG_PAGE_HEADER Header; /* 00h */ 1223 U8 VolumeID; /* 04h */ 1224 U8 VolumeBus; /* 05h */ 1225 U8 VolumeIOC; /* 06h */ 1226 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 1227 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 1228 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 1229 U32 MaxLBA; /* 10h */ 1230 U32 Reserved1; /* 14h */ 1231 U32 StripeSize; /* 18h */ 1232 U32 Reserved2; /* 1Ch */ 1233 U32 Reserved3; /* 20h */ 1234 U8 NumPhysDisks; /* 24h */ 1235 U8 Reserved4; /* 25h */ 1236 U16 Reserved5; /* 26h */ 1237 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 1238 } fCONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 1239 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 1240 1241 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x00) 1242 1243 1244 /**************************************************************************** 1245 * RAID Physical Disk Config Pages 1246 ****************************************************************************/ 1247 1248 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 1249 { 1250 U8 ErrorCdbByte; /* 00h */ 1251 U8 ErrorSenseKey; /* 01h */ 1252 U16 Reserved; /* 02h */ 1253 U16 ErrorCount; /* 04h */ 1254 U8 ErrorASC; /* 06h */ 1255 U8 ErrorASCQ; /* 07h */ 1256 U16 SmartCount; /* 08h */ 1257 U8 SmartASC; /* 0Ah */ 1258 U8 SmartASCQ; /* 0Bh */ 1259 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 1260 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 1261 1262 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 1263 { 1264 U8 VendorID[8]; /* 00h */ 1265 U8 ProductID[16]; /* 08h */ 1266 U8 ProductRevLevel[4]; /* 18h */ 1267 U8 Info[32]; /* 1Ch */ 1268 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 1269 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 1270 1271 typedef struct _RAID_PHYS_DISK0_SETTINGS 1272 { 1273 U8 SepID; /* 00h */ 1274 U8 SepBus; /* 01h */ 1275 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1276 U8 PhysDiskSettings; /* 03h */ 1277 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 1278 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 1279 1280 typedef struct _RAID_PHYS_DISK0_STATUS 1281 { 1282 U8 Flags; /* 00h */ 1283 U8 State; /* 01h */ 1284 U16 Reserved; /* 02h */ 1285 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 1286 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 1287 1288 /* RAID Volume 2 IM Physical Disk DiskStatus flags */ 1289 1290 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 1291 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 1292 1293 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 1294 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 1295 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 1296 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 1297 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 1298 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 1299 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 1300 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 1301 1302 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 1303 { 1304 fCONFIG_PAGE_HEADER Header; /* 00h */ 1305 U8 PhysDiskID; /* 04h */ 1306 U8 PhysDiskBus; /* 05h */ 1307 U8 PhysDiskIOC; /* 06h */ 1308 U8 PhysDiskNum; /* 07h */ 1309 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 1310 U32 Reserved1; /* 0Ch */ 1311 U32 Reserved2; /* 10h */ 1312 U32 Reserved3; /* 14h */ 1313 U8 DiskIdentifier[16]; /* 18h */ 1314 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 1315 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 1316 U32 MaxLBA; /* 68h */ 1317 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 1318 } fCONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 1319 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 1320 1321 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00) 1322 1323 1324 /**************************************************************************** 1325 * LAN Config Pages 1326 ****************************************************************************/ 1327 1328 typedef struct _CONFIG_PAGE_LAN_0 1329 { 1330 ConfigPageHeader_t Header; /* 00h */ 1331 U16 TxRxModes; /* 04h */ 1332 U16 Reserved; /* 06h */ 1333 U32 PacketPrePad; /* 08h */ 1334 } fCONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 1335 LANPage0_t, MPI_POINTER pLANPage0_t; 1336 1337 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 1338 1339 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 1340 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 1341 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 1342 1343 typedef struct _CONFIG_PAGE_LAN_1 1344 { 1345 ConfigPageHeader_t Header; /* 00h */ 1346 U16 Reserved; /* 04h */ 1347 U8 CurrentDeviceState; /* 06h */ 1348 U8 Reserved1; /* 07h */ 1349 U32 MinPacketSize; /* 08h */ 1350 U32 MaxPacketSize; /* 0Ch */ 1351 U32 HardwareAddressLow; /* 10h */ 1352 U32 HardwareAddressHigh; /* 14h */ 1353 U32 MaxWireSpeedLow; /* 18h */ 1354 U32 MaxWireSpeedHigh; /* 1Ch */ 1355 U32 BucketsRemaining; /* 20h */ 1356 U32 MaxReplySize; /* 24h */ 1357 U32 NegWireSpeedLow; /* 28h */ 1358 U32 NegWireSpeedHigh; /* 2Ch */ 1359 } fCONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 1360 LANPage1_t, MPI_POINTER pLANPage1_t; 1361 1362 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 1363 1364 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 1365 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 1366 1367 #endif 1368 1369