xref: /dragonfly/sys/dev/disk/nata/ata-all.h (revision 19fe1c42)
1 /*-
2  * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification, immediately at the beginning of the file.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * $FreeBSD: src/sys/dev/ata/ata-all.h,v 1.123 2007/04/08 19:18:51 sos Exp $
27  * $DragonFly: src/sys/dev/disk/nata/ata-all.h,v 1.12 2008/09/27 11:45:30 sephe Exp $
28  */
29 
30 #include <sys/param.h>
31 #include <sys/bio.h>
32 #include <sys/bus.h>
33 #include <sys/callout.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/nata.h>
37 #include <sys/objcache.h>
38 #include <sys/queue.h>
39 #include <sys/rman.h>
40 #include <sys/spinlock.h>
41 #include <sys/systm.h>
42 #include <sys/taskqueue.h>
43 
44 #include <machine/bus_dma.h>
45 
46 /* ATA register defines */
47 #define ATA_DATA                        0       /* (RW) data */
48 
49 #define ATA_FEATURE                     1       /* (W) feature */
50 #define         ATA_F_DMA               0x01    /* enable DMA */
51 #define         ATA_F_OVL               0x02    /* enable overlap */
52 
53 #define ATA_COUNT                       2       /* (W) sector count */
54 
55 #define ATA_SECTOR                      3       /* (RW) sector # */
56 #define ATA_CYL_LSB                     4       /* (RW) cylinder# LSB */
57 #define ATA_CYL_MSB                     5       /* (RW) cylinder# MSB */
58 #define ATA_DRIVE                       6       /* (W) Sector/Drive/Head */
59 #define         ATA_D_LBA               0x40    /* use LBA addressing */
60 #define         ATA_D_IBM               0xa0    /* 512 byte sectors, ECC */
61 
62 #define ATA_COMMAND                     7       /* (W) command */
63 
64 #define ATA_ERROR                       8       /* (R) error */
65 #define         ATA_E_ILI               0x01    /* illegal length */
66 #define         ATA_E_NM                0x02    /* no media */
67 #define         ATA_E_ABORT             0x04    /* command aborted */
68 #define         ATA_E_MCR               0x08    /* media change request */
69 #define         ATA_E_IDNF              0x10    /* ID not found */
70 #define         ATA_E_MC                0x20    /* media changed */
71 #define         ATA_E_UNC               0x40    /* uncorrectable data */
72 #define         ATA_E_ICRC              0x80    /* UDMA crc error */
73 #define		ATA_E_ATAPI_SENSE_MASK	0xf0	/* ATAPI sense key mask */
74 
75 #define ATA_IREASON                     9       /* (R) interrupt reason */
76 #define         ATA_I_CMD               0x01    /* cmd (1) | data (0) */
77 #define         ATA_I_IN                0x02    /* read (1) | write (0) */
78 #define         ATA_I_RELEASE           0x04    /* released bus (1) */
79 #define         ATA_I_TAGMASK           0xf8    /* tag mask */
80 
81 #define ATA_STATUS                      10      /* (R) status */
82 #define ATA_ALTSTAT                     11      /* (R) alternate status */
83 #define         ATA_S_ERROR             0x01    /* error */
84 #define         ATA_S_INDEX             0x02    /* index */
85 #define         ATA_S_CORR              0x04    /* data corrected */
86 #define         ATA_S_DRQ               0x08    /* data request */
87 #define         ATA_S_DSC               0x10    /* drive seek completed */
88 #define         ATA_S_SERVICE           0x10    /* drive needs service */
89 #define         ATA_S_DWF               0x20    /* drive write fault */
90 #define         ATA_S_DMA               0x20    /* DMA ready */
91 #define         ATA_S_READY             0x40    /* drive ready */
92 #define         ATA_S_BUSY              0x80    /* busy */
93 
94 #define ATA_CONTROL                     12      /* (W) control */
95 
96 #define ATA_CTLOFFSET                   0x206   /* control register offset */
97 #define ATA_PCCARD_CTLOFFSET            0x0e    /* do for PCCARD devices */
98 #define ATA_PC98_CTLOFFSET              0x10c   /* do for PC98 devices */
99 #define         ATA_A_IDS               0x02    /* disable interrupts */
100 #define         ATA_A_RESET             0x04    /* RESET controller */
101 #define         ATA_A_4BIT              0x08    /* 4 head bits */
102 #define         ATA_A_HOB               0x80    /* High Order Byte enable */
103 
104 /* SATA register defines */
105 #define ATA_SSTATUS                     13
106 #define         ATA_SS_DET_MASK         0x0000000f
107 #define         ATA_SS_DET_NO_DEVICE    0x00000000
108 #define         ATA_SS_DET_DEV_PRESENT  0x00000001
109 #define         ATA_SS_DET_PHY_ONLINE   0x00000003
110 #define         ATA_SS_DET_PHY_OFFLINE  0x00000004
111 
112 #define         ATA_SS_SPD_MASK         0x000000f0
113 #define         ATA_SS_SPD_NO_SPEED     0x00000000
114 #define         ATA_SS_SPD_GEN1         0x00000010
115 #define         ATA_SS_SPD_GEN2         0x00000020
116 
117 #define         ATA_SS_IPM_MASK         0x00000f00
118 #define         ATA_SS_IPM_NO_DEVICE    0x00000000
119 #define         ATA_SS_IPM_ACTIVE       0x00000100
120 #define         ATA_SS_IPM_PARTIAL      0x00000200
121 #define         ATA_SS_IPM_SLUMBER      0x00000600
122 
123 #define         ATA_SS_CONWELL_MASK \
124 		    (ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK)
125 #define         ATA_SS_CONWELL_GEN1 \
126 		    (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE)
127 #define         ATA_SS_CONWELL_GEN2 \
128 		    (ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE)
129 
130 #define ATA_SERROR                      14
131 #define         ATA_SE_DATA_CORRECTED   0x00000001
132 #define         ATA_SE_COMM_CORRECTED   0x00000002
133 #define         ATA_SE_DATA_ERR         0x00000100
134 #define         ATA_SE_COMM_ERR         0x00000200
135 #define         ATA_SE_PROT_ERR         0x00000400
136 #define         ATA_SE_HOST_ERR         0x00000800
137 #define         ATA_SE_PHY_CHANGED      0x00010000
138 #define         ATA_SE_PHY_IERROR       0x00020000
139 #define         ATA_SE_COMM_WAKE        0x00040000
140 #define         ATA_SE_DECODE_ERR       0x00080000
141 #define         ATA_SE_PARITY_ERR       0x00100000
142 #define         ATA_SE_CRC_ERR          0x00200000
143 #define         ATA_SE_HANDSHAKE_ERR    0x00400000
144 #define         ATA_SE_LINKSEQ_ERR      0x00800000
145 #define         ATA_SE_TRANSPORT_ERR    0x01000000
146 #define         ATA_SE_UNKNOWN_FIS      0x02000000
147 
148 #define ATA_SCONTROL                    15
149 #define         ATA_SC_DET_MASK         0x0000000f
150 #define         ATA_SC_DET_IDLE         0x00000000
151 #define         ATA_SC_DET_RESET        0x00000001
152 #define         ATA_SC_DET_DISABLE      0x00000004
153 
154 #define         ATA_SC_SPD_MASK         0x000000f0
155 #define         ATA_SC_SPD_NO_SPEED     0x00000000
156 #define         ATA_SC_SPD_SPEED_GEN1   0x00000010
157 #define         ATA_SC_SPD_SPEED_GEN2   0x00000020
158 
159 #define         ATA_SC_IPM_MASK         0x00000f00
160 #define         ATA_SC_IPM_NONE         0x00000000
161 #define         ATA_SC_IPM_DIS_PARTIAL  0x00000100
162 #define         ATA_SC_IPM_DIS_SLUMBER  0x00000200
163 
164 #define ATA_SACTIVE                     16
165 
166 /* SATA AHCI v1.0 register defines */
167 #define ATA_AHCI_CAP                    0x00
168 #define         ATA_AHCI_NPMASK         0x1f
169 #define		ATA_AHCI_CAP_CLO	0x01000000
170 #define		ATA_AHCI_CAP_64BIT	0x80000000
171 
172 #define ATA_AHCI_GHC                    0x04
173 #define         ATA_AHCI_GHC_AE         0x80000000
174 #define         ATA_AHCI_GHC_IE         0x00000002
175 #define         ATA_AHCI_GHC_HR         0x80000001
176 
177 #define ATA_AHCI_IS                     0x08
178 #define ATA_AHCI_PI                     0x0c
179 #define ATA_AHCI_VS                     0x10
180 
181 #define ATA_AHCI_OFFSET                 0x80
182 
183 #define ATA_AHCI_P_CLB                  0x100
184 #define ATA_AHCI_P_CLBU                 0x104
185 #define ATA_AHCI_P_FB                   0x108
186 #define ATA_AHCI_P_FBU                  0x10c
187 #define ATA_AHCI_P_IS                   0x110
188 #define ATA_AHCI_P_IE                   0x114
189 #define         ATA_AHCI_P_IX_DHR       0x00000001
190 #define         ATA_AHCI_P_IX_PS        0x00000002
191 #define         ATA_AHCI_P_IX_DS        0x00000004
192 #define         ATA_AHCI_P_IX_SDB       0x00000008
193 #define         ATA_AHCI_P_IX_UF        0x00000010
194 #define         ATA_AHCI_P_IX_DP        0x00000020
195 #define         ATA_AHCI_P_IX_PC        0x00000040
196 #define         ATA_AHCI_P_IX_DI        0x00000080
197 
198 #define         ATA_AHCI_P_IX_PRC       0x00400000
199 #define         ATA_AHCI_P_IX_IPM       0x00800000
200 #define         ATA_AHCI_P_IX_OF        0x01000000
201 #define         ATA_AHCI_P_IX_INF       0x04000000
202 #define         ATA_AHCI_P_IX_IF        0x08000000
203 #define         ATA_AHCI_P_IX_HBD       0x10000000
204 #define         ATA_AHCI_P_IX_HBF       0x20000000
205 #define         ATA_AHCI_P_IX_TFE       0x40000000
206 #define         ATA_AHCI_P_IX_CPD       0x80000000
207 
208 #define ATA_AHCI_P_CMD                  0x118
209 #define         ATA_AHCI_P_CMD_ST       0x00000001
210 #define         ATA_AHCI_P_CMD_SUD      0x00000002
211 #define         ATA_AHCI_P_CMD_POD      0x00000004
212 #define         ATA_AHCI_P_CMD_CLO      0x00000008
213 #define         ATA_AHCI_P_CMD_FRE      0x00000010
214 #define         ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
215 #define         ATA_AHCI_P_CMD_ISS      0x00002000
216 #define         ATA_AHCI_P_CMD_FR       0x00004000
217 #define         ATA_AHCI_P_CMD_CR       0x00008000
218 #define         ATA_AHCI_P_CMD_CPS      0x00010000
219 #define         ATA_AHCI_P_CMD_PMA      0x00020000
220 #define         ATA_AHCI_P_CMD_HPCP     0x00040000
221 #define         ATA_AHCI_P_CMD_ISP      0x00080000
222 #define         ATA_AHCI_P_CMD_CPD      0x00100000
223 #define         ATA_AHCI_P_CMD_ATAPI    0x01000000
224 #define         ATA_AHCI_P_CMD_DLAE     0x02000000
225 #define         ATA_AHCI_P_CMD_ALPE     0x04000000
226 #define         ATA_AHCI_P_CMD_ASP      0x08000000
227 #define         ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
228 #define         ATA_AHCI_P_CMD_NOOP     0x00000000
229 #define         ATA_AHCI_P_CMD_ACTIVE   0x10000000
230 #define         ATA_AHCI_P_CMD_PARTIAL  0x20000000
231 #define         ATA_AHCI_P_CMD_SLUMPER  0x60000000
232 
233 #define ATA_AHCI_P_TFD                  0x120
234 #define ATA_AHCI_P_SIG                  0x124
235 #define ATA_AHCI_P_SSTS                 0x128
236 #define ATA_AHCI_P_SCTL                 0x12c
237 #define ATA_AHCI_P_SERR                 0x130
238 #define ATA_AHCI_P_SACT                 0x134
239 #define ATA_AHCI_P_CI                   0x138
240 
241 #define ATA_AHCI_CL_SIZE                32
242 #define ATA_AHCI_CL_OFFSET              0
243 #define ATA_AHCI_FB_OFFSET              1024
244 #define ATA_AHCI_CT_OFFSET              1024+256
245 #define ATA_AHCI_CT_SG_OFFSET           128
246 #define ATA_AHCI_CT_SIZE                256
247 
248 struct ata_ahci_dma_prd {
249     u_int64_t			dba;
250     u_int32_t			reserved;
251     u_int32_t			dbc;		/* 0 based */
252 #define ATA_AHCI_PRD_MASK	0x003fffff	/* max 4MB */
253 #define ATA_AHCI_PRD_IPC	(1<<31)
254 } __packed;
255 
256 struct ata_ahci_cmd_tab {
257     u_int8_t			cfis[64];
258     u_int8_t			acmd[32];
259     u_int8_t			reserved[32];
260     struct ata_ahci_dma_prd	prd_tab[16];
261 } __packed;
262 
263 struct ata_ahci_cmd_list {
264     u_int16_t			cmd_flags;
265     u_int16_t			prd_length;	/* PRD entries */
266     u_int32_t			bytecount;
267     u_int64_t			cmd_table_phys;	/* 128byte aligned */
268 } __packed;
269 
270 /* DMA register defines */
271 #define ATA_DMA_ENTRIES                 256
272 #define ATA_DMA_EOT                     0x80000000
273 
274 #define ATA_BMCMD_PORT                  17
275 #define         ATA_BMCMD_START_STOP    0x01
276 #define         ATA_BMCMD_WRITE_READ    0x08
277 
278 #define ATA_BMDEVSPEC_0                 18
279 #define ATA_BMSTAT_PORT                 19
280 #define         ATA_BMSTAT_ACTIVE       0x01
281 #define         ATA_BMSTAT_ERROR        0x02
282 #define         ATA_BMSTAT_INTERRUPT    0x04
283 #define         ATA_BMSTAT_MASK         0x07
284 #define         ATA_BMSTAT_DMA_MASTER   0x20
285 #define         ATA_BMSTAT_DMA_SLAVE    0x40
286 #define         ATA_BMSTAT_DMA_SIMPLEX  0x80
287 
288 #define ATA_BMDEVSPEC_1                 20
289 #define ATA_BMDTP_PORT                  21
290 
291 #define ATA_IDX_ADDR                    22
292 #define ATA_IDX_DATA                    23
293 #define ATA_MAX_RES                     24
294 
295 /* misc defines */
296 #define ATA_PRIMARY                     0x1f0
297 #define ATA_SECONDARY                   0x170
298 #define ATA_PC98_BANK                   0x432
299 #define ATA_IOSIZE                      0x08
300 #define ATA_PC98_IOSIZE                 0x10
301 #define ATA_CTLIOSIZE                   0x01
302 #define ATA_BMIOSIZE                    0x08
303 #define ATA_PC98_BANKIOSIZE             0x01
304 #define ATA_IOADDR_RID                  0
305 #define ATA_CTLADDR_RID                 1
306 #define ATA_BMADDR_RID                  0x20
307 #define ATA_PC98_CTLADDR_RID            8
308 #define ATA_PC98_BANKADDR_RID           9
309 #define ATA_IRQ_RID                     0
310 #define ATA_DEV(device)                 ((device == ATA_MASTER) ? 0 : 1)
311 #define ATA_CFA_MAGIC1                  0x844A
312 #define ATA_CFA_MAGIC2                  0x848A
313 #define ATA_CFA_MAGIC3                  0x8400
314 #define ATAPI_MAGIC_LSB                 0x14
315 #define ATAPI_MAGIC_MSB                 0xeb
316 #define ATAPI_P_READ                    (ATA_S_DRQ | ATA_I_IN)
317 #define ATAPI_P_WRITE                   (ATA_S_DRQ)
318 #define ATAPI_P_CMDOUT                  (ATA_S_DRQ | ATA_I_CMD)
319 #define ATAPI_P_DONEDRQ                 (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
320 #define ATAPI_P_DONE                    (ATA_I_CMD | ATA_I_IN)
321 #define ATAPI_P_ABORT                   0
322 #define ATA_INTR_FLAGS                  (INTR_NOPOLL)
323 #define ATA_OP_CONTINUES                0
324 #define ATA_OP_FINISHED                 1
325 #define ATA_MAX_28BIT_LBA               268435455UL
326 
327 /* structure used for composite atomic operations */
328 #define MAX_COMPOSITES          32              /* u_int32_t bits */
329 struct ata_composite {
330     struct spinlock     lock;                   /* control lock */
331     u_int32_t           rd_needed;              /* needed read subdisks */
332     u_int32_t           rd_done;                /* done read subdisks */
333     u_int32_t           wr_needed;              /* needed write subdisks */
334     u_int32_t           wr_depend;              /* write depends on subdisks */
335     u_int32_t           wr_done;                /* done write subdisks */
336     struct ata_request  *request[MAX_COMPOSITES];
337     u_int32_t           residual;               /* bytes still to transfer */
338     caddr_t             data_1;
339     caddr_t             data_2;
340 };
341 
342 /* structure used to queue an ATA/ATAPI request */
343 struct ata_request {
344     device_t                    dev;            /* device handle */
345     device_t                    parent;         /* channel handle */
346     union {
347 	struct {
348 	    u_int8_t            command;        /* command reg */
349 	    u_int16_t           feature;        /* feature reg */
350 	    u_int16_t           count;          /* count reg */
351 	    u_int64_t           lba;            /* lba reg */
352 	} ata;
353 	struct {
354 	    u_int8_t            ccb[16];        /* ATAPI command block */
355 	    struct atapi_sense  sense;          /* ATAPI request sense data */
356 	    u_int8_t            saved_cmd;      /* ATAPI saved command */
357 	} atapi;
358     } u;
359     u_int32_t                   bytecount;      /* bytes to transfer */
360     u_int32_t                   transfersize;   /* bytes pr transfer */
361     caddr_t                     data;           /* pointer to data buf */
362     int                         flags;
363 #define         ATA_R_CONTROL           0x00000001
364 #define         ATA_R_READ              0x00000002
365 #define         ATA_R_WRITE             0x00000004
366 #define         ATA_R_ATAPI             0x00000008
367 #define         ATA_R_DMA               0x00000010
368 #define         ATA_R_QUIET             0x00000020
369 #define         ATA_R_TIMEOUT           0x00000040
370 #define		ATA_R_COMPLETED		0x00000080
371 
372 #define         ATA_R_ORDERED           0x00000100
373 #define         ATA_R_AT_HEAD           0x00000200
374 #define         ATA_R_REQUEUE           0x00000400
375 #define         ATA_R_THREAD            0x00000800
376 #define         ATA_R_DIRECT            0x00001000
377 
378 #define		ATA_R_HWCMDQUEUED	0x00010000
379 
380 #define         ATA_R_DEBUG             0x10000000
381 #define         ATA_R_DANGER1           0x20000000
382 #define         ATA_R_DANGER2           0x40000000
383 
384     u_int8_t                    status;         /* ATA status */
385     u_int8_t                    error;          /* ATA error */
386     u_int8_t                    dmastat;        /* DMA status */
387     u_int32_t                   donecount;      /* bytes transferred */
388     int                         result;         /* result error code */
389     void                        (*callback)(struct ata_request *request);
390     struct spinlock             done;           /* request done sema */
391     int                         retries;        /* retry count */
392     int                         timeout;        /* timeout for this cmd */
393     int				unused01;
394     struct callout              callout;        /* callout management */
395     struct task                 task;           /* task management */
396     struct bio                  *bio;           /* bio for this request */
397     int                         this;           /* this request ID */
398     struct ata_composite        *composite;     /* for composite atomic ops */
399     void                        *driver;        /* driver specific */
400     TAILQ_ENTRY(ata_request)    chain;          /* list management */
401 };
402 
403 /* define this for debugging request processing */
404 #if 0
405 #define ATA_DEBUG_RQ(request, string) \
406     { \
407     if (request->flags & ATA_R_DEBUG) \
408 	device_printf(request->dev, "req=%p %s " string "\n", \
409 		      request, ata_cmd2str(request)); \
410     }
411 #else
412 #define ATA_DEBUG_RQ(request, string)
413 #endif
414 
415 
416 /* structure describing an ATA/ATAPI device */
417 struct ata_device {
418     device_t                    dev;            /* device handle */
419     int                         unit;           /* physical unit */
420 #define         ATA_MASTER              0x00
421 #define         ATA_SLAVE               0x10
422 
423     struct ata_params           param;          /* ata param structure */
424     int                         mode;           /* current transfermode */
425     u_int32_t                   max_iosize;     /* max IO size */
426     int                         flags;
427 #define         ATA_D_USE_CHS           0x0001
428 #define         ATA_D_MEDIA_CHANGED     0x0002
429 #define         ATA_D_ENC_PRESENT       0x0004
430 #define         ATA_D_48BIT_ACTIVE      0x0008
431     int				opencount;	/* when tracking needed */
432 };
433 
434 /* structure for holding DMA Physical Region Descriptors (PRD) entries */
435 struct ata_dma_prdentry {
436     u_int32_t addr;
437     u_int32_t count;
438 };
439 
440 /* structure used by the setprd function */
441 struct ata_dmasetprd_args {
442     void *dmatab;
443     int nsegs;
444     int error;
445 };
446 
447 /* structure holding DMA related information */
448 struct ata_dma {
449     bus_dma_tag_t               dmatag;         /* parent DMA tag */
450     bus_dma_tag_t               sg_tag;         /* SG list DMA tag */
451     bus_dmamap_t                sg_map;         /* SG list DMA map */
452     void                        *sg;            /* DMA transfer table */
453     bus_addr_t                  sg_bus;         /* bus address of dmatab */
454     bus_dma_tag_t               data_tag;       /* data DMA tag */
455     bus_dmamap_t                data_map;       /* data DMA map */
456     bus_dma_tag_t               work_tag;       /* workspace DMA tag */
457     bus_dmamap_t                work_map;       /* workspace DMA map */
458     u_int8_t                    *work;          /* workspace */
459     bus_addr_t                  work_bus;       /* bus address of dmatab */
460 
461     u_int32_t                   alignment;      /* DMA SG list alignment */
462     u_int32_t                   boundary;       /* DMA SG list boundary */
463     u_int32_t                   segsize;        /* DMA SG list segment size */
464     u_int32_t                   max_iosize;     /* DMA data max IO size */
465     u_int32_t                   cur_iosize;     /* DMA data current IO size */
466     u_int64_t			max_address;	/* highest DMA'able address */
467     int                         flags;
468 #define ATA_DMA_READ                    0x01    /* transaction is a read */
469 #define ATA_DMA_LOADED                  0x02    /* DMA tables etc loaded */
470 #define ATA_DMA_ACTIVE                  0x04    /* DMA transfer in progress */
471 
472     void (*alloc)(device_t dev);
473     void (*free)(device_t dev);
474     void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
475     int (*load)(device_t dev, caddr_t data, int32_t count, int dir, void *addr, int *nsegs);
476     int (*unload)(device_t dev);
477     int (*start)(device_t dev);
478     int (*stop)(device_t dev);
479     void (*reset)(device_t dev);
480 };
481 
482 /* structure holding lowlevel functions */
483 struct ata_lowlevel {
484     int (*status)(device_t dev);
485     int (*begin_transaction)(struct ata_request *request);
486     int (*end_transaction)(struct ata_request *request);
487     int (*command)(struct ata_request *request);
488 };
489 
490 /* structure holding resources for an ATA channel */
491 struct ata_resource {
492     struct resource             *res;
493     int                         offset;
494 };
495 
496 /* structure describing an ATA channel */
497 struct ata_channel {
498     device_t                    dev;            /* device handle */
499     int                         unit;           /* physical channel */
500     struct ata_resource         r_io[ATA_MAX_RES];/* I/O resources */
501     struct resource             *r_irq;         /* interrupt of this channel */
502     void                        *ih;            /* interrupt handle */
503     struct ata_lowlevel         hw;             /* lowlevel HW functions */
504     struct ata_dma              *dma;           /* DMA data / functions */
505     int                         flags;          /* channel flags */
506 #define         ATA_NO_SLAVE            0x01
507 #define         ATA_USE_16BIT           0x02
508 #define         ATA_ATAPI_DMA_RO        0x04
509 #define         ATA_NO_48BIT_DMA        0x08
510 #define         ATA_ALWAYS_DMASTAT      0x10
511 
512     int                         devices;        /* what is present */
513 #define         ATA_ATA_MASTER          0x01
514 #define         ATA_ATA_SLAVE           0x02
515 #define         ATA_ATAPI_MASTER        0x04
516 #define         ATA_ATAPI_SLAVE         0x08
517 #define		ATA_PORTMULTIPLIER	0x10
518 
519     struct spinlock             state_mtx;      /* state lock */
520     int                         state;          /* ATA channel state */
521 #define         ATA_IDLE                0x0000
522 #define         ATA_ACTIVE              0x0001
523 #define         ATA_STALL_QUEUE         0x0002
524 
525     struct spinlock             queue_mtx;      /* queue lock */
526     TAILQ_HEAD(, ata_request)   ata_queue;      /* head of ATA queue */
527     struct ata_request          *freezepoint;   /* freeze point for sortq */
528     struct ata_request          *running;       /* currently running request */
529     int				sortq_lost;	/* limit sort reordering */
530 };
531 
532 /* disk bay/enclosure related */
533 #define         ATA_LED_OFF             0x00
534 #define         ATA_LED_RED             0x01
535 #define         ATA_LED_GREEN           0x02
536 #define         ATA_LED_ORANGE          0x03
537 #define         ATA_LED_MASK            0x03
538 
539 /* externs */
540 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data);
541 extern struct intr_config_hook *ata_delayed_attach;
542 extern devclass_t ata_devclass;
543 extern int ata_wc;
544 
545 /* public prototypes */
546 /* ata-all.c: */
547 int ata_probe(device_t dev);
548 int ata_attach(device_t dev);
549 int ata_detach(device_t dev);
550 int ata_reinit(device_t dev);
551 int ata_suspend(device_t dev);
552 int ata_resume(device_t dev);
553 int ata_interrupt(void *data);
554 int ata_device_ioctl(device_t dev, u_long cmd, caddr_t data);
555 int ata_identify(device_t dev);
556 void ata_default_registers(device_t dev);
557 void ata_modify_if_48bit(struct ata_request *request);
558 void ata_udelay(int interval);
559 char *ata_mode2str(int mode);
560 int ata_pmode(struct ata_params *ap);
561 int ata_wmode(struct ata_params *ap);
562 int ata_umode(struct ata_params *ap);
563 int ata_limit_mode(device_t dev, int mode, int maxmode);
564 
565 /* ata-queue.c: */
566 int ata_controlcmd(device_t dev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count);
567 int ata_atapicmd(device_t dev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout);
568 void ata_queue_request(struct ata_request *request);
569 void ata_start(device_t dev);
570 void ata_finish(struct ata_request *request);
571 void ata_timeout(struct ata_request *);
572 void ata_catch_inflight(device_t dev);
573 void ata_fail_requests(device_t dev);
574 char *ata_cmd2str(struct ata_request *request);
575 
576 /* ata-lowlevel.c: */
577 void ata_generic_hw(device_t dev);
578 int ata_begin_transaction(struct ata_request *);
579 int ata_end_transaction(struct ata_request *);
580 void ata_generic_reset(device_t dev);
581 int ata_generic_command(struct ata_request *request);
582 
583 /* macros for alloc/free of struct ata_request */
584 extern struct objcache *ata_request_cache;
585 #define ata_alloc_request() objcache_get(ata_request_cache, M_WAITOK)
586 /* zero the object so objects in the cache are guaranteed to be zero'ed */
587 #define ata_free_request(request) { \
588 	if (!(request->flags & ATA_R_DANGER2)) { \
589 	    bzero(request, sizeof(struct ata_request)); \
590 	    objcache_put(ata_request_cache, request); \
591 	} \
592 }
593 /* macros for alloc/free of struct ata_composite */
594 extern struct objcache *ata_composite_cache;
595 #define ata_alloc_composite() objcache_get(ata_composite_cache, M_WAITOK)
596 /* zero the object so objects in the cache are guaranteed to be zero'ed */
597 #define ata_free_composite(composite) { \
598 	bzero(composite, sizeof(struct ata_composite)); \
599 	objcache_put(ata_composite_cache, composite); \
600 }
601 
602 MALLOC_DECLARE(M_ATA);
603 
604 /* misc newbus defines */
605 #define GRANDPARENT(dev)        device_get_parent(device_get_parent(dev))
606 
607 /* macros to hide busspace uglyness */
608 #define ATA_INB(res, offset) \
609 	bus_space_read_1(rman_get_bustag((res)), \
610 			 rman_get_bushandle((res)), (offset))
611 
612 #define ATA_INW(res, offset) \
613 	bus_space_read_2(rman_get_bustag((res)), \
614 			 rman_get_bushandle((res)), (offset))
615 #define ATA_INL(res, offset) \
616 	bus_space_read_4(rman_get_bustag((res)), \
617 			 rman_get_bushandle((res)), (offset))
618 #define ATA_INSW(res, offset, addr, count) \
619 	bus_space_read_multi_2(rman_get_bustag((res)), \
620 			       rman_get_bushandle((res)), \
621 			       (offset), (addr), (count))
622 #define ATA_INSW_STRM(res, offset, addr, count) \
623 	bus_space_read_multi_stream_2(rman_get_bustag((res)), \
624 				      rman_get_bushandle((res)), \
625 				      (offset), (addr), (count))
626 #define ATA_INSL(res, offset, addr, count) \
627 	bus_space_read_multi_4(rman_get_bustag((res)), \
628 			       rman_get_bushandle((res)), \
629 			       (offset), (addr), (count))
630 #define ATA_INSL_STRM(res, offset, addr, count) \
631 	bus_space_read_multi_stream_4(rman_get_bustag((res)), \
632 				      rman_get_bushandle((res)), \
633 				      (offset), (addr), (count))
634 #define ATA_OUTB(res, offset, value) \
635 	bus_space_write_1(rman_get_bustag((res)), \
636 			  rman_get_bushandle((res)), (offset), (value))
637 #define ATA_OUTW(res, offset, value) \
638 	bus_space_write_2(rman_get_bustag((res)), \
639 			  rman_get_bushandle((res)), (offset), (value))
640 #define ATA_OUTL(res, offset, value) \
641 	bus_space_write_4(rman_get_bustag((res)), \
642 			  rman_get_bushandle((res)), (offset), (value))
643 #define ATA_OUTSW(res, offset, addr, count) \
644 	bus_space_write_multi_2(rman_get_bustag((res)), \
645 				rman_get_bushandle((res)), \
646 				(offset), (addr), (count))
647 #define ATA_OUTSW_STRM(res, offset, addr, count) \
648 	bus_space_write_multi_stream_2(rman_get_bustag((res)), \
649 				       rman_get_bushandle((res)), \
650 				       (offset), (addr), (count))
651 #define ATA_OUTSL(res, offset, addr, count) \
652 	bus_space_write_multi_4(rman_get_bustag((res)), \
653 				rman_get_bushandle((res)), \
654 				(offset), (addr), (count))
655 #define ATA_OUTSL_STRM(res, offset, addr, count) \
656 	bus_space_write_multi_stream_4(rman_get_bustag((res)), \
657 				       rman_get_bushandle((res)), \
658 				       (offset), (addr), (count))
659 
660 #define ATA_IDX_INB(ch, idx) \
661 	ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
662 
663 #define ATA_IDX_INW(ch, idx) \
664 	ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
665 
666 #define ATA_IDX_INL(ch, idx) \
667 	ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
668 
669 #define ATA_IDX_INSW(ch, idx, addr, count) \
670 	ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
671 
672 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
673 	ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
674 
675 #define ATA_IDX_INSL(ch, idx, addr, count) \
676 	ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
677 
678 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
679 	ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
680 
681 #define ATA_IDX_OUTB(ch, idx, value) \
682 	ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
683 
684 #define ATA_IDX_OUTW(ch, idx, value) \
685 	ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
686 
687 #define ATA_IDX_OUTL(ch, idx, value) \
688 	ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
689 
690 #define ATA_IDX_OUTSW(ch, idx, addr, count) \
691 	ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
692 
693 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
694 	ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
695 
696 #define ATA_IDX_OUTSL(ch, idx, addr, count) \
697 	ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
698 
699 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
700 	ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
701 
702 /* Dragonfly: Default request timeout increased from 5 to 10 */
703 #define ATA_DEFAULT_TIMEOUT	10
704 
705