1 /*- 2 * Copyright (c) 1998 - 2006 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $ 27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.12 2008/01/01 12:16:40 swildner Exp $ 28 */ 29 30 #include "opt_ata.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/bus_dma.h> 35 #include <sys/bus_resource.h> 36 #include <sys/callout.h> 37 #include <sys/endian.h> 38 #include <sys/libkern.h> 39 #include <sys/lock.h> /* for {get,rel}_mplock() */ 40 #include <sys/malloc.h> 41 #include <sys/nata.h> 42 #include <sys/queue.h> 43 #include <sys/rman.h> 44 #include <sys/spinlock.h> 45 #include <sys/spinlock2.h> 46 #include <sys/systm.h> 47 #include <sys/taskqueue.h> 48 49 #include <machine/bus_dma.h> 50 51 #include <bus/pci/pcireg.h> 52 #include <bus/pci/pcivar.h> 53 54 #include "ata-all.h" 55 #include "ata-pci.h" 56 #include "ata_if.h" 57 58 /* local prototypes */ 59 /* ata-chipset.c */ 60 static int ata_generic_chipinit(device_t dev); 61 static void ata_generic_intr(void *data); 62 static void ata_generic_setmode(device_t dev, int mode); 63 static void ata_sata_phy_check_events(device_t dev); 64 static void ata_sata_phy_event(void *context, int dummy); 65 static int ata_sata_phy_reset(device_t dev); 66 static int ata_sata_connect(struct ata_channel *ch); 67 static void ata_sata_setmode(device_t dev, int mode); 68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 69 static int ata_ahci_chipinit(device_t dev); 70 static int ata_ahci_allocate(device_t dev); 71 static int ata_ahci_status(device_t dev); 72 static int ata_ahci_begin_transaction(struct ata_request *request); 73 static int ata_ahci_end_transaction(struct ata_request *request); 74 static void ata_ahci_reset(device_t dev); 75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 76 static void ata_ahci_dmainit(device_t dev); 77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request); 78 static int ata_genahci_chipinit(device_t dev); 79 static int ata_acard_chipinit(device_t dev); 80 static int ata_acard_allocate(device_t dev); 81 static int ata_acard_status(device_t dev); 82 static void ata_acard_850_setmode(device_t dev, int mode); 83 static void ata_acard_86X_setmode(device_t dev, int mode); 84 static int ata_ali_chipinit(device_t dev); 85 static int ata_ali_allocate(device_t dev); 86 static int ata_ali_sata_allocate(device_t dev); 87 static void ata_ali_reset(device_t dev); 88 static void ata_ali_setmode(device_t dev, int mode); 89 static int ata_amd_chipinit(device_t dev); 90 static int ata_ati_chipinit(device_t dev); 91 static void ata_ati_setmode(device_t dev, int mode); 92 static int ata_cyrix_chipinit(device_t dev); 93 static void ata_cyrix_setmode(device_t dev, int mode); 94 static int ata_cypress_chipinit(device_t dev); 95 static void ata_cypress_setmode(device_t dev, int mode); 96 static int ata_highpoint_chipinit(device_t dev); 97 static int ata_highpoint_allocate(device_t dev); 98 static void ata_highpoint_setmode(device_t dev, int mode); 99 static int ata_highpoint_check_80pin(device_t dev, int mode); 100 static int ata_intel_chipinit(device_t dev); 101 static int ata_intel_allocate(device_t dev); 102 static void ata_intel_reset(device_t dev); 103 static void ata_intel_old_setmode(device_t dev, int mode); 104 static void ata_intel_new_setmode(device_t dev, int mode); 105 static int ata_intel_31244_allocate(device_t dev); 106 static int ata_intel_31244_status(device_t dev); 107 static int ata_intel_31244_command(struct ata_request *request); 108 static void ata_intel_31244_reset(device_t dev); 109 static int ata_ite_chipinit(device_t dev); 110 static void ata_ite_setmode(device_t dev, int mode); 111 static int ata_jmicron_chipinit(device_t dev); 112 static int ata_jmicron_allocate(device_t dev); 113 static void ata_jmicron_reset(device_t dev); 114 static void ata_jmicron_dmainit(device_t dev); 115 static void ata_jmicron_setmode(device_t dev, int mode); 116 static int ata_marvell_pata_chipinit(device_t dev); 117 static int ata_marvell_pata_allocate(device_t dev); 118 static void ata_marvell_pata_setmode(device_t dev, int mode); 119 static int ata_marvell_edma_chipinit(device_t dev); 120 static int ata_marvell_edma_allocate(device_t dev); 121 static int ata_marvell_edma_status(device_t dev); 122 static int ata_marvell_edma_begin_transaction(struct ata_request *request); 123 static int ata_marvell_edma_end_transaction(struct ata_request *request); 124 static void ata_marvell_edma_reset(device_t dev); 125 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 126 static void ata_marvell_edma_dmainit(device_t dev); 127 static int ata_national_chipinit(device_t dev); 128 static void ata_national_setmode(device_t dev, int mode); 129 static int ata_netcell_chipinit(device_t dev); 130 static int ata_netcell_allocate(device_t dev); 131 static int ata_nvidia_chipinit(device_t dev); 132 static int ata_nvidia_allocate(device_t dev); 133 static int ata_nvidia_status(device_t dev); 134 static void ata_nvidia_reset(device_t dev); 135 static int ata_promise_chipinit(device_t dev); 136 static int ata_promise_allocate(device_t dev); 137 static int ata_promise_status(device_t dev); 138 static int ata_promise_dmastart(device_t dev); 139 static int ata_promise_dmastop(device_t dev); 140 static void ata_promise_dmareset(device_t dev); 141 static void ata_promise_dmainit(device_t dev); 142 static void ata_promise_setmode(device_t dev, int mode); 143 static int ata_promise_tx2_allocate(device_t dev); 144 static int ata_promise_tx2_status(device_t dev); 145 static int ata_promise_mio_allocate(device_t dev); 146 static void ata_promise_mio_intr(void *data); 147 static int ata_promise_mio_status(device_t dev); 148 static int ata_promise_mio_command(struct ata_request *request); 149 static void ata_promise_mio_reset(device_t dev); 150 static void ata_promise_mio_dmainit(device_t dev); 151 static void ata_promise_mio_setmode(device_t dev, int mode); 152 static void ata_promise_sx4_intr(void *data); 153 static int ata_promise_sx4_command(struct ata_request *request); 154 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 155 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 156 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 157 static int ata_serverworks_chipinit(device_t dev); 158 static int ata_serverworks_allocate(device_t dev); 159 static void ata_serverworks_setmode(device_t dev, int mode); 160 static int ata_sii_chipinit(device_t dev); 161 static int ata_cmd_allocate(device_t dev); 162 static int ata_cmd_status(device_t dev); 163 static void ata_cmd_setmode(device_t dev, int mode); 164 static int ata_sii_allocate(device_t dev); 165 static int ata_sii_status(device_t dev); 166 static void ata_sii_reset(device_t dev); 167 static void ata_sii_setmode(device_t dev, int mode); 168 static int ata_siiprb_allocate(device_t dev); 169 static int ata_siiprb_status(device_t dev); 170 static int ata_siiprb_begin_transaction(struct ata_request *request); 171 static int ata_siiprb_end_transaction(struct ata_request *request); 172 static void ata_siiprb_reset(device_t dev); 173 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 174 static void ata_siiprb_dmainit(device_t dev); 175 static int ata_sis_chipinit(device_t dev); 176 static int ata_sis_allocate(device_t dev); 177 static void ata_sis_reset(device_t dev); 178 static void ata_sis_setmode(device_t dev, int mode); 179 static int ata_via_chipinit(device_t dev); 180 static int ata_via_allocate(device_t dev); 181 static void ata_via_reset(device_t dev); 182 static void ata_via_setmode(device_t dev, int mode); 183 static void ata_via_southbridge_fixup(device_t dev); 184 static void ata_via_family_setmode(device_t dev, int mode); 185 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index); 186 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot); 187 static int ata_setup_interrupt(device_t dev); 188 static int ata_serialize(device_t dev, int flags); 189 static void ata_print_cable(device_t dev, u_int8_t *who); 190 static int ata_atapi(device_t dev); 191 static int ata_check_80pin(device_t dev, int mode); 192 static int ata_mode2idx(int mode); 193 194 195 /* 196 * generic ATA support functions 197 */ 198 int 199 ata_generic_ident(device_t dev) 200 { 201 struct ata_pci_controller *ctlr = device_get_softc(dev); 202 203 device_set_desc(dev, "GENERIC ATA controller"); 204 ctlr->chipinit = ata_generic_chipinit; 205 return 0; 206 } 207 208 static int 209 ata_generic_chipinit(device_t dev) 210 { 211 struct ata_pci_controller *ctlr = device_get_softc(dev); 212 213 if (ata_setup_interrupt(dev)) 214 return ENXIO; 215 ctlr->setmode = ata_generic_setmode; 216 return 0; 217 } 218 219 static void 220 ata_generic_intr(void *data) 221 { 222 struct ata_pci_controller *ctlr = data; 223 struct ata_channel *ch; 224 int unit; 225 226 for (unit = 0; unit < ctlr->channels; unit++) { 227 if ((ch = ctlr->interrupt[unit].argument)) 228 ctlr->interrupt[unit].function(ch); 229 } 230 } 231 232 static void 233 ata_generic_setmode(device_t dev, int mode) 234 { 235 struct ata_device *atadev = device_get_softc(dev); 236 237 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 238 mode = ata_check_80pin(dev, mode); 239 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 240 atadev->mode = mode; 241 } 242 243 244 /* 245 * SATA support functions 246 */ 247 static void 248 ata_sata_phy_check_events(device_t dev) 249 { 250 struct ata_channel *ch = device_get_softc(dev); 251 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR); 252 253 /* clear error bits/interrupt */ 254 ATA_IDX_OUTL(ch, ATA_SERROR, error); 255 256 /* do we have any events flagged ? */ 257 if (error) { 258 struct ata_connect_task *tp; 259 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS); 260 261 /* if we have a connection event deal with it */ 262 if ((error & ATA_SE_PHY_CHANGED) && 263 (tp = (struct ata_connect_task *) 264 kmalloc(sizeof(struct ata_connect_task), 265 M_ATA, M_INTWAIT | M_ZERO))) { 266 267 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) || 268 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) { 269 if (bootverbose) 270 device_printf(ch->dev, "CONNECT requested\n"); 271 tp->action = ATA_C_ATTACH; 272 } 273 else { 274 if (bootverbose) 275 device_printf(ch->dev, "DISCONNECT requested\n"); 276 tp->action = ATA_C_DETACH; 277 } 278 tp->dev = ch->dev; 279 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 280 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 281 } 282 } 283 } 284 285 static void 286 ata_sata_phy_event(void *context, int dummy) 287 { 288 struct ata_connect_task *tp = (struct ata_connect_task *)context; 289 struct ata_channel *ch = device_get_softc(tp->dev); 290 device_t *children; 291 int nchildren, i; 292 293 get_mplock(); 294 if (tp->action == ATA_C_ATTACH) { 295 if (bootverbose) 296 device_printf(tp->dev, "CONNECTED\n"); 297 ATA_RESET(tp->dev); 298 ata_identify(tp->dev); 299 } 300 if (tp->action == ATA_C_DETACH) { 301 if (!device_get_children(tp->dev, &children, &nchildren)) { 302 for (i = 0; i < nchildren; i++) 303 if (children[i]) 304 device_delete_child(tp->dev, children[i]); 305 kfree(children, M_TEMP); 306 } 307 spin_lock_wr(&ch->state_mtx); 308 ch->state = ATA_IDLE; 309 spin_unlock_wr(&ch->state_mtx); 310 if (bootverbose) 311 device_printf(tp->dev, "DISCONNECTED\n"); 312 } 313 rel_mplock(); 314 kfree(tp, M_ATA); 315 } 316 317 static int 318 ata_sata_phy_reset(device_t dev) 319 { 320 struct ata_channel *ch = device_get_softc(dev); 321 int loop, retry; 322 323 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 324 return ata_sata_connect(ch); 325 326 for (retry = 0; retry < 10; retry++) { 327 for (loop = 0; loop < 10; loop++) { 328 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET); 329 ata_udelay(100); 330 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & 331 ATA_SC_DET_MASK) == ATA_SC_DET_RESET) 332 break; 333 } 334 ata_udelay(5000); 335 for (loop = 0; loop < 10; loop++) { 336 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE | 337 ATA_SC_IPM_DIS_PARTIAL | 338 ATA_SC_IPM_DIS_SLUMBER); 339 ata_udelay(100); 340 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0) 341 return ata_sata_connect(ch); 342 } 343 } 344 return 0; 345 } 346 347 static int 348 ata_sata_connect(struct ata_channel *ch) 349 { 350 u_int32_t status; 351 int timeout; 352 353 /* wait up to 1 second for "connect well" */ 354 for (timeout = 0; timeout < 100 ; timeout++) { 355 status = ATA_IDX_INL(ch, ATA_SSTATUS); 356 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 || 357 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2) 358 break; 359 ata_udelay(10000); 360 } 361 if (timeout >= 100) { 362 if (bootverbose) 363 device_printf(ch->dev, "SATA connect status=%08x\n", status); 364 return 0; 365 } 366 367 if (bootverbose) 368 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10); 369 370 /* clear SATA error register */ 371 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 372 373 return 1; 374 } 375 376 static void 377 ata_sata_setmode(device_t dev, int mode) 378 { 379 struct ata_device *atadev = device_get_softc(dev); 380 381 /* 382 * if we detect that the device isn't a real SATA device we limit 383 * the transfer mode to UDMA5/ATA100. 384 * this works around the problems some devices has with the 385 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133. 386 */ 387 if (atadev->param.satacapabilities != 0x0000 && 388 atadev->param.satacapabilities != 0xffff) { 389 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 390 391 /* on some drives we need to set the transfer mode */ 392 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 393 ata_limit_mode(dev, mode, ATA_UDMA6)); 394 395 /* query SATA STATUS for the speed */ 396 if (ch->r_io[ATA_SSTATUS].res && 397 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) == 398 ATA_SS_CONWELL_GEN2)) 399 atadev->mode = ATA_SA300; 400 else 401 atadev->mode = ATA_SA150; 402 } 403 else { 404 mode = ata_limit_mode(dev, mode, ATA_UDMA5); 405 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 406 atadev->mode = mode; 407 } 408 } 409 410 static int 411 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis) 412 { 413 struct ata_device *atadev = device_get_softc(request->dev); 414 415 if (request->flags & ATA_R_ATAPI) { 416 fis[0] = 0x27; /* host to device */ 417 fis[1] = 0x80; /* command FIS (note PM goes here) */ 418 fis[2] = ATA_PACKET_CMD; 419 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) 420 fis[3] = ATA_F_DMA; 421 else { 422 fis[5] = request->transfersize; 423 fis[6] = request->transfersize >> 8; 424 } 425 fis[7] = ATA_D_LBA | atadev->unit; 426 fis[15] = ATA_A_4BIT; 427 return 20; 428 } 429 else { 430 ata_modify_if_48bit(request); 431 fis[0] = 0x27; /* host to device */ 432 fis[1] = 0x80; /* command FIS (note PM goes here) */ 433 fis[2] = request->u.ata.command; 434 fis[3] = request->u.ata.feature; 435 fis[4] = request->u.ata.lba; 436 fis[5] = request->u.ata.lba >> 8; 437 fis[6] = request->u.ata.lba >> 16; 438 fis[7] = ATA_D_LBA | atadev->unit; 439 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 440 fis[7] |= (request->u.ata.lba >> 24 & 0x0f); 441 fis[8] = request->u.ata.lba >> 24; 442 fis[9] = request->u.ata.lba >> 32; 443 fis[10] = request->u.ata.lba >> 40; 444 fis[11] = request->u.ata.feature >> 8; 445 fis[12] = request->u.ata.count; 446 fis[13] = request->u.ata.count >> 8; 447 fis[15] = ATA_A_4BIT; 448 return 20; 449 } 450 return 0; 451 } 452 453 /* 454 * AHCI v1.x compliant SATA chipset support functions 455 */ 456 static int 457 ata_ahci_chipinit(device_t dev) 458 { 459 struct ata_pci_controller *ctlr = device_get_softc(dev); 460 u_int32_t version; 461 int unit; 462 463 /* reset AHCI controller */ 464 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 465 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR); 466 DELAY(1000000); 467 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) { 468 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 469 device_printf(dev, "AHCI controller reset failure\n"); 470 return ENXIO; 471 } 472 473 /* enable AHCI mode */ 474 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 475 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE); 476 477 /* get the number of HW channels */ 478 ctlr->channels = 479 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)), 480 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 481 482 /* disable interrupt sources and clear interrupts */ 483 for (unit = 0; unit < ctlr->channels; unit++) { 484 int offset = unit << 7; 485 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 486 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1); 487 } 488 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 489 490 /* enable AHCI interrupts */ 491 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 492 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 493 494 ctlr->reset = ata_ahci_reset; 495 ctlr->dmainit = ata_ahci_dmainit; 496 ctlr->allocate = ata_ahci_allocate; 497 ctlr->setmode = ata_sata_setmode; 498 499 /* enable PCI interrupt */ 500 pci_write_config(dev, PCIR_COMMAND, 501 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 502 503 /* announce we support the HW */ 504 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 505 device_printf(dev, 506 "AHCI Version %x%x.%x%x controller with %d ports detected\n", 507 (version >> 24) & 0xff, (version >> 16) & 0xff, 508 (version >> 8) & 0xff, version & 0xff, 509 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1); 510 return 0; 511 } 512 513 static int 514 ata_ahci_allocate(device_t dev) 515 { 516 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 517 struct ata_channel *ch = device_get_softc(dev); 518 u_int64_t work; 519 int offset = ch->unit << 7; 520 521 /* set the SATA resources */ 522 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 523 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 524 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 525 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 526 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 527 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 528 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 529 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 530 531 ch->hw.status = ata_ahci_status; 532 ch->hw.begin_transaction = ata_ahci_begin_transaction; 533 ch->hw.end_transaction = ata_ahci_end_transaction; 534 ch->hw.command = NULL; /* not used here */ 535 536 /* setup work areas */ 537 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET; 538 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 539 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 540 541 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET; 542 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 543 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 544 545 /* enable wanted port interrupts */ 546 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 547 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 548 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 549 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP | 550 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS | 551 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 552 553 /* start operations on this channel */ 554 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 555 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 556 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 557 return 0; 558 } 559 560 static int 561 ata_ahci_status(device_t dev) 562 { 563 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 564 struct ata_channel *ch = device_get_softc(dev); 565 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 566 int offset = ch->unit << 7; 567 int tag = 0; 568 569 if (action & (1 << ch->unit)) { 570 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 571 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 572 573 /* clear interrupt(s) */ 574 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit)); 575 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 576 577 /* do we have any PHY events ? */ 578 /* XXX SOS check istatus phy bits */ 579 ata_sata_phy_check_events(dev); 580 581 /* do we have a potentially hanging engine to take care of? */ 582 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) { 583 584 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 585 int timeout = 0; 586 587 /* kill off all activity on this channel */ 588 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 589 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 590 591 /* XXX SOS this is not entirely wrong */ 592 do { 593 DELAY(1000); 594 if (timeout++ > 500) { 595 device_printf(dev, "stopping AHCI engine failed\n"); 596 break; 597 } 598 } while (ATA_INL(ctlr->r_res2, 599 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 600 601 /* start operations on this channel */ 602 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 603 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 604 605 return 1; 606 } 607 else 608 return (!(cstatus & (1 << tag))); 609 } 610 return 0; 611 } 612 613 /* must be called with ATA channel locked and state_mtx held */ 614 static int 615 ata_ahci_begin_transaction(struct ata_request *request) 616 { 617 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 618 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 619 struct ata_ahci_cmd_tab *ctp; 620 struct ata_ahci_cmd_list *clp; 621 int offset = ch->unit << 7; 622 int tag = 0, entries = 0; 623 int fis_size; 624 625 /* get a piece of the workspace for this request */ 626 ctp = (struct ata_ahci_cmd_tab *) 627 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag)); 628 629 /* setup the FIS for this request */ 630 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 631 device_printf(request->dev, "setting up SATA FIS failed\n"); 632 request->result = EIO; 633 return ATA_OP_FINISHED; 634 } 635 636 /* if request moves data setup and load SG list */ 637 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 638 if (ch->dma->load(ch->dev, request->data, request->bytecount, 639 request->flags & ATA_R_READ, 640 ctp->prd_tab, &entries)) { 641 device_printf(request->dev, "setting up DMA failed\n"); 642 request->result = EIO; 643 return ATA_OP_FINISHED; 644 } 645 } 646 647 /* setup the command list entry */ 648 clp = (struct ata_ahci_cmd_list *) 649 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 650 651 clp->prd_length = entries; 652 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) | 653 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) | 654 (fis_size / sizeof(u_int32_t)); 655 clp->bytecount = 0; 656 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET + 657 (ATA_AHCI_CT_SIZE * tag)); 658 659 /* clear eventual ACTIVE bit */ 660 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag)); 661 662 /* set command type bit */ 663 if (request->flags & ATA_R_ATAPI) 664 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 665 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 666 ATA_AHCI_P_CMD_ATAPI); 667 else 668 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 669 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 670 ~ATA_AHCI_P_CMD_ATAPI); 671 672 /* issue command to controller */ 673 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag)); 674 675 if (!(request->flags & ATA_R_ATAPI)) { 676 /* device reset doesn't interrupt */ 677 if (request->u.ata.command == ATA_DEVICE_RESET) { 678 u_int32_t tf_data; 679 int timeout = 1000000; 680 681 do { 682 DELAY(10); 683 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7)); 684 } while ((tf_data & ATA_S_BUSY) && timeout--); 685 if (bootverbose) 686 device_printf(ch->dev, "device_reset timeout=%dus\n", 687 (1000000-timeout)*10); 688 request->status = tf_data; 689 if (request->status & ATA_S_ERROR) 690 request->error = tf_data >> 8; 691 return ATA_OP_FINISHED; 692 } 693 } 694 695 /* start the timeout */ 696 callout_reset(&request->callout, request->timeout * hz, 697 (timeout_t*)ata_timeout, request); 698 return ATA_OP_CONTINUES; 699 } 700 701 /* must be called with ATA channel locked and state_mtx held */ 702 static int 703 ata_ahci_end_transaction(struct ata_request *request) 704 { 705 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 706 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 707 struct ata_ahci_cmd_list *clp; 708 u_int32_t tf_data; 709 int offset = ch->unit << 7; 710 int tag = 0; 711 712 /* kill the timeout */ 713 callout_stop(&request->callout); 714 715 /* get status */ 716 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 717 request->status = tf_data; 718 719 /* if error status get details */ 720 if (request->status & ATA_S_ERROR) 721 request->error = tf_data >> 8; 722 723 /* record how much data we actually moved */ 724 clp = (struct ata_ahci_cmd_list *) 725 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag)); 726 request->donecount = clp->bytecount; 727 728 /* release SG list etc */ 729 ch->dma->unload(ch->dev); 730 731 return ATA_OP_FINISHED; 732 } 733 734 static void 735 ata_ahci_reset(device_t dev) 736 { 737 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 738 struct ata_channel *ch = device_get_softc(dev); 739 u_int32_t cmd, signature; 740 int offset = ch->unit << 7; 741 int timeout; 742 743 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) { 744 device_printf(dev, "port not implemented\n"); 745 return; 746 } 747 ch->devices = 0; 748 749 /* kill off all activity on this channel */ 750 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 751 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 752 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 753 754 /* XXX SOS this is not entirely wrong */ 755 timeout = 0; 756 do { 757 DELAY(1000); 758 if (timeout++ > 500) { 759 device_printf(dev, "stopping AHCI engine failed\n"); 760 break; 761 } 762 } 763 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 764 765 /* issue Command List Override if supported */ 766 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) { 767 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 768 cmd |= ATA_AHCI_P_CMD_CLO; 769 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 770 timeout = 0; 771 do { 772 DELAY(1000); 773 if (timeout++ > 500) { 774 device_printf(dev, "executing CLO failed\n"); 775 break; 776 } 777 } 778 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 779 } 780 781 /* reset PHY and decide what is present */ 782 if (ata_sata_phy_reset(dev)) { 783 784 /* clear any interrupts pending on this channel */ 785 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 786 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 787 788 /* clear SATA error register */ 789 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 790 791 /* start operations on this channel */ 792 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 793 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE | 794 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST)); 795 796 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 797 switch (signature) { 798 case 0x00000101: 799 ch->devices = ATA_ATA_MASTER; 800 break; 801 case 0x96690101: 802 ch->devices = ATA_PORTMULTIPLIER; 803 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 804 ch->devices = 0; 805 break; 806 case 0xeb140101: 807 ch->devices = ATA_ATAPI_MASTER; 808 break; 809 default: /* SOS XXX */ 810 if (bootverbose) 811 device_printf(ch->dev, "No signature, assuming disk device\n"); 812 ch->devices = ATA_ATA_MASTER; 813 } 814 } 815 if (bootverbose) 816 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices, 817 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); 818 } 819 820 static void 821 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 822 { 823 struct ata_dmasetprd_args *args = xsc; 824 struct ata_ahci_dma_prd *prd = args->dmatab; 825 int i; 826 827 if (!(args->error = error)) { 828 for (i = 0; i < nsegs; i++) { 829 prd[i].dba = htole64(segs[i].ds_addr); 830 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 831 } 832 } 833 args->nsegs = nsegs; 834 } 835 836 static void 837 ata_ahci_dmainit(device_t dev) 838 { 839 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 840 struct ata_channel *ch = device_get_softc(dev); 841 842 ata_dmainit(dev); 843 if (ch->dma) { 844 /* note start and stop are not used here */ 845 ch->dma->setprd = ata_ahci_dmasetprd; 846 ch->dma->max_iosize = 8192 * DEV_BSIZE; 847 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 848 ch->dma->max_address = BUS_SPACE_MAXADDR; 849 } 850 } 851 852 static int 853 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 854 { 855 bzero(ctp->cfis, 64); 856 if (request->flags & ATA_R_ATAPI) { 857 bzero(ctp->acmd, 32); 858 bcopy(request->u.atapi.ccb, ctp->acmd, 16); 859 } 860 return ata_request2fis_h2d(request, &ctp->cfis[0]); 861 } 862 863 /* 864 * Generic AHCI part support functions. 865 */ 866 int 867 ata_genahci_ident(device_t dev) 868 { 869 struct ata_pci_controller *ctlr = device_get_softc(dev); 870 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"}; 871 char buffer[64]; 872 873 if(!(pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) { 874 return ENXIO; 875 } 876 877 ksprintf(buffer, "GENERIC %s %s controller", id.text, ata_mode2str(id.max_dma)); 878 device_set_desc_copy(dev, buffer); 879 ctlr->chip = &id; 880 ctlr->chipinit = ata_genahci_chipinit; 881 return 0; 882 } 883 884 static int 885 ata_genahci_chipinit(device_t dev) 886 { 887 struct ata_pci_controller *ctlr = device_get_softc(dev); 888 889 if (ata_setup_interrupt(dev)) 890 return ENXIO; 891 892 /* Check if the chip has PCI BAR 5 as memory resource. */ 893 ctlr->r_type2 = SYS_RES_MEMORY; 894 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */ 895 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 896 &ctlr->r_rid2, RF_ACTIVE))) { 897 return ata_ahci_chipinit(dev); 898 } else 899 return ENXIO; 900 } 901 902 /* 903 * Acard chipset support functions 904 */ 905 int 906 ata_acard_ident(device_t dev) 907 { 908 struct ata_pci_controller *ctlr = device_get_softc(dev); 909 struct ata_chip_id *idx; 910 static struct ata_chip_id ids[] = 911 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" }, 912 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" }, 913 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" }, 914 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" }, 915 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" }, 916 { 0, 0, 0, 0, 0, 0}}; 917 char buffer[64]; 918 919 if (!(idx = ata_match_chip(dev, ids))) 920 return ENXIO; 921 922 ksprintf(buffer, "Acard %s %s controller", 923 idx->text, ata_mode2str(idx->max_dma)); 924 device_set_desc_copy(dev, buffer); 925 ctlr->chip = idx; 926 ctlr->chipinit = ata_acard_chipinit; 927 return 0; 928 } 929 930 static int 931 ata_acard_chipinit(device_t dev) 932 { 933 struct ata_pci_controller *ctlr = device_get_softc(dev); 934 935 if (ata_setup_interrupt(dev)) 936 return ENXIO; 937 938 ctlr->allocate = ata_acard_allocate; 939 if (ctlr->chip->cfg1 == ATPOLD) { 940 ctlr->setmode = ata_acard_850_setmode; 941 ctlr->locking = ata_serialize; 942 } 943 else 944 ctlr->setmode = ata_acard_86X_setmode; 945 return 0; 946 } 947 948 static int 949 ata_acard_allocate(device_t dev) 950 { 951 struct ata_channel *ch = device_get_softc(dev); 952 953 /* setup the usual register normal pci style */ 954 if (ata_pci_allocate(dev)) 955 return ENXIO; 956 957 ch->hw.status = ata_acard_status; 958 return 0; 959 } 960 961 static int 962 ata_acard_status(device_t dev) 963 { 964 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 965 struct ata_channel *ch = device_get_softc(dev); 966 967 if (ctlr->chip->cfg1 == ATPOLD && 968 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit) 969 return 0; 970 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) { 971 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 972 973 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != 974 ATA_BMSTAT_INTERRUPT) 975 return 0; 976 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR); 977 DELAY(1); 978 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 979 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 980 DELAY(1); 981 } 982 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 983 DELAY(100); 984 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 985 return 0; 986 } 987 return 1; 988 } 989 990 static void 991 ata_acard_850_setmode(device_t dev, int mode) 992 { 993 device_t gparent = GRANDPARENT(dev); 994 struct ata_pci_controller *ctlr = device_get_softc(gparent); 995 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 996 struct ata_device *atadev = device_get_softc(dev); 997 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 998 int error; 999 1000 mode = ata_limit_mode(dev, mode, 1001 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1002 1003 /* XXX SOS missing WDMA0+1 + PIO modes */ 1004 if (mode >= ATA_WDMA2) { 1005 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1006 if (bootverbose) 1007 device_printf(dev, "%ssetting %s on %s chip\n", 1008 (error) ? "FAILURE " : "", 1009 ata_mode2str(mode), ctlr->chip->text); 1010 if (!error) { 1011 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1); 1012 1013 reg54 &= ~(0x03 << (devno << 1)); 1014 if (mode >= ATA_UDMA0) 1015 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); 1016 pci_write_config(gparent, 0x54, reg54, 1); 1017 pci_write_config(gparent, 0x4a, 0xa6, 1); 1018 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2); 1019 atadev->mode = mode; 1020 return; 1021 } 1022 } 1023 /* we could set PIO mode timings, but we assume the BIOS did that */ 1024 } 1025 1026 static void 1027 ata_acard_86X_setmode(device_t dev, int mode) 1028 { 1029 device_t gparent = GRANDPARENT(dev); 1030 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1031 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1032 struct ata_device *atadev = device_get_softc(dev); 1033 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1034 int error; 1035 1036 1037 mode = ata_limit_mode(dev, mode, 1038 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma); 1039 1040 mode = ata_check_80pin(dev, mode); 1041 1042 /* XXX SOS missing WDMA0+1 + PIO modes */ 1043 if (mode >= ATA_WDMA2) { 1044 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1045 if (bootverbose) 1046 device_printf(dev, "%ssetting %s on %s chip\n", 1047 (error) ? "FAILURE " : "", 1048 ata_mode2str(mode), ctlr->chip->text); 1049 if (!error) { 1050 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2); 1051 1052 reg44 &= ~(0x000f << (devno << 2)); 1053 if (mode >= ATA_UDMA0) 1054 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); 1055 pci_write_config(gparent, 0x44, reg44, 2); 1056 pci_write_config(gparent, 0x4a, 0xa6, 1); 1057 pci_write_config(gparent, 0x40 + devno, 0x31, 1); 1058 atadev->mode = mode; 1059 return; 1060 } 1061 } 1062 /* we could set PIO mode timings, but we assume the BIOS did that */ 1063 } 1064 1065 1066 /* 1067 * Acer Labs Inc (ALI) chipset support functions 1068 */ 1069 int 1070 ata_ali_ident(device_t dev) 1071 { 1072 struct ata_pci_controller *ctlr = device_get_softc(dev); 1073 struct ata_chip_id *idx; 1074 static struct ata_chip_id ids[] = 1075 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" }, 1076 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" }, 1077 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" }, 1078 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" }, 1079 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" }, 1080 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" }, 1081 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" }, 1082 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" }, 1083 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" }, 1084 { 0, 0, 0, 0, 0, 0}}; 1085 char buffer[64]; 1086 1087 if (!(idx = ata_match_chip(dev, ids))) 1088 return ENXIO; 1089 1090 ksprintf(buffer, "AcerLabs %s %s controller", 1091 idx->text, ata_mode2str(idx->max_dma)); 1092 device_set_desc_copy(dev, buffer); 1093 ctlr->chip = idx; 1094 ctlr->chipinit = ata_ali_chipinit; 1095 return 0; 1096 } 1097 1098 static int 1099 ata_ali_chipinit(device_t dev) 1100 { 1101 struct ata_pci_controller *ctlr = device_get_softc(dev); 1102 1103 if (ata_setup_interrupt(dev)) 1104 return ENXIO; 1105 1106 switch (ctlr->chip->cfg2) { 1107 case ALISATA: 1108 ctlr->channels = ctlr->chip->cfg1; 1109 ctlr->allocate = ata_ali_sata_allocate; 1110 ctlr->setmode = ata_sata_setmode; 1111 1112 /* if we have a memory resource we can likely do AHCI */ 1113 ctlr->r_type2 = SYS_RES_MEMORY; 1114 ctlr->r_rid2 = PCIR_BAR(5); 1115 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1116 &ctlr->r_rid2, RF_ACTIVE))) 1117 return ata_ahci_chipinit(dev); 1118 1119 /* enable PCI interrupt */ 1120 pci_write_config(dev, PCIR_COMMAND, 1121 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1122 break; 1123 1124 case ALINEW: 1125 /* use device interrupt as byte count end */ 1126 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1); 1127 1128 /* enable cable detection and UDMA support on newer chips */ 1129 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); 1130 1131 /* enable ATAPI UDMA mode */ 1132 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1); 1133 1134 /* only chips with revision > 0xc4 can do 48bit DMA */ 1135 if (ctlr->chip->chiprev <= 0xc4) 1136 device_printf(dev, 1137 "using PIO transfers above 137GB as workaround for " 1138 "48bit DMA access bug, expect reduced performance\n"); 1139 ctlr->allocate = ata_ali_allocate; 1140 ctlr->reset = ata_ali_reset; 1141 ctlr->setmode = ata_ali_setmode; 1142 break; 1143 1144 case ALIOLD: 1145 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ 1146 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); 1147 ctlr->setmode = ata_ali_setmode; 1148 break; 1149 } 1150 return 0; 1151 } 1152 1153 static int 1154 ata_ali_allocate(device_t dev) 1155 { 1156 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1157 struct ata_channel *ch = device_get_softc(dev); 1158 1159 /* setup the usual register normal pci style */ 1160 if (ata_pci_allocate(dev)) 1161 return ENXIO; 1162 1163 /* older chips can't do 48bit DMA transfers */ 1164 if (ctlr->chip->chiprev <= 0xc4) 1165 ch->flags |= ATA_NO_48BIT_DMA; 1166 1167 return 0; 1168 } 1169 1170 static int 1171 ata_ali_sata_allocate(device_t dev) 1172 { 1173 device_t parent = device_get_parent(dev); 1174 struct ata_pci_controller *ctlr = device_get_softc(parent); 1175 struct ata_channel *ch = device_get_softc(dev); 1176 struct resource *io = NULL, *ctlio = NULL; 1177 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 1178 int i, rid; 1179 1180 rid = PCIR_BAR(0) + (unit01 ? 8 : 0); 1181 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1182 if (!io) 1183 return ENXIO; 1184 1185 rid = PCIR_BAR(1) + (unit01 ? 8 : 0); 1186 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1187 if (!ctlio) { 1188 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); 1189 return ENXIO; 1190 } 1191 1192 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 1193 ch->r_io[i].res = io; 1194 ch->r_io[i].offset = i + (unit10 ? 8 : 0); 1195 } 1196 ch->r_io[ATA_CONTROL].res = ctlio; 1197 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0); 1198 ch->r_io[ATA_IDX_ADDR].res = io; 1199 ata_default_registers(dev); 1200 if (ctlr->r_res1) { 1201 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 1202 ch->r_io[i].res = ctlr->r_res1; 1203 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 1204 } 1205 } 1206 ch->flags |= ATA_NO_SLAVE; 1207 1208 /* XXX SOS PHY handling awkward in ALI chip not supported yet */ 1209 ata_pci_hw(dev); 1210 return 0; 1211 } 1212 1213 static void 1214 ata_ali_reset(device_t dev) 1215 { 1216 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1217 struct ata_channel *ch = device_get_softc(dev); 1218 device_t *children; 1219 int nchildren, i; 1220 1221 ata_generic_reset(dev); 1222 1223 /* 1224 * workaround for datacorruption bug found on at least SUN Blade-100 1225 * find the ISA function on the southbridge and disable then enable 1226 * the ATA channel tristate buffer 1227 */ 1228 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { 1229 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) { 1230 for (i = 0; i < nchildren; i++) { 1231 if (pci_get_devid(children[i]) == ATA_ALI_1533) { 1232 pci_write_config(children[i], 0x58, 1233 pci_read_config(children[i], 0x58, 1) & 1234 ~(0x04 << ch->unit), 1); 1235 pci_write_config(children[i], 0x58, 1236 pci_read_config(children[i], 0x58, 1) | 1237 (0x04 << ch->unit), 1); 1238 break; 1239 } 1240 } 1241 kfree(children, M_TEMP); 1242 } 1243 } 1244 } 1245 1246 static void 1247 ata_ali_setmode(device_t dev, int mode) 1248 { 1249 device_t gparent = GRANDPARENT(dev); 1250 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1251 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1252 struct ata_device *atadev = device_get_softc(dev); 1253 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1254 int error; 1255 1256 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1257 1258 if (ctlr->chip->cfg2 & ALINEW) { 1259 if (mode > ATA_UDMA2 && 1260 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) { 1261 ata_print_cable(dev, "controller"); 1262 mode = ATA_UDMA2; 1263 } 1264 } 1265 else 1266 mode = ata_check_80pin(dev, mode); 1267 1268 if (ctlr->chip->cfg2 & ALIOLD) { 1269 /* doesn't support ATAPI DMA on write */ 1270 ch->flags |= ATA_ATAPI_DMA_RO; 1271 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 1272 /* doesn't support ATAPI DMA on two ATAPI devices */ 1273 device_printf(dev, "two atapi devices on this channel, no DMA\n"); 1274 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1275 } 1276 } 1277 1278 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1279 1280 if (bootverbose) 1281 device_printf(dev, "%ssetting %s on %s chip\n", 1282 (error) ? "FAILURE " : "", 1283 ata_mode2str(mode), ctlr->chip->text); 1284 if (!error) { 1285 if (mode >= ATA_UDMA0) { 1286 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d}; 1287 u_int32_t word54 = pci_read_config(gparent, 0x54, 4); 1288 1289 word54 &= ~(0x000f000f << (devno << 2)); 1290 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); 1291 pci_write_config(gparent, 0x54, word54, 4); 1292 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1293 0x00310001, 4); 1294 } 1295 else { 1296 u_int32_t piotimings[] = 1297 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 1298 0x00310001, 0x00440001, 0x00330001, 0x00310001}; 1299 1300 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) & 1301 ~(0x0008000f << (devno << 2)), 4); 1302 pci_write_config(gparent, 0x58 + (ch->unit << 2), 1303 piotimings[ata_mode2idx(mode)], 4); 1304 } 1305 atadev->mode = mode; 1306 } 1307 } 1308 1309 1310 /* 1311 * American Micro Devices (AMD) chipset support functions 1312 */ 1313 int 1314 ata_amd_ident(device_t dev) 1315 { 1316 struct ata_pci_controller *ctlr = device_get_softc(dev); 1317 struct ata_chip_id *idx; 1318 static struct ata_chip_id ids[] = 1319 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" }, 1320 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" }, 1321 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" }, 1322 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" }, 1323 { 0, 0, 0, 0, 0, 0}}; 1324 char buffer[64]; 1325 1326 if (!(idx = ata_match_chip(dev, ids))) 1327 return ENXIO; 1328 1329 ksprintf(buffer, "AMD %s %s controller", 1330 idx->text, ata_mode2str(idx->max_dma)); 1331 device_set_desc_copy(dev, buffer); 1332 ctlr->chip = idx; 1333 ctlr->chipinit = ata_amd_chipinit; 1334 return 0; 1335 } 1336 1337 static int 1338 ata_amd_chipinit(device_t dev) 1339 { 1340 struct ata_pci_controller *ctlr = device_get_softc(dev); 1341 1342 if (ata_setup_interrupt(dev)) 1343 return ENXIO; 1344 1345 /* disable/set prefetch, postwrite */ 1346 if (ctlr->chip->cfg2 & AMDBUG) 1347 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); 1348 else 1349 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); 1350 1351 ctlr->setmode = ata_via_family_setmode; 1352 return 0; 1353 } 1354 1355 1356 /* 1357 * ATI chipset support functions 1358 */ 1359 int 1360 ata_ati_ident(device_t dev) 1361 { 1362 struct ata_pci_controller *ctlr = device_get_softc(dev); 1363 struct ata_chip_id *idx; 1364 static struct ata_chip_id ids[] = 1365 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" }, 1366 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" }, 1367 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" }, 1368 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" }, 1369 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" }, 1370 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1371 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" }, 1372 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1373 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" }, 1374 { 0, 0, 0, 0, 0, 0}}; 1375 char buffer[64]; 1376 1377 if (!(idx = ata_match_chip(dev, ids))) 1378 return ENXIO; 1379 1380 ksprintf(buffer, "ATI %s %s controller", 1381 idx->text, ata_mode2str(idx->max_dma)); 1382 device_set_desc_copy(dev, buffer); 1383 ctlr->chip = idx; 1384 1385 /* 1386 * The ATI SATA controllers are actually a SiI 3112 controller, except 1387 * for the SB600. 1388 */ 1389 if (ctlr->chip->cfg1 & SIIMEMIO) 1390 ctlr->chipinit = ata_sii_chipinit; 1391 else 1392 ctlr->chipinit = ata_ati_chipinit; 1393 return 0; 1394 } 1395 1396 static int 1397 ata_ati_chipinit(device_t dev) 1398 { 1399 struct ata_pci_controller *ctlr = device_get_softc(dev); 1400 1401 if (ata_setup_interrupt(dev)) 1402 return ENXIO; 1403 1404 /* The SB600 needs special treatment. */ 1405 if (ctlr->chip->cfg1 & ATIAHCI) { 1406 /* Check if the chip is configured as an AHCI part. */ 1407 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) && 1408 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) { 1409 /* Check if the chip has PCI BAR 5 as memory resource. */ 1410 ctlr->r_type2 = SYS_RES_MEMORY; 1411 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */ 1412 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1413 &ctlr->r_rid2, 1414 RF_ACTIVE))) { 1415 return ata_ahci_chipinit(dev); 1416 } 1417 } 1418 } 1419 1420 ctlr->setmode = ata_ati_setmode; 1421 return 0; 1422 } 1423 1424 static void 1425 ata_ati_setmode(device_t dev, int mode) 1426 { 1427 device_t gparent = GRANDPARENT(dev); 1428 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1429 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1430 struct ata_device *atadev = device_get_softc(dev); 1431 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1432 int offset = (devno ^ 0x01) << 3; 1433 int error; 1434 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 1435 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 1436 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 1437 1438 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1439 1440 mode = ata_check_80pin(dev, mode); 1441 1442 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1443 1444 if (bootverbose) 1445 device_printf(dev, "%ssetting %s on %s chip\n", 1446 (error) ? "FAILURE " : "", 1447 ata_mode2str(mode), ctlr->chip->text); 1448 if (!error) { 1449 if (mode >= ATA_UDMA0) { 1450 pci_write_config(gparent, 0x56, 1451 (pci_read_config(gparent, 0x56, 2) & 1452 ~(0xf << (devno << 2))) | 1453 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 1454 pci_write_config(gparent, 0x54, 1455 pci_read_config(gparent, 0x54, 1) | 1456 (0x01 << devno), 1); 1457 pci_write_config(gparent, 0x44, 1458 (pci_read_config(gparent, 0x44, 4) & 1459 ~(0xff << offset)) | 1460 (dmatimings[2] << offset), 4); 1461 } 1462 else if (mode >= ATA_WDMA0) { 1463 pci_write_config(gparent, 0x54, 1464 pci_read_config(gparent, 0x54, 1) & 1465 ~(0x01 << devno), 1); 1466 pci_write_config(gparent, 0x44, 1467 (pci_read_config(gparent, 0x44, 4) & 1468 ~(0xff << offset)) | 1469 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 1470 } 1471 else 1472 pci_write_config(gparent, 0x54, 1473 pci_read_config(gparent, 0x54, 1) & 1474 ~(0x01 << devno), 1); 1475 1476 pci_write_config(gparent, 0x4a, 1477 (pci_read_config(gparent, 0x4a, 2) & 1478 ~(0xf << (devno << 2))) | 1479 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2); 1480 pci_write_config(gparent, 0x40, 1481 (pci_read_config(gparent, 0x40, 4) & 1482 ~(0xff << offset)) | 1483 (piotimings[ata_mode2idx(mode)] << offset), 4); 1484 atadev->mode = mode; 1485 } 1486 } 1487 1488 /* 1489 * Cyrix chipset support functions 1490 */ 1491 int 1492 ata_cyrix_ident(device_t dev) 1493 { 1494 struct ata_pci_controller *ctlr = device_get_softc(dev); 1495 1496 if (pci_get_devid(dev) == ATA_CYRIX_5530) { 1497 device_set_desc(dev, "Cyrix 5530 ATA33 controller"); 1498 ctlr->chipinit = ata_cyrix_chipinit; 1499 return 0; 1500 } 1501 return ENXIO; 1502 } 1503 1504 static int 1505 ata_cyrix_chipinit(device_t dev) 1506 { 1507 struct ata_pci_controller *ctlr = device_get_softc(dev); 1508 1509 if (ata_setup_interrupt(dev)) 1510 return ENXIO; 1511 1512 if (ctlr->r_res1) 1513 ctlr->setmode = ata_cyrix_setmode; 1514 else 1515 ctlr->setmode = ata_generic_setmode; 1516 return 0; 1517 } 1518 1519 static void 1520 ata_cyrix_setmode(device_t dev, int mode) 1521 { 1522 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1523 struct ata_device *atadev = device_get_softc(dev); 1524 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1525 u_int32_t piotiming[] = 1526 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; 1527 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; 1528 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; 1529 int error; 1530 1531 ch->dma->alignment = 16; 1532 ch->dma->max_iosize = 126 * DEV_BSIZE; 1533 1534 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 1535 1536 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1537 1538 if (bootverbose) 1539 device_printf(dev, "%ssetting %s on Cyrix chip\n", 1540 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1541 if (!error) { 1542 if (mode >= ATA_UDMA0) { 1543 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1544 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); 1545 } 1546 else if (mode >= ATA_WDMA0) { 1547 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1548 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); 1549 } 1550 else { 1551 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 1552 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); 1553 } 1554 atadev->mode = mode; 1555 } 1556 } 1557 1558 1559 /* 1560 * Cypress chipset support functions 1561 */ 1562 int 1563 ata_cypress_ident(device_t dev) 1564 { 1565 struct ata_pci_controller *ctlr = device_get_softc(dev); 1566 1567 /* 1568 * the Cypress chip is a mess, it contains two ATA functions, but 1569 * both channels are visible on the first one. 1570 * simply ignore the second function for now, as the right 1571 * solution (ignoring the second channel on the first function) 1572 * doesn't work with the crappy ATA interrupt setup on the alpha. 1573 */ 1574 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && 1575 pci_get_function(dev) == 1 && 1576 pci_get_subclass(dev) == PCIS_STORAGE_IDE) { 1577 device_set_desc(dev, "Cypress 82C693 ATA controller"); 1578 ctlr->chipinit = ata_cypress_chipinit; 1579 return 0; 1580 } 1581 return ENXIO; 1582 } 1583 1584 static int 1585 ata_cypress_chipinit(device_t dev) 1586 { 1587 struct ata_pci_controller *ctlr = device_get_softc(dev); 1588 1589 if (ata_setup_interrupt(dev)) 1590 return ENXIO; 1591 1592 ctlr->setmode = ata_cypress_setmode; 1593 return 0; 1594 } 1595 1596 static void 1597 ata_cypress_setmode(device_t dev, int mode) 1598 { 1599 device_t gparent = GRANDPARENT(dev); 1600 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1601 struct ata_device *atadev = device_get_softc(dev); 1602 int error; 1603 1604 mode = ata_limit_mode(dev, mode, ATA_WDMA2); 1605 1606 /* XXX SOS missing WDMA0+1 + PIO modes */ 1607 if (mode == ATA_WDMA2) { 1608 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 1609 if (bootverbose) 1610 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n", 1611 error ? "FAILURE " : ""); 1612 if (!error) { 1613 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2); 1614 atadev->mode = mode; 1615 return; 1616 } 1617 } 1618 /* we could set PIO mode timings, but we assume the BIOS did that */ 1619 } 1620 1621 1622 /* 1623 * HighPoint chipset support functions 1624 */ 1625 int 1626 ata_highpoint_ident(device_t dev) 1627 { 1628 struct ata_pci_controller *ctlr = device_get_softc(dev); 1629 struct ata_chip_id *idx; 1630 static struct ata_chip_id ids[] = 1631 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" }, 1632 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" }, 1633 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1634 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" }, 1635 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" }, 1636 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" }, 1637 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" }, 1638 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" }, 1639 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" }, 1640 { 0, 0, 0, 0, 0, 0}}; 1641 char buffer[64]; 1642 1643 if (!(idx = ata_match_chip(dev, ids))) 1644 return ENXIO; 1645 1646 strcpy(buffer, "HighPoint "); 1647 strcat(buffer, idx->text); 1648 if (idx->cfg1 == HPT374) { 1649 if (pci_get_function(dev) == 0) 1650 strcat(buffer, " (channel 0+1)"); 1651 if (pci_get_function(dev) == 1) 1652 strcat(buffer, " (channel 2+3)"); 1653 } 1654 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 1655 device_set_desc_copy(dev, buffer); 1656 ctlr->chip = idx; 1657 ctlr->chipinit = ata_highpoint_chipinit; 1658 return 0; 1659 } 1660 1661 static int 1662 ata_highpoint_chipinit(device_t dev) 1663 { 1664 struct ata_pci_controller *ctlr = device_get_softc(dev); 1665 1666 if (ata_setup_interrupt(dev)) 1667 return ENXIO; 1668 1669 if (ctlr->chip->cfg2 == HPTOLD) { 1670 /* disable interrupt prediction */ 1671 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 1672 } 1673 else { 1674 /* disable interrupt prediction */ 1675 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 1676 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 1677 1678 /* enable interrupts */ 1679 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 1680 1681 /* set clocks etc */ 1682 if (ctlr->chip->cfg1 < HPT372) 1683 pci_write_config(dev, 0x5b, 0x22, 1); 1684 else 1685 pci_write_config(dev, 0x5b, 1686 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 1687 } 1688 ctlr->allocate = ata_highpoint_allocate; 1689 ctlr->setmode = ata_highpoint_setmode; 1690 return 0; 1691 } 1692 1693 static int 1694 ata_highpoint_allocate(device_t dev) 1695 { 1696 struct ata_channel *ch = device_get_softc(dev); 1697 1698 /* setup the usual register normal pci style */ 1699 if (ata_pci_allocate(dev)) 1700 return ENXIO; 1701 1702 ch->flags |= ATA_ALWAYS_DMASTAT; 1703 return 0; 1704 } 1705 1706 static void 1707 ata_highpoint_setmode(device_t dev, int mode) 1708 { 1709 device_t gparent = GRANDPARENT(dev); 1710 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1711 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1712 struct ata_device *atadev = device_get_softc(dev); 1713 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1714 int error; 1715 u_int32_t timings33[][4] = { 1716 /* HPT366 HPT370 HPT372 HPT374 mode */ 1717 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 1718 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 1719 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 1720 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 1721 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 1722 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 1723 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 1724 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 1725 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 1726 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 1727 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 1728 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 1729 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 1730 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 1731 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 1732 }; 1733 1734 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 1735 1736 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev)) 1737 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 1738 1739 mode = ata_highpoint_check_80pin(dev, mode); 1740 1741 /* 1742 * most if not all HPT chips cant really handle that the device is 1743 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 1744 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 1745 */ 1746 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 1747 ata_limit_mode(dev, mode, ATA_UDMA5)); 1748 if (bootverbose) 1749 device_printf(dev, "%ssetting %s on HighPoint chip\n", 1750 (error) ? "FAILURE " : "", ata_mode2str(mode)); 1751 if (!error) 1752 pci_write_config(gparent, 0x40 + (devno << 2), 1753 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 1754 atadev->mode = mode; 1755 } 1756 1757 static int 1758 ata_highpoint_check_80pin(device_t dev, int mode) 1759 { 1760 device_t gparent = GRANDPARENT(dev); 1761 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1762 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1763 u_int8_t reg, val, res; 1764 1765 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) { 1766 reg = ch->unit ? 0x57 : 0x53; 1767 val = pci_read_config(gparent, reg, 1); 1768 pci_write_config(gparent, reg, val | 0x80, 1); 1769 } 1770 else { 1771 reg = 0x5b; 1772 val = pci_read_config(gparent, reg, 1); 1773 pci_write_config(gparent, reg, val & 0xfe, 1); 1774 } 1775 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 1776 pci_write_config(gparent, reg, val, 1); 1777 1778 if (mode > ATA_UDMA2 && res) { 1779 ata_print_cable(dev, "controller"); 1780 mode = ATA_UDMA2; 1781 } 1782 return mode; 1783 } 1784 1785 1786 /* 1787 * Intel chipset support functions 1788 */ 1789 int 1790 ata_intel_ident(device_t dev) 1791 { 1792 struct ata_pci_controller *ctlr = device_get_softc(dev); 1793 struct ata_chip_id *idx; 1794 static struct ata_chip_id ids[] = 1795 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" }, 1796 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" }, 1797 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1798 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1799 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" }, 1800 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" }, 1801 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1802 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" }, 1803 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1804 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" }, 1805 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1806 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" }, 1807 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1808 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" }, 1809 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" }, 1810 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1811 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" }, 1812 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" }, 1813 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1814 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" }, 1815 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" }, 1816 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1817 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" }, 1818 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" }, 1819 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" }, 1820 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1821 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1822 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" }, 1823 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1824 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1825 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" }, 1826 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" }, 1827 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1828 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1829 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1830 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" }, 1831 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1832 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1833 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1834 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1835 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, 1836 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" }, 1837 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1838 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, 1839 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1840 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1841 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1842 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1843 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, 1844 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" }, 1845 { 0, 0, 0, 0, 0, 0}}; 1846 char buffer[64]; 1847 1848 if (!(idx = ata_match_chip(dev, ids))) 1849 return ENXIO; 1850 1851 ksprintf(buffer, "Intel %s %s controller", 1852 idx->text, ata_mode2str(idx->max_dma)); 1853 device_set_desc_copy(dev, buffer); 1854 ctlr->chip = idx; 1855 ctlr->chipinit = ata_intel_chipinit; 1856 return 0; 1857 } 1858 1859 static int 1860 ata_intel_chipinit(device_t dev) 1861 { 1862 struct ata_pci_controller *ctlr = device_get_softc(dev); 1863 1864 if (ata_setup_interrupt(dev)) 1865 return ENXIO; 1866 1867 /* good old PIIX needs special treatment (not implemented) */ 1868 if (ctlr->chip->chipid == ATA_I82371FB) { 1869 ctlr->setmode = ata_intel_old_setmode; 1870 } 1871 1872 /* the intel 31244 needs special care if in DPA mode */ 1873 else if (ctlr->chip->chipid == ATA_I31244) { 1874 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 1875 ctlr->r_type2 = SYS_RES_MEMORY; 1876 ctlr->r_rid2 = PCIR_BAR(0); 1877 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1878 &ctlr->r_rid2, 1879 RF_ACTIVE))) 1880 return ENXIO; 1881 ctlr->channels = 4; 1882 ctlr->allocate = ata_intel_31244_allocate; 1883 ctlr->reset = ata_intel_31244_reset; 1884 } 1885 ctlr->setmode = ata_sata_setmode; 1886 } 1887 1888 /* non SATA intel chips goes here */ 1889 else if (ctlr->chip->max_dma < ATA_SA150) { 1890 ctlr->allocate = ata_intel_allocate; 1891 ctlr->setmode = ata_intel_new_setmode; 1892 } 1893 1894 /* SATA parts can be either compat or AHCI */ 1895 else { 1896 /* force all ports active "the legacy way" */ 1897 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2); 1898 1899 ctlr->allocate = ata_intel_allocate; 1900 ctlr->reset = ata_intel_reset; 1901 1902 /* 1903 * if we have AHCI capability and BAR(5) as a memory resource 1904 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode 1905 */ 1906 if ((ctlr->chip->cfg1 == AHCI) && 1907 (pci_read_config(dev, 0x90, 1) & 0xc0)) { 1908 ctlr->r_type2 = SYS_RES_MEMORY; 1909 ctlr->r_rid2 = PCIR_BAR(5); 1910 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 1911 &ctlr->r_rid2, 1912 RF_ACTIVE))) 1913 return ata_ahci_chipinit(dev); 1914 } 1915 ctlr->setmode = ata_sata_setmode; 1916 1917 /* enable PCI interrupt */ 1918 pci_write_config(dev, PCIR_COMMAND, 1919 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 1920 } 1921 return 0; 1922 } 1923 1924 static int 1925 ata_intel_allocate(device_t dev) 1926 { 1927 struct ata_channel *ch = device_get_softc(dev); 1928 1929 /* setup the usual register normal pci style */ 1930 if (ata_pci_allocate(dev)) 1931 return ENXIO; 1932 1933 ch->flags |= ATA_ALWAYS_DMASTAT; 1934 return 0; 1935 } 1936 1937 static void 1938 ata_intel_reset(device_t dev) 1939 { 1940 device_t parent = device_get_parent(dev); 1941 struct ata_pci_controller *ctlr = device_get_softc(parent); 1942 struct ata_channel *ch = device_get_softc(dev); 1943 int mask, timeout; 1944 1945 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */ 1946 if (ctlr->chip->cfg1) { 1947 mask = (0x0005 << ch->unit); 1948 } 1949 else { 1950 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */ 1951 if (pci_read_config(parent, 0x90, 1) & 0x04) 1952 mask = 0x0003; 1953 else { 1954 mask = (0x0001 << ch->unit); 1955 /* XXX SOS should be in intel_allocate if we grow it */ 1956 ch->flags |= ATA_NO_SLAVE; 1957 } 1958 } 1959 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2); 1960 DELAY(10); 1961 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2); 1962 1963 /* wait up to 1 sec for "connect well" */ 1964 for (timeout = 0; timeout < 100 ; timeout++) { 1965 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) && 1966 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 1967 break; 1968 ata_udelay(10000); 1969 } 1970 ata_generic_reset(dev); 1971 } 1972 1973 static void 1974 ata_intel_old_setmode(device_t dev, int mode) 1975 { 1976 /* NOT YET */ 1977 } 1978 1979 static void 1980 ata_intel_new_setmode(device_t dev, int mode) 1981 { 1982 device_t gparent = GRANDPARENT(dev); 1983 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1984 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 1985 struct ata_device *atadev = device_get_softc(dev); 1986 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 1987 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4); 1988 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1); 1989 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1); 1990 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2); 1991 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2); 1992 u_int32_t mask40 = 0, new40 = 0; 1993 u_int8_t mask44 = 0, new44 = 0; 1994 int error; 1995 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 1996 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; 1997 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */ 1998 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */ 1999 2000 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2001 2002 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { 2003 ata_print_cable(dev, "controller"); 2004 mode = ATA_UDMA2; 2005 } 2006 2007 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2008 2009 if (bootverbose) 2010 device_printf(dev, "%ssetting %s on %s chip\n", 2011 (error) ? "FAILURE " : "", 2012 ata_mode2str(mode), ctlr->chip->text); 2013 if (error) 2014 return; 2015 2016 /* 2017 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary 2018 * drive 0, secondary drive 1) 2019 * 2020 * 0 Disable Ultra DMA mode 2021 * 1 Enable Ultra DMA mode 2022 * 2023 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary 2024 * drive 0, secondary drive 1). 2025 * 0000 UDMA mode 0 2026 * 0001 UDMA mode 1, 3, 5 2027 * 0010 UDMA mode 2, 4, reserved 2028 * 0011 reserved 2029 * (top two bits for each drive reserved) 2030 */ 2031 #if 0 2032 device_printf(dev, 2033 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2034 reg40, reg44, reg48 ,reg4a, reg54); 2035 #endif 2036 reg48 &= ~(0x0001 << devno); 2037 reg4a &= ~(0x3 << (devno << 2)); 2038 if (mode >= ATA_UDMA0) { 2039 reg48 |= 0x0001 << devno; 2040 if (mode > ATA_UDMA0) 2041 reg4a |= (1 + !(mode & 0x01)) << (devno << 2); 2042 } 2043 pci_write_config(gparent, 0x48, reg48, 2); 2044 pci_write_config(gparent, 0x4a, reg4a, 2); 2045 2046 /* 2047 * reg54: 2048 * 2049 * 32:20 reserved 2050 * 19:18 Secondary ATA signal mode 2051 * 17:16 Primary ATA signal mode 2052 * 00 = Normal (enabled) 2053 * 01 = Tri-state (disabled) 2054 * 10 = Drive Low (disabled) 2055 * 11 = Reserved 2056 * 2057 * 15 Secondary drive 1 - Base Clock 2058 * 14 Secondary drive 0 - Base Clock 2059 * 13 Primary drive 1 - Base Clock 2060 * 12 Primary drive 0 - Base Clock 2061 * 0 = Select 33 MHz clock 2062 * 1 = Select 100 Mhz clock 2063 * 2064 * 11 Reserved 2065 * 10 Vendor specific (set by BIOS?) 2066 * 09:08 Reserved 2067 * 2068 * 07 Secondary drive 1 - Cable Type 2069 * 06 Secondary drive 0 - Cable Type 2070 * 05 Primary drive 1 - Cable Type 2071 * 04 Primary drive 0 - Cable Type 2072 * 0 = 40 Conductor 2073 * 1 = 80 Conductor (or high speed cable) 2074 * 2075 * 03 Secondary drive 1 - Select 33/66 clock 2076 * 02 Secondary drive 0 - Select 33/66 clock 2077 * 01 Primary drive 1 - Select 33/66 clock 2078 * 00 Primary drive 0 - Select 33/66 clock 2079 * 0 = Select 33 MHz 2080 * 1 = Select 66 MHz 2081 * 2082 * It is unclear what this should be set to when operating 2083 * in 100MHz mode. 2084 * 2085 * NOTE: UDMA2 = 33 MHz 2086 * UDMA3 = 40 MHz (?) - unsupported 2087 * UDMA4 = 66 MHz 2088 * UDMA5 = 100 MHz 2089 * UDMA6 = 133 Mhz 2090 */ 2091 reg54 |= 0x0400; /* set vendor specific bit */ 2092 reg54 &= ~((0x1 << devno) | (0x1000 << devno)); 2093 2094 if (mode >= ATA_UDMA5) 2095 reg54 |= (0x1000 << devno); 2096 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */ 2097 reg54 |= (0x1 << devno); 2098 2099 pci_write_config(gparent, 0x54, reg54, 2); 2100 2101 /* 2102 * Reg40 (32 bits... well, actually two 16 bit registers) 2103 * 2104 * Primary channel bits 15:00, Secondary channel bits 31:00. Note 2105 * that slave timings are handled in register 44. 2106 * 2107 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges 2108 * 2109 * 14 Slave ATA Timing Register Enable (R/W) 2110 * 2111 * 13:12 IORDY Sample Mode 2112 * 00 PIO-0 2113 * 01 PIO-2, SW-2 2114 * 10 PIO-3, PIO-4, MW-1, MW-2 2115 * 11 Reserved 2116 * 2117 * 11:10 Reserved 2118 * 2119 * 09:08 Recovery Mode 2120 * 00 PIO-0, PIO-2, SW-2 2121 * 01 PIO-3, MW-1 2122 * 10 Reserved 2123 * 11 PIO-4, MW-2 2124 * 2125 * 07:04 Secondary Device Control Bits 2126 * 03:00 Primary Device Control Bits 2127 * 2128 * bit 3 DMA Timing Enable 2129 * 2130 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device 2131 * 2132 * bit 1 Enable IORDY sample point capability for PIO 2133 * xfers. Always enabled for PIO4 and PIO3, enabled 2134 * for PIO2 if indicated by the device, and otherwise 2135 * probably should be 0. 2136 * 2137 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0 2138 * timing modes. 2139 */ 2140 2141 /* 2142 * Modify reg40 according to the table 2143 */ 2144 if (atadev->unit == ATA_MASTER) { 2145 mask40 = 0x3300; 2146 new40 = timings[ata_mode2idx(mode)] << 8; 2147 } 2148 else { 2149 mask44 = 0x0f; 2150 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | 2151 (timings[ata_mode2idx(mode)] & 0x03); 2152 } 2153 2154 /* 2155 * Slave ATA timing register enable 2156 */ 2157 mask40 |= 0x4000; 2158 new40 |= 0x4000; 2159 2160 /* 2161 * Device control bits 3:0 for master, 7:4 for slave. 2162 * 2163 * bit3 DMA Timing enable. 2164 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly 2165 * bit1 Enable IORDY sample point capability for PIO xfers. Always 2166 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by 2167 * the device, and otherwise should be 0. 2168 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes. 2169 * 2170 * Set to: 0 x 1 1 2171 */ 2172 2173 if (atadev->unit == ATA_MASTER) { 2174 mask40 |= 0x0F; 2175 new40 |= 0x03; 2176 if (!ata_atapi(dev)) 2177 new40 |= 0x04; 2178 } else { 2179 mask40 |= 0xF0; 2180 new40 |= 0x30; 2181 if (!ata_atapi(dev)) 2182 new40 |= 0x40; 2183 } 2184 /* 2185 reg40 &= ~0x00ff00ff; 2186 reg40 |= 0x40774077; 2187 */ 2188 2189 /* 2190 * Primary or Secondary controller 2191 */ 2192 if (ch->unit) { 2193 mask40 <<= 16; 2194 new40 <<= 16; 2195 mask44 <<= 4; 2196 new44 <<= 4; 2197 } 2198 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4); 2199 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1); 2200 2201 #if 0 2202 reg40 = pci_read_config(gparent, 0x40, 4); 2203 reg44 = pci_read_config(gparent, 0x44, 1); 2204 reg48 = pci_read_config(gparent, 0x48, 1); 2205 reg4a = pci_read_config(gparent, 0x4a, 2); 2206 reg54 = pci_read_config(gparent, 0x54, 2); 2207 device_printf(dev, 2208 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n", 2209 reg40, reg44, reg48 ,reg4a, reg54); 2210 #endif 2211 2212 atadev->mode = mode; 2213 } 2214 2215 static int 2216 ata_intel_31244_allocate(device_t dev) 2217 { 2218 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2219 struct ata_channel *ch = device_get_softc(dev); 2220 int i; 2221 int ch_offset; 2222 2223 ch_offset = 0x200 + ch->unit * 0x200; 2224 2225 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 2226 ch->r_io[i].res = ctlr->r_res2; 2227 2228 /* setup ATA registers */ 2229 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 2230 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 2231 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 2232 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 2233 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 2234 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 2235 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 2236 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 2237 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 2238 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 2239 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 2240 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 2241 2242 /* setup DMA registers */ 2243 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 2244 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 2245 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 2246 2247 /* setup SATA registers */ 2248 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 2249 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 2250 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 2251 2252 ch->flags |= ATA_NO_SLAVE; 2253 ata_pci_hw(dev); 2254 ch->hw.status = ata_intel_31244_status; 2255 ch->hw.command = ata_intel_31244_command; 2256 2257 /* enable PHY state change interrupt */ 2258 ATA_OUTL(ctlr->r_res2, 0x4, 2259 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 2260 return 0; 2261 } 2262 2263 static int 2264 ata_intel_31244_status(device_t dev) 2265 { 2266 /* do we have any PHY events ? */ 2267 ata_sata_phy_check_events(dev); 2268 2269 /* any drive action to take care of ? */ 2270 return ata_pci_status(dev); 2271 } 2272 2273 static int 2274 ata_intel_31244_command(struct ata_request *request) 2275 { 2276 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2277 struct ata_device *atadev = device_get_softc(request->dev); 2278 u_int64_t lba; 2279 2280 if (!(atadev->flags & ATA_D_48BIT_ACTIVE)) 2281 return (ata_generic_command(request)); 2282 2283 lba = request->u.ata.lba; 2284 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit); 2285 /* enable interrupt */ 2286 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 2287 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 2288 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 2289 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff)); 2290 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) | 2291 ((lba >> 8) & 0x00ff)); 2292 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) | 2293 ((lba >> 16) & 0x00ff)); 2294 2295 /* issue command to controller */ 2296 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 2297 2298 return 0; 2299 } 2300 2301 static void 2302 ata_intel_31244_reset(device_t dev) 2303 { 2304 if (ata_sata_phy_reset(dev)) 2305 ata_generic_reset(dev); 2306 } 2307 2308 2309 /* 2310 * Integrated Technology Express Inc. (ITE) chipset support functions 2311 */ 2312 int 2313 ata_ite_ident(device_t dev) 2314 { 2315 struct ata_pci_controller *ctlr = device_get_softc(dev); 2316 struct ata_chip_id *idx; 2317 static struct ata_chip_id ids[] = 2318 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 2319 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 2320 { 0, 0, 0, 0, 0, 0}}; 2321 char buffer[64]; 2322 2323 if (!(idx = ata_match_chip(dev, ids))) 2324 return ENXIO; 2325 2326 ksprintf(buffer, "ITE %s %s controller", 2327 idx->text, ata_mode2str(idx->max_dma)); 2328 device_set_desc_copy(dev, buffer); 2329 ctlr->chip = idx; 2330 ctlr->chipinit = ata_ite_chipinit; 2331 return 0; 2332 } 2333 2334 static int 2335 ata_ite_chipinit(device_t dev) 2336 { 2337 struct ata_pci_controller *ctlr = device_get_softc(dev); 2338 2339 if (ata_setup_interrupt(dev)) 2340 return ENXIO; 2341 2342 ctlr->setmode = ata_ite_setmode; 2343 2344 /* set PCI mode and 66Mhz reference clock */ 2345 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 2346 2347 /* set default active & recover timings */ 2348 pci_write_config(dev, 0x54, 0x31, 1); 2349 pci_write_config(dev, 0x56, 0x31, 1); 2350 return 0; 2351 } 2352 2353 static void 2354 ata_ite_setmode(device_t dev, int mode) 2355 { 2356 device_t gparent = GRANDPARENT(dev); 2357 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2358 struct ata_device *atadev = device_get_softc(dev); 2359 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 2360 int error; 2361 2362 /* correct the mode for what the HW supports */ 2363 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2364 2365 /* check the CBLID bits for 80 conductor cable detection */ 2366 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) & 2367 (ch->unit ? (1<<3) : (1<<2)))) { 2368 ata_print_cable(dev, "controller"); 2369 mode = ATA_UDMA2; 2370 } 2371 2372 /* set the wanted mode on the device */ 2373 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 2374 2375 if (bootverbose) 2376 device_printf(dev, "%s setting %s on ITE8212F chip\n", 2377 (error) ? "failed" : "success", ata_mode2str(mode)); 2378 2379 /* if the device accepted the mode change, setup the HW accordingly */ 2380 if (!error) { 2381 if (mode >= ATA_UDMA0) { 2382 u_int8_t udmatiming[] = 2383 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 2384 2385 /* enable UDMA mode */ 2386 pci_write_config(gparent, 0x50, 2387 pci_read_config(gparent, 0x50, 1) & 2388 ~(1 << (devno + 3)), 1); 2389 2390 /* set UDMA timing */ 2391 pci_write_config(gparent, 2392 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit), 2393 udmatiming[mode & ATA_MODE_MASK], 1); 2394 } 2395 else { 2396 u_int8_t chtiming[] = 2397 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 2398 2399 /* disable UDMA mode */ 2400 pci_write_config(gparent, 0x50, 2401 pci_read_config(gparent, 0x50, 1) | 2402 (1 << (devno + 3)), 1); 2403 2404 /* set active and recover timing (shared between master & slave) */ 2405 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) < 2406 chtiming[ata_mode2idx(mode)]) 2407 pci_write_config(gparent, 0x54 + (ch->unit << 2), 2408 chtiming[ata_mode2idx(mode)], 1); 2409 } 2410 atadev->mode = mode; 2411 } 2412 } 2413 2414 2415 /* 2416 * JMicron chipset support functions 2417 */ 2418 int 2419 ata_jmicron_ident(device_t dev) 2420 { 2421 struct ata_pci_controller *ctlr = device_get_softc(dev); 2422 struct ata_chip_id *idx; 2423 static struct ata_chip_id ids[] = 2424 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" }, 2425 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" }, 2426 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" }, 2427 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" }, 2428 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" }, 2429 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" }, 2430 { 0, 0, 0, 0, 0, 0}}; 2431 char buffer[64]; 2432 2433 if (!(idx = ata_match_chip(dev, ids))) 2434 return ENXIO; 2435 2436 if ((pci_read_config(dev, 0xdf, 1) & 0x40) && 2437 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1))) 2438 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2439 idx->text, ata_mode2str(ATA_UDMA6)); 2440 else 2441 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller", 2442 idx->text, ata_mode2str(idx->max_dma)); 2443 device_set_desc_copy(dev, buffer); 2444 ctlr->chip = idx; 2445 ctlr->chipinit = ata_jmicron_chipinit; 2446 return 0; 2447 } 2448 2449 static int 2450 ata_jmicron_chipinit(device_t dev) 2451 { 2452 struct ata_pci_controller *ctlr = device_get_softc(dev); 2453 int error; 2454 2455 if (ata_setup_interrupt(dev)) 2456 return ENXIO; 2457 2458 /* do we have multiple PCI functions ? */ 2459 if (pci_read_config(dev, 0xdf, 1) & 0x40) { 2460 /* if we have a memory BAR(5) we are on the AHCI part */ 2461 ctlr->r_type2 = SYS_RES_MEMORY; 2462 ctlr->r_rid2 = PCIR_BAR(5); 2463 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 2464 &ctlr->r_rid2, RF_ACTIVE))) 2465 return ata_ahci_chipinit(dev); 2466 2467 /* otherwise we are on the PATA part */ 2468 ctlr->allocate = ata_pci_allocate; 2469 ctlr->reset = ata_generic_reset; 2470 ctlr->dmainit = ata_pci_dmainit; 2471 ctlr->setmode = ata_jmicron_setmode; 2472 ctlr->channels = ctlr->chip->cfg2; 2473 } 2474 else { 2475 /* set controller configuration to a combined setup we support */ 2476 pci_write_config(dev, 0x40, 0x80c0a131, 4); 2477 pci_write_config(dev, 0x80, 0x01200000, 4); 2478 2479 ctlr->r_type2 = SYS_RES_MEMORY; 2480 ctlr->r_rid2 = PCIR_BAR(5); 2481 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 2482 &ctlr->r_rid2, RF_ACTIVE))) { 2483 if ((error = ata_ahci_chipinit(dev))) 2484 return error; 2485 } 2486 2487 ctlr->allocate = ata_jmicron_allocate; 2488 ctlr->reset = ata_jmicron_reset; 2489 ctlr->dmainit = ata_jmicron_dmainit; 2490 ctlr->setmode = ata_jmicron_setmode; 2491 2492 /* set the number of HW channels */ 2493 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2; 2494 } 2495 return 0; 2496 } 2497 2498 static int 2499 ata_jmicron_allocate(device_t dev) 2500 { 2501 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2502 struct ata_channel *ch = device_get_softc(dev); 2503 int error; 2504 2505 if (ch->unit >= ctlr->chip->cfg1) { 2506 ch->unit -= ctlr->chip->cfg1; 2507 error = ata_pci_allocate(dev); 2508 ch->unit += ctlr->chip->cfg1; 2509 } 2510 else 2511 error = ata_ahci_allocate(dev); 2512 return error; 2513 } 2514 2515 static void 2516 ata_jmicron_reset(device_t dev) 2517 { 2518 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2519 struct ata_channel *ch = device_get_softc(dev); 2520 2521 if (ch->unit >= ctlr->chip->cfg1) 2522 ata_generic_reset(dev); 2523 else 2524 ata_ahci_reset(dev); 2525 } 2526 2527 static void 2528 ata_jmicron_dmainit(device_t dev) 2529 { 2530 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2531 struct ata_channel *ch = device_get_softc(dev); 2532 2533 if (ch->unit >= ctlr->chip->cfg1) 2534 ata_pci_dmainit(dev); 2535 else 2536 ata_ahci_dmainit(dev); 2537 } 2538 2539 static void 2540 ata_jmicron_setmode(device_t dev, int mode) 2541 { 2542 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 2543 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 2544 2545 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) { 2546 struct ata_device *atadev = device_get_softc(dev); 2547 2548 /* check for 80pin cable present */ 2549 if (pci_read_config(dev, 0x40, 1) & 0x08) 2550 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 2551 else 2552 mode = ata_limit_mode(dev, mode, ATA_UDMA6); 2553 2554 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2555 atadev->mode = mode; 2556 } 2557 else 2558 ata_sata_setmode(dev, mode); 2559 } 2560 2561 2562 /* 2563 * Marvell chipset support functions 2564 */ 2565 #define ATA_MV_HOST_BASE(ch) \ 2566 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 2567 #define ATA_MV_EDMA_BASE(ch) \ 2568 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 2569 2570 struct ata_marvell_response { 2571 u_int16_t tag; 2572 u_int8_t edma_status; 2573 u_int8_t dev_status; 2574 u_int32_t timestamp; 2575 }; 2576 2577 struct ata_marvell_dma_prdentry { 2578 u_int32_t addrlo; 2579 u_int32_t count; 2580 u_int32_t addrhi; 2581 u_int32_t reserved; 2582 }; 2583 2584 int 2585 ata_marvell_ident(device_t dev) 2586 { 2587 struct ata_pci_controller *ctlr = device_get_softc(dev); 2588 struct ata_chip_id *idx; 2589 static struct ata_chip_id ids[] = 2590 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" }, 2591 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" }, 2592 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" }, 2593 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" }, 2594 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" }, 2595 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" }, 2596 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" }, 2597 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" }, 2598 { 0, 0, 0, 0, 0, 0}}; 2599 char buffer[64]; 2600 2601 if (!(idx = ata_match_chip(dev, ids))) 2602 return ENXIO; 2603 2604 ksprintf(buffer, "Marvell %s %s controller", 2605 idx->text, ata_mode2str(idx->max_dma)); 2606 device_set_desc_copy(dev, buffer); 2607 ctlr->chip = idx; 2608 switch (ctlr->chip->cfg2) { 2609 case MV50XX: 2610 case MV60XX: 2611 ctlr->chipinit = ata_marvell_edma_chipinit; 2612 break; 2613 case MV61XX: 2614 ctlr->chipinit = ata_marvell_pata_chipinit; 2615 break; 2616 } 2617 return 0; 2618 } 2619 2620 static int 2621 ata_marvell_pata_chipinit(device_t dev) 2622 { 2623 struct ata_pci_controller *ctlr = device_get_softc(dev); 2624 2625 if (ata_setup_interrupt(dev)) 2626 return ENXIO; 2627 2628 ctlr->allocate = ata_marvell_pata_allocate; 2629 ctlr->setmode = ata_marvell_pata_setmode; 2630 ctlr->channels = ctlr->chip->cfg1; 2631 return 0; 2632 } 2633 2634 static int 2635 ata_marvell_pata_allocate(device_t dev) 2636 { 2637 struct ata_channel *ch = device_get_softc(dev); 2638 2639 /* setup the usual register normal pci style */ 2640 if (ata_pci_allocate(dev)) 2641 return ENXIO; 2642 2643 /* dont use 32 bit PIO transfers */ 2644 ch->flags |= ATA_USE_16BIT; 2645 2646 return 0; 2647 } 2648 2649 static void 2650 ata_marvell_pata_setmode(device_t dev, int mode) 2651 { 2652 device_t gparent = GRANDPARENT(dev); 2653 struct ata_pci_controller *ctlr = device_get_softc(gparent); 2654 struct ata_device *atadev = device_get_softc(dev); 2655 2656 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 2657 mode = ata_check_80pin(dev, mode); 2658 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) 2659 atadev->mode = mode; 2660 } 2661 2662 static int 2663 ata_marvell_edma_chipinit(device_t dev) 2664 { 2665 struct ata_pci_controller *ctlr = device_get_softc(dev); 2666 2667 if (ata_setup_interrupt(dev)) 2668 return ENXIO; 2669 2670 ctlr->r_type1 = SYS_RES_MEMORY; 2671 ctlr->r_rid1 = PCIR_BAR(0); 2672 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 2673 &ctlr->r_rid1, RF_ACTIVE))) 2674 return ENXIO; 2675 2676 /* mask all host controller interrupts */ 2677 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 2678 2679 /* mask all PCI interrupts */ 2680 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 2681 2682 ctlr->allocate = ata_marvell_edma_allocate; 2683 ctlr->reset = ata_marvell_edma_reset; 2684 ctlr->dmainit = ata_marvell_edma_dmainit; 2685 ctlr->setmode = ata_sata_setmode; 2686 ctlr->channels = ctlr->chip->cfg1; 2687 2688 /* clear host controller interrupts */ 2689 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 2690 if (ctlr->chip->cfg1 > 4) 2691 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 2692 2693 /* clear PCI interrupts */ 2694 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 2695 2696 /* unmask PCI interrupts we want */ 2697 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 2698 2699 /* unmask host controller interrupts we want */ 2700 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 2701 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 2702 2703 /* enable PCI interrupt */ 2704 pci_write_config(dev, PCIR_COMMAND, 2705 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 2706 return 0; 2707 } 2708 2709 static int 2710 ata_marvell_edma_allocate(device_t dev) 2711 { 2712 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2713 struct ata_channel *ch = device_get_softc(dev); 2714 u_int64_t work = ch->dma->work_bus; 2715 int i; 2716 2717 /* clear work area */ 2718 bzero(ch->dma->work, 1024+256); 2719 2720 /* set legacy ATA resources */ 2721 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 2722 ch->r_io[i].res = ctlr->r_res1; 2723 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 2724 } 2725 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 2726 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 2727 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 2728 ata_default_registers(dev); 2729 2730 /* set SATA resources */ 2731 switch (ctlr->chip->cfg2) { 2732 case MV50XX: 2733 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2734 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 2735 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2736 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 2737 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2738 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 2739 break; 2740 case MV60XX: 2741 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 2742 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 2743 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 2744 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 2745 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 2746 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 2747 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 2748 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 2749 break; 2750 } 2751 2752 ch->flags |= ATA_NO_SLAVE; 2753 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 2754 ata_generic_hw(dev); 2755 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 2756 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 2757 ch->hw.status = ata_marvell_edma_status; 2758 2759 /* disable the EDMA machinery */ 2760 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2761 DELAY(100000); /* SOS should poll for disabled */ 2762 2763 /* set configuration to non-queued 128b read transfers stop on error */ 2764 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 2765 2766 /* request queue base high */ 2767 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 2768 2769 /* request queue in ptr */ 2770 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2771 2772 /* request queue out ptr */ 2773 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 2774 2775 /* response queue base high */ 2776 work += 1024; 2777 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 2778 2779 /* response queue in ptr */ 2780 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 2781 2782 /* response queue out ptr */ 2783 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 2784 2785 /* clear SATA error register */ 2786 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2787 2788 /* clear any outstanding error interrupts */ 2789 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2790 2791 /* unmask all error interrupts */ 2792 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2793 2794 /* enable EDMA machinery */ 2795 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2796 return 0; 2797 } 2798 2799 static int 2800 ata_marvell_edma_status(device_t dev) 2801 { 2802 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2803 struct ata_channel *ch = device_get_softc(dev); 2804 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 2805 int shift = (ch->unit << 1) + (ch->unit > 3); 2806 2807 if (cause & (1 << shift)) { 2808 2809 /* clear interrupt(s) */ 2810 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2811 2812 /* do we have any PHY events ? */ 2813 ata_sata_phy_check_events(dev); 2814 } 2815 2816 /* do we have any device action ? */ 2817 return (cause & (2 << shift)); 2818 } 2819 2820 /* must be called with ATA channel locked and state_mtx held */ 2821 static int 2822 ata_marvell_edma_begin_transaction(struct ata_request *request) 2823 { 2824 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2825 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2826 u_int32_t req_in; 2827 u_int8_t *bytep; 2828 u_int16_t *wordp; 2829 u_int32_t *quadp; 2830 int i, tag = 0x07; 2831 int dummy, error, slot; 2832 2833 /* only DMA R/W goes through the EMDA machine */ 2834 if (request->u.ata.command != ATA_READ_DMA && 2835 request->u.ata.command != ATA_WRITE_DMA) { 2836 2837 /* disable the EDMA machinery */ 2838 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 2839 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2840 return ata_begin_transaction(request); 2841 } 2842 2843 /* check for 48 bit access and convert if needed */ 2844 ata_modify_if_48bit(request); 2845 2846 /* check sanity, setup SG list and DMA engine */ 2847 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount, 2848 request->flags & ATA_R_READ, ch->dma->sg, 2849 &dummy))) { 2850 device_printf(request->dev, "setting up DMA failed\n"); 2851 request->result = error; 2852 return ATA_OP_FINISHED; 2853 } 2854 2855 /* get next free request queue slot */ 2856 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 2857 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 2858 bytep = (u_int8_t *)(ch->dma->work); 2859 bytep += (slot << 5); 2860 wordp = (u_int16_t *)bytep; 2861 quadp = (u_int32_t *)bytep; 2862 2863 /* fill in this request */ 2864 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff; 2865 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32; 2866 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1); 2867 2868 i = 10; 2869 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 2870 bytep[i++] = 0x10 | ATA_COUNT; 2871 bytep[i++] = request->u.ata.count & 0xff; 2872 bytep[i++] = 0x10 | ATA_COUNT; 2873 2874 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 2875 bytep[i++] = 0x10 | ATA_SECTOR; 2876 bytep[i++] = request->u.ata.lba & 0xff; 2877 bytep[i++] = 0x10 | ATA_SECTOR; 2878 2879 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 2880 bytep[i++] = 0x10 | ATA_CYL_LSB; 2881 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 2882 bytep[i++] = 0x10 | ATA_CYL_LSB; 2883 2884 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 2885 bytep[i++] = 0x10 | ATA_CYL_MSB; 2886 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 2887 bytep[i++] = 0x10 | ATA_CYL_MSB; 2888 2889 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 2890 bytep[i++] = 0x10 | ATA_DRIVE; 2891 2892 bytep[i++] = request->u.ata.command; 2893 bytep[i++] = 0x90 | ATA_COMMAND; 2894 2895 /* enable EDMA machinery if needed */ 2896 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 2897 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2898 while (!(ATA_INL(ctlr->r_res1, 2899 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2900 DELAY(10); 2901 } 2902 2903 /* tell EDMA it has a new request */ 2904 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 2905 req_in &= 0xfffffc00; 2906 req_in += (slot << 5); 2907 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 2908 2909 return ATA_OP_CONTINUES; 2910 } 2911 2912 /* must be called with ATA channel locked and state_mtx held */ 2913 static int 2914 ata_marvell_edma_end_transaction(struct ata_request *request) 2915 { 2916 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 2917 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 2918 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 2919 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 2920 int res; 2921 2922 /* EDMA interrupt */ 2923 if ((icr & (0x0001 << (ch->unit & 3)))) { 2924 struct ata_marvell_response *response; 2925 u_int32_t rsp_in, rsp_out; 2926 int slot; 2927 2928 /* stop timeout */ 2929 callout_stop(&request->callout); 2930 2931 /* get response ptr's */ 2932 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 2933 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 2934 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 2935 rsp_out &= 0xffffff00; 2936 rsp_out += (slot << 3); 2937 response = (struct ata_marvell_response *) 2938 (ch->dma->work + 1024 + (slot << 3)); 2939 2940 /* record status for this request */ 2941 request->status = response->dev_status; 2942 request->error = 0; 2943 2944 /* ack response */ 2945 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 2946 2947 /* update progress */ 2948 if (!(request->status & ATA_S_ERROR) && 2949 !(request->flags & ATA_R_TIMEOUT)) 2950 request->donecount = request->bytecount; 2951 2952 /* unload SG list */ 2953 ch->dma->unload(ch->dev); 2954 2955 res = ATA_OP_FINISHED; 2956 } 2957 2958 /* legacy ATA interrupt */ 2959 else { 2960 res = ata_end_transaction(request); 2961 } 2962 2963 /* ack interrupt */ 2964 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 2965 return res; 2966 } 2967 2968 static void 2969 ata_marvell_edma_reset(device_t dev) 2970 { 2971 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2972 struct ata_channel *ch = device_get_softc(dev); 2973 2974 /* disable the EDMA machinery */ 2975 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 2976 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 2977 DELAY(10); 2978 2979 /* clear SATA error register */ 2980 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 2981 2982 /* clear any outstanding error interrupts */ 2983 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 2984 2985 /* unmask all error interrupts */ 2986 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 2987 2988 /* enable channel and test for devices */ 2989 if (ata_sata_phy_reset(dev)) 2990 ata_generic_reset(dev); 2991 2992 /* enable EDMA machinery */ 2993 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 2994 } 2995 2996 static void 2997 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 2998 int error) 2999 { 3000 struct ata_dmasetprd_args *args = xsc; 3001 struct ata_marvell_dma_prdentry *prd = args->dmatab; 3002 int i; 3003 3004 if ((args->error = error)) 3005 return; 3006 3007 for (i = 0; i < nsegs; i++) { 3008 prd[i].addrlo = htole32(segs[i].ds_addr); 3009 prd[i].count = htole32(segs[i].ds_len); 3010 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 3011 } 3012 prd[i - 1].count |= htole32(ATA_DMA_EOT); 3013 } 3014 3015 static void 3016 ata_marvell_edma_dmainit(device_t dev) 3017 { 3018 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3019 struct ata_channel *ch = device_get_softc(dev); 3020 3021 ata_dmainit(dev); 3022 if (ch->dma) { 3023 /* note start and stop are not used here */ 3024 ch->dma->setprd = ata_marvell_edma_dmasetprd; 3025 3026 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 3027 ch->dma->max_address = BUS_SPACE_MAXADDR; 3028 } 3029 } 3030 3031 3032 /* 3033 * National chipset support functions 3034 */ 3035 int 3036 ata_national_ident(device_t dev) 3037 { 3038 struct ata_pci_controller *ctlr = device_get_softc(dev); 3039 3040 /* this chip is a clone of the Cyrix chip, bugs and all */ 3041 if (pci_get_devid(dev) == ATA_SC1100) { 3042 device_set_desc(dev, "National Geode SC1100 ATA33 controller"); 3043 ctlr->chipinit = ata_national_chipinit; 3044 return 0; 3045 } 3046 return ENXIO; 3047 } 3048 3049 static int 3050 ata_national_chipinit(device_t dev) 3051 { 3052 struct ata_pci_controller *ctlr = device_get_softc(dev); 3053 3054 if (ata_setup_interrupt(dev)) 3055 return ENXIO; 3056 3057 ctlr->setmode = ata_national_setmode; 3058 return 0; 3059 } 3060 3061 static void 3062 ata_national_setmode(device_t dev, int mode) 3063 { 3064 device_t gparent = GRANDPARENT(dev); 3065 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3066 struct ata_device *atadev = device_get_softc(dev); 3067 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3068 u_int32_t piotiming[] = 3069 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 3070 0x00803020, 0x20102010, 0x00100010, 3071 0x00100010, 0x00100010, 0x00100010 }; 3072 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; 3073 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; 3074 int error; 3075 3076 ch->dma->alignment = 16; 3077 ch->dma->max_iosize = 126 * DEV_BSIZE; 3078 3079 mode = ata_limit_mode(dev, mode, ATA_UDMA2); 3080 3081 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3082 3083 if (bootverbose) 3084 device_printf(dev, "%s setting %s on National chip\n", 3085 (error) ? "failed" : "success", ata_mode2str(mode)); 3086 if (!error) { 3087 if (mode >= ATA_UDMA0) { 3088 pci_write_config(gparent, 0x44 + (devno << 3), 3089 udmatiming[mode & ATA_MODE_MASK], 4); 3090 } 3091 else if (mode >= ATA_WDMA0) { 3092 pci_write_config(gparent, 0x44 + (devno << 3), 3093 dmatiming[mode & ATA_MODE_MASK], 4); 3094 } 3095 else { 3096 pci_write_config(gparent, 0x44 + (devno << 3), 3097 pci_read_config(gparent, 0x44 + (devno << 3), 4) | 3098 0x80000000, 4); 3099 } 3100 pci_write_config(gparent, 0x40 + (devno << 3), 3101 piotiming[ata_mode2idx(mode)], 4); 3102 atadev->mode = mode; 3103 } 3104 } 3105 3106 /* 3107 * NetCell chipset support functions 3108 */ 3109 int 3110 ata_netcell_ident(device_t dev) 3111 { 3112 struct ata_pci_controller *ctlr = device_get_softc(dev); 3113 3114 if (pci_get_devid(dev) == ATA_NETCELL_SR) { 3115 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller"); 3116 ctlr->chipinit = ata_netcell_chipinit; 3117 return 0; 3118 } 3119 return ENXIO; 3120 } 3121 3122 static int 3123 ata_netcell_chipinit(device_t dev) 3124 { 3125 struct ata_pci_controller *ctlr = device_get_softc(dev); 3126 3127 if (ata_generic_chipinit(dev)) 3128 return ENXIO; 3129 3130 ctlr->allocate = ata_netcell_allocate; 3131 return 0; 3132 } 3133 3134 static int 3135 ata_netcell_allocate(device_t dev) 3136 { 3137 struct ata_channel *ch = device_get_softc(dev); 3138 3139 /* setup the usual register normal pci style */ 3140 if (ata_pci_allocate(dev)) 3141 return ENXIO; 3142 3143 /* the NetCell only supports 16 bit PIO transfers */ 3144 ch->flags |= ATA_USE_16BIT; 3145 3146 return 0; 3147 } 3148 3149 3150 /* 3151 * nVidia chipset support functions 3152 */ 3153 int 3154 ata_nvidia_ident(device_t dev) 3155 { 3156 struct ata_pci_controller *ctlr = device_get_softc(dev); 3157 struct ata_chip_id *idx; 3158 static struct ata_chip_id ids[] = 3159 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" }, 3160 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" }, 3161 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" }, 3162 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" }, 3163 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" }, 3164 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" }, 3165 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3166 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" }, 3167 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" }, 3168 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3169 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" }, 3170 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" }, 3171 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3172 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" }, 3173 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" }, 3174 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3175 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" }, 3176 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" }, 3177 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3178 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" }, 3179 { 0, 0, 0, 0, 0, 0}} ; 3180 char buffer[64] ; 3181 3182 if (!(idx = ata_match_chip(dev, ids))) 3183 return ENXIO; 3184 3185 ksprintf(buffer, "nVidia %s %s controller", 3186 idx->text, ata_mode2str(idx->max_dma)); 3187 device_set_desc_copy(dev, buffer); 3188 ctlr->chip = idx; 3189 ctlr->chipinit = ata_nvidia_chipinit; 3190 return 0; 3191 } 3192 3193 static int 3194 ata_nvidia_chipinit(device_t dev) 3195 { 3196 struct ata_pci_controller *ctlr = device_get_softc(dev); 3197 3198 if (ata_setup_interrupt(dev)) 3199 return ENXIO; 3200 3201 if (ctlr->chip->max_dma >= ATA_SA150) { 3202 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1) 3203 ctlr->r_type2 = SYS_RES_IOPORT; 3204 else 3205 ctlr->r_type2 = SYS_RES_MEMORY; 3206 ctlr->r_rid2 = PCIR_BAR(5); 3207 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3208 &ctlr->r_rid2, RF_ACTIVE))) { 3209 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3210 3211 ctlr->allocate = ata_nvidia_allocate; 3212 ctlr->reset = ata_nvidia_reset; 3213 3214 /* enable control access */ 3215 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1); 3216 3217 if (ctlr->chip->cfg2 & NVQ) { 3218 /* clear interrupt status */ 3219 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff); 3220 3221 /* enable device and PHY state change interrupts */ 3222 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d); 3223 3224 /* disable NCQ support */ 3225 ATA_OUTL(ctlr->r_res2, 0x0400, 3226 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9); 3227 } 3228 else { 3229 /* clear interrupt status */ 3230 ATA_OUTB(ctlr->r_res2, offset, 0xff); 3231 3232 /* enable device and PHY state change interrupts */ 3233 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd); 3234 } 3235 3236 /* enable PCI interrupt */ 3237 pci_write_config(dev, PCIR_COMMAND, 3238 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 3239 3240 } 3241 ctlr->setmode = ata_sata_setmode; 3242 } 3243 else { 3244 /* disable prefetch, postwrite */ 3245 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); 3246 ctlr->setmode = ata_via_family_setmode; 3247 } 3248 return 0; 3249 } 3250 3251 static int 3252 ata_nvidia_allocate(device_t dev) 3253 { 3254 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3255 struct ata_channel *ch = device_get_softc(dev); 3256 3257 /* setup the usual register normal pci style */ 3258 if (ata_pci_allocate(dev)) 3259 return ENXIO; 3260 3261 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3262 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); 3263 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3264 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); 3265 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3266 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); 3267 3268 ch->hw.status = ata_nvidia_status; 3269 ch->flags |= ATA_NO_SLAVE; 3270 3271 return 0; 3272 } 3273 3274 static int 3275 ata_nvidia_status(device_t dev) 3276 { 3277 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3278 struct ata_channel *ch = device_get_softc(dev); 3279 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010; 3280 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2); 3281 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset); 3282 3283 /* do we have any PHY events ? */ 3284 if (istatus & (0x0c << shift)) 3285 ata_sata_phy_check_events(dev); 3286 3287 /* clear interrupt(s) */ 3288 ATA_OUTB(ctlr->r_res2, offset, 3289 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0)); 3290 3291 /* do we have any device action ? */ 3292 return (istatus & (0x01 << shift)); 3293 } 3294 3295 static void 3296 ata_nvidia_reset(device_t dev) 3297 { 3298 if (ata_sata_phy_reset(dev)) 3299 ata_generic_reset(dev); 3300 } 3301 3302 3303 /* 3304 * Promise chipset support functions 3305 */ 3306 #define ATA_PDC_APKT_OFFSET 0x00000010 3307 #define ATA_PDC_HPKT_OFFSET 0x00000040 3308 #define ATA_PDC_ASG_OFFSET 0x00000080 3309 #define ATA_PDC_LSG_OFFSET 0x000000c0 3310 #define ATA_PDC_HSG_OFFSET 0x00000100 3311 #define ATA_PDC_CHN_OFFSET 0x00000400 3312 #define ATA_PDC_BUF_BASE 0x00400000 3313 #define ATA_PDC_BUF_OFFSET 0x00100000 3314 #define ATA_PDC_MAX_HPKT 8 3315 #define ATA_PDC_WRITE_REG 0x00 3316 #define ATA_PDC_WRITE_CTL 0x0e 3317 #define ATA_PDC_WRITE_END 0x08 3318 #define ATA_PDC_WAIT_NBUSY 0x10 3319 #define ATA_PDC_WAIT_READY 0x18 3320 #define ATA_PDC_1B 0x20 3321 #define ATA_PDC_2B 0x40 3322 3323 struct host_packet { 3324 u_int32_t addr; 3325 TAILQ_ENTRY(host_packet) chain; 3326 }; 3327 3328 struct ata_promise_sx4 { 3329 struct spinlock mtx; 3330 TAILQ_HEAD(, host_packet) queue; 3331 int busy; 3332 }; 3333 3334 int 3335 ata_promise_ident(device_t dev) 3336 { 3337 struct ata_pci_controller *ctlr = device_get_softc(dev); 3338 struct ata_chip_id *idx; 3339 static struct ata_chip_id ids[] = 3340 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" }, 3341 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" }, 3342 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" }, 3343 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" }, 3344 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" }, 3345 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" }, 3346 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" }, 3347 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" }, 3348 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" }, 3349 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" }, 3350 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" }, 3351 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" }, 3352 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" }, 3353 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" }, 3354 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" }, 3355 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" }, 3356 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" }, 3357 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" }, 3358 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" }, 3359 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" }, 3360 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" }, 3361 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" }, 3362 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" }, 3363 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" }, 3364 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" }, 3365 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" }, 3366 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" }, 3367 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" }, 3368 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" }, 3369 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" }, 3370 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" }, 3371 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" }, 3372 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" }, 3373 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" }, 3374 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" }, 3375 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" }, 3376 { 0, 0, 0, 0, 0, 0}}; 3377 char buffer[64]; 3378 uintptr_t devid = 0; 3379 3380 if (!(idx = ata_match_chip(dev, ids))) 3381 return ENXIO; 3382 3383 /* if we are on a SuperTrak SX6000 dont attach */ 3384 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3385 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3386 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3387 devid == ATA_I960RM) 3388 return ENXIO; 3389 3390 strcpy(buffer, "Promise "); 3391 strcat(buffer, idx->text); 3392 3393 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 3394 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 3395 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 3396 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 3397 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 3398 static long start = 0, end = 0; 3399 3400 if (pci_get_slot(dev) == 1) { 3401 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 3402 strcat(buffer, " (channel 0+1)"); 3403 } 3404 else if (pci_get_slot(dev) == 2 && start && end) { 3405 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 3406 strcat(buffer, " (channel 2+3)"); 3407 } 3408 else { 3409 start = end = 0; 3410 } 3411 } 3412 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 3413 device_set_desc_copy(dev, buffer); 3414 ctlr->chip = idx; 3415 ctlr->chipinit = ata_promise_chipinit; 3416 return 0; 3417 } 3418 3419 static int 3420 ata_promise_chipinit(device_t dev) 3421 { 3422 struct ata_pci_controller *ctlr = device_get_softc(dev); 3423 int fake_reg, stat_reg; 3424 3425 if (ata_setup_interrupt(dev)) 3426 return ENXIO; 3427 3428 switch (ctlr->chip->cfg1) { 3429 case PRNEW: 3430 /* setup clocks */ 3431 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 3432 3433 ctlr->dmainit = ata_promise_dmainit; 3434 /* FALLTHROUGH */ 3435 3436 case PROLD: 3437 /* enable burst mode */ 3438 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 3439 ctlr->allocate = ata_promise_allocate; 3440 ctlr->setmode = ata_promise_setmode; 3441 return 0; 3442 3443 case PRTX: 3444 ctlr->allocate = ata_promise_tx2_allocate; 3445 ctlr->setmode = ata_promise_setmode; 3446 return 0; 3447 3448 case PRMIO: 3449 ctlr->r_type1 = SYS_RES_MEMORY; 3450 ctlr->r_rid1 = PCIR_BAR(4); 3451 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 3452 &ctlr->r_rid1, RF_ACTIVE))) 3453 goto failnfree; 3454 3455 ctlr->r_type2 = SYS_RES_MEMORY; 3456 ctlr->r_rid2 = PCIR_BAR(3); 3457 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 3458 &ctlr->r_rid2, RF_ACTIVE))) 3459 goto failnfree; 3460 3461 if (ctlr->chip->cfg2 == PRSX4X) { 3462 struct ata_promise_sx4 *hpkt; 3463 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 3464 3465 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3466 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3467 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) { 3468 device_printf(dev, "unable to setup interrupt\n"); 3469 goto failnfree; 3470 } 3471 3472 /* print info about cache memory */ 3473 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 3474 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 3475 ((dimm >> 24) & 0xff), 3476 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 3477 " ECC enabled" : "" ); 3478 3479 /* adjust cache memory parameters */ 3480 ATA_OUTL(ctlr->r_res2, 0x000c000c, 3481 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 3482 3483 /* setup host packet controls */ 3484 hpkt = kmalloc(sizeof(struct ata_promise_sx4), 3485 M_TEMP, M_INTWAIT | M_ZERO); 3486 spin_init(&hpkt->mtx); 3487 TAILQ_INIT(&hpkt->queue); 3488 hpkt->busy = 0; 3489 device_set_ivars(dev, hpkt); 3490 ctlr->allocate = ata_promise_mio_allocate; 3491 ctlr->reset = ata_promise_mio_reset; 3492 ctlr->dmainit = ata_promise_mio_dmainit; 3493 ctlr->setmode = ata_promise_setmode; 3494 ctlr->channels = 4; 3495 return 0; 3496 } 3497 3498 /* mio type controllers need an interrupt intercept */ 3499 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 3500 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 3501 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) { 3502 device_printf(dev, "unable to setup interrupt\n"); 3503 goto failnfree; 3504 } 3505 3506 switch (ctlr->chip->cfg2) { 3507 case PRPATA: 3508 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 3509 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 3510 goto sata150; 3511 case PRCMBO: 3512 ctlr->channels = 3; 3513 goto sata150; 3514 case PRSATA: 3515 ctlr->channels = 4; 3516 sata150: 3517 fake_reg = 0x60; 3518 stat_reg = 0x6c; 3519 break; 3520 3521 case PRCMBO2: 3522 ctlr->channels = 3; 3523 goto sataii; 3524 case PRSATA2: 3525 default: 3526 ctlr->channels = 4; 3527 sataii: 3528 fake_reg = 0x54; 3529 stat_reg = 0x60; 3530 break; 3531 } 3532 3533 /* prime fake interrupt register */ 3534 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3535 3536 /* clear SATA status */ 3537 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 3538 3539 ctlr->allocate = ata_promise_mio_allocate; 3540 ctlr->reset = ata_promise_mio_reset; 3541 ctlr->dmainit = ata_promise_mio_dmainit; 3542 ctlr->setmode = ata_promise_mio_setmode; 3543 3544 return 0; 3545 } 3546 3547 failnfree: 3548 if (ctlr->r_res2) 3549 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 3550 if (ctlr->r_res1) 3551 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 3552 return ENXIO; 3553 } 3554 3555 static int 3556 ata_promise_allocate(device_t dev) 3557 { 3558 struct ata_channel *ch = device_get_softc(dev); 3559 3560 if (ata_pci_allocate(dev)) 3561 return ENXIO; 3562 3563 ch->hw.status = ata_promise_status; 3564 return 0; 3565 } 3566 3567 static int 3568 ata_promise_status(device_t dev) 3569 { 3570 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3571 struct ata_channel *ch = device_get_softc(dev); 3572 3573 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 3574 return ata_pci_status(dev); 3575 } 3576 return 0; 3577 } 3578 3579 static int 3580 ata_promise_dmastart(device_t dev) 3581 { 3582 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3583 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3584 struct ata_device *atadev = device_get_softc(dev); 3585 3586 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3587 ATA_OUTB(ctlr->r_res1, 0x11, 3588 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 3589 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 3590 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | 3591 (ch->dma->cur_iosize >> 1)); 3592 } 3593 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 3594 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 3595 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus); 3596 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3597 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | 3598 ATA_BMCMD_START_STOP); 3599 ch->flags |= ATA_DMA_ACTIVE; 3600 return 0; 3601 } 3602 3603 static int 3604 ata_promise_dmastop(device_t dev) 3605 { 3606 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev)); 3607 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3608 struct ata_device *atadev = device_get_softc(dev); 3609 int error; 3610 3611 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 3612 ATA_OUTB(ctlr->r_res1, 0x11, 3613 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 3614 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 3615 } 3616 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 3617 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3618 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3619 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3620 ch->flags &= ~ATA_DMA_ACTIVE; 3621 return error; 3622 } 3623 3624 static void 3625 ata_promise_dmareset(device_t dev) 3626 { 3627 struct ata_channel *ch = device_get_softc(dev); 3628 3629 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 3630 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 3631 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 3632 ch->flags &= ~ATA_DMA_ACTIVE; 3633 } 3634 3635 static void 3636 ata_promise_dmainit(device_t dev) 3637 { 3638 struct ata_channel *ch = device_get_softc(dev); 3639 3640 ata_dmainit(dev); 3641 if (ch->dma) { 3642 ch->dma->start = ata_promise_dmastart; 3643 ch->dma->stop = ata_promise_dmastop; 3644 ch->dma->reset = ata_promise_dmareset; 3645 } 3646 } 3647 3648 static void 3649 ata_promise_setmode(device_t dev, int mode) 3650 { 3651 device_t gparent = GRANDPARENT(dev); 3652 struct ata_pci_controller *ctlr = device_get_softc(gparent); 3653 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 3654 struct ata_device *atadev = device_get_softc(dev); 3655 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 3656 int error; 3657 u_int32_t timings[][2] = { 3658 /* PROLD PRNEW mode */ 3659 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 3660 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 3661 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 3662 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 3663 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 3664 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 3665 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 3666 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 3667 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 3668 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 3669 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 3670 { 0, 0x00424ef6 }, /* UDMA 3 */ 3671 { 0, 0x004127f3 }, /* UDMA 4 */ 3672 { 0, 0x004127f3 } /* UDMA 5 */ 3673 }; 3674 3675 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 3676 3677 switch (ctlr->chip->cfg1) { 3678 case PROLD: 3679 case PRNEW: 3680 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) & 3681 (ch->unit ? 1 << 11 : 1 << 10))) { 3682 ata_print_cable(dev, "controller"); 3683 mode = ATA_UDMA2; 3684 } 3685 if (ata_atapi(dev) && mode > ATA_PIO_MAX) 3686 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 3687 break; 3688 3689 case PRTX: 3690 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3691 if (mode > ATA_UDMA2 && 3692 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 3693 ata_print_cable(dev, "controller"); 3694 mode = ATA_UDMA2; 3695 } 3696 break; 3697 3698 case PRMIO: 3699 if (mode > ATA_UDMA2 && 3700 (ATA_INL(ctlr->r_res2, 3701 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) + 3702 (ch->unit << 7)) & 0x01000000)) { 3703 ata_print_cable(dev, "controller"); 3704 mode = ATA_UDMA2; 3705 } 3706 break; 3707 } 3708 3709 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 3710 3711 if (bootverbose) 3712 device_printf(dev, "%ssetting %s on %s chip\n", 3713 (error) ? "FAILURE " : "", 3714 ata_mode2str(mode), ctlr->chip->text); 3715 if (!error) { 3716 if (ctlr->chip->cfg1 < PRTX) 3717 pci_write_config(gparent, 0x60 + (devno << 2), 3718 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 3719 atadev->mode = mode; 3720 } 3721 return; 3722 } 3723 3724 static int 3725 ata_promise_tx2_allocate(device_t dev) 3726 { 3727 struct ata_channel *ch = device_get_softc(dev); 3728 3729 if (ata_pci_allocate(dev)) 3730 return ENXIO; 3731 3732 ch->hw.status = ata_promise_tx2_status; 3733 return 0; 3734 } 3735 3736 static int 3737 ata_promise_tx2_status(device_t dev) 3738 { 3739 struct ata_channel *ch = device_get_softc(dev); 3740 3741 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 3742 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 3743 return ata_pci_status(dev); 3744 } 3745 return 0; 3746 } 3747 3748 static int 3749 ata_promise_mio_allocate(device_t dev) 3750 { 3751 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3752 struct ata_channel *ch = device_get_softc(dev); 3753 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0; 3754 int i; 3755 3756 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 3757 ch->r_io[i].res = ctlr->r_res2; 3758 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 3759 } 3760 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 3761 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 3762 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 3763 ata_default_registers(dev); 3764 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) || 3765 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) { 3766 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 3767 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 3768 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 3769 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 3770 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 3771 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 3772 ch->flags |= ATA_NO_SLAVE; 3773 } 3774 ch->flags |= ATA_USE_16BIT; 3775 3776 ata_generic_hw(dev); 3777 if (ctlr->chip->cfg2 & PRSX4X) { 3778 ch->hw.command = ata_promise_sx4_command; 3779 } 3780 else { 3781 ch->hw.command = ata_promise_mio_command; 3782 ch->hw.status = ata_promise_mio_status; 3783 } 3784 return 0; 3785 } 3786 3787 static void 3788 ata_promise_mio_intr(void *data) 3789 { 3790 struct ata_pci_controller *ctlr = data; 3791 struct ata_channel *ch; 3792 u_int32_t vector; 3793 int unit, fake_reg; 3794 3795 switch (ctlr->chip->cfg2) { 3796 case PRPATA: 3797 case PRCMBO: 3798 case PRSATA: 3799 fake_reg = 0x60; 3800 break; 3801 case PRCMBO2: 3802 case PRSATA2: 3803 default: 3804 fake_reg = 0x54; 3805 break; 3806 } 3807 3808 /* 3809 * since reading interrupt status register on early "mio" chips 3810 * clears the status bits we cannot read it for each channel later on 3811 * in the generic interrupt routine. 3812 * store the bits in an unused register in the chip so we can read 3813 * it from there safely to get around this "feature". 3814 */ 3815 vector = ATA_INL(ctlr->r_res2, 0x040); 3816 ATA_OUTL(ctlr->r_res2, 0x040, vector); 3817 ATA_OUTL(ctlr->r_res2, fake_reg, vector); 3818 3819 for (unit = 0; unit < ctlr->channels; unit++) { 3820 if ((ch = ctlr->interrupt[unit].argument)) 3821 ctlr->interrupt[unit].function(ch); 3822 } 3823 3824 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff); 3825 } 3826 3827 static int 3828 ata_promise_mio_status(device_t dev) 3829 { 3830 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3831 struct ata_channel *ch = device_get_softc(dev); 3832 struct ata_connect_task *tp; 3833 u_int32_t fake_reg, stat_reg, vector, status; 3834 3835 switch (ctlr->chip->cfg2) { 3836 case PRPATA: 3837 case PRCMBO: 3838 case PRSATA: 3839 fake_reg = 0x60; 3840 stat_reg = 0x6c; 3841 break; 3842 case PRCMBO2: 3843 case PRSATA2: 3844 default: 3845 fake_reg = 0x54; 3846 stat_reg = 0x60; 3847 break; 3848 } 3849 3850 /* read and acknowledge interrupt */ 3851 vector = ATA_INL(ctlr->r_res2, fake_reg); 3852 3853 /* read and clear interface status */ 3854 status = ATA_INL(ctlr->r_res2, stat_reg); 3855 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 3856 3857 /* check for and handle disconnect events */ 3858 if ((status & (0x00000001 << ch->unit)) && 3859 (tp = (struct ata_connect_task *) 3860 kmalloc(sizeof(struct ata_connect_task), 3861 M_ATA, M_INTWAIT | M_ZERO))) { 3862 3863 if (bootverbose) 3864 device_printf(ch->dev, "DISCONNECT requested\n"); 3865 tp->action = ATA_C_DETACH; 3866 tp->dev = ch->dev; 3867 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3868 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3869 } 3870 3871 /* check for and handle connect events */ 3872 if ((status & (0x00000010 << ch->unit)) && 3873 (tp = (struct ata_connect_task *) 3874 kmalloc(sizeof(struct ata_connect_task), 3875 M_ATA, M_INTWAIT | M_ZERO))) { 3876 3877 if (bootverbose) 3878 device_printf(ch->dev, "CONNECT requested\n"); 3879 tp->action = ATA_C_ATTACH; 3880 tp->dev = ch->dev; 3881 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp); 3882 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task); 3883 } 3884 3885 /* do we have any device action ? */ 3886 return (vector & (1 << (ch->unit + 1))); 3887 } 3888 3889 static int 3890 ata_promise_mio_command(struct ata_request *request) 3891 { 3892 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 3893 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 3894 u_int32_t *wordp = (u_int32_t *)ch->dma->work; 3895 3896 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 3897 3898 /* XXX SOS add ATAPI commands support later */ 3899 switch (request->u.ata.command) { 3900 default: 3901 return ata_generic_command(request); 3902 3903 case ATA_READ_DMA: 3904 case ATA_READ_DMA48: 3905 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3906 break; 3907 3908 case ATA_WRITE_DMA: 3909 case ATA_WRITE_DMA48: 3910 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 3911 break; 3912 } 3913 wordp[1] = htole32(ch->dma->sg_bus); 3914 wordp[2] = 0; 3915 ata_promise_apkt((u_int8_t*)wordp, request); 3916 3917 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus); 3918 return 0; 3919 } 3920 3921 static void 3922 ata_promise_mio_reset(device_t dev) 3923 { 3924 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 3925 struct ata_channel *ch = device_get_softc(dev); 3926 struct ata_promise_sx4 *hpktp; 3927 3928 switch (ctlr->chip->cfg2) { 3929 case PRSX4X: 3930 3931 /* softreset channel ATA module */ 3932 hpktp = device_get_ivars(ctlr->dev); 3933 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 3934 ata_udelay(1000); 3935 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 3936 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 3937 ~0x00003f9f) | (ch->unit + 1)); 3938 3939 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 3940 spin_lock_wr(&hpktp->mtx); 3941 ATA_OUTL(ctlr->r_res2, 0xc012c, 3942 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 3943 DELAY(10); 3944 ATA_OUTL(ctlr->r_res2, 0xc012c, 3945 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 3946 hpktp->busy = 0; 3947 spin_unlock_wr(&hpktp->mtx); 3948 ata_generic_reset(dev); 3949 break; 3950 3951 case PRPATA: 3952 case PRCMBO: 3953 case PRSATA: 3954 if ((ctlr->chip->cfg2 == PRSATA) || 3955 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3956 3957 /* mask plug/unplug intr */ 3958 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 3959 } 3960 3961 /* softreset channels ATA module */ 3962 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3963 ata_udelay(10000); 3964 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3965 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3966 ~0x00003f9f) | (ch->unit + 1)); 3967 3968 if ((ctlr->chip->cfg2 == PRSATA) || 3969 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) { 3970 3971 if (ata_sata_phy_reset(dev)) 3972 ata_generic_reset(dev); 3973 3974 /* reset and enable plug/unplug intr */ 3975 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 3976 } 3977 else 3978 ata_generic_reset(dev); 3979 break; 3980 3981 case PRCMBO2: 3982 case PRSATA2: 3983 if ((ctlr->chip->cfg2 == PRSATA2) || 3984 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 3985 /* set portmultiplier port */ 3986 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 3987 3988 /* mask plug/unplug intr */ 3989 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 3990 } 3991 3992 /* softreset channels ATA module */ 3993 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 3994 ata_udelay(10000); 3995 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 3996 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 3997 ~0x00003f9f) | (ch->unit + 1)); 3998 3999 if ((ctlr->chip->cfg2 == PRSATA2) || 4000 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) { 4001 4002 /* set PHY mode to "improved" */ 4003 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 4004 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 4005 ~0x00000003) | 0x00000001); 4006 4007 if (ata_sata_phy_reset(dev)) 4008 ata_generic_reset(dev); 4009 4010 /* reset and enable plug/unplug intr */ 4011 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 4012 4013 /* set portmultiplier port */ 4014 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 4015 } 4016 else 4017 ata_generic_reset(dev); 4018 break; 4019 4020 } 4021 } 4022 4023 static void 4024 ata_promise_mio_dmainit(device_t dev) 4025 { 4026 /* note start and stop are not used here */ 4027 ata_dmainit(dev); 4028 } 4029 4030 static void 4031 ata_promise_mio_setmode(device_t dev, int mode) 4032 { 4033 device_t gparent = GRANDPARENT(dev); 4034 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4035 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4036 4037 if ( (ctlr->chip->cfg2 == PRSATA) || 4038 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) || 4039 (ctlr->chip->cfg2 == PRSATA2) || 4040 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) 4041 ata_sata_setmode(dev, mode); 4042 else 4043 ata_promise_setmode(dev, mode); 4044 } 4045 4046 static void 4047 ata_promise_sx4_intr(void *data) 4048 { 4049 struct ata_pci_controller *ctlr = data; 4050 struct ata_channel *ch; 4051 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 4052 int unit; 4053 4054 for (unit = 0; unit < ctlr->channels; unit++) { 4055 if (vector & (1 << (unit + 1))) 4056 if ((ch = ctlr->interrupt[unit].argument)) 4057 ctlr->interrupt[unit].function(ch); 4058 if (vector & (1 << (unit + 5))) 4059 if ((ch = ctlr->interrupt[unit].argument)) 4060 ata_promise_queue_hpkt(ctlr, 4061 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4062 ATA_PDC_HPKT_OFFSET)); 4063 if (vector & (1 << (unit + 9))) { 4064 ata_promise_next_hpkt(ctlr); 4065 if ((ch = ctlr->interrupt[unit].argument)) 4066 ctlr->interrupt[unit].function(ch); 4067 } 4068 if (vector & (1 << (unit + 13))) { 4069 ata_promise_next_hpkt(ctlr); 4070 if ((ch = ctlr->interrupt[unit].argument)) 4071 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4072 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 4073 ATA_PDC_APKT_OFFSET)); 4074 } 4075 } 4076 } 4077 4078 static int 4079 ata_promise_sx4_command(struct ata_request *request) 4080 { 4081 device_t gparent = GRANDPARENT(request->dev); 4082 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4083 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4084 struct ata_dma_prdentry *prd = ch->dma->sg; 4085 caddr_t window = rman_get_virtual(ctlr->r_res1); 4086 u_int32_t *wordp; 4087 int i, idx, length = 0; 4088 4089 /* XXX SOS add ATAPI commands support later */ 4090 switch (request->u.ata.command) { 4091 4092 default: 4093 return -1; 4094 4095 case ATA_ATA_IDENTIFY: 4096 case ATA_READ: 4097 case ATA_READ48: 4098 case ATA_READ_MUL: 4099 case ATA_READ_MUL48: 4100 case ATA_WRITE: 4101 case ATA_WRITE48: 4102 case ATA_WRITE_MUL: 4103 case ATA_WRITE_MUL48: 4104 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4105 return ata_generic_command(request); 4106 4107 case ATA_SETFEATURES: 4108 case ATA_FLUSHCACHE: 4109 case ATA_FLUSHCACHE48: 4110 case ATA_SLEEP: 4111 case ATA_SET_MULTI: 4112 wordp = (u_int32_t *) 4113 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4114 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 4115 wordp[1] = 0; 4116 wordp[2] = 0; 4117 ata_promise_apkt((u_int8_t *)wordp, request); 4118 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4119 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 4120 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4121 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 4122 return 0; 4123 4124 case ATA_READ_DMA: 4125 case ATA_READ_DMA48: 4126 case ATA_WRITE_DMA: 4127 case ATA_WRITE_DMA48: 4128 wordp = (u_int32_t *) 4129 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 4130 i = idx = 0; 4131 do { 4132 wordp[idx++] = prd[i].addr; 4133 wordp[idx++] = prd[i].count; 4134 length += (prd[i].count & ~ATA_DMA_EOT); 4135 } while (!(prd[i++].count & ATA_DMA_EOT)); 4136 4137 wordp = (u_int32_t *) 4138 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 4139 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4140 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4141 4142 wordp = (u_int32_t *) 4143 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 4144 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 4145 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 4146 4147 wordp = (u_int32_t *) 4148 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 4149 if (request->flags & ATA_R_READ) 4150 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 4151 if (request->flags & ATA_R_WRITE) 4152 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 4153 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 4154 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 4155 wordp[3] = 0; 4156 4157 wordp = (u_int32_t *) 4158 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 4159 if (request->flags & ATA_R_READ) 4160 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 4161 if (request->flags & ATA_R_WRITE) 4162 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 4163 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 4164 wordp[2] = 0; 4165 ata_promise_apkt((u_int8_t *)wordp, request); 4166 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 4167 4168 if (request->flags & ATA_R_READ) { 4169 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 4170 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 4171 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 4172 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 4173 } 4174 if (request->flags & ATA_R_WRITE) { 4175 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 4176 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 4177 ata_promise_queue_hpkt(ctlr, 4178 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 4179 } 4180 return 0; 4181 } 4182 } 4183 4184 static int 4185 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 4186 { 4187 struct ata_device *atadev = device_get_softc(request->dev); 4188 int i = 12; 4189 4190 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 4191 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit; 4192 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 4193 bytep[i++] = ATA_A_4BIT; 4194 4195 if (atadev->flags & ATA_D_48BIT_ACTIVE) { 4196 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4197 bytep[i++] = request->u.ata.feature >> 8; 4198 bytep[i++] = request->u.ata.feature; 4199 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 4200 bytep[i++] = request->u.ata.count >> 8; 4201 bytep[i++] = request->u.ata.count; 4202 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4203 bytep[i++] = request->u.ata.lba >> 24; 4204 bytep[i++] = request->u.ata.lba; 4205 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4206 bytep[i++] = request->u.ata.lba >> 32; 4207 bytep[i++] = request->u.ata.lba >> 8; 4208 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4209 bytep[i++] = request->u.ata.lba >> 40; 4210 bytep[i++] = request->u.ata.lba >> 16; 4211 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4212 bytep[i++] = ATA_D_LBA | atadev->unit; 4213 } 4214 else { 4215 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 4216 bytep[i++] = request->u.ata.feature; 4217 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 4218 bytep[i++] = request->u.ata.count; 4219 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 4220 bytep[i++] = request->u.ata.lba; 4221 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 4222 bytep[i++] = request->u.ata.lba >> 8; 4223 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 4224 bytep[i++] = request->u.ata.lba >> 16; 4225 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 4226 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) | 4227 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf); 4228 } 4229 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 4230 bytep[i++] = request->u.ata.command; 4231 return i; 4232 } 4233 4234 static void 4235 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 4236 { 4237 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4238 4239 spin_lock_wr(&hpktp->mtx); 4240 if (hpktp->busy) { 4241 struct host_packet *hp = 4242 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO); 4243 hp->addr = hpkt; 4244 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 4245 } 4246 else { 4247 hpktp->busy = 1; 4248 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 4249 } 4250 spin_unlock_wr(&hpktp->mtx); 4251 } 4252 4253 static void 4254 ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 4255 { 4256 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev); 4257 struct host_packet *hp; 4258 4259 spin_lock_wr(&hpktp->mtx); 4260 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 4261 TAILQ_REMOVE(&hpktp->queue, hp, chain); 4262 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 4263 kfree(hp, M_TEMP); 4264 } 4265 else 4266 hpktp->busy = 0; 4267 spin_unlock_wr(&hpktp->mtx); 4268 } 4269 4270 4271 /* 4272 * ServerWorks chipset support functions 4273 */ 4274 int 4275 ata_serverworks_ident(device_t dev) 4276 { 4277 struct ata_pci_controller *ctlr = device_get_softc(dev); 4278 struct ata_chip_id *idx; 4279 static struct ata_chip_id ids[] = 4280 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" }, 4281 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" }, 4282 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" }, 4283 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" }, 4284 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" }, 4285 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" }, 4286 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" }, 4287 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" }, 4288 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" }, 4289 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" }, 4290 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" }, 4291 { 0, 0, 0, 0, 0, 0}}; 4292 char buffer[64]; 4293 4294 if (!(idx = ata_match_chip(dev, ids))) 4295 return ENXIO; 4296 4297 ksprintf(buffer, "ServerWorks %s %s controller", 4298 idx->text, ata_mode2str(idx->max_dma)); 4299 device_set_desc_copy(dev, buffer); 4300 ctlr->chip = idx; 4301 ctlr->chipinit = ata_serverworks_chipinit; 4302 return 0; 4303 } 4304 4305 static int 4306 ata_serverworks_chipinit(device_t dev) 4307 { 4308 struct ata_pci_controller *ctlr = device_get_softc(dev); 4309 4310 if (ata_setup_interrupt(dev)) 4311 return ENXIO; 4312 4313 if (ctlr->chip->cfg1 == SWKSMIO) { 4314 ctlr->r_type2 = SYS_RES_MEMORY; 4315 ctlr->r_rid2 = PCIR_BAR(5); 4316 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4317 &ctlr->r_rid2, RF_ACTIVE))) 4318 return ENXIO; 4319 4320 ctlr->channels = ctlr->chip->cfg2; 4321 ctlr->allocate = ata_serverworks_allocate; 4322 ctlr->setmode = ata_sata_setmode; 4323 return 0; 4324 } 4325 else if (ctlr->chip->cfg1 == SWKS33) { 4326 device_t *children; 4327 int nchildren, i; 4328 4329 /* locate the ISA part in the southbridge and enable UDMA33 */ 4330 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 4331 for (i = 0; i < nchildren; i++) { 4332 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 4333 pci_write_config(children[i], 0x64, 4334 (pci_read_config(children[i], 0x64, 4) & 4335 ~0x00002000) | 0x00004000, 4); 4336 break; 4337 } 4338 } 4339 kfree(children, M_TEMP); 4340 } 4341 } 4342 else { 4343 pci_write_config(dev, 0x5a, 4344 (pci_read_config(dev, 0x5a, 1) & ~0x40) | 4345 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); 4346 } 4347 ctlr->setmode = ata_serverworks_setmode; 4348 return 0; 4349 } 4350 4351 static int 4352 ata_serverworks_allocate(device_t dev) 4353 { 4354 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4355 struct ata_channel *ch = device_get_softc(dev); 4356 int ch_offset; 4357 int i; 4358 4359 ch_offset = ch->unit * 0x100; 4360 4361 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 4362 ch->r_io[i].res = ctlr->r_res2; 4363 4364 /* setup ATA registers */ 4365 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 4366 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 4367 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 4368 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 4369 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 4370 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 4371 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 4372 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 4373 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 4374 ata_default_registers(dev); 4375 4376 /* setup DMA registers */ 4377 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 4378 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 4379 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 4380 4381 /* setup SATA registers */ 4382 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 4383 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 4384 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 4385 4386 ch->flags |= ATA_NO_SLAVE; 4387 ata_pci_hw(dev); 4388 return 0; 4389 } 4390 4391 static void 4392 ata_serverworks_setmode(device_t dev, int mode) 4393 { 4394 device_t gparent = GRANDPARENT(dev); 4395 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4396 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4397 struct ata_device *atadev = device_get_softc(dev); 4398 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4399 int offset = (devno ^ 0x01) << 3; 4400 int error; 4401 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 4402 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 4403 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 4404 4405 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4406 4407 mode = ata_check_80pin(dev, mode); 4408 4409 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4410 4411 if (bootverbose) 4412 device_printf(dev, "%ssetting %s on %s chip\n", 4413 (error) ? "FAILURE " : "", 4414 ata_mode2str(mode), ctlr->chip->text); 4415 if (!error) { 4416 if (mode >= ATA_UDMA0) { 4417 pci_write_config(gparent, 0x56, 4418 (pci_read_config(gparent, 0x56, 2) & 4419 ~(0xf << (devno << 2))) | 4420 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 4421 pci_write_config(gparent, 0x54, 4422 pci_read_config(gparent, 0x54, 1) | 4423 (0x01 << devno), 1); 4424 pci_write_config(gparent, 0x44, 4425 (pci_read_config(gparent, 0x44, 4) & 4426 ~(0xff << offset)) | 4427 (dmatimings[2] << offset), 4); 4428 } 4429 else if (mode >= ATA_WDMA0) { 4430 pci_write_config(gparent, 0x54, 4431 pci_read_config(gparent, 0x54, 1) & 4432 ~(0x01 << devno), 1); 4433 pci_write_config(gparent, 0x44, 4434 (pci_read_config(gparent, 0x44, 4) & 4435 ~(0xff << offset)) | 4436 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 4437 } 4438 else 4439 pci_write_config(gparent, 0x54, 4440 pci_read_config(gparent, 0x54, 1) & 4441 ~(0x01 << devno), 1); 4442 4443 pci_write_config(gparent, 0x40, 4444 (pci_read_config(gparent, 0x40, 4) & 4445 ~(0xff << offset)) | 4446 (piotimings[ata_mode2idx(mode)] << offset), 4); 4447 atadev->mode = mode; 4448 } 4449 } 4450 4451 4452 /* 4453 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 4454 */ 4455 int 4456 ata_sii_ident(device_t dev) 4457 { 4458 struct ata_pci_controller *ctlr = device_get_softc(dev); 4459 struct ata_chip_id *idx; 4460 static struct ata_chip_id ids[] = 4461 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" }, 4462 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" }, 4463 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4464 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, 4465 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" }, 4466 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4467 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" }, 4468 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" }, 4469 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" }, 4470 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, 4471 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, 4472 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, 4473 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, 4474 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, 4475 { 0, 0, 0, 0, 0, 0}}; 4476 char buffer[64]; 4477 4478 if (!(idx = ata_match_chip(dev, ids))) 4479 return ENXIO; 4480 4481 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); 4482 device_set_desc_copy(dev, buffer); 4483 ctlr->chip = idx; 4484 ctlr->chipinit = ata_sii_chipinit; 4485 return 0; 4486 } 4487 4488 static int 4489 ata_sii_chipinit(device_t dev) 4490 { 4491 struct ata_pci_controller *ctlr = device_get_softc(dev); 4492 4493 if (ata_setup_interrupt(dev)) 4494 return ENXIO; 4495 4496 switch (ctlr->chip->cfg1) { 4497 case SIIPRBIO: 4498 ctlr->r_type1 = SYS_RES_MEMORY; 4499 ctlr->r_rid1 = PCIR_BAR(0); 4500 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 4501 &ctlr->r_rid1, RF_ACTIVE))) 4502 return ENXIO; 4503 4504 ctlr->r_rid2 = PCIR_BAR(2); 4505 ctlr->r_type2 = SYS_RES_MEMORY; 4506 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4507 &ctlr->r_rid2, RF_ACTIVE))){ 4508 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1); 4509 return ENXIO; 4510 } 4511 ctlr->allocate = ata_siiprb_allocate; 4512 ctlr->reset = ata_siiprb_reset; 4513 ctlr->dmainit = ata_siiprb_dmainit; 4514 ctlr->setmode = ata_sata_setmode; 4515 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2; 4516 4517 /* reset controller */ 4518 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000); 4519 DELAY(10000); 4520 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f); 4521 4522 /* enable PCI interrupt */ 4523 pci_write_config(dev, PCIR_COMMAND, 4524 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 4525 break; 4526 4527 case SIIMEMIO: 4528 ctlr->r_type2 = SYS_RES_MEMORY; 4529 ctlr->r_rid2 = PCIR_BAR(5); 4530 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 4531 &ctlr->r_rid2, RF_ACTIVE))) 4532 return ENXIO; 4533 4534 if (ctlr->chip->cfg2 & SIISETCLK) { 4535 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4536 pci_write_config(dev, 0x8a, 4537 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 4538 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 4539 device_printf(dev, "%s could not set ATA133 clock\n", 4540 ctlr->chip->text); 4541 } 4542 4543 /* if we have 4 channels enable the second set */ 4544 if (ctlr->chip->cfg2 & SII4CH) { 4545 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 4546 ctlr->channels = 4; 4547 } 4548 4549 /* dont block interrupts from any channel */ 4550 pci_write_config(dev, 0x48, 4551 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 4552 4553 /* enable PCI interrupt as BIOS might not */ 4554 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 4555 4556 ctlr->allocate = ata_sii_allocate; 4557 if (ctlr->chip->max_dma >= ATA_SA150) { 4558 ctlr->reset = ata_sii_reset; 4559 ctlr->setmode = ata_sata_setmode; 4560 } 4561 else 4562 ctlr->setmode = ata_sii_setmode; 4563 break; 4564 4565 default: 4566 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 4567 device_printf(dev, "HW has secondary channel disabled\n"); 4568 ctlr->channels = 1; 4569 } 4570 4571 /* enable interrupt as BIOS might not */ 4572 pci_write_config(dev, 0x71, 0x01, 1); 4573 4574 ctlr->allocate = ata_cmd_allocate; 4575 ctlr->setmode = ata_cmd_setmode; 4576 break; 4577 } 4578 return 0; 4579 } 4580 4581 static int 4582 ata_cmd_allocate(device_t dev) 4583 { 4584 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4585 struct ata_channel *ch = device_get_softc(dev); 4586 4587 /* setup the usual register normal pci style */ 4588 if (ata_pci_allocate(dev)) 4589 return ENXIO; 4590 4591 if (ctlr->chip->cfg2 & SIIINTR) 4592 ch->hw.status = ata_cmd_status; 4593 4594 return 0; 4595 } 4596 4597 static int 4598 ata_cmd_status(device_t dev) 4599 { 4600 struct ata_channel *ch = device_get_softc(dev); 4601 u_int8_t reg71; 4602 4603 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & 4604 (ch->unit ? 0x08 : 0x04))) { 4605 pci_write_config(device_get_parent(ch->dev), 0x71, 4606 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 4607 return ata_pci_status(dev); 4608 } 4609 return 0; 4610 } 4611 4612 static void 4613 ata_cmd_setmode(device_t dev, int mode) 4614 { 4615 device_t gparent = GRANDPARENT(dev); 4616 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4617 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4618 struct ata_device *atadev = device_get_softc(dev); 4619 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 4620 int error; 4621 4622 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4623 4624 mode = ata_check_80pin(dev, mode); 4625 4626 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4627 4628 if (bootverbose) 4629 device_printf(dev, "%ssetting %s on %s chip\n", 4630 (error) ? "FAILURE " : "", 4631 ata_mode2str(mode), ctlr->chip->text); 4632 if (!error) { 4633 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 4634 int ureg = ch->unit ? 0x7b : 0x73; 4635 4636 if (mode >= ATA_UDMA0) { 4637 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, 4638 { 0x11, 0x42 }, { 0x25, 0x8a }, 4639 { 0x15, 0x4a }, { 0x05, 0x0a } }; 4640 4641 u_int8_t umode = pci_read_config(gparent, ureg, 1); 4642 4643 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); 4644 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; 4645 pci_write_config(gparent, ureg, umode, 1); 4646 } 4647 else if (mode >= ATA_WDMA0) { 4648 int dmatimings[] = { 0x87, 0x32, 0x3f }; 4649 4650 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1); 4651 pci_write_config(gparent, ureg, 4652 pci_read_config(gparent, ureg, 1) & 4653 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4654 } 4655 else { 4656 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; 4657 pci_write_config(gparent, treg, 4658 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); 4659 pci_write_config(gparent, ureg, 4660 pci_read_config(gparent, ureg, 1) & 4661 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); 4662 } 4663 atadev->mode = mode; 4664 } 4665 } 4666 4667 static int 4668 ata_sii_allocate(device_t dev) 4669 { 4670 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4671 struct ata_channel *ch = device_get_softc(dev); 4672 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 4673 int i; 4674 4675 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 4676 ch->r_io[i].res = ctlr->r_res2; 4677 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 4678 } 4679 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 4680 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 4681 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 4682 ata_default_registers(dev); 4683 4684 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 4685 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 4686 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 4687 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 4688 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 4689 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 4690 4691 if (ctlr->chip->max_dma >= ATA_SA150) { 4692 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4693 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 4694 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4695 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 4696 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4697 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 4698 ch->flags |= ATA_NO_SLAVE; 4699 4700 /* enable PHY state change interrupt */ 4701 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 4702 } 4703 4704 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) { 4705 /* work around errata in early chips */ 4706 ch->dma->boundary = 16 * DEV_BSIZE; 4707 ch->dma->segsize = 15 * DEV_BSIZE; 4708 } 4709 4710 ata_pci_hw(dev); 4711 ch->hw.status = ata_sii_status; 4712 return 0; 4713 } 4714 4715 static int 4716 ata_sii_status(device_t dev) 4717 { 4718 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4719 struct ata_channel *ch = device_get_softc(dev); 4720 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 4721 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 4722 4723 /* do we have any PHY events ? */ 4724 if (ctlr->chip->max_dma >= ATA_SA150 && 4725 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 4726 ata_sata_phy_check_events(dev); 4727 4728 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 4729 return ata_pci_status(dev); 4730 else 4731 return 0; 4732 } 4733 4734 static void 4735 ata_sii_reset(device_t dev) 4736 { 4737 if (ata_sata_phy_reset(dev)) 4738 ata_generic_reset(dev); 4739 } 4740 4741 static void 4742 ata_sii_setmode(device_t dev, int mode) 4743 { 4744 device_t gparent = GRANDPARENT(dev); 4745 struct ata_pci_controller *ctlr = device_get_softc(gparent); 4746 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 4747 struct ata_device *atadev = device_get_softc(dev); 4748 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1); 4749 int mreg = ch->unit ? 0x84 : 0x80; 4750 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); 4751 int mval = pci_read_config(gparent, mreg, 1) & ~mask; 4752 int error; 4753 4754 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 4755 4756 if (ctlr->chip->cfg2 & SIISETCLK) { 4757 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) & 4758 (ch->unit ? 0x02 : 0x01))) { 4759 ata_print_cable(dev, "controller"); 4760 mode = ATA_UDMA2; 4761 } 4762 } 4763 else 4764 mode = ata_check_80pin(dev, mode); 4765 4766 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 4767 4768 if (bootverbose) 4769 device_printf(dev, "%ssetting %s on %s chip\n", 4770 (error) ? "FAILURE " : "", 4771 ata_mode2str(mode), ctlr->chip->text); 4772 if (error) 4773 return; 4774 4775 if (mode >= ATA_UDMA0) { 4776 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 4777 u_int8_t ureg = 0xac + rego; 4778 4779 pci_write_config(gparent, mreg, 4780 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); 4781 pci_write_config(gparent, ureg, 4782 (pci_read_config(gparent, ureg, 1) & ~0x3f) | 4783 udmatimings[mode & ATA_MODE_MASK], 1); 4784 4785 } 4786 else if (mode >= ATA_WDMA0) { 4787 u_int8_t dreg = 0xa8 + rego; 4788 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 4789 4790 pci_write_config(gparent, mreg, 4791 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); 4792 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 4793 4794 } 4795 else { 4796 u_int8_t preg = 0xa4 + rego; 4797 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 4798 4799 pci_write_config(gparent, mreg, 4800 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); 4801 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2); 4802 } 4803 atadev->mode = mode; 4804 } 4805 4806 struct ata_siiprb_dma_prdentry { 4807 u_int64_t addr; 4808 u_int32_t count; 4809 u_int32_t control; 4810 } __packed; 4811 4812 struct ata_siiprb_ata_command { 4813 u_int32_t reserved0; 4814 struct ata_siiprb_dma_prdentry prd[126]; 4815 } __packed; 4816 4817 struct ata_siiprb_atapi_command { 4818 u_int8_t cdb[16]; 4819 struct ata_siiprb_dma_prdentry prd[125]; 4820 } __packed; 4821 4822 struct ata_siiprb_command { 4823 u_int16_t control; 4824 u_int16_t protocol_override; 4825 u_int32_t transfer_count; 4826 u_int8_t fis[20]; 4827 union { 4828 struct ata_siiprb_ata_command ata; 4829 struct ata_siiprb_atapi_command atapi; 4830 } u; 4831 } __packed; 4832 4833 static int 4834 ata_siiprb_allocate(device_t dev) 4835 { 4836 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4837 struct ata_channel *ch = device_get_softc(dev); 4838 int offset = ch->unit * 0x2000; 4839 4840 /* set the SATA resources */ 4841 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 4842 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset; 4843 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 4844 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset; 4845 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 4846 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset; 4847 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 4848 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset; 4849 4850 ch->hw.begin_transaction = ata_siiprb_begin_transaction; 4851 ch->hw.end_transaction = ata_siiprb_end_transaction; 4852 ch->hw.status = ata_siiprb_status; 4853 ch->hw.command = NULL; /* not used here */ 4854 return 0; 4855 } 4856 4857 static int 4858 ata_siiprb_status(device_t dev) 4859 { 4860 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4861 struct ata_channel *ch = device_get_softc(dev); 4862 int offset = ch->unit * 0x2000; 4863 4864 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) { 4865 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset); 4866 4867 /* do we have any PHY events ? */ 4868 ata_sata_phy_check_events(dev); 4869 4870 /* clear interrupt(s) */ 4871 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus); 4872 4873 /* do we have any device action ? */ 4874 return (istatus & 0x00000001); 4875 } 4876 return 0; 4877 } 4878 4879 static int 4880 ata_siiprb_begin_transaction(struct ata_request *request) 4881 { 4882 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4883 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4884 struct ata_siiprb_command *prb; 4885 int offset = ch->unit * 0x2000; 4886 u_int64_t prb_bus; 4887 int tag = 0, dummy; 4888 4889 /* check for 48 bit access and convert if needed */ 4890 ata_modify_if_48bit(request); 4891 4892 /* get a piece of the workspace for this request */ 4893 prb = (struct ata_siiprb_command *) 4894 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 4895 4896 /* set basic prd options ata/atapi etc etc */ 4897 bzero(prb, sizeof(struct ata_siiprb_command)); 4898 4899 /* setup the FIS for this request */ 4900 if (!ata_request2fis_h2d(request, &prb->fis[0])) { 4901 device_printf(request->dev, "setting up SATA FIS failed\n"); 4902 request->result = EIO; 4903 return ATA_OP_FINISHED; 4904 } 4905 4906 /* if request moves data setup and load SG list */ 4907 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 4908 struct ata_siiprb_dma_prdentry *prd; 4909 4910 if (request->flags & ATA_R_ATAPI) 4911 prd = &prb->u.atapi.prd[0]; 4912 else 4913 prd = &prb->u.ata.prd[0]; 4914 if (ch->dma->load(ch->dev, request->data, request->bytecount, 4915 request->flags & ATA_R_READ, prd, &dummy)) { 4916 device_printf(request->dev, "setting up DMA failed\n"); 4917 request->result = EIO; 4918 return ATA_OP_FINISHED; 4919 } 4920 } 4921 4922 /* activate the prb */ 4923 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 4924 ATA_OUTL(ctlr->r_res2, 4925 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 4926 ATA_OUTL(ctlr->r_res2, 4927 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 4928 4929 /* start the timeout */ 4930 callout_reset(&request->callout, request->timeout * hz, 4931 (timeout_t*)ata_timeout, request); 4932 return ATA_OP_CONTINUES; 4933 } 4934 4935 static int 4936 ata_siiprb_end_transaction(struct ata_request *request) 4937 { 4938 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 4939 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev)); 4940 struct ata_siiprb_command *prb; 4941 int offset = ch->unit * 0x2000; 4942 int error, tag = 0; 4943 4944 /* kill the timeout */ 4945 callout_stop(&request->callout); 4946 4947 prb = (struct ata_siiprb_command *) 4948 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 4949 4950 /* if error status get details */ 4951 request->status = prb->fis[2]; 4952 if (request->status & ATA_S_ERROR) 4953 request->error = prb->fis[3]; 4954 4955 /* update progress */ 4956 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { 4957 if (request->flags & ATA_R_READ) 4958 request->donecount = prb->transfer_count; 4959 else 4960 request->donecount = request->bytecount; 4961 } 4962 4963 /* any controller errors flagged ? */ 4964 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { 4965 kprintf("ata_siiprb_end_transaction %s error=%08x\n", 4966 ata_cmd2str(request), error); 4967 } 4968 4969 /* release SG list etc */ 4970 ch->dma->unload(ch->dev); 4971 4972 return ATA_OP_FINISHED; 4973 } 4974 4975 static void 4976 ata_siiprb_reset(device_t dev) 4977 { 4978 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 4979 struct ata_channel *ch = device_get_softc(dev); 4980 int offset = ch->unit * 0x2000; 4981 struct ata_siiprb_command *prb; 4982 u_int64_t prb_bus; 4983 u_int32_t status, signature; 4984 int timeout, tag = 0; 4985 4986 /* reset channel HW */ 4987 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001); 4988 DELAY(1000); 4989 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001); 4990 DELAY(10000); 4991 4992 /* poll for channel ready */ 4993 for (timeout = 0; timeout < 1000; timeout++) { 4994 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000) 4995 break; 4996 DELAY(1000); 4997 } 4998 if (timeout >= 1000) { 4999 device_printf(ch->dev, "channel HW reset timeout reset failure\n"); 5000 ch->devices = 0; 5001 goto finish; 5002 } 5003 if (bootverbose) 5004 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1); 5005 5006 /* reset phy */ 5007 if (!ata_sata_phy_reset(dev)) { 5008 if (bootverbose) 5009 device_printf(ch->dev, "phy reset found no device\n"); 5010 ch->devices = 0; 5011 goto finish; 5012 } 5013 5014 /* get a piece of the workspace for a soft reset request */ 5015 prb = (struct ata_siiprb_command *) 5016 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag)); 5017 bzero(prb, sizeof(struct ata_siiprb_command)); 5018 prb->control = htole16(0x0080); 5019 5020 /* activate the soft reset prb */ 5021 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag); 5022 ATA_OUTL(ctlr->r_res2, 5023 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus); 5024 ATA_OUTL(ctlr->r_res2, 5025 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32); 5026 5027 /* poll for channel ready */ 5028 for (timeout = 0; timeout < 1000; timeout++) { 5029 DELAY(1000); 5030 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000) 5031 break; 5032 } 5033 if (timeout >= 1000) { 5034 device_printf(ch->dev, "reset timeout - no device found\n"); 5035 ch->devices = 0; 5036 goto finish; 5037 } 5038 if (bootverbose) 5039 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n", 5040 timeout, status); 5041 5042 /* find out whats there */ 5043 prb = (struct ata_siiprb_command *) 5044 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset); 5045 signature = 5046 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24); 5047 if (bootverbose) 5048 device_printf(ch->dev, "signature=%08x\n", signature); 5049 switch (signature) { 5050 case 0xeb140101: 5051 ch->devices = ATA_ATAPI_MASTER; 5052 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n"); 5053 ch->devices = 0; 5054 break; 5055 case 0x96690101: 5056 ch->devices = ATA_PORTMULTIPLIER; 5057 device_printf(ch->dev, "Portmultipliers not supported yet\n"); 5058 ch->devices = 0; 5059 break; 5060 case 0x00000101: 5061 ch->devices = ATA_ATA_MASTER; 5062 break; 5063 default: 5064 ch->devices = 0; 5065 } 5066 5067 finish: 5068 /* clear interrupt(s) */ 5069 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff); 5070 5071 /* require explicit interrupt ack */ 5072 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008); 5073 5074 /* 64bit mode */ 5075 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400); 5076 5077 /* enable interrupts wanted */ 5078 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff); 5079 } 5080 5081 static void 5082 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 5083 { 5084 struct ata_dmasetprd_args *args = xsc; 5085 struct ata_siiprb_dma_prdentry *prd = args->dmatab; 5086 int i; 5087 5088 if ((args->error = error)) 5089 return; 5090 5091 for (i = 0; i < nsegs; i++) { 5092 prd[i].addr = htole64(segs[i].ds_addr); 5093 prd[i].count = htole32(segs[i].ds_len); 5094 } 5095 prd[i - 1].control = htole32(ATA_DMA_EOT); 5096 } 5097 5098 static void 5099 ata_siiprb_dmainit(device_t dev) 5100 { 5101 struct ata_channel *ch = device_get_softc(dev); 5102 5103 ata_dmainit(dev); 5104 if (ch->dma) { 5105 /* note start and stop are not used here */ 5106 ch->dma->setprd = ata_siiprb_dmasetprd; 5107 ch->dma->max_address = BUS_SPACE_MAXADDR; 5108 } 5109 } 5110 5111 5112 /* 5113 * Silicon Integrated Systems Corp. (SiS) chipset support functions 5114 */ 5115 int 5116 ata_sis_ident(device_t dev) 5117 { 5118 struct ata_pci_controller *ctlr = device_get_softc(dev); 5119 struct ata_chip_id *idx; 5120 static struct ata_chip_id ids[] = 5121 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */ 5122 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */ 5123 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */ 5124 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */ 5125 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */ 5126 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */ 5127 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */ 5128 5129 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */ 5130 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */ 5131 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */ 5132 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */ 5133 5134 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */ 5135 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */ 5136 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */ 5137 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */ 5138 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */ 5139 5140 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" }, 5141 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" }, 5142 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" }, 5143 5144 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" }, 5145 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" }, 5146 { 0, 0, 0, 0, 0, 0 }}; 5147 char buffer[64]; 5148 int found = 0; 5149 5150 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev)))) 5151 return ENXIO; 5152 5153 if (idx->cfg2 && !found) { 5154 u_int8_t reg57 = pci_read_config(dev, 0x57, 1); 5155 5156 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1); 5157 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) { 5158 found = 1; 5159 idx->cfg1 = SIS133NEW; 5160 idx->max_dma = ATA_UDMA6; 5161 ksprintf(buffer, "SiS 962/963 %s controller", 5162 ata_mode2str(idx->max_dma)); 5163 } 5164 pci_write_config(dev, 0x57, reg57, 1); 5165 } 5166 if (idx->cfg2 && !found) { 5167 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1); 5168 5169 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1); 5170 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) { 5171 struct ata_chip_id id[] = 5172 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }}; 5173 5174 found = 1; 5175 if (ata_find_chip(dev, id, pci_get_slot(dev))) { 5176 idx->cfg1 = SIS133OLD; 5177 idx->max_dma = ATA_UDMA6; 5178 } 5179 else { 5180 idx->cfg1 = SIS100NEW; 5181 idx->max_dma = ATA_UDMA5; 5182 } 5183 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); 5184 } 5185 pci_write_config(dev, 0x4a, reg4a, 1); 5186 } 5187 if (!found) 5188 ksprintf(buffer,"SiS %s %s controller", 5189 idx->text, ata_mode2str(idx->max_dma)); 5190 5191 device_set_desc_copy(dev, buffer); 5192 ctlr->chip = idx; 5193 ctlr->chipinit = ata_sis_chipinit; 5194 return 0; 5195 } 5196 5197 static int 5198 ata_sis_chipinit(device_t dev) 5199 { 5200 struct ata_pci_controller *ctlr = device_get_softc(dev); 5201 5202 if (ata_setup_interrupt(dev)) 5203 return ENXIO; 5204 5205 switch (ctlr->chip->cfg1) { 5206 case SIS33: 5207 break; 5208 case SIS66: 5209 case SIS100OLD: 5210 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1); 5211 break; 5212 case SIS100NEW: 5213 case SIS133OLD: 5214 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1); 5215 break; 5216 case SIS133NEW: 5217 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2); 5218 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2); 5219 break; 5220 case SISSATA: 5221 ctlr->r_type2 = SYS_RES_IOPORT; 5222 ctlr->r_rid2 = PCIR_BAR(5); 5223 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5224 &ctlr->r_rid2, RF_ACTIVE))) { 5225 ctlr->allocate = ata_sis_allocate; 5226 ctlr->reset = ata_sis_reset; 5227 5228 /* enable PCI interrupt */ 5229 pci_write_config(dev, PCIR_COMMAND, 5230 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5231 } 5232 ctlr->setmode = ata_sata_setmode; 5233 return 0; 5234 default: 5235 return ENXIO; 5236 } 5237 ctlr->setmode = ata_sis_setmode; 5238 return 0; 5239 } 5240 5241 static int 5242 ata_sis_allocate(device_t dev) 5243 { 5244 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5245 struct ata_channel *ch = device_get_softc(dev); 5246 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); 5247 5248 /* setup the usual register normal pci style */ 5249 if (ata_pci_allocate(dev)) 5250 return ENXIO; 5251 5252 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5253 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; 5254 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5255 ch->r_io[ATA_SERROR].offset = 0x04 + offset; 5256 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5257 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; 5258 ch->flags |= ATA_NO_SLAVE; 5259 5260 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ 5261 /* XXX SOS unknown how to enable PHY state change interrupt */ 5262 return 0; 5263 } 5264 5265 static void 5266 ata_sis_reset(device_t dev) 5267 { 5268 if (ata_sata_phy_reset(dev)) 5269 ata_generic_reset(dev); 5270 } 5271 5272 static void 5273 ata_sis_setmode(device_t dev, int mode) 5274 { 5275 device_t gparent = GRANDPARENT(dev); 5276 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5277 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5278 struct ata_device *atadev = device_get_softc(dev); 5279 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5280 int error; 5281 5282 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5283 5284 if (ctlr->chip->cfg1 == SIS133NEW) { 5285 if (mode > ATA_UDMA2 && 5286 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) { 5287 ata_print_cable(dev, "controller"); 5288 mode = ATA_UDMA2; 5289 } 5290 } 5291 else { 5292 if (mode > ATA_UDMA2 && 5293 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) { 5294 ata_print_cable(dev, "controller"); 5295 mode = ATA_UDMA2; 5296 } 5297 } 5298 5299 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5300 5301 if (bootverbose) 5302 device_printf(dev, "%ssetting %s on %s chip\n", 5303 (error) ? "FAILURE " : "", 5304 ata_mode2str(mode), ctlr->chip->text); 5305 if (!error) { 5306 switch (ctlr->chip->cfg1) { 5307 case SIS133NEW: { 5308 u_int32_t timings[] = 5309 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 5310 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 5311 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; 5312 u_int32_t reg; 5313 5314 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); 5315 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4); 5316 break; 5317 } 5318 case SIS133OLD: { 5319 u_int16_t timings[] = 5320 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 5321 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; 5322 5323 u_int16_t reg = 0x40 + (devno << 1); 5324 5325 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5326 break; 5327 } 5328 case SIS100NEW: { 5329 u_int16_t timings[] = 5330 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 5331 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; 5332 u_int16_t reg = 0x40 + (devno << 1); 5333 5334 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5335 break; 5336 } 5337 case SIS100OLD: 5338 case SIS66: 5339 case SIS33: { 5340 u_int16_t timings[] = 5341 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 5342 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; 5343 u_int16_t reg = 0x40 + (devno << 1); 5344 5345 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2); 5346 break; 5347 } 5348 } 5349 atadev->mode = mode; 5350 } 5351 } 5352 5353 5354 /* VIA Technologies Inc. chipset support functions */ 5355 int 5356 ata_via_ident(device_t dev) 5357 { 5358 struct ata_pci_controller *ctlr = device_get_softc(dev); 5359 struct ata_chip_id *idx; 5360 static struct ata_chip_id ids[] = 5361 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" }, 5362 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" }, 5363 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" }, 5364 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" }, 5365 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"}, 5366 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" }, 5367 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" }, 5368 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" }, 5369 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" }, 5370 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" }, 5371 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" }, 5372 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" }, 5373 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" }, 5374 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" }, 5375 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" }, 5376 { 0, 0, 0, 0, 0, 0 }}; 5377 static struct ata_chip_id new_ids[] = 5378 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" }, 5379 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" }, 5380 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" }, 5381 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" }, 5382 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" }, 5383 { 0, 0, 0, 0, 0, 0 }}; 5384 char buffer[64]; 5385 5386 if (pci_get_devid(dev) == ATA_VIA82C571) { 5387 if (!(idx = ata_find_chip(dev, ids, -99))) 5388 return ENXIO; 5389 } 5390 else { 5391 if (!(idx = ata_match_chip(dev, new_ids))) 5392 return ENXIO; 5393 } 5394 5395 ksprintf(buffer, "VIA %s %s controller", 5396 idx->text, ata_mode2str(idx->max_dma)); 5397 device_set_desc_copy(dev, buffer); 5398 ctlr->chip = idx; 5399 ctlr->chipinit = ata_via_chipinit; 5400 return 0; 5401 } 5402 5403 static int 5404 ata_via_chipinit(device_t dev) 5405 { 5406 struct ata_pci_controller *ctlr = device_get_softc(dev); 5407 5408 if (ata_setup_interrupt(dev)) 5409 return ENXIO; 5410 5411 if (ctlr->chip->max_dma >= ATA_SA150) { 5412 if (ctlr->chip->cfg2 == VIAAHCI) { 5413 ctlr->r_type2 = SYS_RES_MEMORY; 5414 ctlr->r_rid2 = PCIR_BAR(5); 5415 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5416 &ctlr->r_rid2, 5417 RF_ACTIVE))) { 5418 return ata_ahci_chipinit(dev); 5419 } 5420 } 5421 ctlr->r_type2 = SYS_RES_IOPORT; 5422 ctlr->r_rid2 = PCIR_BAR(5); 5423 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 5424 &ctlr->r_rid2, RF_ACTIVE))) { 5425 ctlr->allocate = ata_via_allocate; 5426 ctlr->reset = ata_via_reset; 5427 5428 /* enable PCI interrupt */ 5429 pci_write_config(dev, PCIR_COMMAND, 5430 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2); 5431 } 5432 5433 if (ctlr->chip->cfg2 & VIABAR) { 5434 ctlr->channels = 3; 5435 ctlr->setmode = ata_via_setmode; 5436 } 5437 else 5438 ctlr->setmode = ata_sata_setmode; 5439 return 0; 5440 } 5441 5442 /* prepare for ATA-66 on the 82C686a and 82C596b */ 5443 if (ctlr->chip->cfg2 & VIACLK) 5444 pci_write_config(dev, 0x50, 0x030b030b, 4); 5445 5446 /* the southbridge might need the data corruption fix */ 5447 if (ctlr->chip->cfg2 & VIABUG) 5448 ata_via_southbridge_fixup(dev); 5449 5450 /* set fifo configuration half'n'half */ 5451 pci_write_config(dev, 0x43, 5452 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); 5453 5454 /* set status register read retry */ 5455 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); 5456 5457 /* set DMA read & end-of-sector fifo flush */ 5458 pci_write_config(dev, 0x46, 5459 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); 5460 5461 /* set sector size */ 5462 pci_write_config(dev, 0x60, DEV_BSIZE, 2); 5463 pci_write_config(dev, 0x68, DEV_BSIZE, 2); 5464 5465 ctlr->setmode = ata_via_family_setmode; 5466 return 0; 5467 } 5468 5469 static int 5470 ata_via_allocate(device_t dev) 5471 { 5472 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5473 struct ata_channel *ch = device_get_softc(dev); 5474 5475 /* newer SATA chips has resources in one BAR for each channel */ 5476 if (ctlr->chip->cfg2 & VIABAR) { 5477 struct resource *r_io; 5478 int i, rid; 5479 5480 rid = PCIR_BAR(ch->unit); 5481 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), 5482 SYS_RES_IOPORT, 5483 &rid, RF_ACTIVE))) 5484 return ENXIO; 5485 5486 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { 5487 ch->r_io[i].res = r_io; 5488 ch->r_io[i].offset = i; 5489 } 5490 ch->r_io[ATA_CONTROL].res = r_io; 5491 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; 5492 ch->r_io[ATA_IDX_ADDR].res = r_io; 5493 ata_default_registers(dev); 5494 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { 5495 ch->r_io[i].res = ctlr->r_res1; 5496 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); 5497 } 5498 ata_pci_hw(dev); 5499 if (ch->unit > 1) 5500 return 0; 5501 } 5502 else { 5503 /* setup the usual register normal pci style */ 5504 if (ata_pci_allocate(dev)) 5505 return ENXIO; 5506 } 5507 5508 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 5509 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); 5510 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 5511 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); 5512 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 5513 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); 5514 ch->flags |= ATA_NO_SLAVE; 5515 5516 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ 5517 /* XXX SOS unknown how to enable PHY state change interrupt */ 5518 return 0; 5519 } 5520 5521 static void 5522 ata_via_reset(device_t dev) 5523 { 5524 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5525 struct ata_channel *ch = device_get_softc(dev); 5526 5527 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) 5528 ata_generic_reset(dev); 5529 else 5530 if (ata_sata_phy_reset(dev)) 5531 ata_generic_reset(dev); 5532 } 5533 5534 static void 5535 ata_via_setmode(device_t dev, int mode) 5536 { 5537 device_t gparent = GRANDPARENT(dev); 5538 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5539 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5540 struct ata_device *atadev = device_get_softc(dev); 5541 int error; 5542 5543 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { 5544 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20, 5545 0x65, 0x32, 0x20, 5546 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5547 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 }; 5548 5549 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6)); 5550 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5551 if (bootverbose) 5552 device_printf(dev, "%ssetting %s on %s chip\n", 5553 (error) ? "FAILURE " : "", ata_mode2str(mode), 5554 ctlr->chip->text); 5555 if (!error) { 5556 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1); 5557 if (mode >= ATA_UDMA0) 5558 pci_write_config(gparent, 0xb3, 5559 dma_timings[mode & ATA_MODE_MASK], 1); 5560 atadev->mode = mode; 5561 } 5562 } 5563 else 5564 ata_sata_setmode(dev, mode); 5565 } 5566 5567 static void 5568 ata_via_southbridge_fixup(device_t dev) 5569 { 5570 device_t *children; 5571 int nchildren, i; 5572 5573 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5574 return; 5575 5576 for (i = 0; i < nchildren; i++) { 5577 if (pci_get_devid(children[i]) == ATA_VIA8363 || 5578 pci_get_devid(children[i]) == ATA_VIA8371 || 5579 pci_get_devid(children[i]) == ATA_VIA8662 || 5580 pci_get_devid(children[i]) == ATA_VIA8361) { 5581 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); 5582 5583 if ((reg76 & 0xf0) != 0xd0) { 5584 device_printf(dev, 5585 "Correcting VIA config for southbridge data corruption bug\n"); 5586 pci_write_config(children[i], 0x75, 0x80, 1); 5587 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); 5588 } 5589 break; 5590 } 5591 } 5592 kfree(children, M_TEMP); 5593 } 5594 5595 5596 /* common code for VIA, AMD & nVidia */ 5597 static void 5598 ata_via_family_setmode(device_t dev, int mode) 5599 { 5600 device_t gparent = GRANDPARENT(dev); 5601 struct ata_pci_controller *ctlr = device_get_softc(gparent); 5602 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5603 struct ata_device *atadev = device_get_softc(dev); 5604 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20, 5605 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; 5606 int modes[][7] = { 5607 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 5608 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 5609 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 5610 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 5611 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 5612 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit); 5613 int reg = 0x53 - devno; 5614 int error; 5615 5616 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 5617 5618 if (ctlr->chip->cfg2 & AMDCABLE) { 5619 if (mode > ATA_UDMA2 && 5620 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) { 5621 ata_print_cable(dev, "controller"); 5622 mode = ATA_UDMA2; 5623 } 5624 } 5625 else 5626 mode = ata_check_80pin(dev, mode); 5627 5628 if (ctlr->chip->cfg2 & NVIDIA) 5629 reg += 0x10; 5630 5631 if (ctlr->chip->cfg1 != VIA133) 5632 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1); 5633 5634 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); 5635 5636 if (bootverbose) 5637 device_printf(dev, "%ssetting %s on %s chip\n", 5638 (error) ? "FAILURE " : "", ata_mode2str(mode), 5639 ctlr->chip->text); 5640 if (!error) { 5641 if (mode >= ATA_UDMA0) 5642 pci_write_config(gparent, reg, 5643 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); 5644 else 5645 pci_write_config(gparent, reg, 0x8b, 1); 5646 atadev->mode = mode; 5647 } 5648 } 5649 5650 5651 /* misc functions */ 5652 static struct ata_chip_id * 5653 ata_match_chip(device_t dev, struct ata_chip_id *index) 5654 { 5655 while (index->chipid != 0) { 5656 if (pci_get_devid(dev) == index->chipid && 5657 pci_get_revid(dev) >= index->chiprev) 5658 return index; 5659 index++; 5660 } 5661 return NULL; 5662 } 5663 5664 static struct ata_chip_id * 5665 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) 5666 { 5667 device_t *children; 5668 int nchildren, i; 5669 5670 if (device_get_children(device_get_parent(dev), &children, &nchildren)) 5671 return 0; 5672 5673 while (index->chipid != 0) { 5674 for (i = 0; i < nchildren; i++) { 5675 if (((slot >= 0 && pci_get_slot(children[i]) == slot) || 5676 (slot < 0 && pci_get_slot(children[i]) <= -slot)) && 5677 pci_get_devid(children[i]) == index->chipid && 5678 pci_get_revid(children[i]) >= index->chiprev) { 5679 kfree(children, M_TEMP); 5680 return index; 5681 } 5682 } 5683 index++; 5684 } 5685 kfree(children, M_TEMP); 5686 return NULL; 5687 } 5688 5689 static int 5690 ata_setup_interrupt(device_t dev) 5691 { 5692 struct ata_pci_controller *ctlr = device_get_softc(dev); 5693 int rid = ATA_IRQ_RID; 5694 5695 if (!ata_legacy(dev)) { 5696 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 5697 RF_SHAREABLE | RF_ACTIVE))) { 5698 device_printf(dev, "unable to map interrupt\n"); 5699 return ENXIO; 5700 } 5701 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, 5702 ata_generic_intr, ctlr, &ctlr->handle, NULL))) { 5703 device_printf(dev, "unable to setup interrupt\n"); 5704 return ENXIO; 5705 } 5706 } 5707 return 0; 5708 } 5709 5710 struct ata_serialize { 5711 struct spinlock locked_mtx; 5712 int locked_ch; 5713 int restart_ch; 5714 }; 5715 5716 static int 5717 ata_serialize(device_t dev, int flags) 5718 { 5719 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 5720 struct ata_channel *ch = device_get_softc(dev); 5721 struct ata_serialize *serial; 5722 static int inited = 0; 5723 int res; 5724 5725 if (!inited) { 5726 serial = kmalloc(sizeof(struct ata_serialize), 5727 M_TEMP, M_INTWAIT | M_ZERO); 5728 spin_init(&serial->locked_mtx); 5729 serial->locked_ch = -1; 5730 serial->restart_ch = -1; 5731 device_set_ivars(ctlr->dev, serial); 5732 inited = 1; 5733 } 5734 else 5735 serial = device_get_ivars(ctlr->dev); 5736 5737 spin_lock_wr(&serial->locked_mtx); 5738 switch (flags) { 5739 case ATA_LF_LOCK: 5740 if (serial->locked_ch == -1) 5741 serial->locked_ch = ch->unit; 5742 if (serial->locked_ch != ch->unit) 5743 serial->restart_ch = ch->unit; 5744 break; 5745 5746 case ATA_LF_UNLOCK: 5747 if (serial->locked_ch == ch->unit) { 5748 serial->locked_ch = -1; 5749 if (serial->restart_ch != -1) { 5750 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) { 5751 serial->restart_ch = -1; 5752 spin_unlock_wr(&serial->locked_mtx); 5753 ata_start(ch->dev); 5754 return -1; 5755 } 5756 } 5757 } 5758 break; 5759 5760 case ATA_LF_WHICH: 5761 break; 5762 } 5763 res = serial->locked_ch; 5764 spin_unlock_wr(&serial->locked_mtx); 5765 return res; 5766 } 5767 5768 static void 5769 ata_print_cable(device_t dev, u_int8_t *who) 5770 { 5771 device_printf(dev, 5772 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who); 5773 } 5774 5775 static int 5776 ata_atapi(device_t dev) 5777 { 5778 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 5779 struct ata_device *atadev = device_get_softc(dev); 5780 5781 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 5782 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)); 5783 } 5784 5785 static int 5786 ata_check_80pin(device_t dev, int mode) 5787 { 5788 struct ata_device *atadev = device_get_softc(dev); 5789 5790 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) { 5791 ata_print_cable(dev, "device"); 5792 mode = ATA_UDMA2; 5793 } 5794 return mode; 5795 } 5796 5797 static int 5798 ata_mode2idx(int mode) 5799 { 5800 if ((mode & ATA_DMA_MASK) == ATA_UDMA0) 5801 return (mode & ATA_MODE_MASK) + 8; 5802 if ((mode & ATA_DMA_MASK) == ATA_WDMA0) 5803 return (mode & ATA_MODE_MASK) + 5; 5804 return (mode & ATA_MODE_MASK) - ATA_PIO0; 5805 } 5806