1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* local prototypes */ 28 static int ata_highpoint_chipinit(device_t dev); 29 static int ata_highpoint_allocate(device_t dev); 30 static void ata_highpoint_setmode(device_t dev, int mode); 31 static int ata_highpoint_check_80pin(device_t dev, int mode); 32 33 /* misc defines */ 34 #define HPT_366 0 35 #define HPT_370 1 36 #define HPT_372 2 37 #define HPT_374 3 38 #define HPT_OLD 0x01 39 40 /* 41 * HighPoint chipset support functions 42 */ 43 int 44 ata_highpoint_ident(device_t dev) 45 { 46 struct ata_pci_controller *ctlr = device_get_softc(dev); 47 const struct ata_chip_id *idx; 48 static const struct ata_chip_id ids[] = 49 {{ ATA_HPT374, 0x07, HPT_374, 0x00, ATA_UDMA6, "HPT374" }, 50 { ATA_HPT372, 0x02, HPT_372, 0x00, ATA_UDMA6, "HPT372N" }, 51 { ATA_HPT372, 0x01, HPT_372, 0x00, ATA_UDMA6, "HPT372" }, 52 { ATA_HPT371, 0x01, HPT_372, 0x00, ATA_UDMA6, "HPT371" }, 53 { ATA_HPT366, 0x05, HPT_372, 0x00, ATA_UDMA6, "HPT372" }, 54 { ATA_HPT366, 0x03, HPT_370, 0x00, ATA_UDMA5, "HPT370" }, 55 { ATA_HPT366, 0x02, HPT_366, 0x00, ATA_UDMA4, "HPT368" }, 56 { ATA_HPT366, 0x00, HPT_366, HPT_OLD, ATA_UDMA4, "HPT366" }, 57 { ATA_HPT302, 0x01, HPT_372, 0x00, ATA_UDMA6, "HPT302" }, 58 { 0, 0, 0, 0, 0, 0}}; 59 char buffer[64]; 60 61 if (pci_get_vendor(dev) != ATA_HIGHPOINT_ID) 62 return ENXIO; 63 64 if (!(idx = ata_match_chip(dev, ids))) 65 return ENXIO; 66 67 strcpy(buffer, "HighPoint "); 68 strcat(buffer, idx->text); 69 if (idx->cfg1 == HPT_374) { 70 if (pci_get_function(dev) == 0) 71 strcat(buffer, " (channel 0+1)"); 72 if (pci_get_function(dev) == 1) 73 strcat(buffer, " (channel 2+3)"); 74 } 75 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 76 device_set_desc_copy(dev, buffer); 77 ctlr->chip = idx; 78 ctlr->chipinit = ata_highpoint_chipinit; 79 return 0; 80 } 81 82 static int 83 ata_highpoint_chipinit(device_t dev) 84 { 85 struct ata_pci_controller *ctlr = device_get_softc(dev); 86 87 if (ata_setup_interrupt(dev, ata_generic_intr)) 88 return ENXIO; 89 90 if (ctlr->chip->cfg2 == HPT_OLD) { 91 /* disable interrupt prediction */ 92 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); 93 } 94 else { 95 /* disable interrupt prediction */ 96 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); 97 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); 98 99 /* enable interrupts */ 100 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); 101 102 /* set clocks etc */ 103 if (ctlr->chip->cfg1 < HPT_372) 104 pci_write_config(dev, 0x5b, 0x22, 1); 105 else 106 pci_write_config(dev, 0x5b, 107 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); 108 } 109 ctlr->allocate = ata_highpoint_allocate; 110 ctlr->setmode = ata_highpoint_setmode; 111 return 0; 112 } 113 114 static int 115 ata_highpoint_allocate(device_t dev) 116 { 117 struct ata_channel *ch = device_get_softc(dev); 118 119 /* setup the usual register normal pci style */ 120 if (ata_pci_allocate(dev)) 121 return ENXIO; 122 123 ch->flags |= ATA_ALWAYS_DMASTAT; 124 return 0; 125 } 126 127 static void 128 ata_highpoint_setmode(device_t dev, int mode) 129 { 130 device_t gparent = GRANDPARENT(dev); 131 struct ata_pci_controller *ctlr = device_get_softc(gparent); 132 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 133 struct ata_device *atadev = device_get_softc(dev); 134 int devno = (ch->unit << 1) + atadev->unit; 135 int error; 136 static const uint32_t timings33[][4] = { 137 /* HPT366 HPT370 HPT372 HPT374 mode */ 138 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ 139 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ 140 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ 141 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ 142 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ 143 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ 144 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ 145 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ 146 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */ 147 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */ 148 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */ 149 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */ 150 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */ 151 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */ 152 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */ 153 }; 154 155 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); 156 157 if (ctlr->chip->cfg1 == HPT_366 && ata_atapi(dev)) 158 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX); 159 160 mode = ata_highpoint_check_80pin(dev, mode); 161 162 /* 163 * most if not all HPT chips cant really handle that the device is 164 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to 165 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance 166 */ 167 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, 168 ata_limit_mode(dev, mode, ATA_UDMA5)); 169 if (bootverbose) 170 device_printf(dev, "%ssetting %s on HighPoint chip\n", 171 (error) ? "FAILURE " : "", ata_mode2str(mode)); 172 if (!error) 173 pci_write_config(gparent, 0x40 + (devno << 2), 174 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 175 atadev->mode = mode; 176 } 177 178 static int 179 ata_highpoint_check_80pin(device_t dev, int mode) 180 { 181 device_t gparent = GRANDPARENT(dev); 182 struct ata_pci_controller *ctlr = device_get_softc(gparent); 183 struct ata_channel *ch = device_get_softc(device_get_parent(dev)); 184 u_int8_t reg, val, res; 185 186 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(gparent) == 1) { 187 reg = ch->unit ? 0x57 : 0x53; 188 val = pci_read_config(gparent, reg, 1); 189 pci_write_config(gparent, reg, val | 0x80, 1); 190 } 191 else { 192 reg = 0x5b; 193 val = pci_read_config(gparent, reg, 1); 194 pci_write_config(gparent, reg, val & 0xfe, 1); 195 } 196 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2); 197 pci_write_config(gparent, reg, val, 1); 198 199 if (mode > ATA_UDMA2 && res) { 200 ata_print_cable(dev, "controller"); 201 mode = ATA_UDMA2; 202 } 203 return mode; 204 } 205