1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/callout.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/spinlock.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <bus/mmc/bridge.h> 43 #include <bus/mmc/mmcreg.h> 44 #include <bus/mmc/mmcbrvar.h> 45 46 #include "mmcbr_if.h" 47 #include "sdhci.h" 48 #include "sdhci_if.h" 49 50 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 51 52 int sdhci_debug = 0; 53 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 54 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 55 56 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 57 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 58 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 59 #define RD_MULTI_4(slot, off, ptr, count) \ 60 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 61 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 62 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 63 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 64 #define WR_MULTI_4(slot, off, ptr, count) \ 65 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 66 67 static int slot_printf(struct sdhci_slot *, const char *, ...) 68 __printflike(2, 3); 69 70 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 71 static void sdhci_start(struct sdhci_slot *slot); 72 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 73 74 static void sdhci_card_task(void *, int); 75 76 /* helper routines */ 77 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE) 78 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE) 79 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE) 80 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock); 81 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0); 82 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0); 83 84 #define SDHCI_DEFAULT_MAX_FREQ 50 85 86 #define SDHCI_200_MAX_DIVIDER 256 87 #define SDHCI_300_MAX_DIVIDER 2046 88 89 /* 90 * Broadcom BCM577xx Controller Constants 91 */ 92 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Maximum divider supported by the default clock source. */ 93 #define BCM577XX_ALT_CLOCK_BASE 63000000 /* Alternative clock's base frequency. */ 94 95 #define BCM577XX_HOST_CONTROL 0x198 96 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 97 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 98 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 99 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 100 101 static int 102 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 103 { 104 __va_list ap; 105 int retval; 106 107 retval = kprintf("%s-slot%d: ", 108 device_get_nameunit(slot->bus), slot->num); 109 110 __va_start(ap, fmt); 111 retval += kvprintf(fmt, ap); 112 __va_end(ap); 113 return (retval); 114 } 115 116 static void 117 sdhci_dumpregs(struct sdhci_slot *slot) 118 { 119 slot_printf(slot, 120 "============== REGISTER DUMP ==============\n"); 121 122 slot_printf(slot, "SDMA addr: 0x%08x | Version: 0x%08x\n", 123 RD4(slot, SDHCI_SDMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 124 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 125 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 126 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 127 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 128 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 129 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 130 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 131 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 132 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 133 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 134 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 135 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 136 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 137 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 138 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n", 139 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 140 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 141 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 142 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 143 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 144 slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n", 145 RD4(slot, SDHCI_ADMA_ADDRESS_LOW), RD2(slot, SDHCI_SLOT_INT_STATUS)); 146 147 slot_printf(slot, 148 "===========================================\n"); 149 } 150 151 static void 152 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 153 { 154 int timeout; 155 156 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 157 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 158 return; 159 } 160 161 /* Some controllers need this kick or reset won't work. */ 162 if ((mask & SDHCI_RESET_ALL) == 0 && 163 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 164 uint32_t clock; 165 166 /* This is to force an update */ 167 clock = slot->clock; 168 slot->clock = 0; 169 sdhci_set_clock(slot, clock); 170 } 171 172 if (mask & SDHCI_RESET_ALL) { 173 slot->clock = 0; 174 slot->power = 0; 175 } 176 177 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 178 179 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 180 /* 181 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 182 * specification. The reset bit has internal propagation delay, 183 * so a fast read after write returns 0 even if reset process is 184 * in progress. The workaround is to poll for 1 before polling 185 * for 0. In the worst case, if we miss seeing it asserted the 186 * time we spent waiting is enough to ensure the reset finishes. 187 */ 188 timeout = 10000; 189 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 190 if (timeout <= 0) 191 break; 192 timeout--; 193 DELAY(1); 194 } 195 } 196 197 /* Wait max 100 ms */ 198 timeout = 10000; 199 /* Controller clears the bits when it's done */ 200 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 201 if (timeout <= 0) { 202 slot_printf(slot, "Reset 0x%x never completed.\n", 203 mask); 204 sdhci_dumpregs(slot); 205 return; 206 } 207 timeout--; 208 DELAY(10); 209 } 210 } 211 212 static void 213 sdhci_init(struct sdhci_slot *slot) 214 { 215 216 sdhci_reset(slot, SDHCI_RESET_ALL); 217 218 /* Enable interrupts. */ 219 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 220 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 221 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 222 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 223 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 224 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 225 SDHCI_INT_ACMD12ERR; 226 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 227 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 228 } 229 230 static void 231 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 232 { 233 uint32_t clk_base; 234 uint32_t clk_sel; 235 uint32_t res; 236 uint16_t clk; 237 uint16_t div; 238 int timeout; 239 240 if (clock == slot->clock) 241 return; 242 slot->clock = clock; 243 244 /* Turn off the clock. */ 245 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 246 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 247 /* If no clock requested - left it so. */ 248 if (clock == 0) 249 return; 250 251 /* Determine the clock base frequency */ 252 clk_base = slot->max_clk; 253 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 254 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK; 255 256 /* Select clock source appropriate for the requested frequency. */ 257 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 258 clk_base = BCM577XX_ALT_CLOCK_BASE; 259 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT); 260 } else { 261 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT); 262 } 263 264 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 265 } 266 267 /* Recalculate timeout clock frequency based on the new sd clock. */ 268 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 269 slot->timeout_clk = slot->clock / 1000; 270 271 if (slot->version < SDHCI_SPEC_300) { 272 /* Looking for highest freq <= clock. */ 273 res = clk_base; 274 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 275 if (res <= clock) 276 break; 277 res >>= 1; 278 } 279 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 280 div >>= 1; 281 } 282 else { 283 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 284 if (clock >= clk_base) 285 div = 0; 286 else { 287 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 288 if ((clk_base / div) <= clock) 289 break; 290 } 291 } 292 div >>= 1; 293 } 294 295 if (bootverbose || sdhci_debug) 296 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 297 div, clock, clk_base); 298 299 /* Now we have got divider, set it. */ 300 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 301 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 302 << SDHCI_DIVIDER_HI_SHIFT; 303 304 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 305 /* Enable clock. */ 306 clk |= SDHCI_CLOCK_INT_EN; 307 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 308 /* Wait up to 10 ms until it stabilize. */ 309 timeout = 10; 310 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 311 & SDHCI_CLOCK_INT_STABLE)) { 312 if (timeout == 0) { 313 slot_printf(slot, 314 "Internal clock never stabilised.\n"); 315 sdhci_dumpregs(slot); 316 return; 317 } 318 timeout--; 319 DELAY(1000); 320 } 321 /* Pass clock signal to the bus. */ 322 clk |= SDHCI_CLOCK_CARD_EN; 323 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 324 } 325 326 static void 327 sdhci_set_power(struct sdhci_slot *slot, u_char power) 328 { 329 uint8_t pwr; 330 331 if (slot->power == power) 332 return; 333 334 slot->power = power; 335 336 /* Turn off the power. */ 337 pwr = 0; 338 WR1(slot, SDHCI_POWER_CONTROL, pwr); 339 /* If power down requested - left it so. */ 340 if (power == 0) 341 return; 342 /* Set voltage. */ 343 switch (1 << power) { 344 case MMC_OCR_LOW_VOLTAGE: 345 pwr |= SDHCI_POWER_180; 346 break; 347 case MMC_OCR_290_300: 348 case MMC_OCR_300_310: 349 pwr |= SDHCI_POWER_300; 350 break; 351 case MMC_OCR_320_330: 352 case MMC_OCR_330_340: 353 pwr |= SDHCI_POWER_330; 354 break; 355 } 356 WR1(slot, SDHCI_POWER_CONTROL, pwr); 357 /* Turn on the power. */ 358 pwr |= SDHCI_POWER_ON; 359 WR1(slot, SDHCI_POWER_CONTROL, pwr); 360 } 361 362 static void 363 sdhci_read_block_pio(struct sdhci_slot *slot) 364 { 365 uint32_t data; 366 char *buffer; 367 size_t left; 368 369 buffer = slot->curcmd->data->data; 370 buffer += slot->offset; 371 /* Transfer one block at a time. */ 372 left = min(512, slot->curcmd->data->len - slot->offset); 373 slot->offset += left; 374 375 /* If we are too fast, broken controllers return zeroes. */ 376 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 377 DELAY(10); 378 /* Handle unaligned and aligned buffer cases. */ 379 if ((intptr_t)buffer & 3) { 380 while (left > 3) { 381 data = RD4(slot, SDHCI_BUFFER); 382 buffer[0] = data; 383 buffer[1] = (data >> 8); 384 buffer[2] = (data >> 16); 385 buffer[3] = (data >> 24); 386 buffer += 4; 387 left -= 4; 388 } 389 } else { 390 RD_MULTI_4(slot, SDHCI_BUFFER, 391 (uint32_t *)buffer, left >> 2); 392 left &= 3; 393 } 394 /* Handle uneven size case. */ 395 if (left > 0) { 396 data = RD4(slot, SDHCI_BUFFER); 397 while (left > 0) { 398 *(buffer++) = data; 399 data >>= 8; 400 left--; 401 } 402 } 403 } 404 405 static void 406 sdhci_write_block_pio(struct sdhci_slot *slot) 407 { 408 uint32_t data = 0; 409 char *buffer; 410 size_t left; 411 412 buffer = slot->curcmd->data->data; 413 buffer += slot->offset; 414 /* Transfer one block at a time. */ 415 left = min(512, slot->curcmd->data->len - slot->offset); 416 slot->offset += left; 417 418 /* Handle unaligned and aligned buffer cases. */ 419 if ((intptr_t)buffer & 3) { 420 while (left > 3) { 421 data = buffer[0] + 422 (buffer[1] << 8) + 423 (buffer[2] << 16) + 424 (buffer[3] << 24); 425 left -= 4; 426 buffer += 4; 427 WR4(slot, SDHCI_BUFFER, data); 428 } 429 } else { 430 WR_MULTI_4(slot, SDHCI_BUFFER, 431 (uint32_t *)buffer, left >> 2); 432 left &= 3; 433 } 434 /* Handle uneven size case. */ 435 if (left > 0) { 436 while (left > 0) { 437 data <<= 8; 438 data += *(buffer++); 439 left--; 440 } 441 WR4(slot, SDHCI_BUFFER, data); 442 } 443 } 444 445 static void 446 sdhci_transfer_pio(struct sdhci_slot *slot) 447 { 448 449 /* Read as many blocks as possible. */ 450 if (slot->curcmd->data->flags & MMC_DATA_READ) { 451 while (RD4(slot, SDHCI_PRESENT_STATE) & 452 SDHCI_DATA_AVAILABLE) { 453 sdhci_read_block_pio(slot); 454 if (slot->offset >= slot->curcmd->data->len) 455 break; 456 } 457 } else { 458 while (RD4(slot, SDHCI_PRESENT_STATE) & 459 SDHCI_SPACE_AVAILABLE) { 460 sdhci_write_block_pio(slot); 461 if (slot->offset >= slot->curcmd->data->len) 462 break; 463 } 464 } 465 } 466 467 static void 468 sdhci_card_delay(void *arg) 469 { 470 struct sdhci_slot *slot = arg; 471 472 taskqueue_enqueue(taskqueue_swi_mp, &slot->card_task); 473 } 474 475 static void 476 sdhci_card_task(void *arg, int pending) 477 { 478 struct sdhci_slot *slot = arg; 479 480 SDHCI_LOCK(slot); 481 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 482 if (slot->dev == NULL) { 483 /* If card is present - attach mmc bus. */ 484 slot->dev = device_add_child(slot->bus, "mmc", -1); 485 device_set_ivars(slot->dev, slot); 486 SDHCI_UNLOCK(slot); 487 device_probe_and_attach(slot->dev); 488 } else 489 SDHCI_UNLOCK(slot); 490 } else { 491 if (slot->dev != NULL) { 492 /* If no card present - detach mmc bus. */ 493 device_t d = slot->dev; 494 slot->dev = NULL; 495 SDHCI_UNLOCK(slot); 496 device_delete_child(slot->bus, d); 497 } else 498 SDHCI_UNLOCK(slot); 499 } 500 } 501 502 int 503 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 504 { 505 uint32_t caps, freq; 506 int err; 507 508 SDHCI_LOCK_INIT(slot); 509 slot->num = num; 510 slot->bus = dev; 511 512 /* Allocate DMA memory for SDMA. */ 513 err = bus_dmamem_coherent(bus_get_dma_tag(dev), 514 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 515 BUS_SPACE_MAXADDR, DMA_BLOCK_SIZE, BUS_DMA_NOWAIT, 516 &slot->sdma_mem); 517 if (err != 0) { 518 device_printf(dev, "Can't alloc DMA memory for SDMA\n"); 519 SDHCI_LOCK_DESTROY(slot); 520 return (err); 521 } 522 523 /* Initialize slot. */ 524 sdhci_init(slot); 525 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 526 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 527 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 528 caps = slot->caps; 529 else 530 caps = RD4(slot, SDHCI_CAPABILITIES); 531 /* Calculate base clock frequency. */ 532 if (slot->version >= SDHCI_SPEC_300) 533 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 534 SDHCI_CLOCK_BASE_SHIFT; 535 else 536 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 537 SDHCI_CLOCK_BASE_SHIFT; 538 if (freq != 0) 539 slot->max_clk = freq * 1000000; 540 /* 541 * If the frequency wasn't in the capabilities and the hardware driver 542 * hasn't already set max_clk we're probably not going to work right 543 * with an assumption, so complain about it. 544 */ 545 if (slot->max_clk == 0) { 546 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 547 device_printf(dev, "Hardware doesn't specify base clock " 548 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 549 } 550 /* Calculate timeout clock frequency. */ 551 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 552 slot->timeout_clk = slot->max_clk / 1000; 553 } else { 554 slot->timeout_clk = 555 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 556 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 557 slot->timeout_clk *= 1000; 558 } 559 /* 560 * If the frequency wasn't in the capabilities and the hardware driver 561 * hasn't already set timeout_clk we'll probably work okay using the 562 * max timeout, but still mention it. 563 */ 564 if (slot->timeout_clk == 0) { 565 device_printf(dev, "Hardware doesn't specify timeout clock " 566 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 567 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 568 } 569 570 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 571 slot->host.f_max = slot->max_clk; 572 slot->host.host_ocr = 0; 573 if (caps & SDHCI_CAN_VDD_330) 574 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 575 if (caps & SDHCI_CAN_VDD_300) 576 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 577 if (caps & SDHCI_CAN_VDD_180) 578 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 579 if (slot->host.host_ocr == 0) { 580 device_printf(dev, "Hardware doesn't report any " 581 "support voltages.\n"); 582 } 583 slot->host.caps = MMC_CAP_4_BIT_DATA; 584 if (caps & SDHCI_CAN_DO_8BITBUS) 585 slot->host.caps |= MMC_CAP_8_BIT_DATA; 586 if (caps & SDHCI_CAN_DO_HISPD) 587 slot->host.caps |= MMC_CAP_HSPEED; 588 /* Decide if we have usable DMA. */ 589 if (caps & SDHCI_CAN_DO_DMA) 590 slot->opt |= SDHCI_HAVE_SDMA; 591 592 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 593 slot->opt &= ~SDHCI_HAVE_SDMA; 594 if (slot->quirks & SDHCI_QUIRK_FORCE_SDMA) 595 slot->opt |= SDHCI_HAVE_SDMA; 596 597 /* 598 * Use platform-provided transfer backend 599 * with PIO as a fallback mechanism 600 */ 601 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 602 slot->opt &= ~SDHCI_HAVE_SDMA; 603 604 if (bootverbose || sdhci_debug) { 605 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n", 606 slot->max_clk / 1000000, 607 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 608 (slot->host.caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 609 ((slot->host.caps & MMC_CAP_4_BIT_DATA) ? "4bits" : 610 "1bit"), 611 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 612 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 613 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 614 (slot->opt & SDHCI_HAVE_SDMA) ? "SDMA" : "PIO"); 615 sdhci_dumpregs(slot); 616 } 617 618 slot->timeout = 10; 619 slot->failures = 0; 620 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 621 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 622 "timeout", CTLFLAG_RW, &slot->timeout, 0, 623 "Maximum timeout for SDHCI transfers (in secs)"); 624 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 625 callout_init_mp(&slot->card_callout); 626 callout_init_lk(&slot->timeout_callout, &slot->lock); 627 return (0); 628 } 629 630 void 631 sdhci_start_slot(struct sdhci_slot *slot) 632 { 633 sdhci_card_task(slot, 0); 634 } 635 636 int 637 sdhci_cleanup_slot(struct sdhci_slot *slot) 638 { 639 device_t d; 640 bus_dmamem_t *sdma; 641 642 callout_drain(&slot->timeout_callout); 643 callout_drain(&slot->card_callout); 644 taskqueue_drain(taskqueue_swi_mp, &slot->card_task); 645 646 SDHCI_LOCK(slot); 647 d = slot->dev; 648 slot->dev = NULL; 649 SDHCI_UNLOCK(slot); 650 if (d != NULL) 651 device_delete_child(slot->bus, d); 652 653 SDHCI_LOCK(slot); 654 sdhci_reset(slot, SDHCI_RESET_ALL); 655 SDHCI_UNLOCK(slot); 656 657 sdma = &slot->sdma_mem; 658 bus_dmamap_unload(sdma->dmem_tag, sdma->dmem_map); 659 bus_dmamem_free(sdma->dmem_tag, sdma->dmem_addr, sdma->dmem_map); 660 bus_dma_tag_destroy(sdma->dmem_tag); 661 662 SDHCI_LOCK_DESTROY(slot); 663 664 return (0); 665 } 666 667 int 668 sdhci_generic_suspend(struct sdhci_slot *slot) 669 { 670 sdhci_reset(slot, SDHCI_RESET_ALL); 671 672 return (0); 673 } 674 675 int 676 sdhci_generic_resume(struct sdhci_slot *slot) 677 { 678 sdhci_init(slot); 679 680 return (0); 681 } 682 683 uint32_t 684 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 685 { 686 if (slot->version >= SDHCI_SPEC_300) 687 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 688 else 689 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 690 } 691 692 boolean_t 693 sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot) 694 { 695 696 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 697 } 698 699 int 700 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 701 { 702 struct sdhci_slot *slot = device_get_ivars(reqdev); 703 struct mmc_ios *ios = &slot->host.ios; 704 705 SDHCI_LOCK(slot); 706 /* Do full reset on bus power down to clear from any state. */ 707 if (ios->power_mode == power_off) { 708 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 709 sdhci_init(slot); 710 } 711 /* Configure the bus. */ 712 sdhci_set_clock(slot, ios->clock); 713 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 714 if (ios->bus_width == bus_width_8) { 715 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 716 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 717 } else if (ios->bus_width == bus_width_4) { 718 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 719 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 720 } else if (ios->bus_width == bus_width_1) { 721 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 722 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 723 } else { 724 panic("Invalid bus width: %d", ios->bus_width); 725 } 726 if (ios->timing == bus_timing_hs && 727 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 728 slot->hostctrl |= SDHCI_CTRL_HISPD; 729 else 730 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 731 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 732 /* Some controllers like reset after bus changes. */ 733 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 734 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 735 736 SDHCI_UNLOCK(slot); 737 return (0); 738 } 739 740 static void 741 sdhci_req_done(struct sdhci_slot *slot) 742 { 743 struct mmc_request *req; 744 745 if (slot->req != NULL && slot->curcmd != NULL) { 746 callout_stop(&slot->timeout_callout); 747 if (slot->curcmd->error != MMC_ERR_TIMEOUT) 748 slot->failures = 0; 749 req = slot->req; 750 slot->req = NULL; 751 slot->curcmd = NULL; 752 req->done(req); 753 } 754 } 755 756 static void 757 sdhci_timeout(void *arg) 758 { 759 struct sdhci_slot *slot = arg; 760 761 if (slot->curcmd != NULL) { 762 slot_printf(slot, " Controller timeout\n"); 763 sdhci_dumpregs(slot); 764 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 765 slot->curcmd->error = MMC_ERR_TIMEOUT; 766 sdhci_req_done(slot); 767 } else { 768 slot_printf(slot, " Spurious timeout - no active command\n"); 769 } 770 } 771 772 static void 773 sdhci_set_transfer_mode(struct sdhci_slot *slot, 774 struct mmc_data *data) 775 { 776 uint16_t mode; 777 778 if (data == NULL) 779 return; 780 781 mode = SDHCI_TRNS_BLK_CNT_EN; 782 if (data->len > 512) 783 mode |= SDHCI_TRNS_MULTI; 784 if (data->flags & MMC_DATA_READ) 785 mode |= SDHCI_TRNS_READ; 786 if (slot->req->stop) 787 mode |= SDHCI_TRNS_ACMD12; 788 if (slot->flags & SDHCI_USE_SDMA) 789 mode |= SDHCI_TRNS_DMA; 790 791 WR2(slot, SDHCI_TRANSFER_MODE, mode); 792 } 793 794 static void 795 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 796 { 797 int flags, timeout; 798 uint32_t mask; 799 800 slot->curcmd = cmd; 801 slot->cmd_done = 0; 802 803 cmd->error = MMC_ERR_NONE; 804 805 /* This flags combination is not supported by controller. */ 806 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 807 slot_printf(slot, "Unsupported response type!\n"); 808 cmd->error = MMC_ERR_FAILED; 809 sdhci_req_done(slot); 810 return; 811 } 812 813 /* Do not issue command if there is no card, clock or power. 814 * Controller will not detect timeout without clock active. */ 815 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 816 slot->power == 0 || 817 slot->clock == 0) { 818 cmd->error = MMC_ERR_FAILED; 819 sdhci_req_done(slot); 820 return; 821 } 822 /* Always wait for free CMD bus. */ 823 mask = SDHCI_CMD_INHIBIT; 824 /* Wait for free DAT if we have data or busy signal. */ 825 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 826 mask |= SDHCI_DAT_INHIBIT; 827 /* We shouldn't wait for DAT for stop commands. */ 828 if (cmd == slot->req->stop) 829 mask &= ~SDHCI_DAT_INHIBIT; 830 /* 831 * Wait for bus no more then 250 ms. Typically there will be no wait 832 * here at all, but when writing a crash dump we may be bypassing the 833 * host platform's interrupt handler, and in some cases that handler 834 * may be working around hardware quirks such as not respecting r1b 835 * busy indications. In those cases, this wait-loop serves the purpose 836 * of waiting for the prior command and data transfers to be done, and 837 * SD cards are allowed to take up to 250ms for write and erase ops. 838 * (It's usually more like 20-30ms in the real world.) 839 */ 840 timeout = 250; 841 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 842 if (timeout == 0) { 843 slot_printf(slot, "Controller never released " 844 "inhibit bit(s).\n"); 845 sdhci_dumpregs(slot); 846 cmd->error = MMC_ERR_FAILED; 847 sdhci_req_done(slot); 848 return; 849 } 850 timeout--; 851 DELAY(1000); 852 } 853 854 /* Prepare command flags. */ 855 if (!(cmd->flags & MMC_RSP_PRESENT)) 856 flags = SDHCI_CMD_RESP_NONE; 857 else if (cmd->flags & MMC_RSP_136) 858 flags = SDHCI_CMD_RESP_LONG; 859 else if (cmd->flags & MMC_RSP_BUSY) 860 flags = SDHCI_CMD_RESP_SHORT_BUSY; 861 else 862 flags = SDHCI_CMD_RESP_SHORT; 863 if (cmd->flags & MMC_RSP_CRC) 864 flags |= SDHCI_CMD_CRC; 865 if (cmd->flags & MMC_RSP_OPCODE) 866 flags |= SDHCI_CMD_INDEX; 867 if (cmd->data) 868 flags |= SDHCI_CMD_DATA; 869 if (cmd->opcode == MMC_STOP_TRANSMISSION) 870 flags |= SDHCI_CMD_TYPE_ABORT; 871 /* Prepare data. */ 872 sdhci_start_data(slot, cmd->data); 873 /* 874 * Interrupt aggregation: To reduce total number of interrupts 875 * group response interrupt with data interrupt when possible. 876 * If there going to be data interrupt, mask response one. 877 */ 878 if (slot->data_done == 0) { 879 WR4(slot, SDHCI_SIGNAL_ENABLE, 880 slot->intmask &= ~SDHCI_INT_RESPONSE); 881 } 882 /* Set command argument. */ 883 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 884 /* Set data transfer mode. */ 885 sdhci_set_transfer_mode(slot, cmd->data); 886 /* Start command. */ 887 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 888 889 /* 890 * Start timeout callout. Timeout is dropped to 2 seconds with 891 * repeated controller timeouts. 892 */ 893 if (slot->failures) 894 timeout = slot->timeout / 5; 895 else 896 timeout = slot->timeout; 897 if (timeout < 2) 898 timeout = 2; 899 callout_reset(&slot->timeout_callout, timeout * hz, 900 sdhci_timeout, slot); 901 } 902 903 static void 904 sdhci_finish_command(struct sdhci_slot *slot) 905 { 906 int i; 907 908 slot->cmd_done = 1; 909 /* Interrupt aggregation: Restore command interrupt. 910 * Main restore point for the case when command interrupt 911 * happened first. */ 912 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 913 /* In case of error - reset host and return. */ 914 if (slot->curcmd->error) { 915 sdhci_reset(slot, SDHCI_RESET_CMD); 916 sdhci_reset(slot, SDHCI_RESET_DATA); 917 sdhci_start(slot); 918 return; 919 } 920 /* If command has response - fetch it. */ 921 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 922 if (slot->curcmd->flags & MMC_RSP_136) { 923 /* CRC is stripped so we need one byte shift. */ 924 uint8_t extra = 0; 925 for (i = 0; i < 4; i++) { 926 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 927 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) { 928 slot->curcmd->resp[3 - i] = val; 929 } else { 930 slot->curcmd->resp[3 - i] = 931 (val << 8) | extra; 932 extra = val >> 24; 933 } 934 } 935 } else { 936 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 937 } 938 } 939 /* If data ready - finish. */ 940 if (slot->data_done) 941 sdhci_start(slot); 942 } 943 944 static void 945 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 946 { 947 uint32_t target_timeout, current_timeout; 948 uint8_t div; 949 950 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 951 slot->data_done = 1; 952 return; 953 } 954 955 slot->data_done = 0; 956 957 /* Calculate and set data timeout.*/ 958 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 959 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 960 div = 0xe; 961 } else { 962 target_timeout = 1000000; 963 div = 0; 964 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 965 while (current_timeout < target_timeout && div < 0xE) { 966 ++div; 967 current_timeout <<= 1; 968 } 969 /* Compensate for an off-by-one error in the CaFe chip.*/ 970 if (div < 0xE && 971 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 972 ++div; 973 } 974 } 975 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 976 977 if (data == NULL) 978 return; 979 980 /* Use DMA if possible. */ 981 if ((slot->opt & SDHCI_HAVE_SDMA)) 982 slot->flags |= SDHCI_USE_SDMA; 983 /* If data is small, broken DMA may return zeroes instead of data. */ 984 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 985 (data->len <= 512)) 986 slot->flags &= ~SDHCI_USE_SDMA; 987 /* Some controllers require even block sizes. */ 988 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 989 ((data->len) & 0x3)) 990 slot->flags &= ~SDHCI_USE_SDMA; 991 /* Load DMA buffer. */ 992 if (slot->flags & SDHCI_USE_SDMA) { 993 bus_dmamem_t *sdma = &slot->sdma_mem; 994 995 if (data->flags & MMC_DATA_READ) { 996 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 997 BUS_DMASYNC_PREREAD); 998 } else { 999 memcpy(sdma->dmem_addr, data->data, 1000 (data->len < DMA_BLOCK_SIZE) ? 1001 data->len : DMA_BLOCK_SIZE); 1002 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1003 BUS_DMASYNC_PREWRITE); 1004 } 1005 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr); 1006 /* Interrupt aggregation: Mask border interrupt 1007 * for the last page and unmask else. */ 1008 if (data->len == DMA_BLOCK_SIZE) 1009 slot->intmask &= ~SDHCI_INT_DMA_END; 1010 else 1011 slot->intmask |= SDHCI_INT_DMA_END; 1012 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1013 } 1014 /* Current data offset for both PIO and DMA. */ 1015 slot->offset = 0; 1016 /* Set block size and request IRQ on 4K border. */ 1017 WR2(slot, SDHCI_BLOCK_SIZE, 1018 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1019 /* Set block count. */ 1020 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1021 } 1022 1023 void 1024 sdhci_finish_data(struct sdhci_slot *slot) 1025 { 1026 struct mmc_data *data = slot->curcmd->data; 1027 1028 /* Interrupt aggregation: Restore command interrupt. 1029 * Auxiliary restore point for the case when data interrupt 1030 * happened first. */ 1031 if (!slot->cmd_done) { 1032 WR4(slot, SDHCI_SIGNAL_ENABLE, 1033 slot->intmask |= SDHCI_INT_RESPONSE); 1034 } 1035 /* Unload rest of data from DMA buffer. */ 1036 if (!slot->data_done && (slot->flags & SDHCI_USE_SDMA)) { 1037 bus_dmamem_t *sdma = &slot->sdma_mem; 1038 1039 if (data->flags & MMC_DATA_READ) { 1040 size_t left = data->len - slot->offset; 1041 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1042 BUS_DMASYNC_POSTREAD); 1043 memcpy((u_char*)data->data + slot->offset, 1044 sdma->dmem_addr, 1045 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1046 } else 1047 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1048 BUS_DMASYNC_POSTWRITE); 1049 } 1050 slot->data_done = 1; 1051 /* If there was error - reset the host. */ 1052 if (slot->curcmd->error) { 1053 sdhci_reset(slot, SDHCI_RESET_CMD); 1054 sdhci_reset(slot, SDHCI_RESET_DATA); 1055 sdhci_start(slot); 1056 return; 1057 } 1058 /* If we already have command response - finish. */ 1059 if (slot->cmd_done) 1060 sdhci_start(slot); 1061 } 1062 1063 static void 1064 sdhci_start(struct sdhci_slot *slot) 1065 { 1066 struct mmc_request *req; 1067 1068 req = slot->req; 1069 if (req == NULL) 1070 return; 1071 1072 if (!(slot->flags & CMD_STARTED)) { 1073 slot->flags |= CMD_STARTED; 1074 sdhci_start_command(slot, req->cmd); 1075 return; 1076 } 1077 /* We don't need this until using Auto-CMD12 feature 1078 if (!(slot->flags & STOP_STARTED) && req->stop) { 1079 slot->flags |= STOP_STARTED; 1080 sdhci_start_command(slot, req->stop); 1081 return; 1082 } 1083 */ 1084 if (sdhci_debug > 1) 1085 slot_printf(slot, "result: %d\n", req->cmd->error); 1086 if (!req->cmd->error && 1087 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1088 sdhci_reset(slot, SDHCI_RESET_CMD); 1089 sdhci_reset(slot, SDHCI_RESET_DATA); 1090 } 1091 1092 sdhci_req_done(slot); 1093 } 1094 1095 int 1096 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1097 { 1098 struct sdhci_slot *slot = device_get_ivars(reqdev); 1099 1100 SDHCI_LOCK(slot); 1101 if (slot->req != NULL) { 1102 SDHCI_UNLOCK(slot); 1103 return (EBUSY); 1104 } 1105 if (sdhci_debug > 1) { 1106 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1107 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1108 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1109 (req->cmd->data)?req->cmd->data->flags:0); 1110 } 1111 slot->req = req; 1112 slot->flags = 0; 1113 sdhci_start(slot); 1114 SDHCI_UNLOCK(slot); 1115 if (dumping) { 1116 while (slot->req != NULL) { 1117 sdhci_generic_intr(slot); 1118 DELAY(10); 1119 } 1120 } 1121 return (0); 1122 } 1123 1124 int 1125 sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1126 { 1127 struct sdhci_slot *slot = device_get_ivars(reqdev); 1128 uint32_t val; 1129 1130 SDHCI_LOCK(slot); 1131 val = RD4(slot, SDHCI_PRESENT_STATE); 1132 SDHCI_UNLOCK(slot); 1133 return (!(val & SDHCI_WRITE_PROTECT)); 1134 } 1135 1136 int 1137 sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1138 { 1139 struct sdhci_slot *slot = device_get_ivars(reqdev); 1140 int err = 0; 1141 1142 SDHCI_LOCK(slot); 1143 while (slot->bus_busy) 1144 lksleep(slot, &slot->lock, 0, "sdhciah", 0); 1145 slot->bus_busy++; 1146 /* Activate led. */ 1147 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1148 SDHCI_UNLOCK(slot); 1149 return (err); 1150 } 1151 1152 int 1153 sdhci_generic_release_host(device_t brdev, device_t reqdev) 1154 { 1155 struct sdhci_slot *slot = device_get_ivars(reqdev); 1156 1157 SDHCI_LOCK(slot); 1158 /* Deactivate led. */ 1159 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1160 slot->bus_busy--; 1161 SDHCI_UNLOCK(slot); 1162 wakeup(slot); 1163 return (0); 1164 } 1165 1166 static void 1167 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1168 { 1169 1170 if (!slot->curcmd) { 1171 slot_printf(slot, "Got command interrupt 0x%08x, but " 1172 "there is no active command.\n", intmask); 1173 sdhci_dumpregs(slot); 1174 return; 1175 } 1176 if (intmask & SDHCI_INT_TIMEOUT) 1177 slot->curcmd->error = MMC_ERR_TIMEOUT; 1178 else if (intmask & SDHCI_INT_CRC) 1179 slot->curcmd->error = MMC_ERR_BADCRC; 1180 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1181 slot->curcmd->error = MMC_ERR_FIFO; 1182 1183 sdhci_finish_command(slot); 1184 } 1185 1186 static void 1187 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1188 { 1189 1190 if (!slot->curcmd) { 1191 slot_printf(slot, "Got data interrupt 0x%08x, but " 1192 "there is no active command.\n", intmask); 1193 sdhci_dumpregs(slot); 1194 return; 1195 } 1196 if (slot->curcmd->data == NULL && 1197 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1198 slot_printf(slot, "Got data interrupt 0x%08x, but " 1199 "there is no active data operation.\n", 1200 intmask); 1201 sdhci_dumpregs(slot); 1202 return; 1203 } 1204 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1205 slot->curcmd->error = MMC_ERR_TIMEOUT; 1206 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1207 slot->curcmd->error = MMC_ERR_BADCRC; 1208 if (slot->curcmd->data == NULL && 1209 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1210 SDHCI_INT_DMA_END))) { 1211 slot_printf(slot, "Got data interrupt 0x%08x, but " 1212 "there is busy-only command.\n", intmask); 1213 sdhci_dumpregs(slot); 1214 slot->curcmd->error = MMC_ERR_INVALID; 1215 } 1216 if (slot->curcmd->error) { 1217 /* No need to continue after any error. */ 1218 goto done; 1219 } 1220 1221 /* Handle PIO interrupt. */ 1222 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1223 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1224 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1225 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1226 slot->flags |= PLATFORM_DATA_STARTED; 1227 } else 1228 sdhci_transfer_pio(slot); 1229 } 1230 /* Handle DMA border. */ 1231 if (intmask & SDHCI_INT_DMA_END) { 1232 struct mmc_data *data = slot->curcmd->data; 1233 bus_dmamem_t *sdma = &slot->sdma_mem; 1234 size_t left; 1235 1236 /* Unload DMA buffer... */ 1237 left = data->len - slot->offset; 1238 if (data->flags & MMC_DATA_READ) { 1239 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1240 BUS_DMASYNC_POSTREAD); 1241 memcpy((u_char*)data->data + slot->offset, 1242 sdma->dmem_addr, 1243 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1244 } else { 1245 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1246 BUS_DMASYNC_POSTWRITE); 1247 } 1248 /* ... and reload it again. */ 1249 slot->offset += DMA_BLOCK_SIZE; 1250 left = data->len - slot->offset; 1251 if (data->flags & MMC_DATA_READ) { 1252 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1253 BUS_DMASYNC_PREREAD); 1254 } else { 1255 memcpy(sdma->dmem_addr, 1256 (u_char*)data->data + slot->offset, 1257 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1258 bus_dmamap_sync(sdma->dmem_tag, sdma->dmem_map, 1259 BUS_DMASYNC_PREWRITE); 1260 } 1261 /* Interrupt aggregation: Mask border interrupt 1262 * for the last page. */ 1263 if (left == DMA_BLOCK_SIZE) { 1264 slot->intmask &= ~SDHCI_INT_DMA_END; 1265 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1266 } 1267 /* Restart DMA. */ 1268 WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr); 1269 } 1270 /* We have got all data. */ 1271 if (intmask & SDHCI_INT_DATA_END) { 1272 if (slot->flags & PLATFORM_DATA_STARTED) { 1273 slot->flags &= ~PLATFORM_DATA_STARTED; 1274 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1275 } else { 1276 sdhci_finish_data(slot); 1277 } 1278 } 1279 done: 1280 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1281 if (slot->flags & PLATFORM_DATA_STARTED) { 1282 slot->flags &= ~PLATFORM_DATA_STARTED; 1283 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1284 } else 1285 sdhci_finish_data(slot); 1286 return; 1287 } 1288 } 1289 1290 static void 1291 sdhci_acmd_irq(struct sdhci_slot *slot) 1292 { 1293 uint16_t err; 1294 1295 err = RD4(slot, SDHCI_ACMD12_ERR); 1296 if (!slot->curcmd) { 1297 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1298 "there is no active command.\n", err); 1299 sdhci_dumpregs(slot); 1300 return; 1301 } 1302 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1303 sdhci_reset(slot, SDHCI_RESET_CMD); 1304 } 1305 1306 void 1307 sdhci_generic_intr(struct sdhci_slot *slot) 1308 { 1309 uint32_t intmask; 1310 1311 SDHCI_LOCK(slot); 1312 /* Read slot interrupt status. */ 1313 intmask = RD4(slot, SDHCI_INT_STATUS); 1314 if (intmask == 0 || intmask == 0xffffffff) { 1315 SDHCI_UNLOCK(slot); 1316 return; 1317 } 1318 if (sdhci_debug > 2) 1319 slot_printf(slot, "Interrupt %#x\n", intmask); 1320 1321 /* Handle card presence interrupts. */ 1322 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1323 WR4(slot, SDHCI_INT_STATUS, intmask & 1324 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1325 1326 if (intmask & SDHCI_INT_CARD_REMOVE) { 1327 if (bootverbose || sdhci_debug) 1328 slot_printf(slot, "Card removed\n"); 1329 callout_stop(&slot->card_callout); 1330 taskqueue_enqueue(taskqueue_swi_mp, &slot->card_task); 1331 } 1332 if (intmask & SDHCI_INT_CARD_INSERT) { 1333 if (bootverbose || sdhci_debug) 1334 slot_printf(slot, "Card inserted\n"); 1335 callout_reset(&slot->card_callout, hz / 2, 1336 sdhci_card_delay, slot); 1337 } 1338 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1339 } 1340 /* Handle command interrupts. */ 1341 if (intmask & SDHCI_INT_CMD_MASK) { 1342 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1343 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1344 } 1345 /* Handle data interrupts. */ 1346 if (intmask & SDHCI_INT_DATA_MASK) { 1347 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1348 /* Dont call data_irq in case of errored command */ 1349 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1350 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1351 } 1352 /* Handle AutoCMD12 error interrupt. */ 1353 if (intmask & SDHCI_INT_ACMD12ERR) { 1354 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1355 sdhci_acmd_irq(slot); 1356 } 1357 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1358 intmask &= ~SDHCI_INT_ACMD12ERR; 1359 intmask &= ~SDHCI_INT_ERROR; 1360 /* Handle bus power interrupt. */ 1361 if (intmask & SDHCI_INT_BUS_POWER) { 1362 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1363 slot_printf(slot, 1364 "Card is consuming too much power!\n"); 1365 intmask &= ~SDHCI_INT_BUS_POWER; 1366 } 1367 /* The rest is unknown. */ 1368 if (intmask) { 1369 WR4(slot, SDHCI_INT_STATUS, intmask); 1370 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1371 intmask); 1372 sdhci_dumpregs(slot); 1373 } 1374 1375 SDHCI_UNLOCK(slot); 1376 } 1377 1378 int 1379 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1380 { 1381 struct sdhci_slot *slot = device_get_ivars(child); 1382 1383 switch (which) { 1384 default: 1385 return (EINVAL); 1386 case MMCBR_IVAR_BUS_MODE: 1387 *(int *)result = slot->host.ios.bus_mode; 1388 break; 1389 case MMCBR_IVAR_BUS_WIDTH: 1390 *(int *)result = slot->host.ios.bus_width; 1391 break; 1392 case MMCBR_IVAR_CHIP_SELECT: 1393 *(int *)result = slot->host.ios.chip_select; 1394 break; 1395 case MMCBR_IVAR_CLOCK: 1396 *(int *)result = slot->host.ios.clock; 1397 break; 1398 case MMCBR_IVAR_F_MIN: 1399 *(int *)result = slot->host.f_min; 1400 break; 1401 case MMCBR_IVAR_F_MAX: 1402 *(int *)result = slot->host.f_max; 1403 break; 1404 case MMCBR_IVAR_HOST_OCR: 1405 *(int *)result = slot->host.host_ocr; 1406 break; 1407 case MMCBR_IVAR_MODE: 1408 *(int *)result = slot->host.mode; 1409 break; 1410 case MMCBR_IVAR_OCR: 1411 *(int *)result = slot->host.ocr; 1412 break; 1413 case MMCBR_IVAR_POWER_MODE: 1414 *(int *)result = slot->host.ios.power_mode; 1415 break; 1416 case MMCBR_IVAR_VDD: 1417 *(int *)result = slot->host.ios.vdd; 1418 break; 1419 case MMCBR_IVAR_CAPS: 1420 *(int *)result = slot->host.caps; 1421 break; 1422 case MMCBR_IVAR_TIMING: 1423 *(int *)result = slot->host.ios.timing; 1424 break; 1425 case MMCBR_IVAR_MAX_DATA: 1426 *(int *)result = 65535; 1427 break; 1428 } 1429 return (0); 1430 } 1431 1432 int 1433 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1434 { 1435 struct sdhci_slot *slot = device_get_ivars(child); 1436 1437 switch (which) { 1438 default: 1439 return (EINVAL); 1440 case MMCBR_IVAR_BUS_MODE: 1441 slot->host.ios.bus_mode = value; 1442 break; 1443 case MMCBR_IVAR_BUS_WIDTH: 1444 slot->host.ios.bus_width = value; 1445 break; 1446 case MMCBR_IVAR_CHIP_SELECT: 1447 slot->host.ios.chip_select = value; 1448 break; 1449 case MMCBR_IVAR_CLOCK: 1450 if (value > 0) { 1451 uint32_t max_clock; 1452 uint32_t clock; 1453 int i; 1454 1455 max_clock = slot->max_clk; 1456 clock = max_clock; 1457 1458 if (slot->version < SDHCI_SPEC_300) { 1459 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1460 i <<= 1) { 1461 if (clock <= value) 1462 break; 1463 clock >>= 1; 1464 } 1465 } 1466 else { 1467 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1468 i += 2) { 1469 if (clock <= value) 1470 break; 1471 clock = max_clock / (i + 2); 1472 } 1473 } 1474 1475 slot->host.ios.clock = clock; 1476 } else 1477 slot->host.ios.clock = 0; 1478 break; 1479 case MMCBR_IVAR_MODE: 1480 slot->host.mode = value; 1481 break; 1482 case MMCBR_IVAR_OCR: 1483 slot->host.ocr = value; 1484 break; 1485 case MMCBR_IVAR_POWER_MODE: 1486 slot->host.ios.power_mode = value; 1487 break; 1488 case MMCBR_IVAR_VDD: 1489 slot->host.ios.vdd = value; 1490 break; 1491 case MMCBR_IVAR_TIMING: 1492 slot->host.ios.timing = value; 1493 break; 1494 case MMCBR_IVAR_CAPS: 1495 case MMCBR_IVAR_HOST_OCR: 1496 case MMCBR_IVAR_F_MIN: 1497 case MMCBR_IVAR_F_MAX: 1498 case MMCBR_IVAR_MAX_DATA: 1499 return (EINVAL); 1500 } 1501 return (0); 1502 } 1503 1504 MODULE_VERSION(sdhci, 1); 1505