1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: src/sys/dev/sdhci/sdhci.c,v 1.8 2009/02/17 19:12:15 mav Exp $ 26 */ 27 28 #include <stdarg.h> 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/spinlock.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <bus/pci/pcireg.h> 44 #include <bus/pci/pcivar.h> 45 46 #include <bus/mmc/bridge.h> 47 #include <bus/mmc/mmcreg.h> 48 #include <bus/mmc/mmcbrvar.h> 49 50 #include "mmcbr_if.h" 51 #include "sdhci.h" 52 53 #define DMA_BLOCK_SIZE 4096 54 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ 55 56 /* Controller doesn't honor resets unless we touch the clock register */ 57 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 58 /* Controller really supports DMA */ 59 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 60 /* Controller has unusable DMA engine */ 61 #define SDHCI_QUIRK_BROKEN_DMA (1<<2) 62 /* Controller doesn't like to be reset when there is no card inserted. */ 63 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) 64 /* Controller has flaky internal state so reset it on each ios change */ 65 #define SDHCI_QUIRK_RESET_ON_IOS (1<<4) 66 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 67 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) 68 /* Controller needs to be reset after each request to stay stable */ 69 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) 70 /* Controller has an off-by-one issue with timeout value */ 71 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) 72 /* Controller has broken read timings */ 73 #define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) 74 75 static const struct sdhci_device { 76 uint32_t model; 77 uint16_t subvendor; 78 char *desc; 79 u_int quirks; 80 } sdhci_devices[] = { 81 { 0x08221180, 0xffff, "RICOH R5C822 SD", 82 SDHCI_QUIRK_FORCE_DMA }, 83 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 84 SDHCI_QUIRK_FORCE_DMA }, 85 { 0x05501524, 0xffff, "ENE CB712 SD", 86 SDHCI_QUIRK_BROKEN_TIMINGS }, 87 { 0x05511524, 0xffff, "ENE CB712 SD 2", 88 SDHCI_QUIRK_BROKEN_TIMINGS }, 89 { 0x07501524, 0xffff, "ENE CB714 SD", 90 SDHCI_QUIRK_RESET_ON_IOS | 91 SDHCI_QUIRK_BROKEN_TIMINGS }, 92 { 0x07511524, 0xffff, "ENE CB714 SD 2", 93 SDHCI_QUIRK_RESET_ON_IOS | 94 SDHCI_QUIRK_BROKEN_TIMINGS }, 95 { 0x410111ab, 0xffff, "Marvell CaFe SD", 96 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 97 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 98 SDHCI_QUIRK_32BIT_DMA_SIZE | 99 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 100 { 0, 0xffff, NULL, 101 0 } 102 }; 103 104 struct sdhci_softc; 105 106 struct sdhci_slot { 107 struct sdhci_softc *sc; 108 device_t dev; /* Slot device */ 109 u_char num; /* Slot number */ 110 u_char opt; /* Slot options */ 111 #define SDHCI_HAVE_DMA 1 112 uint32_t max_clk; /* Max possible freq */ 113 uint32_t timeout_clk; /* Timeout freq */ 114 struct resource *mem_res; /* Memory resource */ 115 int mem_rid; 116 bus_dma_tag_t dmatag; 117 bus_dmamap_t dmamap; 118 u_char *dmamem; 119 bus_addr_t paddr; /* DMA buffer address */ 120 struct task card_task; /* Card presence check task */ 121 struct callout card_callout; /* Card insert delay callout */ 122 struct mmc_host host; /* Host parameters */ 123 struct mmc_request *req; /* Current request */ 124 struct mmc_command *curcmd; /* Current command of current request */ 125 126 uint32_t intmask; /* Current interrupt mask */ 127 uint32_t clock; /* Current clock freq. */ 128 size_t offset; /* Data buffer offset */ 129 uint8_t hostctrl; /* Current host control register */ 130 u_char power; /* Current power */ 131 u_char bus_busy; /* Bus busy status */ 132 u_char cmd_done; /* CMD command part done flag */ 133 u_char data_done; /* DAT command part done flag */ 134 u_char flags; /* Request execution flags */ 135 #define CMD_STARTED 1 136 #define STOP_STARTED 2 137 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 138 struct lock lock; /* Slot lock */ 139 }; 140 141 struct sdhci_softc { 142 device_t dev; /* Controller device */ 143 u_int quirks; /* Chip specific quirks */ 144 struct resource *irq_res; /* IRQ resource */ 145 int irq_rid; 146 void *intrhand; /* Interrupt handle */ 147 148 int num_slots; /* Number of slots on this controller */ 149 struct sdhci_slot slots[6]; 150 }; 151 152 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 153 154 int sdhci_debug; 155 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 156 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 157 158 static inline uint8_t 159 RD1(struct sdhci_slot *slot, bus_size_t off) 160 { 161 bus_barrier(slot->mem_res, 0, 0xFF, 162 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 163 return bus_read_1(slot->mem_res, off); 164 } 165 166 static inline void 167 WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val) 168 { 169 bus_barrier(slot->mem_res, 0, 0xFF, 170 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 171 bus_write_1(slot->mem_res, off, val); 172 } 173 174 static inline uint16_t 175 RD2(struct sdhci_slot *slot, bus_size_t off) 176 { 177 bus_barrier(slot->mem_res, 0, 0xFF, 178 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 179 return bus_read_2(slot->mem_res, off); 180 } 181 182 static inline void 183 WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val) 184 { 185 bus_barrier(slot->mem_res, 0, 0xFF, 186 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 187 bus_write_2(slot->mem_res, off, val); 188 } 189 190 static inline uint32_t 191 RD4(struct sdhci_slot *slot, bus_size_t off) 192 { 193 bus_barrier(slot->mem_res, 0, 0xFF, 194 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 195 return bus_read_4(slot->mem_res, off); 196 } 197 198 static inline void 199 WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val) 200 { 201 bus_barrier(slot->mem_res, 0, 0xFF, 202 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 203 bus_write_4(slot->mem_res, off, val); 204 } 205 206 /* bus entry points */ 207 static int sdhci_probe(device_t dev); 208 static int sdhci_attach(device_t dev); 209 static int sdhci_detach(device_t dev); 210 static void sdhci_intr(void *); 211 212 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 213 static void sdhci_start(struct sdhci_slot *slot); 214 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 215 216 static void sdhci_card_task(void *, int); 217 218 /* helper routines */ 219 #define SDHCI_LOCK(_slot) lockmgr(&(_slot)->lock, LK_EXCLUSIVE) 220 #define SDHCI_UNLOCK(_slot) lockmgr(&(_slot)->lock, LK_RELEASE) 221 #define SDHCI_LOCK_INIT(_slot) lockinit(&(_slot)->lock, "sdhci", 0, LK_CANRECURSE) 222 #define SDHCI_LOCK_DESTROY(_slot) lockuninit(&(_slot)->lock); 223 #define SDHCI_ASSERT_LOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) != 0); 224 #define SDHCI_ASSERT_UNLOCKED(_slot) KKASSERT(lockstatus(&(_slot)->lock, curthread) == 0); 225 226 static int 227 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 228 { 229 va_list ap; 230 int retval; 231 232 retval = kprintf("%s-slot%d: ", 233 device_get_nameunit(slot->sc->dev), slot->num); 234 235 va_start(ap, fmt); 236 retval += kvprintf(fmt, ap); 237 va_end(ap); 238 return (retval); 239 } 240 241 static void 242 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 243 { 244 if (error != 0) { 245 kprintf("getaddr: error %d\n", error); 246 return; 247 } 248 *(bus_addr_t *)arg = segs[0].ds_addr; 249 } 250 251 static void 252 sdhci_dumpregs(struct sdhci_slot *slot) 253 { 254 slot_printf(slot, 255 "============== REGISTER DUMP ==============\n"); 256 257 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 258 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 259 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 260 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 261 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 262 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 263 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 264 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 265 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 266 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 267 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 268 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 269 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 270 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 271 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 272 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 273 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 274 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 275 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 276 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 277 278 slot_printf(slot, 279 "===========================================\n"); 280 } 281 282 static void 283 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 284 { 285 int timeout; 286 uint8_t res; 287 288 if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 289 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 290 SDHCI_CARD_PRESENT)) 291 return; 292 } 293 294 /* Some controllers need this kick or reset won't work. */ 295 if ((mask & SDHCI_RESET_ALL) == 0 && 296 (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 297 uint32_t clock; 298 299 /* This is to force an update */ 300 clock = slot->clock; 301 slot->clock = 0; 302 sdhci_set_clock(slot, clock); 303 } 304 305 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 306 307 if (mask & SDHCI_RESET_ALL) { 308 slot->clock = 0; 309 slot->power = 0; 310 } 311 312 /* Wait max 100 ms */ 313 timeout = 100; 314 /* Controller clears the bits when it's done */ 315 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 316 if (timeout == 0) { 317 slot_printf(slot, 318 "Reset 0x%x never completed - 0x%x.\n", 319 (int)mask, (int)res); 320 sdhci_dumpregs(slot); 321 return; 322 } 323 timeout--; 324 DELAY(1000); 325 } 326 } 327 328 static void 329 sdhci_init(struct sdhci_slot *slot) 330 { 331 332 sdhci_reset(slot, SDHCI_RESET_ALL); 333 334 /* Enable interrupts. */ 335 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 336 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 337 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 338 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 339 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 340 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 341 SDHCI_INT_ACMD12ERR; 342 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 343 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 344 } 345 346 static void 347 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 348 { 349 uint32_t res; 350 uint16_t clk; 351 int timeout; 352 353 if (clock == slot->clock) 354 return; 355 slot->clock = clock; 356 357 /* Turn off the clock. */ 358 WR2(slot, SDHCI_CLOCK_CONTROL, 0); 359 /* If no clock requested - left it so. */ 360 if (clock == 0) 361 return; 362 /* Looking for highest freq <= clock. */ 363 res = slot->max_clk; 364 for (clk = 1; clk < 256; clk <<= 1) { 365 if (res <= clock) 366 break; 367 res >>= 1; 368 } 369 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 370 clk >>= 1; 371 /* Now we have got divider, set it. */ 372 clk <<= SDHCI_DIVIDER_SHIFT; 373 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 374 /* Enable clock. */ 375 clk |= SDHCI_CLOCK_INT_EN; 376 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 377 /* Wait up to 10 ms until it stabilize. */ 378 timeout = 10; 379 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 380 & SDHCI_CLOCK_INT_STABLE)) { 381 if (timeout == 0) { 382 slot_printf(slot, 383 "Internal clock never stabilised.\n"); 384 sdhci_dumpregs(slot); 385 return; 386 } 387 timeout--; 388 DELAY(1000); 389 } 390 /* Pass clock signal to the bus. */ 391 clk |= SDHCI_CLOCK_CARD_EN; 392 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 393 } 394 395 static void 396 sdhci_set_power(struct sdhci_slot *slot, u_char power) 397 { 398 uint8_t pwr; 399 400 if (slot->power == power) 401 return; 402 slot->power = power; 403 404 /* Turn off the power. */ 405 pwr = 0; 406 WR1(slot, SDHCI_POWER_CONTROL, pwr); 407 /* If power down requested - left it so. */ 408 if (power == 0) 409 return; 410 /* Set voltage. */ 411 switch (1 << power) { 412 case MMC_OCR_LOW_VOLTAGE: 413 pwr |= SDHCI_POWER_180; 414 break; 415 case MMC_OCR_290_300: 416 case MMC_OCR_300_310: 417 pwr |= SDHCI_POWER_300; 418 break; 419 case MMC_OCR_320_330: 420 case MMC_OCR_330_340: 421 pwr |= SDHCI_POWER_330; 422 break; 423 } 424 WR1(slot, SDHCI_POWER_CONTROL, pwr); 425 /* Turn on the power. */ 426 pwr |= SDHCI_POWER_ON; 427 WR1(slot, SDHCI_POWER_CONTROL, pwr); 428 } 429 430 static void 431 sdhci_read_block_pio(struct sdhci_slot *slot) 432 { 433 uint32_t data; 434 char *buffer; 435 size_t left; 436 437 buffer = slot->curcmd->data->data; 438 buffer += slot->offset; 439 /* Transfer one block at a time. */ 440 left = min(512, slot->curcmd->data->len - slot->offset); 441 slot->offset += left; 442 443 /* If we are too fast, broken controllers return zeroes. */ 444 if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 445 DELAY(10); 446 /* Handle unalligned and alligned buffer cases. */ 447 if ((intptr_t)buffer & 3) { 448 while (left > 3) { 449 data = RD4(slot, SDHCI_BUFFER); 450 buffer[0] = data; 451 buffer[1] = (data >> 8); 452 buffer[2] = (data >> 16); 453 buffer[3] = (data >> 24); 454 buffer += 4; 455 left -= 4; 456 } 457 } else { 458 bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 459 (uint32_t *)buffer, left >> 2); 460 left &= 3; 461 } 462 /* Handle uneven size case. */ 463 if (left > 0) { 464 data = RD4(slot, SDHCI_BUFFER); 465 while (left > 0) { 466 *(buffer++) = data; 467 data >>= 8; 468 left--; 469 } 470 } 471 } 472 473 static void 474 sdhci_write_block_pio(struct sdhci_slot *slot) 475 { 476 uint32_t data = 0; 477 char *buffer; 478 size_t left; 479 480 buffer = slot->curcmd->data->data; 481 buffer += slot->offset; 482 /* Transfer one block at a time. */ 483 left = min(512, slot->curcmd->data->len - slot->offset); 484 slot->offset += left; 485 486 /* Handle unalligned and alligned buffer cases. */ 487 if ((intptr_t)buffer & 3) { 488 while (left > 3) { 489 data = buffer[0] + 490 (buffer[1] << 8) + 491 (buffer[2] << 16) + 492 (buffer[3] << 24); 493 left -= 4; 494 buffer += 4; 495 WR4(slot, SDHCI_BUFFER, data); 496 } 497 } else { 498 bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 499 (uint32_t *)buffer, left >> 2); 500 left &= 3; 501 } 502 /* Handle uneven size case. */ 503 if (left > 0) { 504 while (left > 0) { 505 data <<= 8; 506 data += *(buffer++); 507 left--; 508 } 509 WR4(slot, SDHCI_BUFFER, data); 510 } 511 } 512 513 static void 514 sdhci_transfer_pio(struct sdhci_slot *slot) 515 { 516 517 /* Read as many blocks as possible. */ 518 if (slot->curcmd->data->flags & MMC_DATA_READ) { 519 while (RD4(slot, SDHCI_PRESENT_STATE) & 520 SDHCI_DATA_AVAILABLE) { 521 sdhci_read_block_pio(slot); 522 if (slot->offset >= slot->curcmd->data->len) 523 break; 524 } 525 } else { 526 while (RD4(slot, SDHCI_PRESENT_STATE) & 527 SDHCI_SPACE_AVAILABLE) { 528 sdhci_write_block_pio(slot); 529 if (slot->offset >= slot->curcmd->data->len) 530 break; 531 } 532 } 533 } 534 535 static void 536 sdhci_card_delay(void *arg) 537 { 538 struct sdhci_slot *slot = arg; 539 540 taskqueue_enqueue(taskqueue_swi, &slot->card_task); 541 } 542 543 static void 544 sdhci_card_task(void *arg, int pending) 545 { 546 struct sdhci_slot *slot = arg; 547 548 SDHCI_LOCK(slot); 549 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 550 if (slot->dev == NULL) { 551 /* If card is present - attach mmc bus. */ 552 slot->dev = device_add_child(slot->sc->dev, "mmc", -1); 553 device_set_ivars(slot->dev, slot); 554 SDHCI_UNLOCK(slot); 555 device_probe_and_attach(slot->dev); 556 } else 557 SDHCI_UNLOCK(slot); 558 } else { 559 if (slot->dev != NULL) { 560 /* If no card present - detach mmc bus. */ 561 device_t d = slot->dev; 562 slot->dev = NULL; 563 SDHCI_UNLOCK(slot); 564 device_delete_child(slot->sc->dev, d); 565 } else 566 SDHCI_UNLOCK(slot); 567 } 568 } 569 570 static int 571 sdhci_probe(device_t dev) 572 { 573 uint32_t model; 574 uint16_t subvendor; 575 uint8_t class, subclass; 576 int i, result; 577 578 model = (uint32_t)pci_get_device(dev) << 16; 579 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 580 subvendor = pci_get_subvendor(dev); 581 class = pci_get_class(dev); 582 subclass = pci_get_subclass(dev); 583 584 result = ENXIO; 585 for (i = 0; sdhci_devices[i].model != 0; i++) { 586 if (sdhci_devices[i].model == model && 587 (sdhci_devices[i].subvendor == 0xffff || 588 sdhci_devices[i].subvendor == subvendor)) { 589 device_set_desc(dev, sdhci_devices[i].desc); 590 result = BUS_PROBE_DEFAULT; 591 break; 592 } 593 } 594 if (result == ENXIO && class == PCIC_BASEPERIPH && 595 subclass == PCIS_BASEPERIPH_SDHC) { 596 device_set_desc(dev, "Generic SD HCI"); 597 result = BUS_PROBE_GENERIC; 598 } 599 600 return (result); 601 } 602 603 static int 604 sdhci_attach(device_t dev) 605 { 606 struct sdhci_softc *sc = device_get_softc(dev); 607 uint32_t model; 608 uint16_t subvendor; 609 uint8_t class, subclass, progif; 610 int err, slots, bar, i; 611 612 sc->dev = dev; 613 model = (uint32_t)pci_get_device(dev) << 16; 614 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 615 subvendor = pci_get_subvendor(dev); 616 class = pci_get_class(dev); 617 subclass = pci_get_subclass(dev); 618 progif = pci_get_progif(dev); 619 /* Apply chip specific quirks. */ 620 for (i = 0; sdhci_devices[i].model != 0; i++) { 621 if (sdhci_devices[i].model == model && 622 (sdhci_devices[i].subvendor == 0xffff || 623 sdhci_devices[i].subvendor == subvendor)) { 624 sc->quirks = sdhci_devices[i].quirks; 625 break; 626 } 627 } 628 /* Read slots info from PCI registers. */ 629 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 630 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 631 slots = PCI_SLOT_INFO_SLOTS(slots); 632 if (slots > 6 || bar > 5) { 633 device_printf(dev, "Incorrect slots information (%d, %d).\n", 634 slots, bar); 635 return (EINVAL); 636 } 637 /* Allocate IRQ. */ 638 sc->irq_rid = 0; 639 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 640 RF_SHAREABLE | RF_ACTIVE); 641 if (sc->irq_res == NULL) { 642 device_printf(dev, "Can't allocate IRQ\n"); 643 return (ENOMEM); 644 } 645 /* Scan all slots. */ 646 for (i = 0; i < slots; i++) { 647 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 648 uint32_t caps; 649 650 SDHCI_LOCK_INIT(slot); 651 slot->sc = sc; 652 slot->num = sc->num_slots; 653 /* Allocate memory. */ 654 slot->mem_rid = PCIR_BAR(bar + i); 655 slot->mem_res = bus_alloc_resource(dev, 656 SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 657 if (slot->mem_res == NULL) { 658 device_printf(dev, "Can't allocate memory\n"); 659 SDHCI_LOCK_DESTROY(slot); 660 continue; 661 } 662 /* Allocate DMA tag. */ 663 err = bus_dma_tag_create(NULL, 664 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 665 BUS_SPACE_MAXADDR, NULL, NULL, 666 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 667 BUS_DMA_ALLOCNOW, &slot->dmatag); 668 if (err != 0) { 669 device_printf(dev, "Can't create DMA tag\n"); 670 SDHCI_LOCK_DESTROY(slot); 671 continue; 672 } 673 /* Allocate DMA memory. */ 674 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 675 BUS_DMA_NOWAIT, &slot->dmamap); 676 if (err != 0) { 677 device_printf(dev, "Can't alloc DMA memory\n"); 678 SDHCI_LOCK_DESTROY(slot); 679 continue; 680 } 681 /* Map the memory. */ 682 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 683 (void *)slot->dmamem, DMA_BLOCK_SIZE, 684 sdhci_getaddr, &slot->paddr, 0); 685 if (err != 0 || slot->paddr == 0) { 686 device_printf(dev, "Can't load DMA memory\n"); 687 SDHCI_LOCK_DESTROY(slot); 688 continue; 689 } 690 /* Initialize slot. */ 691 sdhci_init(slot); 692 caps = RD4(slot, SDHCI_CAPABILITIES); 693 /* Calculate base clock frequency. */ 694 slot->max_clk = 695 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 696 if (slot->max_clk == 0) { 697 device_printf(dev, "Hardware doesn't specify base clock " 698 "frequency.\n"); 699 } 700 slot->max_clk *= 1000000; 701 /* Calculate timeout clock frequency. */ 702 slot->timeout_clk = 703 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 704 if (slot->timeout_clk == 0) { 705 device_printf(dev, "Hardware doesn't specify timeout clock " 706 "frequency.\n"); 707 } 708 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 709 slot->timeout_clk *= 1000; 710 711 slot->host.f_min = slot->max_clk / 256; 712 slot->host.f_max = slot->max_clk; 713 slot->host.host_ocr = 0; 714 if (caps & SDHCI_CAN_VDD_330) 715 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 716 if (caps & SDHCI_CAN_VDD_300) 717 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 718 if (caps & SDHCI_CAN_VDD_180) 719 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 720 if (slot->host.host_ocr == 0) { 721 device_printf(dev, "Hardware doesn't report any " 722 "support voltages.\n"); 723 } 724 slot->host.caps = MMC_CAP_4_BIT_DATA; 725 if (caps & SDHCI_CAN_DO_HISPD) 726 slot->host.caps |= MMC_CAP_HSPEED; 727 /* Decide if we have usable DMA. */ 728 if (caps & SDHCI_CAN_DO_DMA) 729 slot->opt |= SDHCI_HAVE_DMA; 730 if (class == PCIC_BASEPERIPH && 731 subclass == PCIS_BASEPERIPH_SDHC && 732 progif != PCI_SDHCI_IFDMA) 733 slot->opt &= ~SDHCI_HAVE_DMA; 734 if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA) 735 slot->opt &= ~SDHCI_HAVE_DMA; 736 if (sc->quirks & SDHCI_QUIRK_FORCE_DMA) 737 slot->opt |= SDHCI_HAVE_DMA; 738 739 if (bootverbose || sdhci_debug) { 740 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 741 slot->max_clk / 1000000, 742 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 743 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 744 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 745 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 746 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 747 sdhci_dumpregs(slot); 748 } 749 750 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 751 callout_init(&slot->card_callout); 752 sc->num_slots++; 753 } 754 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 755 /* Activate the interrupt */ 756 err = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE, sdhci_intr, sc, &sc->intrhand, NULL); 757 if (err) 758 device_printf(dev, "Can't setup IRQ\n"); 759 pci_enable_busmaster(dev); 760 /* Process cards detection. */ 761 for (i = 0; i < sc->num_slots; i++) { 762 struct sdhci_slot *slot = &sc->slots[i]; 763 764 sdhci_card_task(slot, 0); 765 } 766 767 return (0); 768 } 769 770 static int 771 sdhci_detach(device_t dev) 772 { 773 struct sdhci_softc *sc = device_get_softc(dev); 774 int i; 775 776 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 777 bus_release_resource(dev, SYS_RES_IRQ, 778 sc->irq_rid, sc->irq_res); 779 780 for (i = 0; i < sc->num_slots; i++) { 781 struct sdhci_slot *slot = &sc->slots[i]; 782 device_t d; 783 784 #if 0 785 /* XXX: need implementation of callout_drain or workaround */ 786 callout_drain(&slot->card_callout); 787 #endif 788 taskqueue_drain(taskqueue_swi, &slot->card_task); 789 790 SDHCI_LOCK(slot); 791 d = slot->dev; 792 slot->dev = NULL; 793 SDHCI_UNLOCK(slot); 794 if (d != NULL) 795 device_delete_child(dev, d); 796 797 SDHCI_LOCK(slot); 798 sdhci_reset(slot, SDHCI_RESET_ALL); 799 SDHCI_UNLOCK(slot); 800 bus_dmamap_unload(slot->dmatag, slot->dmamap); 801 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 802 bus_dma_tag_destroy(slot->dmatag); 803 bus_release_resource(dev, SYS_RES_MEMORY, 804 slot->mem_rid, slot->mem_res); 805 SDHCI_LOCK_DESTROY(slot); 806 } 807 return (0); 808 } 809 810 static int 811 sdhci_suspend(device_t dev) 812 { 813 struct sdhci_softc *sc = device_get_softc(dev); 814 int i, err; 815 816 err = bus_generic_suspend(dev); 817 if (err) 818 return (err); 819 for (i = 0; i < sc->num_slots; i++) 820 sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL); 821 return (0); 822 } 823 824 static int 825 sdhci_resume(device_t dev) 826 { 827 struct sdhci_softc *sc = device_get_softc(dev); 828 int i; 829 830 for (i = 0; i < sc->num_slots; i++) 831 sdhci_init(&sc->slots[i]); 832 return (bus_generic_resume(dev)); 833 } 834 835 static int 836 sdhci_update_ios(device_t brdev, device_t reqdev) 837 { 838 struct sdhci_slot *slot = device_get_ivars(reqdev); 839 struct mmc_ios *ios = &slot->host.ios; 840 841 SDHCI_LOCK(slot); 842 /* Do full reset on bus power down to clear from any state. */ 843 if (ios->power_mode == power_off) { 844 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 845 sdhci_init(slot); 846 } 847 /* Configure the bus. */ 848 sdhci_set_clock(slot, ios->clock); 849 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 850 if (ios->bus_width == bus_width_4) 851 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 852 else 853 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 854 if (ios->timing == bus_timing_hs) 855 slot->hostctrl |= SDHCI_CTRL_HISPD; 856 else 857 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 858 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 859 /* Some controllers like reset after bus changes. */ 860 if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS) 861 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 862 863 SDHCI_UNLOCK(slot); 864 return (0); 865 } 866 867 static void 868 sdhci_set_transfer_mode(struct sdhci_slot *slot, 869 struct mmc_data *data) 870 { 871 uint16_t mode; 872 873 if (data == NULL) 874 return; 875 876 mode = SDHCI_TRNS_BLK_CNT_EN; 877 if (data->len > 512) 878 mode |= SDHCI_TRNS_MULTI; 879 if (data->flags & MMC_DATA_READ) 880 mode |= SDHCI_TRNS_READ; 881 if (slot->req->stop) 882 mode |= SDHCI_TRNS_ACMD12; 883 if (slot->flags & SDHCI_USE_DMA) 884 mode |= SDHCI_TRNS_DMA; 885 886 WR2(slot, SDHCI_TRANSFER_MODE, mode); 887 } 888 889 static void 890 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 891 { 892 struct mmc_request *req = slot->req; 893 int flags, timeout; 894 uint32_t mask, state; 895 896 slot->curcmd = cmd; 897 slot->cmd_done = 0; 898 899 cmd->error = MMC_ERR_NONE; 900 901 /* This flags combination is not supported by controller. */ 902 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 903 slot_printf(slot, "Unsupported response type!\n"); 904 cmd->error = MMC_ERR_FAILED; 905 slot->req = NULL; 906 slot->curcmd = NULL; 907 req->done(req); 908 return; 909 } 910 911 /* Read controller present state. */ 912 state = RD4(slot, SDHCI_PRESENT_STATE); 913 /* Do not issue command if there is no card, clock or power. 914 * Controller will not detect timeout without clock active. */ 915 if ((state & SDHCI_CARD_PRESENT) == 0 || 916 slot->power == 0 || 917 slot->clock == 0) { 918 cmd->error = MMC_ERR_FAILED; 919 slot->req = NULL; 920 slot->curcmd = NULL; 921 req->done(req); 922 return; 923 } 924 /* Always wait for free CMD bus. */ 925 mask = SDHCI_CMD_INHIBIT; 926 /* Wait for free DAT if we have data or busy signal. */ 927 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 928 mask |= SDHCI_DAT_INHIBIT; 929 /* We shouldn't wait for DAT for stop commands. */ 930 if (cmd == slot->req->stop) 931 mask &= ~SDHCI_DAT_INHIBIT; 932 /* Wait for bus no more then 10 ms. */ 933 timeout = 10; 934 while (state & mask) { 935 if (timeout == 0) { 936 slot_printf(slot, "Controller never released " 937 "inhibit bit(s).\n"); 938 sdhci_dumpregs(slot); 939 cmd->error = MMC_ERR_FAILED; 940 slot->req = NULL; 941 slot->curcmd = NULL; 942 req->done(req); 943 return; 944 } 945 timeout--; 946 DELAY(1000); 947 state = RD4(slot, SDHCI_PRESENT_STATE); 948 } 949 950 /* Prepare command flags. */ 951 if (!(cmd->flags & MMC_RSP_PRESENT)) 952 flags = SDHCI_CMD_RESP_NONE; 953 else if (cmd->flags & MMC_RSP_136) 954 flags = SDHCI_CMD_RESP_LONG; 955 else if (cmd->flags & MMC_RSP_BUSY) 956 flags = SDHCI_CMD_RESP_SHORT_BUSY; 957 else 958 flags = SDHCI_CMD_RESP_SHORT; 959 if (cmd->flags & MMC_RSP_CRC) 960 flags |= SDHCI_CMD_CRC; 961 if (cmd->flags & MMC_RSP_OPCODE) 962 flags |= SDHCI_CMD_INDEX; 963 if (cmd->data) 964 flags |= SDHCI_CMD_DATA; 965 if (cmd->opcode == MMC_STOP_TRANSMISSION) 966 flags |= SDHCI_CMD_TYPE_ABORT; 967 /* Prepare data. */ 968 sdhci_start_data(slot, cmd->data); 969 /* 970 * Interrupt aggregation: To reduce total number of interrupts 971 * group response interrupt with data interrupt when possible. 972 * If there going to be data interrupt, mask response one. 973 */ 974 if (slot->data_done == 0) { 975 WR4(slot, SDHCI_SIGNAL_ENABLE, 976 slot->intmask &= ~SDHCI_INT_RESPONSE); 977 } 978 /* Set command argument. */ 979 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 980 /* Set data transfer mode. */ 981 sdhci_set_transfer_mode(slot, cmd->data); 982 /* Set command flags. */ 983 WR1(slot, SDHCI_COMMAND_FLAGS, flags); 984 /* Start command. */ 985 WR1(slot, SDHCI_COMMAND, cmd->opcode); 986 } 987 988 static void 989 sdhci_finish_command(struct sdhci_slot *slot) 990 { 991 int i; 992 993 slot->cmd_done = 1; 994 /* Interrupt aggregation: Restore command interrupt. 995 * Main restore point for the case when command interrupt 996 * happened first. */ 997 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 998 /* In case of error - reset host and return. */ 999 if (slot->curcmd->error) { 1000 sdhci_reset(slot, SDHCI_RESET_CMD); 1001 sdhci_reset(slot, SDHCI_RESET_DATA); 1002 sdhci_start(slot); 1003 return; 1004 } 1005 /* If command has response - fetch it. */ 1006 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1007 if (slot->curcmd->flags & MMC_RSP_136) { 1008 /* CRC is stripped so we need one byte shift. */ 1009 uint8_t extra = 0; 1010 for (i = 0; i < 4; i++) { 1011 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 1012 slot->curcmd->resp[3 - i] = (val << 8) + extra; 1013 extra = val >> 24; 1014 } 1015 } else 1016 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1017 } 1018 /* If data ready - finish. */ 1019 if (slot->data_done) 1020 sdhci_start(slot); 1021 } 1022 1023 static void 1024 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1025 { 1026 uint32_t target_timeout, current_timeout; 1027 uint8_t div; 1028 1029 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1030 slot->data_done = 1; 1031 return; 1032 } 1033 1034 slot->data_done = 0; 1035 1036 /* Calculate and set data timeout.*/ 1037 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1038 target_timeout = 1000000; 1039 div = 0; 1040 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1041 while (current_timeout < target_timeout) { 1042 div++; 1043 current_timeout <<= 1; 1044 if (div >= 0xF) 1045 break; 1046 } 1047 /* Compensate for an off-by-one error in the CaFe chip.*/ 1048 if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) 1049 div++; 1050 if (div >= 0xF) { 1051 slot_printf(slot, "Timeout too large!\n"); 1052 div = 0xE; 1053 } 1054 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1055 1056 if (data == NULL) 1057 return; 1058 1059 /* Use DMA if possible. */ 1060 if ((slot->opt & SDHCI_HAVE_DMA)) 1061 slot->flags |= SDHCI_USE_DMA; 1062 /* If data is small, broken DMA may return zeroes instead of data, */ 1063 if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1064 (data->len <= 512)) 1065 slot->flags &= ~SDHCI_USE_DMA; 1066 /* Some controllers require even block sizes. */ 1067 if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1068 ((data->len) & 0x3)) 1069 slot->flags &= ~SDHCI_USE_DMA; 1070 /* Load DMA buffer. */ 1071 if (slot->flags & SDHCI_USE_DMA) { 1072 if (data->flags & MMC_DATA_READ) { 1073 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 1074 } else { 1075 memcpy(slot->dmamem, data->data, 1076 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 1077 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 1078 } 1079 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1080 /* Interrupt aggregation: Mask border interrupt 1081 * for the last page and unmask else. */ 1082 if (data->len == DMA_BLOCK_SIZE) 1083 slot->intmask &= ~SDHCI_INT_DMA_END; 1084 else 1085 slot->intmask |= SDHCI_INT_DMA_END; 1086 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1087 } 1088 /* Current data offset for both PIO and DMA. */ 1089 slot->offset = 0; 1090 /* Set block size and request IRQ on 4K border. */ 1091 WR2(slot, SDHCI_BLOCK_SIZE, 1092 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1093 /* Set block count. */ 1094 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1095 } 1096 1097 static void 1098 sdhci_finish_data(struct sdhci_slot *slot) 1099 { 1100 struct mmc_data *data = slot->curcmd->data; 1101 1102 slot->data_done = 1; 1103 /* Interrupt aggregation: Restore command interrupt. 1104 * Auxillary restore point for the case when data interrupt 1105 * happened first. */ 1106 if (!slot->cmd_done) { 1107 WR4(slot, SDHCI_SIGNAL_ENABLE, 1108 slot->intmask |= SDHCI_INT_RESPONSE); 1109 } 1110 /* Unload rest of data from DMA buffer. */ 1111 if (slot->flags & SDHCI_USE_DMA) { 1112 if (data->flags & MMC_DATA_READ) { 1113 size_t left = data->len - slot->offset; 1114 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1115 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1116 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1117 } else 1118 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1119 } 1120 /* If there was error - reset the host. */ 1121 if (slot->curcmd->error) { 1122 sdhci_reset(slot, SDHCI_RESET_CMD); 1123 sdhci_reset(slot, SDHCI_RESET_DATA); 1124 sdhci_start(slot); 1125 return; 1126 } 1127 /* If we already have command response - finish. */ 1128 if (slot->cmd_done) 1129 sdhci_start(slot); 1130 } 1131 1132 static void 1133 sdhci_start(struct sdhci_slot *slot) 1134 { 1135 struct mmc_request *req; 1136 1137 req = slot->req; 1138 if (req == NULL) 1139 return; 1140 1141 if (!(slot->flags & CMD_STARTED)) { 1142 slot->flags |= CMD_STARTED; 1143 sdhci_start_command(slot, req->cmd); 1144 return; 1145 } 1146 /* We don't need this until using Auto-CMD12 feature 1147 if (!(slot->flags & STOP_STARTED) && req->stop) { 1148 slot->flags |= STOP_STARTED; 1149 sdhci_start_command(slot, req->stop); 1150 return; 1151 } 1152 */ 1153 if (sdhci_debug > 1) 1154 slot_printf(slot, "result: %d\n", req->cmd->error); 1155 if (!req->cmd->error && 1156 (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1157 sdhci_reset(slot, SDHCI_RESET_CMD); 1158 sdhci_reset(slot, SDHCI_RESET_DATA); 1159 } 1160 1161 /* We must be done -- bad idea to do this while locked? */ 1162 slot->req = NULL; 1163 slot->curcmd = NULL; 1164 req->done(req); 1165 } 1166 1167 static int 1168 sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1169 { 1170 struct sdhci_slot *slot = device_get_ivars(reqdev); 1171 1172 SDHCI_LOCK(slot); 1173 if (slot->req != NULL) { 1174 SDHCI_UNLOCK(slot); 1175 return (EBUSY); 1176 } 1177 if (sdhci_debug > 1) { 1178 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1179 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1180 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1181 (req->cmd->data)?req->cmd->data->flags:0); 1182 } 1183 slot->req = req; 1184 slot->flags = 0; 1185 sdhci_start(slot); 1186 SDHCI_UNLOCK(slot); 1187 if (dumping) { 1188 while (slot->req != NULL) { 1189 sdhci_intr(slot->sc); 1190 DELAY(10); 1191 } 1192 } 1193 return (0); 1194 } 1195 1196 static int 1197 sdhci_get_ro(device_t brdev, device_t reqdev) 1198 { 1199 struct sdhci_slot *slot = device_get_ivars(reqdev); 1200 uint32_t val; 1201 1202 SDHCI_LOCK(slot); 1203 val = RD4(slot, SDHCI_PRESENT_STATE); 1204 SDHCI_UNLOCK(slot); 1205 return (!(val & SDHCI_WRITE_PROTECT)); 1206 } 1207 1208 static int 1209 sdhci_acquire_host(device_t brdev, device_t reqdev) 1210 { 1211 struct sdhci_slot *slot = device_get_ivars(reqdev); 1212 int err = 0; 1213 1214 SDHCI_LOCK(slot); 1215 while (slot->bus_busy) 1216 lksleep(slot, &slot->lock, 0, "sdhciah", 0); 1217 slot->bus_busy++; 1218 /* Activate led. */ 1219 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1220 SDHCI_UNLOCK(slot); 1221 return (err); 1222 } 1223 1224 static int 1225 sdhci_release_host(device_t brdev, device_t reqdev) 1226 { 1227 struct sdhci_slot *slot = device_get_ivars(reqdev); 1228 1229 SDHCI_LOCK(slot); 1230 /* Deactivate led. */ 1231 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1232 slot->bus_busy--; 1233 SDHCI_UNLOCK(slot); 1234 wakeup(slot); 1235 return (0); 1236 } 1237 1238 static void 1239 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1240 { 1241 1242 if (!slot->curcmd) { 1243 slot_printf(slot, "Got command interrupt 0x%08x, but " 1244 "there is no active command.\n", intmask); 1245 sdhci_dumpregs(slot); 1246 return; 1247 } 1248 if (intmask & SDHCI_INT_TIMEOUT) 1249 slot->curcmd->error = MMC_ERR_TIMEOUT; 1250 else if (intmask & SDHCI_INT_CRC) 1251 slot->curcmd->error = MMC_ERR_BADCRC; 1252 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1253 slot->curcmd->error = MMC_ERR_FIFO; 1254 1255 sdhci_finish_command(slot); 1256 } 1257 1258 static void 1259 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1260 { 1261 1262 if (!slot->curcmd) { 1263 slot_printf(slot, "Got data interrupt 0x%08x, but " 1264 "there is no active command.\n", intmask); 1265 sdhci_dumpregs(slot); 1266 return; 1267 } 1268 if (slot->curcmd->data == NULL && 1269 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1270 slot_printf(slot, "Got data interrupt 0x%08x, but " 1271 "there is no active data operation.\n", 1272 intmask); 1273 sdhci_dumpregs(slot); 1274 return; 1275 } 1276 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1277 slot->curcmd->error = MMC_ERR_TIMEOUT; 1278 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1279 slot->curcmd->error = MMC_ERR_BADCRC; 1280 if (slot->curcmd->data == NULL && 1281 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1282 SDHCI_INT_DMA_END))) { 1283 slot_printf(slot, "Got data interrupt 0x%08x, but " 1284 "there is busy-only command.\n", intmask); 1285 sdhci_dumpregs(slot); 1286 slot->curcmd->error = MMC_ERR_INVALID; 1287 } 1288 if (slot->curcmd->error) { 1289 /* No need to continue after any error. */ 1290 sdhci_finish_data(slot); 1291 return; 1292 } 1293 1294 /* Handle PIO interrupt. */ 1295 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1296 sdhci_transfer_pio(slot); 1297 /* Handle DMA border. */ 1298 if (intmask & SDHCI_INT_DMA_END) { 1299 struct mmc_data *data = slot->curcmd->data; 1300 size_t left; 1301 1302 /* Unload DMA buffer... */ 1303 left = data->len - slot->offset; 1304 if (data->flags & MMC_DATA_READ) { 1305 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1306 BUS_DMASYNC_POSTREAD); 1307 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1308 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1309 } else { 1310 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1311 BUS_DMASYNC_POSTWRITE); 1312 } 1313 /* ... and reload it again. */ 1314 slot->offset += DMA_BLOCK_SIZE; 1315 left = data->len - slot->offset; 1316 if (data->flags & MMC_DATA_READ) { 1317 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1318 BUS_DMASYNC_PREREAD); 1319 } else { 1320 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1321 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1322 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1323 BUS_DMASYNC_PREWRITE); 1324 } 1325 /* Interrupt aggregation: Mask border interrupt 1326 * for the last page. */ 1327 if (left == DMA_BLOCK_SIZE) { 1328 slot->intmask &= ~SDHCI_INT_DMA_END; 1329 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1330 } 1331 /* Restart DMA. */ 1332 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1333 } 1334 /* We have got all data. */ 1335 if (intmask & SDHCI_INT_DATA_END) 1336 sdhci_finish_data(slot); 1337 } 1338 1339 static void 1340 sdhci_acmd_irq(struct sdhci_slot *slot) 1341 { 1342 uint16_t err; 1343 1344 err = RD4(slot, SDHCI_ACMD12_ERR); 1345 if (!slot->curcmd) { 1346 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1347 "there is no active command.\n", err); 1348 sdhci_dumpregs(slot); 1349 return; 1350 } 1351 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1352 sdhci_reset(slot, SDHCI_RESET_CMD); 1353 } 1354 1355 static void 1356 sdhci_intr(void *arg) 1357 { 1358 struct sdhci_softc *sc = (struct sdhci_softc *)arg; 1359 int i; 1360 1361 for (i = 0; i < sc->num_slots; i++) { 1362 struct sdhci_slot *slot = &sc->slots[i]; 1363 uint32_t intmask; 1364 1365 SDHCI_LOCK(slot); 1366 /* Read slot interrupt status. */ 1367 intmask = RD4(slot, SDHCI_INT_STATUS); 1368 if (intmask == 0 || intmask == 0xffffffff) { 1369 SDHCI_UNLOCK(slot); 1370 continue; 1371 } 1372 if (sdhci_debug > 2) 1373 slot_printf(slot, "Interrupt %#x\n", intmask); 1374 1375 /* Handle card presence interrupts. */ 1376 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1377 WR4(slot, SDHCI_INT_STATUS, intmask & 1378 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1379 1380 if (intmask & SDHCI_INT_CARD_REMOVE) { 1381 if (bootverbose || sdhci_debug) 1382 slot_printf(slot, "Card removed\n"); 1383 callout_stop(&slot->card_callout); 1384 taskqueue_enqueue(taskqueue_swi, 1385 &slot->card_task); 1386 } 1387 if (intmask & SDHCI_INT_CARD_INSERT) { 1388 if (bootverbose || sdhci_debug) 1389 slot_printf(slot, "Card inserted\n"); 1390 callout_reset(&slot->card_callout, hz / 2, 1391 sdhci_card_delay, slot); 1392 } 1393 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1394 } 1395 /* Handle command interrupts. */ 1396 if (intmask & SDHCI_INT_CMD_MASK) { 1397 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1398 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1399 } 1400 /* Handle data interrupts. */ 1401 if (intmask & SDHCI_INT_DATA_MASK) { 1402 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1403 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1404 } 1405 /* Handle AutoCMD12 error interrupt. */ 1406 if (intmask & SDHCI_INT_ACMD12ERR) { 1407 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1408 sdhci_acmd_irq(slot); 1409 } 1410 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1411 intmask &= ~SDHCI_INT_ACMD12ERR; 1412 intmask &= ~SDHCI_INT_ERROR; 1413 /* Handle bus power interrupt. */ 1414 if (intmask & SDHCI_INT_BUS_POWER) { 1415 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1416 slot_printf(slot, 1417 "Card is consuming too much power!\n"); 1418 intmask &= ~SDHCI_INT_BUS_POWER; 1419 } 1420 /* The rest is unknown. */ 1421 if (intmask) { 1422 WR4(slot, SDHCI_INT_STATUS, intmask); 1423 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1424 intmask); 1425 sdhci_dumpregs(slot); 1426 } 1427 1428 SDHCI_UNLOCK(slot); 1429 } 1430 } 1431 1432 static int 1433 sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1434 { 1435 struct sdhci_slot *slot = device_get_ivars(child); 1436 1437 switch (which) { 1438 default: 1439 return (EINVAL); 1440 case MMCBR_IVAR_BUS_MODE: 1441 *(int *)result = slot->host.ios.bus_mode; 1442 break; 1443 case MMCBR_IVAR_BUS_WIDTH: 1444 *(int *)result = slot->host.ios.bus_width; 1445 break; 1446 case MMCBR_IVAR_CHIP_SELECT: 1447 *(int *)result = slot->host.ios.chip_select; 1448 break; 1449 case MMCBR_IVAR_CLOCK: 1450 *(int *)result = slot->host.ios.clock; 1451 break; 1452 case MMCBR_IVAR_F_MIN: 1453 *(int *)result = slot->host.f_min; 1454 break; 1455 case MMCBR_IVAR_F_MAX: 1456 *(int *)result = slot->host.f_max; 1457 break; 1458 case MMCBR_IVAR_HOST_OCR: 1459 *(int *)result = slot->host.host_ocr; 1460 break; 1461 case MMCBR_IVAR_MODE: 1462 *(int *)result = slot->host.mode; 1463 break; 1464 case MMCBR_IVAR_OCR: 1465 *(int *)result = slot->host.ocr; 1466 break; 1467 case MMCBR_IVAR_POWER_MODE: 1468 *(int *)result = slot->host.ios.power_mode; 1469 break; 1470 case MMCBR_IVAR_VDD: 1471 *(int *)result = slot->host.ios.vdd; 1472 break; 1473 case MMCBR_IVAR_CAPS: 1474 *(int *)result = slot->host.caps; 1475 break; 1476 case MMCBR_IVAR_TIMING: 1477 *(int *)result = slot->host.ios.timing; 1478 break; 1479 case MMCBR_IVAR_MAX_DATA: 1480 *(int *)result = 65535; 1481 break; 1482 } 1483 return (0); 1484 } 1485 1486 static int 1487 sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1488 { 1489 struct sdhci_slot *slot = device_get_ivars(child); 1490 1491 switch (which) { 1492 default: 1493 return (EINVAL); 1494 case MMCBR_IVAR_BUS_MODE: 1495 slot->host.ios.bus_mode = value; 1496 break; 1497 case MMCBR_IVAR_BUS_WIDTH: 1498 slot->host.ios.bus_width = value; 1499 break; 1500 case MMCBR_IVAR_CHIP_SELECT: 1501 slot->host.ios.chip_select = value; 1502 break; 1503 case MMCBR_IVAR_CLOCK: 1504 if (value > 0) { 1505 uint32_t clock = slot->max_clk; 1506 int i; 1507 1508 for (i = 0; i < 8; i++) { 1509 if (clock <= value) 1510 break; 1511 clock >>= 1; 1512 } 1513 slot->host.ios.clock = clock; 1514 } else 1515 slot->host.ios.clock = 0; 1516 break; 1517 case MMCBR_IVAR_MODE: 1518 slot->host.mode = value; 1519 break; 1520 case MMCBR_IVAR_OCR: 1521 slot->host.ocr = value; 1522 break; 1523 case MMCBR_IVAR_POWER_MODE: 1524 slot->host.ios.power_mode = value; 1525 break; 1526 case MMCBR_IVAR_VDD: 1527 slot->host.ios.vdd = value; 1528 break; 1529 case MMCBR_IVAR_TIMING: 1530 slot->host.ios.timing = value; 1531 break; 1532 case MMCBR_IVAR_CAPS: 1533 case MMCBR_IVAR_HOST_OCR: 1534 case MMCBR_IVAR_F_MIN: 1535 case MMCBR_IVAR_F_MAX: 1536 case MMCBR_IVAR_MAX_DATA: 1537 return (EINVAL); 1538 } 1539 return (0); 1540 } 1541 1542 static device_method_t sdhci_methods[] = { 1543 /* device_if */ 1544 DEVMETHOD(device_probe, sdhci_probe), 1545 DEVMETHOD(device_attach, sdhci_attach), 1546 DEVMETHOD(device_detach, sdhci_detach), 1547 DEVMETHOD(device_suspend, sdhci_suspend), 1548 DEVMETHOD(device_resume, sdhci_resume), 1549 1550 /* Bus interface */ 1551 DEVMETHOD(bus_read_ivar, sdhci_read_ivar), 1552 DEVMETHOD(bus_write_ivar, sdhci_write_ivar), 1553 1554 /* mmcbr_if */ 1555 DEVMETHOD(mmcbr_update_ios, sdhci_update_ios), 1556 DEVMETHOD(mmcbr_request, sdhci_request), 1557 DEVMETHOD(mmcbr_get_ro, sdhci_get_ro), 1558 DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host), 1559 DEVMETHOD(mmcbr_release_host, sdhci_release_host), 1560 1561 {0, 0}, 1562 }; 1563 1564 static driver_t sdhci_driver = { 1565 "sdhci", 1566 sdhci_methods, 1567 sizeof(struct sdhci_softc), 1568 }; 1569 static devclass_t sdhci_devclass; 1570 1571 1572 DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0); 1573