1 /*- 2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 3 * PCI-SCSI controllers. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * 7 * This driver also supports the following Symbios/LSI PCI-SCSI chips: 8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 10 * 11 * 12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 13 * Copyright (C) 1998-1999 Gerard Roudier 14 * 15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 16 * a port of the FreeBSD ncr driver to Linux-1.2.13. 17 * 18 * The original ncr driver has been written for 386bsd and FreeBSD by 19 * Wolfgang Stanglmeier <wolf@cologne.de> 20 * Stefan Esser <se@mi.Uni-Koeln.de> 21 * Copyright (C) 1994 Wolfgang Stanglmeier 22 * 23 * The initialisation code, and part of the code that addresses 24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 25 * written by Justin T. Gibbs. 26 * 27 * Other major contributions: 28 * 29 * NVRAM detection and reading. 30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 31 * 32 *----------------------------------------------------------------------------- 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 * 57 * $FreeBSD: src/sys/dev/sym/sym_hipd.c,v 1.76 2011/10/07 08:59:54 marius Exp $ 58 */ 59 60 #define SYM_DRIVER_NAME "sym-1.6.5-20000902" 61 62 /* #define SYM_DEBUG_GENERIC_SUPPORT */ 63 64 #include <sys/param.h> 65 66 /* 67 * Driver configuration options. 68 */ 69 #include "opt_sym.h" 70 #include <dev/disk/sym/sym_conf.h> 71 72 73 #include <sys/systm.h> 74 #include <sys/malloc.h> 75 #include <sys/endian.h> 76 #include <sys/kernel.h> 77 #include <sys/lock.h> 78 #include <sys/module.h> 79 #include <sys/bus.h> 80 81 #include <sys/proc.h> 82 83 #include <bus/pci/pcireg.h> 84 #include <bus/pci/pcivar.h> 85 86 #include <sys/rman.h> 87 88 #include <bus/cam/cam.h> 89 #include <bus/cam/cam_ccb.h> 90 #include <bus/cam/cam_sim.h> 91 #include <bus/cam/cam_xpt_sim.h> 92 #include <bus/cam/cam_debug.h> 93 94 #include <bus/cam/scsi/scsi_all.h> 95 #include <bus/cam/scsi/scsi_message.h> 96 97 /* Short and quite clear integer types */ 98 typedef int8_t s8; 99 typedef int16_t s16; 100 typedef int32_t s32; 101 typedef u_int8_t u8; 102 typedef u_int16_t u16; 103 typedef u_int32_t u32; 104 105 /* 106 * Driver definitions. 107 */ 108 #include <dev/disk/sym/sym_defs.h> 109 #include <dev/disk/sym/sym_fw.h> 110 111 /* 112 * IA32 architecture does not reorder STORES and prevents 113 * LOADS from passing STORES. It is called `program order' 114 * by Intel and allows device drivers to deal with memory 115 * ordering by only ensuring that the code is not reordered 116 * by the compiler when ordering is required. 117 * Other architectures implement a weaker ordering that 118 * requires memory barriers (and also IO barriers when they 119 * make sense) to be used. 120 */ 121 122 #if defined __x86_64__ 123 #define MEMORY_BARRIER() do { ; } while(0) 124 #else 125 #error "Not supported platform" 126 #endif 127 128 /* 129 * A la VMS/CAM-3 queue management. 130 */ 131 132 typedef struct sym_quehead { 133 struct sym_quehead *flink; /* Forward pointer */ 134 struct sym_quehead *blink; /* Backward pointer */ 135 } SYM_QUEHEAD; 136 137 #define sym_que_init(ptr) do { \ 138 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \ 139 } while (0) 140 141 static __inline struct sym_quehead *sym_que_first(struct sym_quehead *head) 142 { 143 return (head->flink == head) ? NULL : head->flink; 144 } 145 146 static __inline struct sym_quehead *sym_que_last(struct sym_quehead *head) 147 { 148 return (head->blink == head) ? NULL : head->blink; 149 } 150 151 static __inline void __sym_que_add(struct sym_quehead * new, 152 struct sym_quehead * blink, 153 struct sym_quehead * flink) 154 { 155 flink->blink = new; 156 new->flink = flink; 157 new->blink = blink; 158 blink->flink = new; 159 } 160 161 static __inline void __sym_que_del(struct sym_quehead * blink, 162 struct sym_quehead * flink) 163 { 164 flink->blink = blink; 165 blink->flink = flink; 166 } 167 168 static __inline int sym_que_empty(struct sym_quehead *head) 169 { 170 return head->flink == head; 171 } 172 173 static __inline void sym_que_splice(struct sym_quehead *list, 174 struct sym_quehead *head) 175 { 176 struct sym_quehead *first = list->flink; 177 178 if (first != list) { 179 struct sym_quehead *last = list->blink; 180 struct sym_quehead *at = head->flink; 181 182 first->blink = head; 183 head->flink = first; 184 185 last->flink = at; 186 at->blink = last; 187 } 188 } 189 190 #define sym_que_entry(ptr, type, member) \ 191 ((type *)((char *)(ptr)-(size_t)(&((type *)0)->member))) 192 193 194 #define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink) 195 196 #define sym_remque(el) __sym_que_del((el)->blink, (el)->flink) 197 198 #define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink) 199 200 static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head) 201 { 202 struct sym_quehead *elem = head->flink; 203 204 if (elem != head) 205 __sym_que_del(head, elem->flink); 206 else 207 elem = NULL; 208 return elem; 209 } 210 211 #define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head) 212 213 static __inline struct sym_quehead *sym_remque_tail(struct sym_quehead *head) 214 { 215 struct sym_quehead *elem = head->blink; 216 217 if (elem != head) 218 __sym_que_del(elem->blink, head); 219 else 220 elem = NULL; 221 return elem; 222 } 223 224 /* 225 * This one may be useful. 226 */ 227 #define FOR_EACH_QUEUED_ELEMENT(head, qp) \ 228 for (qp = (head)->flink; qp != (head); qp = qp->flink) 229 /* 230 * FreeBSD does not offer our kind of queue in the CAM CCB. 231 * So, we have to cast. 232 */ 233 #define sym_qptr(p) ((struct sym_quehead *) (p)) 234 235 /* 236 * Simple bitmap operations. 237 */ 238 #define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f))) 239 #define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f))) 240 #define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f))) 241 242 /* 243 * Number of tasks per device we want to handle. 244 */ 245 #if SYM_CONF_MAX_TAG_ORDER > 8 246 #error "more than 256 tags per logical unit not allowed." 247 #endif 248 #define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER) 249 250 /* 251 * Donnot use more tasks that we can handle. 252 */ 253 #ifndef SYM_CONF_MAX_TAG 254 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 255 #endif 256 #if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK 257 #undef SYM_CONF_MAX_TAG 258 #define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 259 #endif 260 261 /* 262 * This one means 'NO TAG for this job' 263 */ 264 #define NO_TAG (256) 265 266 /* 267 * Number of SCSI targets. 268 */ 269 #if SYM_CONF_MAX_TARGET > 16 270 #error "more than 16 targets not allowed." 271 #endif 272 273 /* 274 * Number of logical units per target. 275 */ 276 #if SYM_CONF_MAX_LUN > 64 277 #error "more than 64 logical units per target not allowed." 278 #endif 279 280 /* 281 * Asynchronous pre-scaler (ns). Shall be 40 for 282 * the SCSI timings to be compliant. 283 */ 284 #define SYM_CONF_MIN_ASYNC (40) 285 286 /* 287 * Number of entries in the START and DONE queues. 288 * 289 * We limit to 1 PAGE in order to succeed allocation of 290 * these queues. Each entry is 8 bytes long (2 DWORDS). 291 */ 292 #ifdef SYM_CONF_MAX_START 293 #define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2) 294 #else 295 #define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2) 296 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 297 #endif 298 299 #if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8 300 #undef SYM_CONF_MAX_QUEUE 301 #define SYM_CONF_MAX_QUEUE PAGE_SIZE/8 302 #undef SYM_CONF_MAX_START 303 #define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 304 #endif 305 306 /* 307 * For this one, we want a short name :-) 308 */ 309 #define MAX_QUEUE SYM_CONF_MAX_QUEUE 310 311 /* 312 * Active debugging tags and verbosity. 313 */ 314 #define DEBUG_ALLOC (0x0001) 315 #define DEBUG_PHASE (0x0002) 316 #define DEBUG_POLL (0x0004) 317 #define DEBUG_QUEUE (0x0008) 318 #define DEBUG_RESULT (0x0010) 319 #define DEBUG_SCATTER (0x0020) 320 #define DEBUG_SCRIPT (0x0040) 321 #define DEBUG_TINY (0x0080) 322 #define DEBUG_TIMING (0x0100) 323 #define DEBUG_NEGO (0x0200) 324 #define DEBUG_TAGS (0x0400) 325 #define DEBUG_POINTER (0x0800) 326 327 #if 0 328 static int sym_debug = 0; 329 #define DEBUG_FLAGS sym_debug 330 #else 331 /* #define DEBUG_FLAGS (0x0631) */ 332 #define DEBUG_FLAGS (0x0000) 333 334 #endif 335 #define sym_verbose (np->verbose) 336 337 /* 338 * Insert a delay in micro-seconds and milli-seconds. 339 */ 340 static void UDELAY(int us) { DELAY(us); } 341 static void MDELAY(int ms) { while (ms--) UDELAY(1000); } 342 343 /* 344 * Simple power of two buddy-like allocator. 345 * 346 * This simple code is not intended to be fast, but to 347 * provide power of 2 aligned memory allocations. 348 * Since the SCRIPTS processor only supplies 8 bit arithmetic, 349 * this allocator allows simple and fast address calculations 350 * from the SCRIPTS code. In addition, cache line alignment 351 * is guaranteed for power of 2 cache line size. 352 * 353 * This allocator has been developed for the Linux sym53c8xx 354 * driver, since this O/S does not provide naturally aligned 355 * allocations. 356 * It has the advantage of allowing the driver to use private 357 * pages of memory that will be useful if we ever need to deal 358 * with IO MMUs for PCI. 359 */ 360 361 #define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */ 362 #define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */ 363 #if 0 364 #define MEMO_FREE_UNUSED /* Free unused pages immediately */ 365 #endif 366 #define MEMO_WARN 1 367 #define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER) 368 #define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT) 369 #define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1) 370 371 #define get_pages() kmalloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_INTWAIT) 372 #define free_pages(p) kfree((p), M_DEVBUF) 373 374 typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */ 375 376 typedef struct m_link { /* Link between free memory chunks */ 377 struct m_link *next; 378 } m_link_s; 379 380 typedef struct m_vtob { /* Virtual to Bus address translation */ 381 struct m_vtob *next; 382 bus_dmamap_t dmamap; /* Map for this chunk */ 383 m_addr_t vaddr; /* Virtual address */ 384 m_addr_t baddr; /* Bus physical address */ 385 } m_vtob_s; 386 /* Hash this stuff a bit to speed up translations */ 387 #define VTOB_HASH_SHIFT 5 388 #define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT) 389 #define VTOB_HASH_MASK (VTOB_HASH_SIZE-1) 390 #define VTOB_HASH_CODE(m) \ 391 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK) 392 393 typedef struct m_pool { /* Memory pool of a given kind */ 394 bus_dma_tag_t dev_dmat; /* Identifies the pool */ 395 bus_dma_tag_t dmat; /* Tag for our fixed allocations */ 396 m_addr_t (*getp)(struct m_pool *); 397 #ifdef MEMO_FREE_UNUSED 398 void (*freep)(struct m_pool *, m_addr_t); 399 #endif 400 #define M_GETP() mp->getp(mp) 401 #define M_FREEP(p) mp->freep(mp, p) 402 int nump; 403 m_vtob_s *(vtob[VTOB_HASH_SIZE]); 404 struct m_pool *next; 405 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1]; 406 } m_pool_s; 407 408 static void *___sym_malloc(m_pool_s *mp, int size) 409 { 410 int i = 0; 411 int s = (1 << MEMO_SHIFT); 412 int j; 413 m_addr_t a; 414 m_link_s *h = mp->h; 415 416 if (size > MEMO_CLUSTER_SIZE) 417 return NULL; 418 419 while (size > s) { 420 s <<= 1; 421 ++i; 422 } 423 424 j = i; 425 while (!h[j].next) { 426 if (s == MEMO_CLUSTER_SIZE) { 427 h[j].next = (m_link_s *) M_GETP(); 428 if (h[j].next) 429 h[j].next->next = NULL; 430 break; 431 } 432 ++j; 433 s <<= 1; 434 } 435 a = (m_addr_t) h[j].next; 436 if (a) { 437 h[j].next = h[j].next->next; 438 while (j > i) { 439 j -= 1; 440 s >>= 1; 441 h[j].next = (m_link_s *) (a+s); 442 h[j].next->next = NULL; 443 } 444 } 445 #ifdef DEBUG 446 kprintf("___sym_malloc(%d) = %p\n", size, (void *) a); 447 #endif 448 return (void *) a; 449 } 450 451 static void ___sym_mfree(m_pool_s *mp, void *ptr, int size) 452 { 453 int i = 0; 454 int s = (1 << MEMO_SHIFT); 455 m_link_s *q; 456 m_addr_t a, b; 457 m_link_s *h = mp->h; 458 459 #ifdef DEBUG 460 kprintf("___sym_mfree(%p, %d)\n", ptr, size); 461 #endif 462 463 if (size > MEMO_CLUSTER_SIZE) 464 return; 465 466 while (size > s) { 467 s <<= 1; 468 ++i; 469 } 470 471 a = (m_addr_t) ptr; 472 473 while (1) { 474 #ifdef MEMO_FREE_UNUSED 475 if (s == MEMO_CLUSTER_SIZE) { 476 M_FREEP(a); 477 break; 478 } 479 #endif 480 b = a ^ s; 481 q = &h[i]; 482 while (q->next && q->next != (m_link_s *) b) { 483 q = q->next; 484 } 485 if (!q->next) { 486 ((m_link_s *) a)->next = h[i].next; 487 h[i].next = (m_link_s *) a; 488 break; 489 } 490 q->next = q->next->next; 491 a = a & b; 492 s <<= 1; 493 ++i; 494 } 495 } 496 497 static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags) 498 { 499 void *p; 500 501 p = ___sym_malloc(mp, size); 502 503 if (DEBUG_FLAGS & DEBUG_ALLOC) 504 kprintf ("new %-10s[%4d] @%p.\n", name, size, p); 505 506 if (p) 507 bzero(p, size); 508 else if (uflags & MEMO_WARN) 509 kprintf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size); 510 511 return p; 512 } 513 514 #define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN) 515 516 static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name) 517 { 518 if (DEBUG_FLAGS & DEBUG_ALLOC) 519 kprintf ("freeing %-10s[%4d] @%p.\n", name, size, ptr); 520 521 ___sym_mfree(mp, ptr, size); 522 523 } 524 525 /* 526 * Default memory pool we donnot need to involve in DMA. 527 */ 528 /* 529 * With the `bus dma abstraction', we use a separate pool for 530 * memory we donnot need to involve in DMA. 531 */ 532 static m_addr_t ___mp0_getp(m_pool_s *mp) 533 { 534 m_addr_t m = (m_addr_t) get_pages(); 535 if (m) 536 ++mp->nump; 537 return m; 538 } 539 540 #ifdef MEMO_FREE_UNUSED 541 static void ___mp0_freep(m_pool_s *mp, m_addr_t m) 542 { 543 free_pages(m); 544 --mp->nump; 545 } 546 #endif 547 548 #ifdef MEMO_FREE_UNUSED 549 static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep}; 550 #else 551 static m_pool_s mp0 = {0, 0, ___mp0_getp}; 552 #endif 553 554 555 /* 556 * Actual memory allocation routine for non-DMAed memory. 557 */ 558 static void *sym_calloc(int size, char *name) 559 { 560 void *m; 561 /* Lock */ 562 m = __sym_calloc(&mp0, size, name); 563 /* Unlock */ 564 return m; 565 } 566 567 /* 568 * Actual memory allocation routine for non-DMAed memory. 569 */ 570 static void sym_mfree(void *ptr, int size, char *name) 571 { 572 /* Lock */ 573 __sym_mfree(&mp0, ptr, size, name); 574 /* Unlock */ 575 } 576 577 /* 578 * DMAable pools. 579 */ 580 /* 581 * With `bus dma abstraction', we use a separate pool per parent 582 * BUS handle. A reverse table (hashed) is maintained for virtual 583 * to BUS address translation. 584 */ 585 static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 586 { 587 bus_addr_t *baddr; 588 baddr = (bus_addr_t *)arg; 589 *baddr = segs->ds_addr; 590 } 591 592 static m_addr_t ___dma_getp(m_pool_s *mp) 593 { 594 m_vtob_s *vbp; 595 void *vaddr = NULL; 596 bus_addr_t baddr = 0; 597 598 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB"); 599 if (!vbp) 600 goto out_err; 601 602 if (bus_dmamem_alloc(mp->dmat, &vaddr, 603 BUS_DMA_COHERENT | BUS_DMA_WAITOK, &vbp->dmamap)) 604 goto out_err; 605 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr, 606 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, BUS_DMA_NOWAIT); 607 if (baddr) { 608 int hc = VTOB_HASH_CODE(vaddr); 609 vbp->vaddr = (m_addr_t) vaddr; 610 vbp->baddr = (m_addr_t) baddr; 611 vbp->next = mp->vtob[hc]; 612 mp->vtob[hc] = vbp; 613 ++mp->nump; 614 return (m_addr_t) vaddr; 615 } 616 out_err: 617 if (baddr) 618 bus_dmamap_unload(mp->dmat, vbp->dmamap); 619 if (vaddr) 620 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap); 621 if (vbp) { 622 if (vbp->dmamap) 623 bus_dmamap_destroy(mp->dmat, vbp->dmamap); 624 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 625 } 626 return 0; 627 } 628 629 #ifdef MEMO_FREE_UNUSED 630 static void ___dma_freep(m_pool_s *mp, m_addr_t m) 631 { 632 m_vtob_s **vbpp, *vbp; 633 int hc = VTOB_HASH_CODE(m); 634 635 vbpp = &mp->vtob[hc]; 636 while (*vbpp && (*vbpp)->vaddr != m) 637 vbpp = &(*vbpp)->next; 638 if (*vbpp) { 639 vbp = *vbpp; 640 *vbpp = (*vbpp)->next; 641 bus_dmamap_unload(mp->dmat, vbp->dmamap); 642 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap); 643 bus_dmamap_destroy(mp->dmat, vbp->dmamap); 644 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB"); 645 --mp->nump; 646 } 647 } 648 #endif 649 650 static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat) 651 { 652 m_pool_s *mp; 653 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next); 654 return mp; 655 } 656 657 static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat) 658 { 659 m_pool_s *mp = NULL; 660 661 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL"); 662 if (mp) { 663 mp->dev_dmat = dev_dmat; 664 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE, 665 BUS_SPACE_MAXADDR_32BIT, 666 BUS_SPACE_MAXADDR, 667 NULL, NULL, MEMO_CLUSTER_SIZE, 1, 668 MEMO_CLUSTER_SIZE, 0, 669 &mp->dmat)) { 670 mp->getp = ___dma_getp; 671 #ifdef MEMO_FREE_UNUSED 672 mp->freep = ___dma_freep; 673 #endif 674 mp->next = mp0.next; 675 mp0.next = mp; 676 return mp; 677 } 678 } 679 if (mp) 680 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL"); 681 return NULL; 682 } 683 684 #ifdef MEMO_FREE_UNUSED 685 static void ___del_dma_pool(m_pool_s *p) 686 { 687 struct m_pool **pp = &mp0.next; 688 689 while (*pp && *pp != p) 690 pp = &(*pp)->next; 691 if (*pp) { 692 *pp = (*pp)->next; 693 bus_dma_tag_destroy(p->dmat); 694 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL"); 695 } 696 } 697 #endif 698 699 static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name) 700 { 701 struct m_pool *mp; 702 void *m = NULL; 703 704 /* Lock */ 705 mp = ___get_dma_pool(dev_dmat); 706 if (!mp) 707 mp = ___cre_dma_pool(dev_dmat); 708 if (mp) 709 m = __sym_calloc(mp, size, name); 710 #ifdef MEMO_FREE_UNUSED 711 if (mp && !mp->nump) 712 ___del_dma_pool(mp); 713 #endif 714 /* Unlock */ 715 716 return m; 717 } 718 719 static void 720 __sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name) 721 { 722 struct m_pool *mp; 723 724 /* Lock */ 725 mp = ___get_dma_pool(dev_dmat); 726 if (mp) 727 __sym_mfree(mp, m, size, name); 728 #ifdef MEMO_FREE_UNUSED 729 if (mp && !mp->nump) 730 ___del_dma_pool(mp); 731 #endif 732 /* Unlock */ 733 } 734 735 static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m) 736 { 737 m_pool_s *mp; 738 int hc = VTOB_HASH_CODE(m); 739 m_vtob_s *vp = NULL; 740 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK; 741 742 /* Lock */ 743 mp = ___get_dma_pool(dev_dmat); 744 if (mp) { 745 vp = mp->vtob[hc]; 746 while (vp && vp->vaddr != a) 747 vp = vp->next; 748 } 749 /* Unlock */ 750 if (!vp) 751 panic("sym: VTOBUS FAILED!"); 752 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0; 753 } 754 755 756 /* 757 * Verbs for DMAable memory handling. 758 * The _uvptv_ macro avoids a nasty warning about pointer to volatile 759 * being discarded. 760 */ 761 #define _uvptv_(p) ((void *)((vm_offset_t)(p))) 762 #define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n) 763 #define _sym_mfree_dma(np, p, s, n) \ 764 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n) 765 #define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n) 766 #define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n) 767 #define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p)) 768 #define vtobus(p) _vtobus(np, p) 769 770 771 /* 772 * Print a buffer in hexadecimal format. 773 */ 774 static void sym_printb_hex (u_char *p, int n) 775 { 776 while (n-- > 0) 777 kprintf (" %x", *p++); 778 } 779 780 /* 781 * Same with a label at beginning and .\n at end. 782 */ 783 static void sym_printl_hex (char *label, u_char *p, int n) 784 { 785 kprintf ("%s", label); 786 sym_printb_hex (p, n); 787 kprintf (".\n"); 788 } 789 790 /* 791 * Return a string for SCSI BUS mode. 792 */ 793 static const char *sym_scsi_bus_mode(int mode) 794 { 795 switch(mode) { 796 case SMODE_HVD: return "HVD"; 797 case SMODE_SE: return "SE"; 798 case SMODE_LVD: return "LVD"; 799 } 800 return "??"; 801 } 802 803 /* 804 * Some poor and bogus sync table that refers to Tekram NVRAM layout. 805 */ 806 #ifdef SYM_CONF_NVRAM_SUPPORT 807 static const u_char Tekram_sync[16] = 808 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10}; 809 #endif 810 811 /* 812 * Union of supported NVRAM formats. 813 */ 814 struct sym_nvram { 815 int type; 816 #define SYM_SYMBIOS_NVRAM (1) 817 #define SYM_TEKRAM_NVRAM (2) 818 #ifdef SYM_CONF_NVRAM_SUPPORT 819 union { 820 Symbios_nvram Symbios; 821 Tekram_nvram Tekram; 822 } data; 823 #endif 824 }; 825 826 /* 827 * This one is hopefully useless, but actually useful. :-) 828 */ 829 #ifndef assert 830 #define assert(expression) { \ 831 if (!(expression)) { \ 832 (void)panic( \ 833 "assertion \"%s\" failed: file \"%s\", line %d", \ 834 #expression, \ 835 __FILE__, __LINE__); \ 836 } \ 837 } 838 #endif 839 840 /* 841 * Some provision for a possible big endian mode supported by 842 * Symbios chips (never seen, by the way). 843 * For now, this stuff does not deserve any comments. :) 844 */ 845 846 #define sym_offb(o) (o) 847 #define sym_offw(o) (o) 848 849 /* 850 * Some provision for support for BIG ENDIAN CPU. 851 */ 852 853 #define cpu_to_scr(dw) htole32(dw) 854 #define scr_to_cpu(dw) le32toh(dw) 855 856 /* 857 * Access to the chip IO registers and on-chip RAM. 858 * We use the `bus space' interface under FreeBSD-4 and 859 * later kernel versions. 860 */ 861 862 863 #if defined(SYM_CONF_IOMAPPED) 864 865 #define INB_OFF(o) bus_read_1(np->io_res, (o)) 866 #define INW_OFF(o) bus_read_2(np->io_res, (o)) 867 #define INL_OFF(o) bus_read_4(np->io_res, (o)) 868 869 #define OUTB_OFF(o, v) bus_write_1(np->io_res, (o), (v)) 870 #define OUTW_OFF(o, v) bus_write_2(np->io_res, (o), (v)) 871 #define OUTL_OFF(o, v) bus_write_4(np->io_res, (o), (v)) 872 873 #else /* Memory mapped IO */ 874 875 #define INB_OFF(o) bus_read_1(np->mmio_res, (o)) 876 #define INW_OFF(o) bus_read_2(np->mmio_res, (o)) 877 #define INL_OFF(o) bus_read_4(np->mmio_res, (o)) 878 879 #define OUTB_OFF(o, v) bus_write_1(np->mmio_res, (o), (v)) 880 #define OUTW_OFF(o, v) bus_write_2(np->mmio_res, (o), (v)) 881 #define OUTL_OFF(o, v) bus_write_4(np->mmio_res, (o), (v)) 882 883 #endif /* SYM_CONF_IOMAPPED */ 884 885 #define OUTRAM_OFF(o, a, l) \ 886 bus_write_region_1(np->ram_res, (o), (a), (l)) 887 888 889 /* 890 * Common definitions for both bus space and legacy IO methods. 891 */ 892 #define INB(r) INB_OFF(offsetof(struct sym_reg,r)) 893 #define INW(r) INW_OFF(offsetof(struct sym_reg,r)) 894 #define INL(r) INL_OFF(offsetof(struct sym_reg,r)) 895 896 #define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v)) 897 #define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v)) 898 #define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v)) 899 900 #define OUTONB(r, m) OUTB(r, INB(r) | (m)) 901 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) 902 #define OUTONW(r, m) OUTW(r, INW(r) | (m)) 903 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) 904 #define OUTONL(r, m) OUTL(r, INL(r) | (m)) 905 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) 906 907 /* 908 * We normally want the chip to have a consistent view 909 * of driver internal data structures when we restart it. 910 * Thus these macros. 911 */ 912 #define OUTL_DSP(v) \ 913 do { \ 914 MEMORY_BARRIER(); \ 915 OUTL (nc_dsp, (v)); \ 916 } while (0) 917 918 #define OUTONB_STD() \ 919 do { \ 920 MEMORY_BARRIER(); \ 921 OUTONB (nc_dcntl, (STD|NOCOM)); \ 922 } while (0) 923 924 /* 925 * Command control block states. 926 */ 927 #define HS_IDLE (0) 928 #define HS_BUSY (1) 929 #define HS_NEGOTIATE (2) /* sync/wide data transfer*/ 930 #define HS_DISCONNECT (3) /* Disconnected by target */ 931 #define HS_WAIT (4) /* waiting for resource */ 932 933 #define HS_DONEMASK (0x80) 934 #define HS_COMPLETE (4|HS_DONEMASK) 935 #define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */ 936 #define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */ 937 #define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */ 938 939 /* 940 * Software Interrupt Codes 941 */ 942 #define SIR_BAD_SCSI_STATUS (1) 943 #define SIR_SEL_ATN_NO_MSG_OUT (2) 944 #define SIR_MSG_RECEIVED (3) 945 #define SIR_MSG_WEIRD (4) 946 #define SIR_NEGO_FAILED (5) 947 #define SIR_NEGO_PROTO (6) 948 #define SIR_SCRIPT_STOPPED (7) 949 #define SIR_REJECT_TO_SEND (8) 950 #define SIR_SWIDE_OVERRUN (9) 951 #define SIR_SODL_UNDERRUN (10) 952 #define SIR_RESEL_NO_MSG_IN (11) 953 #define SIR_RESEL_NO_IDENTIFY (12) 954 #define SIR_RESEL_BAD_LUN (13) 955 #define SIR_TARGET_SELECTED (14) 956 #define SIR_RESEL_BAD_I_T_L (15) 957 #define SIR_RESEL_BAD_I_T_L_Q (16) 958 #define SIR_ABORT_SENT (17) 959 #define SIR_RESEL_ABORTED (18) 960 #define SIR_MSG_OUT_DONE (19) 961 #define SIR_COMPLETE_ERROR (20) 962 #define SIR_DATA_OVERRUN (21) 963 #define SIR_BAD_PHASE (22) 964 #define SIR_MAX (22) 965 966 /* 967 * Extended error bit codes. 968 * xerr_status field of struct sym_ccb. 969 */ 970 #define XE_EXTRA_DATA (1) /* unexpected data phase */ 971 #define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */ 972 #define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */ 973 #define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */ 974 #define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */ 975 976 /* 977 * Negotiation status. 978 * nego_status field of struct sym_ccb. 979 */ 980 #define NS_SYNC (1) 981 #define NS_WIDE (2) 982 #define NS_PPR (3) 983 984 /* 985 * A CCB hashed table is used to retrieve CCB address 986 * from DSA value. 987 */ 988 #define CCB_HASH_SHIFT 8 989 #define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT) 990 #define CCB_HASH_MASK (CCB_HASH_SIZE-1) 991 #define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK) 992 993 /* 994 * Device flags. 995 */ 996 #define SYM_DISC_ENABLED (1) 997 #define SYM_TAGS_ENABLED (1<<1) 998 #define SYM_SCAN_BOOT_DISABLED (1<<2) 999 #define SYM_SCAN_LUNS_DISABLED (1<<3) 1000 1001 /* 1002 * Host adapter miscellaneous flags. 1003 */ 1004 #define SYM_AVOID_BUS_RESET (1) 1005 #define SYM_SCAN_TARGETS_HILO (1<<1) 1006 1007 /* 1008 * Device quirks. 1009 * Some devices, for example the CHEETAH 2 LVD, disconnects without 1010 * saving the DATA POINTER then reselects and terminates the IO. 1011 * On reselection, the automatic RESTORE DATA POINTER makes the 1012 * CURRENT DATA POINTER not point at the end of the IO. 1013 * This behaviour just breaks our calculation of the residual. 1014 * For now, we just force an AUTO SAVE on disconnection and will 1015 * fix that in a further driver version. 1016 */ 1017 #define SYM_QUIRK_AUTOSAVE 1 1018 1019 /* 1020 * Misc. 1021 */ 1022 #define SYM_LOCK() lockmgr(&np->lock, LK_EXCLUSIVE) 1023 #define SYM_LOCK_ASSERT(_what) KKASSERT(lockstatus(&np->lock, curthread) == (_what)) 1024 #define SYM_LOCK_DESTROY() lockuninit(&np->lock) 1025 #define SYM_LOCK_INIT() lockinit(&np->lock, "sym_lock", 0, LK_CANRECURSE) 1026 #if 0 /* XXX swildner */ 1027 #define SYM_LOCK_INITIALIZED() mtx_initialized(&np->lock) 1028 #endif 1029 #define SYM_UNLOCK() lockmgr(&np->lock, LK_RELEASE) 1030 1031 #define SYM_SNOOP_TIMEOUT (10000000) 1032 #define SYM_PCI_IO PCIR_BAR(0) 1033 #define SYM_PCI_MMIO PCIR_BAR(1) 1034 #define SYM_PCI_RAM PCIR_BAR(2) 1035 #define SYM_PCI_RAM64 PCIR_BAR(3) 1036 1037 /* 1038 * Back-pointer from the CAM CCB to our data structures. 1039 */ 1040 #define sym_hcb_ptr spriv_ptr0 1041 /* #define sym_ccb_ptr spriv_ptr1 */ 1042 1043 /* 1044 * We mostly have to deal with pointers. 1045 * Thus these typedef's. 1046 */ 1047 typedef struct sym_tcb *tcb_p; 1048 typedef struct sym_lcb *lcb_p; 1049 typedef struct sym_ccb *ccb_p; 1050 typedef struct sym_hcb *hcb_p; 1051 1052 /* 1053 * Gather negotiable parameters value 1054 */ 1055 struct sym_trans { 1056 u8 scsi_version; 1057 u8 spi_version; 1058 u8 period; 1059 u8 offset; 1060 u8 width; 1061 u8 options; /* PPR options */ 1062 }; 1063 1064 struct sym_tinfo { 1065 struct sym_trans current; 1066 struct sym_trans goal; 1067 struct sym_trans user; 1068 }; 1069 1070 #define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT 1071 #define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT 1072 1073 /* 1074 * Global TCB HEADER. 1075 * 1076 * Due to lack of indirect addressing on earlier NCR chips, 1077 * this substructure is copied from the TCB to a global 1078 * address after selection. 1079 * For SYMBIOS chips that support LOAD/STORE this copy is 1080 * not needed and thus not performed. 1081 */ 1082 struct sym_tcbh { 1083 /* 1084 * Scripts bus addresses of LUN table accessed from scripts. 1085 * LUN #0 is a special case, since multi-lun devices are rare, 1086 * and we we want to speed-up the general case and not waste 1087 * resources. 1088 */ 1089 u32 luntbl_sa; /* bus address of this table */ 1090 u32 lun0_sa; /* bus address of LCB #0 */ 1091 /* 1092 * Actual SYNC/WIDE IO registers value for this target. 1093 * 'sval', 'wval' and 'uval' are read from SCRIPTS and 1094 * so have alignment constraints. 1095 */ 1096 /*0*/ u_char uval; /* -> SCNTL4 register */ 1097 /*1*/ u_char sval; /* -> SXFER io register */ 1098 /*2*/ u_char filler1; 1099 /*3*/ u_char wval; /* -> SCNTL3 io register */ 1100 }; 1101 1102 /* 1103 * Target Control Block 1104 */ 1105 struct sym_tcb { 1106 /* 1107 * TCB header. 1108 * Assumed at offset 0. 1109 */ 1110 /*0*/ struct sym_tcbh head; 1111 1112 /* 1113 * LUN table used by the SCRIPTS processor. 1114 * An array of bus addresses is used on reselection. 1115 */ 1116 u32 *luntbl; /* LCBs bus address table */ 1117 1118 /* 1119 * LUN table used by the C code. 1120 */ 1121 lcb_p lun0p; /* LCB of LUN #0 (usual case) */ 1122 #if SYM_CONF_MAX_LUN > 1 1123 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */ 1124 #endif 1125 1126 /* 1127 * Bitmap that tells about LUNs that succeeded at least 1128 * 1 IO and therefore assumed to be a real device. 1129 * Avoid useless allocation of the LCB structure. 1130 */ 1131 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32]; 1132 1133 /* 1134 * Bitmap that tells about LUNs that haven't yet an LCB 1135 * allocated (not discovered or LCB allocation failed). 1136 */ 1137 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32]; 1138 1139 /* 1140 * Transfer capabilities (SIP) 1141 */ 1142 struct sym_tinfo tinfo; 1143 1144 /* 1145 * Keep track of the CCB used for the negotiation in order 1146 * to ensure that only 1 negotiation is queued at a time. 1147 */ 1148 ccb_p nego_cp; /* CCB used for the nego */ 1149 1150 /* 1151 * Set when we want to reset the device. 1152 */ 1153 u_char to_reset; 1154 1155 /* 1156 * Other user settable limits and options. 1157 * These limits are read from the NVRAM if present. 1158 */ 1159 u_char usrflags; 1160 u_short usrtags; 1161 }; 1162 1163 /* 1164 * Global LCB HEADER. 1165 * 1166 * Due to lack of indirect addressing on earlier NCR chips, 1167 * this substructure is copied from the LCB to a global 1168 * address after selection. 1169 * For SYMBIOS chips that support LOAD/STORE this copy is 1170 * not needed and thus not performed. 1171 */ 1172 struct sym_lcbh { 1173 /* 1174 * SCRIPTS address jumped by SCRIPTS on reselection. 1175 * For not probed logical units, this address points to 1176 * SCRIPTS that deal with bad LU handling (must be at 1177 * offset zero of the LCB for that reason). 1178 */ 1179 /*0*/ u32 resel_sa; 1180 1181 /* 1182 * Task (bus address of a CCB) read from SCRIPTS that points 1183 * to the unique ITL nexus allowed to be disconnected. 1184 */ 1185 u32 itl_task_sa; 1186 1187 /* 1188 * Task table bus address (read from SCRIPTS). 1189 */ 1190 u32 itlq_tbl_sa; 1191 }; 1192 1193 /* 1194 * Logical Unit Control Block 1195 */ 1196 struct sym_lcb { 1197 /* 1198 * TCB header. 1199 * Assumed at offset 0. 1200 */ 1201 /*0*/ struct sym_lcbh head; 1202 1203 /* 1204 * Task table read from SCRIPTS that contains pointers to 1205 * ITLQ nexuses. The bus address read from SCRIPTS is 1206 * inside the header. 1207 */ 1208 u32 *itlq_tbl; /* Kernel virtual address */ 1209 1210 /* 1211 * Busy CCBs management. 1212 */ 1213 u_short busy_itlq; /* Number of busy tagged CCBs */ 1214 u_short busy_itl; /* Number of busy untagged CCBs */ 1215 1216 /* 1217 * Circular tag allocation buffer. 1218 */ 1219 u_short ia_tag; /* Tag allocation index */ 1220 u_short if_tag; /* Tag release index */ 1221 u_char *cb_tags; /* Circular tags buffer */ 1222 1223 /* 1224 * Set when we want to clear all tasks. 1225 */ 1226 u_char to_clear; 1227 1228 /* 1229 * Capabilities. 1230 */ 1231 u_char user_flags; 1232 u_char current_flags; 1233 }; 1234 1235 /* 1236 * Action from SCRIPTS on a task. 1237 * Is part of the CCB, but is also used separately to plug 1238 * error handling action to perform from SCRIPTS. 1239 */ 1240 struct sym_actscr { 1241 u32 start; /* Jumped by SCRIPTS after selection */ 1242 u32 restart; /* Jumped by SCRIPTS on relection */ 1243 }; 1244 1245 /* 1246 * Phase mismatch context. 1247 * 1248 * It is part of the CCB and is used as parameters for the 1249 * DATA pointer. We need two contexts to handle correctly the 1250 * SAVED DATA POINTER. 1251 */ 1252 struct sym_pmc { 1253 struct sym_tblmove sg; /* Updated interrupted SG block */ 1254 u32 ret; /* SCRIPT return address */ 1255 }; 1256 1257 /* 1258 * LUN control block lookup. 1259 * We use a direct pointer for LUN #0, and a table of 1260 * pointers which is only allocated for devices that support 1261 * LUN(s) > 0. 1262 */ 1263 #if SYM_CONF_MAX_LUN <= 1 1264 #define sym_lp(np, tp, lun) (!lun) ? (tp)->lun0p : 0 1265 #else 1266 #define sym_lp(np, tp, lun) \ 1267 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0 1268 #endif 1269 1270 /* 1271 * Status are used by the host and the script processor. 1272 * 1273 * The last four bytes (status[4]) are copied to the 1274 * scratchb register (declared as scr0..scr3) just after the 1275 * select/reselect, and copied back just after disconnecting. 1276 * Inside the script the XX_REG are used. 1277 */ 1278 1279 /* 1280 * Last four bytes (script) 1281 */ 1282 #define QU_REG scr0 1283 #define HS_REG scr1 1284 #define HS_PRT nc_scr1 1285 #define SS_REG scr2 1286 #define SS_PRT nc_scr2 1287 #define HF_REG scr3 1288 #define HF_PRT nc_scr3 1289 1290 /* 1291 * Last four bytes (host) 1292 */ 1293 #define actualquirks phys.head.status[0] 1294 #define host_status phys.head.status[1] 1295 #define ssss_status phys.head.status[2] 1296 #define host_flags phys.head.status[3] 1297 1298 /* 1299 * Host flags 1300 */ 1301 #define HF_IN_PM0 1u 1302 #define HF_IN_PM1 (1u<<1) 1303 #define HF_ACT_PM (1u<<2) 1304 #define HF_DP_SAVED (1u<<3) 1305 #define HF_SENSE (1u<<4) 1306 #define HF_EXT_ERR (1u<<5) 1307 #define HF_DATA_IN (1u<<6) 1308 #ifdef SYM_CONF_IARB_SUPPORT 1309 #define HF_HINT_IARB (1u<<7) 1310 #endif 1311 1312 /* 1313 * Global CCB HEADER. 1314 * 1315 * Due to lack of indirect addressing on earlier NCR chips, 1316 * this substructure is copied from the ccb to a global 1317 * address after selection (or reselection) and copied back 1318 * before disconnect. 1319 * For SYMBIOS chips that support LOAD/STORE this copy is 1320 * not needed and thus not performed. 1321 */ 1322 1323 struct sym_ccbh { 1324 /* 1325 * Start and restart SCRIPTS addresses (must be at 0). 1326 */ 1327 /*0*/ struct sym_actscr go; 1328 1329 /* 1330 * SCRIPTS jump address that deal with data pointers. 1331 * 'savep' points to the position in the script responsible 1332 * for the actual transfer of data. 1333 * It's written on reception of a SAVE_DATA_POINTER message. 1334 */ 1335 u32 savep; /* Jump address to saved data pointer */ 1336 u32 lastp; /* SCRIPTS address at end of data */ 1337 u32 goalp; /* Not accessed for now from SCRIPTS */ 1338 1339 /* 1340 * Status fields. 1341 */ 1342 u8 status[4]; 1343 }; 1344 1345 /* 1346 * Data Structure Block 1347 * 1348 * During execution of a ccb by the script processor, the 1349 * DSA (data structure address) register points to this 1350 * substructure of the ccb. 1351 */ 1352 struct sym_dsb { 1353 /* 1354 * CCB header. 1355 * Also assumed at offset 0 of the sym_ccb structure. 1356 */ 1357 /*0*/ struct sym_ccbh head; 1358 1359 /* 1360 * Phase mismatch contexts. 1361 * We need two to handle correctly the SAVED DATA POINTER. 1362 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic 1363 * for address calculation from SCRIPTS. 1364 */ 1365 struct sym_pmc pm0; 1366 struct sym_pmc pm1; 1367 1368 /* 1369 * Table data for Script 1370 */ 1371 struct sym_tblsel select; 1372 struct sym_tblmove smsg; 1373 struct sym_tblmove smsg_ext; 1374 struct sym_tblmove cmd; 1375 struct sym_tblmove sense; 1376 struct sym_tblmove wresid; 1377 struct sym_tblmove data [SYM_CONF_MAX_SG]; 1378 }; 1379 1380 /* 1381 * Our Command Control Block 1382 */ 1383 struct sym_ccb { 1384 /* 1385 * This is the data structure which is pointed by the DSA 1386 * register when it is executed by the script processor. 1387 * It must be the first entry. 1388 */ 1389 struct sym_dsb phys; 1390 1391 /* 1392 * Pointer to CAM ccb and related stuff. 1393 */ 1394 struct callout ch; /* callout handle */ 1395 union ccb *cam_ccb; /* CAM scsiio ccb */ 1396 u8 cdb_buf[16]; /* Copy of CDB */ 1397 u8 *sns_bbuf; /* Bounce buffer for sense data */ 1398 #define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data) 1399 int data_len; /* Total data length */ 1400 int segments; /* Number of SG segments */ 1401 1402 /* 1403 * Miscellaneous status'. 1404 */ 1405 u_char nego_status; /* Negotiation status */ 1406 u_char xerr_status; /* Extended error flags */ 1407 u32 extra_bytes; /* Extraneous bytes transferred */ 1408 1409 /* 1410 * Message areas. 1411 * We prepare a message to be sent after selection. 1412 * We may use a second one if the command is rescheduled 1413 * due to CHECK_CONDITION or COMMAND TERMINATED. 1414 * Contents are IDENTIFY and SIMPLE_TAG. 1415 * While negotiating sync or wide transfer, 1416 * a SDTR or WDTR message is appended. 1417 */ 1418 u_char scsi_smsg [12]; 1419 u_char scsi_smsg2[12]; 1420 1421 /* 1422 * Auto request sense related fields. 1423 */ 1424 u_char sensecmd[6]; /* Request Sense command */ 1425 u_char sv_scsi_status; /* Saved SCSI status */ 1426 u_char sv_xerr_status; /* Saved extended status */ 1427 int sv_resid; /* Saved residual */ 1428 1429 /* 1430 * Map for the DMA of user data. 1431 */ 1432 void *arg; /* Argument for some callback */ 1433 bus_dmamap_t dmamap; /* DMA map for user data */ 1434 u_char dmamapped; 1435 #define SYM_DMA_NONE 0 1436 #define SYM_DMA_READ 1 1437 #define SYM_DMA_WRITE 2 1438 /* 1439 * Other fields. 1440 */ 1441 u32 ccb_ba; /* BUS address of this CCB */ 1442 u_short tag; /* Tag for this transfer */ 1443 /* NO_TAG means no tag */ 1444 u_char target; 1445 u_char lun; 1446 ccb_p link_ccbh; /* Host adapter CCB hash chain */ 1447 SYM_QUEHEAD 1448 link_ccbq; /* Link to free/busy CCB queue */ 1449 u32 startp; /* Initial data pointer */ 1450 int ext_sg; /* Extreme data pointer, used */ 1451 int ext_ofs; /* to calculate the residual. */ 1452 u_char to_abort; /* Want this IO to be aborted */ 1453 }; 1454 1455 #define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl)) 1456 1457 /* 1458 * Host Control Block 1459 */ 1460 struct sym_hcb { 1461 struct lock lock; 1462 1463 /* 1464 * Global headers. 1465 * Due to poorness of addressing capabilities, earlier 1466 * chips (810, 815, 825) copy part of the data structures 1467 * (CCB, TCB and LCB) in fixed areas. 1468 */ 1469 #ifdef SYM_CONF_GENERIC_SUPPORT 1470 struct sym_ccbh ccb_head; 1471 struct sym_tcbh tcb_head; 1472 struct sym_lcbh lcb_head; 1473 #endif 1474 /* 1475 * Idle task and invalid task actions and 1476 * their bus addresses. 1477 */ 1478 struct sym_actscr idletask, notask, bad_itl, bad_itlq; 1479 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba; 1480 1481 /* 1482 * Dummy lun table to protect us against target 1483 * returning bad lun number on reselection. 1484 */ 1485 u32 *badluntbl; /* Table physical address */ 1486 u32 badlun_sa; /* SCRIPT handler BUS address */ 1487 1488 /* 1489 * Bus address of this host control block. 1490 */ 1491 u32 hcb_ba; 1492 1493 /* 1494 * Bit 32-63 of the on-chip RAM bus address in LE format. 1495 * The START_RAM64 script loads the MMRS and MMWS from this 1496 * field. 1497 */ 1498 u32 scr_ram_seg; 1499 1500 /* 1501 * Chip and controller indentification. 1502 */ 1503 device_t device; 1504 1505 /* 1506 * Initial value of some IO register bits. 1507 * These values are assumed to have been set by BIOS, and may 1508 * be used to probe adapter implementation differences. 1509 */ 1510 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4, 1511 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4, 1512 sv_stest1; 1513 1514 /* 1515 * Actual initial value of IO register bits used by the 1516 * driver. They are loaded at initialisation according to 1517 * features that are to be enabled/disabled. 1518 */ 1519 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4, 1520 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4; 1521 1522 /* 1523 * Target data. 1524 */ 1525 #ifdef __x86_64__ 1526 struct sym_tcb *target; 1527 #else 1528 struct sym_tcb target[SYM_CONF_MAX_TARGET]; 1529 #endif 1530 1531 /* 1532 * Target control block bus address array used by the SCRIPT 1533 * on reselection. 1534 */ 1535 u32 *targtbl; 1536 u32 targtbl_ba; 1537 1538 /* 1539 * CAM SIM information for this instance. 1540 */ 1541 struct cam_sim *sim; 1542 struct cam_path *path; 1543 1544 /* 1545 * Allocated hardware resources. 1546 */ 1547 struct resource *irq_res; 1548 struct resource *io_res; 1549 struct resource *mmio_res; 1550 struct resource *ram_res; 1551 int ram_id; 1552 void *intr; 1553 1554 /* 1555 * Bus stuff. 1556 * 1557 * My understanding of PCI is that all agents must share the 1558 * same addressing range and model. 1559 * But some hardware architecture guys provide complex and 1560 * brain-deaded stuff that makes shit. 1561 * This driver only support PCI compliant implementations and 1562 * deals with part of the BUS stuff complexity only to fit O/S 1563 * requirements. 1564 */ 1565 1566 /* 1567 * DMA stuff. 1568 */ 1569 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */ 1570 bus_dma_tag_t data_dmat; /* DMA tag for user data */ 1571 /* 1572 * BUS addresses of the chip 1573 */ 1574 vm_offset_t mmio_ba; /* MMIO BUS address */ 1575 int mmio_ws; /* MMIO Window size */ 1576 1577 vm_offset_t ram_ba; /* RAM BUS address */ 1578 int ram_ws; /* RAM window size */ 1579 1580 /* 1581 * SCRIPTS virtual and physical bus addresses. 1582 * 'script' is loaded in the on-chip RAM if present. 1583 * 'scripth' stays in main memory for all chips except the 1584 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM. 1585 */ 1586 u_char *scripta0; /* Copies of script and scripth */ 1587 u_char *scriptb0; /* Copies of script and scripth */ 1588 vm_offset_t scripta_ba; /* Actual script and scripth */ 1589 vm_offset_t scriptb_ba; /* bus addresses. */ 1590 vm_offset_t scriptb0_ba; 1591 u_short scripta_sz; /* Actual size of script A */ 1592 u_short scriptb_sz; /* Actual size of script B */ 1593 1594 /* 1595 * Bus addresses, setup and patch methods for 1596 * the selected firmware. 1597 */ 1598 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */ 1599 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */ 1600 void (*fw_setup)(hcb_p np, const struct sym_fw *fw); 1601 void (*fw_patch)(hcb_p np); 1602 const char *fw_name; 1603 1604 /* 1605 * General controller parameters and configuration. 1606 */ 1607 u_short device_id; /* PCI device id */ 1608 u_char revision_id; /* PCI device revision id */ 1609 u_int features; /* Chip features map */ 1610 u_char myaddr; /* SCSI id of the adapter */ 1611 u_char maxburst; /* log base 2 of dwords burst */ 1612 u_char maxwide; /* Maximum transfer width */ 1613 u_char minsync; /* Min sync period factor (ST) */ 1614 u_char maxsync; /* Max sync period factor (ST) */ 1615 u_char maxoffs; /* Max scsi offset (ST) */ 1616 u_char minsync_dt; /* Min sync period factor (DT) */ 1617 u_char maxsync_dt; /* Max sync period factor (DT) */ 1618 u_char maxoffs_dt; /* Max scsi offset (DT) */ 1619 u_char multiplier; /* Clock multiplier (1,2,4) */ 1620 u_char clock_divn; /* Number of clock divisors */ 1621 u32 clock_khz; /* SCSI clock frequency in KHz */ 1622 u32 pciclk_khz; /* Estimated PCI clock in KHz */ 1623 /* 1624 * Start queue management. 1625 * It is filled up by the host processor and accessed by the 1626 * SCRIPTS processor in order to start SCSI commands. 1627 */ 1628 volatile /* Prevent code optimizations */ 1629 u32 *squeue; /* Start queue virtual address */ 1630 u32 squeue_ba; /* Start queue BUS address */ 1631 u_short squeueput; /* Next free slot of the queue */ 1632 u_short actccbs; /* Number of allocated CCBs */ 1633 1634 /* 1635 * Command completion queue. 1636 * It is the same size as the start queue to avoid overflow. 1637 */ 1638 u_short dqueueget; /* Next position to scan */ 1639 volatile /* Prevent code optimizations */ 1640 u32 *dqueue; /* Completion (done) queue */ 1641 u32 dqueue_ba; /* Done queue BUS address */ 1642 1643 /* 1644 * Miscellaneous buffers accessed by the scripts-processor. 1645 * They shall be DWORD aligned, because they may be read or 1646 * written with a script command. 1647 */ 1648 u_char msgout[8]; /* Buffer for MESSAGE OUT */ 1649 u_char msgin [8]; /* Buffer for MESSAGE IN */ 1650 u32 lastmsg; /* Last SCSI message sent */ 1651 u_char scratch; /* Scratch for SCSI receive */ 1652 1653 /* 1654 * Miscellaneous configuration and status parameters. 1655 */ 1656 u_char usrflags; /* Miscellaneous user flags */ 1657 u_char scsi_mode; /* Current SCSI BUS mode */ 1658 u_char verbose; /* Verbosity for this controller*/ 1659 u32 cache; /* Used for cache test at init. */ 1660 1661 /* 1662 * CCB lists and queue. 1663 */ 1664 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */ 1665 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */ 1666 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */ 1667 1668 /* 1669 * During error handling and/or recovery, 1670 * active CCBs that are to be completed with 1671 * error or requeued are moved from the busy_ccbq 1672 * to the comp_ccbq prior to completion. 1673 */ 1674 SYM_QUEHEAD comp_ccbq; 1675 1676 /* 1677 * CAM CCB pending queue. 1678 */ 1679 SYM_QUEHEAD cam_ccbq; 1680 1681 /* 1682 * IMMEDIATE ARBITRATION (IARB) control. 1683 * 1684 * We keep track in 'last_cp' of the last CCB that has been 1685 * queued to the SCRIPTS processor and clear 'last_cp' when 1686 * this CCB completes. If last_cp is not zero at the moment 1687 * we queue a new CCB, we set a flag in 'last_cp' that is 1688 * used by the SCRIPTS as a hint for setting IARB. 1689 * We donnot set more than 'iarb_max' consecutive hints for 1690 * IARB in order to leave devices a chance to reselect. 1691 * By the way, any non zero value of 'iarb_max' is unfair. :) 1692 */ 1693 #ifdef SYM_CONF_IARB_SUPPORT 1694 u_short iarb_max; /* Max. # consecutive IARB hints*/ 1695 u_short iarb_count; /* Actual # of these hints */ 1696 ccb_p last_cp; 1697 #endif 1698 1699 /* 1700 * Command abort handling. 1701 * We need to synchronize tightly with the SCRIPTS 1702 * processor in order to handle things correctly. 1703 */ 1704 u_char abrt_msg[4]; /* Message to send buffer */ 1705 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */ 1706 struct sym_tblsel abrt_sel; /* Sync params for selection */ 1707 u_char istat_sem; /* Tells the chip to stop (SEM) */ 1708 }; 1709 1710 #define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl)) 1711 1712 /* 1713 * Return the name of the controller. 1714 */ 1715 static __inline const char *sym_name(hcb_p np) 1716 { 1717 return device_get_nameunit(np->device); 1718 } 1719 1720 /*--------------------------------------------------------------------------*/ 1721 /*------------------------------ FIRMWARES ---------------------------------*/ 1722 /*--------------------------------------------------------------------------*/ 1723 1724 /* 1725 * This stuff will be moved to a separate source file when 1726 * the driver will be broken into several source modules. 1727 */ 1728 1729 /* 1730 * Macros used for all firmwares. 1731 */ 1732 #define SYM_GEN_A(s, label) ((short) offsetof(s, label)), 1733 #define SYM_GEN_B(s, label) ((short) offsetof(s, label)), 1734 #define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label) 1735 #define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label) 1736 1737 1738 #ifdef SYM_CONF_GENERIC_SUPPORT 1739 /* 1740 * Allocate firmware #1 script area. 1741 */ 1742 #define SYM_FWA_SCR sym_fw1a_scr 1743 #define SYM_FWB_SCR sym_fw1b_scr 1744 #include <dev/disk/sym/sym_fw1.h> 1745 static const struct sym_fwa_ofs sym_fw1a_ofs = { 1746 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1747 }; 1748 static const struct sym_fwb_ofs sym_fw1b_ofs = { 1749 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1750 }; 1751 #undef SYM_FWA_SCR 1752 #undef SYM_FWB_SCR 1753 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1754 1755 /* 1756 * Allocate firmware #2 script area. 1757 */ 1758 #define SYM_FWA_SCR sym_fw2a_scr 1759 #define SYM_FWB_SCR sym_fw2b_scr 1760 #include <dev/disk/sym/sym_fw2.h> 1761 static const struct sym_fwa_ofs sym_fw2a_ofs = { 1762 SYM_GEN_FW_A(struct SYM_FWA_SCR) 1763 }; 1764 static const struct sym_fwb_ofs sym_fw2b_ofs = { 1765 SYM_GEN_FW_B(struct SYM_FWB_SCR) 1766 SYM_GEN_B(struct SYM_FWB_SCR, start64) 1767 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle) 1768 }; 1769 #undef SYM_FWA_SCR 1770 #undef SYM_FWB_SCR 1771 1772 #undef SYM_GEN_A 1773 #undef SYM_GEN_B 1774 #undef PADDR_A 1775 #undef PADDR_B 1776 1777 #ifdef SYM_CONF_GENERIC_SUPPORT 1778 /* 1779 * Patch routine for firmware #1. 1780 */ 1781 static void 1782 sym_fw1_patch(hcb_p np) 1783 { 1784 struct sym_fw1a_scr *scripta0; 1785 struct sym_fw1b_scr *scriptb0; 1786 1787 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 1788 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0; 1789 1790 /* 1791 * Remove LED support if not needed. 1792 */ 1793 if (!(np->features & FE_LED0)) { 1794 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 1795 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 1796 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 1797 } 1798 1799 #ifdef SYM_CONF_IARB_SUPPORT 1800 /* 1801 * If user does not want to use IMMEDIATE ARBITRATION 1802 * when we are reselected while attempting to arbitrate, 1803 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 1804 */ 1805 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 1806 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 1807 #endif 1808 /* 1809 * Patch some data in SCRIPTS. 1810 * - start and done queue initial bus address. 1811 * - target bus address table bus address. 1812 */ 1813 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 1814 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 1815 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 1816 } 1817 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1818 1819 /* 1820 * Patch routine for firmware #2. 1821 */ 1822 static void 1823 sym_fw2_patch(hcb_p np) 1824 { 1825 struct sym_fw2a_scr *scripta0; 1826 struct sym_fw2b_scr *scriptb0; 1827 1828 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 1829 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0; 1830 1831 /* 1832 * Remove LED support if not needed. 1833 */ 1834 if (!(np->features & FE_LED0)) { 1835 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP); 1836 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP); 1837 scripta0->start[0] = cpu_to_scr(SCR_NO_OP); 1838 } 1839 1840 #ifdef SYM_CONF_IARB_SUPPORT 1841 /* 1842 * If user does not want to use IMMEDIATE ARBITRATION 1843 * when we are reselected while attempting to arbitrate, 1844 * patch the SCRIPTS accordingly with a SCRIPT NO_OP. 1845 */ 1846 if (!SYM_CONF_SET_IARB_ON_ARB_LOST) 1847 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP); 1848 #endif 1849 /* 1850 * Patch some variable in SCRIPTS. 1851 * - start and done queue initial bus address. 1852 * - target bus address table bus address. 1853 */ 1854 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba); 1855 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba); 1856 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba); 1857 1858 /* 1859 * Remove the load of SCNTL4 on reselection if not a C10. 1860 */ 1861 if (!(np->features & FE_C10)) { 1862 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP); 1863 scripta0->resel_scntl4[1] = cpu_to_scr(0); 1864 } 1865 1866 /* 1867 * Remove a couple of work-arounds specific to C1010 if 1868 * they are not desirable. See `sym_fw2.h' for more details. 1869 */ 1870 if (!(np->device_id == PCI_ID_LSI53C1010_2 && 1871 np->revision_id < 0x1 && 1872 np->pciclk_khz < 60000)) { 1873 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP); 1874 scripta0->datao_phase[1] = cpu_to_scr(0); 1875 } 1876 if (!(np->device_id == PCI_ID_LSI53C1010 && 1877 /* np->revision_id < 0xff */ 1)) { 1878 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP); 1879 scripta0->sel_done[1] = cpu_to_scr(0); 1880 } 1881 1882 /* 1883 * Patch some other variables in SCRIPTS. 1884 * These ones are loaded by the SCRIPTS processor. 1885 */ 1886 scriptb0->pm0_data_addr[0] = 1887 cpu_to_scr(np->scripta_ba + 1888 offsetof(struct sym_fw2a_scr, pm0_data)); 1889 scriptb0->pm1_data_addr[0] = 1890 cpu_to_scr(np->scripta_ba + 1891 offsetof(struct sym_fw2a_scr, pm1_data)); 1892 } 1893 1894 /* 1895 * Fill the data area in scripts. 1896 * To be done for all firmwares. 1897 */ 1898 static void 1899 sym_fw_fill_data (u32 *in, u32 *out) 1900 { 1901 int i; 1902 1903 for (i = 0; i < SYM_CONF_MAX_SG; i++) { 1904 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN; 1905 *in++ = offsetof (struct sym_dsb, data[i]); 1906 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT; 1907 *out++ = offsetof (struct sym_dsb, data[i]); 1908 } 1909 } 1910 1911 /* 1912 * Setup useful script bus addresses. 1913 * To be done for all firmwares. 1914 */ 1915 static void 1916 sym_fw_setup_bus_addresses(hcb_p np, const struct sym_fw *fw) 1917 { 1918 u32 *pa; 1919 const u_short *po; 1920 int i; 1921 1922 /* 1923 * Build the bus address table for script A 1924 * from the script A offset table. 1925 */ 1926 po = (const u_short *) fw->a_ofs; 1927 pa = (u32 *) &np->fwa_bas; 1928 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++) 1929 pa[i] = np->scripta_ba + po[i]; 1930 1931 /* 1932 * Same for script B. 1933 */ 1934 po = (const u_short *) fw->b_ofs; 1935 pa = (u32 *) &np->fwb_bas; 1936 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++) 1937 pa[i] = np->scriptb_ba + po[i]; 1938 } 1939 1940 #ifdef SYM_CONF_GENERIC_SUPPORT 1941 /* 1942 * Setup routine for firmware #1. 1943 */ 1944 static void 1945 sym_fw1_setup(hcb_p np, const struct sym_fw *fw) 1946 { 1947 struct sym_fw1a_scr *scripta0; 1948 1949 scripta0 = (struct sym_fw1a_scr *) np->scripta0; 1950 1951 /* 1952 * Fill variable parts in scripts. 1953 */ 1954 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 1955 1956 /* 1957 * Setup bus addresses used from the C code.. 1958 */ 1959 sym_fw_setup_bus_addresses(np, fw); 1960 } 1961 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1962 1963 /* 1964 * Setup routine for firmware #2. 1965 */ 1966 static void 1967 sym_fw2_setup(hcb_p np, const struct sym_fw *fw) 1968 { 1969 struct sym_fw2a_scr *scripta0; 1970 1971 scripta0 = (struct sym_fw2a_scr *) np->scripta0; 1972 1973 /* 1974 * Fill variable parts in scripts. 1975 */ 1976 sym_fw_fill_data(scripta0->data_in, scripta0->data_out); 1977 1978 /* 1979 * Setup bus addresses used from the C code.. 1980 */ 1981 sym_fw_setup_bus_addresses(np, fw); 1982 } 1983 1984 /* 1985 * Allocate firmware descriptors. 1986 */ 1987 #ifdef SYM_CONF_GENERIC_SUPPORT 1988 static const struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic"); 1989 #endif /* SYM_CONF_GENERIC_SUPPORT */ 1990 static const struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based"); 1991 1992 /* 1993 * Find the most appropriate firmware for a chip. 1994 */ 1995 static const struct sym_fw * 1996 sym_find_firmware(const struct sym_pci_chip *chip) 1997 { 1998 if (chip->features & FE_LDSTR) 1999 return &sym_fw2; 2000 #ifdef SYM_CONF_GENERIC_SUPPORT 2001 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC))) 2002 return &sym_fw1; 2003 #endif 2004 else 2005 return NULL; 2006 } 2007 2008 /* 2009 * Bind a script to physical addresses. 2010 */ 2011 static void sym_fw_bind_script (hcb_p np, u32 *start, int len) 2012 { 2013 u32 opcode, new, old, tmp1, tmp2; 2014 u32 *end, *cur; 2015 int relocs; 2016 2017 cur = start; 2018 end = start + len/4; 2019 2020 while (cur < end) { 2021 2022 opcode = *cur; 2023 2024 /* 2025 * If we forget to change the length 2026 * in scripts, a field will be 2027 * padded with 0. This is an illegal 2028 * command. 2029 */ 2030 if (opcode == 0) { 2031 kprintf ("%s: ERROR0 IN SCRIPT at %d.\n", 2032 sym_name(np), (int) (cur-start)); 2033 MDELAY (10000); 2034 ++cur; 2035 continue; 2036 } 2037 2038 /* 2039 * We use the bogus value 0xf00ff00f ;-) 2040 * to reserve data area in SCRIPTS. 2041 */ 2042 if (opcode == SCR_DATA_ZERO) { 2043 *cur++ = 0; 2044 continue; 2045 } 2046 2047 if (DEBUG_FLAGS & DEBUG_SCRIPT) 2048 kprintf ("%d: <%x>\n", (int) (cur-start), 2049 (unsigned)opcode); 2050 2051 /* 2052 * We don't have to decode ALL commands 2053 */ 2054 switch (opcode >> 28) { 2055 case 0xf: 2056 /* 2057 * LOAD / STORE DSA relative, don't relocate. 2058 */ 2059 relocs = 0; 2060 break; 2061 case 0xe: 2062 /* 2063 * LOAD / STORE absolute. 2064 */ 2065 relocs = 1; 2066 break; 2067 case 0xc: 2068 /* 2069 * COPY has TWO arguments. 2070 */ 2071 relocs = 2; 2072 tmp1 = cur[1]; 2073 tmp2 = cur[2]; 2074 if ((tmp1 ^ tmp2) & 3) { 2075 kprintf ("%s: ERROR1 IN SCRIPT at %d.\n", 2076 sym_name(np), (int) (cur-start)); 2077 MDELAY (10000); 2078 } 2079 /* 2080 * If PREFETCH feature not enabled, remove 2081 * the NO FLUSH bit if present. 2082 */ 2083 if ((opcode & SCR_NO_FLUSH) && 2084 !(np->features & FE_PFEN)) { 2085 opcode = (opcode & ~SCR_NO_FLUSH); 2086 } 2087 break; 2088 case 0x0: 2089 /* 2090 * MOVE/CHMOV (absolute address) 2091 */ 2092 if (!(np->features & FE_WIDE)) 2093 opcode = (opcode | OPC_MOVE); 2094 relocs = 1; 2095 break; 2096 case 0x1: 2097 /* 2098 * MOVE/CHMOV (table indirect) 2099 */ 2100 if (!(np->features & FE_WIDE)) 2101 opcode = (opcode | OPC_MOVE); 2102 relocs = 0; 2103 break; 2104 case 0x8: 2105 /* 2106 * JUMP / CALL 2107 * dont't relocate if relative :-) 2108 */ 2109 if (opcode & 0x00800000) 2110 relocs = 0; 2111 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/ 2112 relocs = 2; 2113 else 2114 relocs = 1; 2115 break; 2116 case 0x4: 2117 case 0x5: 2118 case 0x6: 2119 case 0x7: 2120 relocs = 1; 2121 break; 2122 default: 2123 relocs = 0; 2124 break; 2125 } 2126 2127 /* 2128 * Scriptify:) the opcode. 2129 */ 2130 *cur++ = cpu_to_scr(opcode); 2131 2132 /* 2133 * If no relocation, assume 1 argument 2134 * and just scriptize:) it. 2135 */ 2136 if (!relocs) { 2137 *cur = cpu_to_scr(*cur); 2138 ++cur; 2139 continue; 2140 } 2141 2142 /* 2143 * Otherwise performs all needed relocations. 2144 */ 2145 while (relocs--) { 2146 old = *cur; 2147 2148 switch (old & RELOC_MASK) { 2149 case RELOC_REGISTER: 2150 new = (old & ~RELOC_MASK) + np->mmio_ba; 2151 break; 2152 case RELOC_LABEL_A: 2153 new = (old & ~RELOC_MASK) + np->scripta_ba; 2154 break; 2155 case RELOC_LABEL_B: 2156 new = (old & ~RELOC_MASK) + np->scriptb_ba; 2157 break; 2158 case RELOC_SOFTC: 2159 new = (old & ~RELOC_MASK) + np->hcb_ba; 2160 break; 2161 case 0: 2162 /* 2163 * Don't relocate a 0 address. 2164 * They are mostly used for patched or 2165 * script self-modified areas. 2166 */ 2167 if (old == 0) { 2168 new = old; 2169 break; 2170 } 2171 /* fall through */ 2172 default: 2173 new = 0; 2174 panic("sym_fw_bind_script: " 2175 "weird relocation %x\n", old); 2176 break; 2177 } 2178 2179 *cur++ = cpu_to_scr(new); 2180 } 2181 } 2182 } 2183 2184 /*---------------------------------------------------------------------------*/ 2185 /*--------------------------- END OF FIRMWARES -----------------------------*/ 2186 /*---------------------------------------------------------------------------*/ 2187 2188 /* 2189 * Function prototypes. 2190 */ 2191 static void sym_save_initial_setting (hcb_p np); 2192 static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram); 2193 static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr); 2194 static void sym_put_start_queue (hcb_p np, ccb_p cp); 2195 static void sym_chip_reset (hcb_p np); 2196 static void sym_soft_reset (hcb_p np); 2197 static void sym_start_reset (hcb_p np); 2198 static int sym_reset_scsi_bus (hcb_p np, int enab_int); 2199 static int sym_wakeup_done (hcb_p np); 2200 static void sym_flush_busy_queue (hcb_p np, int cam_status); 2201 static void sym_flush_comp_queue (hcb_p np, int cam_status); 2202 static void sym_init (hcb_p np, int reason); 2203 static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, 2204 u_char *fakp); 2205 static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per, 2206 u_char div, u_char fak); 2207 static void sym_setwide (hcb_p np, ccb_p cp, u_char wide); 2208 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2209 u_char per, u_char wide, u_char div, u_char fak); 2210 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 2211 u_char per, u_char wide, u_char div, u_char fak); 2212 static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat); 2213 static void sym_intr (void *arg); 2214 static void sym_poll (struct cam_sim *sim); 2215 static void sym_recover_scsi_int (hcb_p np, u_char hsts); 2216 static void sym_int_sto (hcb_p np); 2217 static void sym_int_udc (hcb_p np); 2218 static void sym_int_sbmc (hcb_p np); 2219 static void sym_int_par (hcb_p np, u_short sist); 2220 static void sym_int_ma (hcb_p np); 2221 static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, 2222 int task); 2223 static void sym_sir_bad_scsi_status (hcb_p np, int num, ccb_p cp); 2224 static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task); 2225 static void sym_sir_task_recovery (hcb_p np, int num); 2226 static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs); 2227 static void sym_modify_dp (hcb_p np, tcb_p tp, ccb_p cp, int ofs); 2228 static int sym_compute_residual (hcb_p np, ccb_p cp); 2229 static int sym_show_msg (u_char * msg); 2230 static void sym_print_msg (ccb_p cp, char *label, u_char *msg); 2231 static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp); 2232 static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp); 2233 static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp); 2234 static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp); 2235 static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp); 2236 static void sym_int_sir (hcb_p np); 2237 static void sym_free_ccb (hcb_p np, ccb_p cp); 2238 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order); 2239 static ccb_p sym_alloc_ccb (hcb_p np); 2240 static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa); 2241 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln); 2242 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln); 2243 static int sym_snooptest (hcb_p np); 2244 static void sym_selectclock(hcb_p np, u_char scntl3); 2245 static void sym_getclock (hcb_p np, int mult); 2246 static int sym_getpciclock (hcb_p np); 2247 static void sym_complete_ok (hcb_p np, ccb_p cp); 2248 static void sym_complete_error (hcb_p np, ccb_p cp); 2249 static void sym_callout (void *arg); 2250 static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out); 2251 static void sym_reset_dev (hcb_p np, union ccb *ccb); 2252 static void sym_action (struct cam_sim *sim, union ccb *ccb); 2253 static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp); 2254 static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio, 2255 ccb_p cp); 2256 static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 2257 bus_dma_segment_t *psegs, int nsegs); 2258 static int sym_scatter_sg_physical (hcb_p np, ccb_p cp, 2259 bus_dma_segment_t *psegs, int nsegs); 2260 static void sym_action2 (struct cam_sim *sim, union ccb *ccb); 2261 static void sym_update_trans (hcb_p np, tcb_p tp, struct sym_trans *tip, 2262 struct ccb_trans_settings *cts); 2263 static void sym_update_dflags(hcb_p np, u_char *flags, 2264 struct ccb_trans_settings *cts); 2265 2266 static const struct sym_pci_chip *sym_find_pci_chip (device_t dev); 2267 static int sym_pci_probe (device_t dev); 2268 static int sym_pci_attach (device_t dev); 2269 2270 static void sym_pci_free (hcb_p np); 2271 static int sym_cam_attach (hcb_p np); 2272 static void sym_cam_free (hcb_p np); 2273 2274 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram); 2275 static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp); 2276 static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp); 2277 2278 /* 2279 * Print something which allows to retrieve the controller type, 2280 * unit, target, lun concerned by a kernel message. 2281 */ 2282 static void PRINT_TARGET (hcb_p np, int target) 2283 { 2284 kprintf ("%s:%d:", sym_name(np), target); 2285 } 2286 2287 static void PRINT_LUN(hcb_p np, int target, int lun) 2288 { 2289 kprintf ("%s:%d:%d:", sym_name(np), target, lun); 2290 } 2291 2292 static void PRINT_ADDR (ccb_p cp) 2293 { 2294 if (cp && cp->cam_ccb) 2295 xpt_print_path(cp->cam_ccb->ccb_h.path); 2296 } 2297 2298 /* 2299 * Take into account this ccb in the freeze count. 2300 */ 2301 static void sym_freeze_cam_ccb(union ccb *ccb) 2302 { 2303 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) { 2304 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2305 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2306 xpt_freeze_devq(ccb->ccb_h.path, 1); 2307 } 2308 } 2309 } 2310 2311 /* 2312 * Set the status field of a CAM CCB. 2313 */ 2314 static __inline void sym_set_cam_status(union ccb *ccb, cam_status status) 2315 { 2316 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2317 ccb->ccb_h.status |= status; 2318 } 2319 2320 /* 2321 * Get the status field of a CAM CCB. 2322 */ 2323 static __inline int sym_get_cam_status(union ccb *ccb) 2324 { 2325 return ccb->ccb_h.status & CAM_STATUS_MASK; 2326 } 2327 2328 /* 2329 * Enqueue a CAM CCB. 2330 */ 2331 static void sym_enqueue_cam_ccb(ccb_p cp) 2332 { 2333 hcb_p np; 2334 union ccb *ccb; 2335 2336 ccb = cp->cam_ccb; 2337 np = (hcb_p) cp->arg; 2338 2339 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED)); 2340 ccb->ccb_h.status = CAM_REQ_INPROG; 2341 2342 callout_reset(&cp->ch, ccb->ccb_h.timeout * hz / 1000, sym_callout, 2343 (caddr_t) ccb); 2344 ccb->ccb_h.status |= CAM_SIM_QUEUED; 2345 ccb->ccb_h.sym_hcb_ptr = np; 2346 2347 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq); 2348 } 2349 2350 /* 2351 * Complete a pending CAM CCB. 2352 */ 2353 static void _sym_xpt_done(hcb_p np, union ccb *ccb) 2354 { 2355 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 2356 2357 KASSERT((ccb->ccb_h.status & CAM_SIM_QUEUED) == 0, 2358 ("%s: status=CAM_SIM_QUEUED", __func__)); 2359 2360 if (ccb->ccb_h.flags & CAM_DEV_QFREEZE) 2361 sym_freeze_cam_ccb(ccb); 2362 xpt_done(ccb); 2363 } 2364 2365 static void sym_xpt_done(hcb_p np, union ccb *ccb, ccb_p cp) 2366 { 2367 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 2368 2369 if (ccb->ccb_h.status & CAM_SIM_QUEUED) { 2370 callout_stop(&cp->ch); 2371 sym_remque(sym_qptr(&ccb->ccb_h.sim_links)); 2372 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2373 ccb->ccb_h.sym_hcb_ptr = NULL; 2374 } 2375 _sym_xpt_done(np, ccb); 2376 } 2377 2378 static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status) 2379 { 2380 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 2381 2382 sym_set_cam_status(ccb, cam_status); 2383 _sym_xpt_done(np, ccb); 2384 } 2385 2386 /* 2387 * SYMBIOS chip clock divisor table. 2388 * 2389 * Divisors are multiplied by 10,000,000 in order to make 2390 * calculations more simple. 2391 */ 2392 #define _5M 5000000 2393 static const u32 div_10M[] = 2394 {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M}; 2395 2396 /* 2397 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64, 2398 * 128 transfers. All chips support at least 16 transfers 2399 * bursts. The 825A, 875 and 895 chips support bursts of up 2400 * to 128 transfers and the 895A and 896 support bursts of up 2401 * to 64 transfers. All other chips support up to 16 2402 * transfers bursts. 2403 * 2404 * For PCI 32 bit data transfers each transfer is a DWORD. 2405 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers. 2406 * 2407 * We use log base 2 (burst length) as internal code, with 2408 * value 0 meaning "burst disabled". 2409 */ 2410 2411 /* 2412 * Burst length from burst code. 2413 */ 2414 #define burst_length(bc) (!(bc))? 0 : 1 << (bc) 2415 2416 /* 2417 * Burst code from io register bits. 2418 */ 2419 #define burst_code(dmode, ctest4, ctest5) \ 2420 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1 2421 2422 /* 2423 * Set initial io register bits from burst code. 2424 */ 2425 static __inline void sym_init_burst(hcb_p np, u_char bc) 2426 { 2427 np->rv_ctest4 &= ~0x80; 2428 np->rv_dmode &= ~(0x3 << 6); 2429 np->rv_ctest5 &= ~0x4; 2430 2431 if (!bc) { 2432 np->rv_ctest4 |= 0x80; 2433 } 2434 else { 2435 --bc; 2436 np->rv_dmode |= ((bc & 0x3) << 6); 2437 np->rv_ctest5 |= (bc & 0x4); 2438 } 2439 } 2440 2441 2442 /* 2443 * Print out the list of targets that have some flag disabled by user. 2444 */ 2445 static void sym_print_targets_flag(hcb_p np, int mask, char *msg) 2446 { 2447 int cnt; 2448 int i; 2449 2450 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2451 if (i == np->myaddr) 2452 continue; 2453 if (np->target[i].usrflags & mask) { 2454 if (!cnt++) 2455 kprintf("%s: %s disabled for targets", 2456 sym_name(np), msg); 2457 kprintf(" %d", i); 2458 } 2459 } 2460 if (cnt) 2461 kprintf(".\n"); 2462 } 2463 2464 /* 2465 * Save initial settings of some IO registers. 2466 * Assumed to have been set by BIOS. 2467 * We cannot reset the chip prior to reading the 2468 * IO registers, since informations will be lost. 2469 * Since the SCRIPTS processor may be running, this 2470 * is not safe on paper, but it seems to work quite 2471 * well. :) 2472 */ 2473 static void sym_save_initial_setting (hcb_p np) 2474 { 2475 np->sv_scntl0 = INB(nc_scntl0) & 0x0a; 2476 np->sv_scntl3 = INB(nc_scntl3) & 0x07; 2477 np->sv_dmode = INB(nc_dmode) & 0xce; 2478 np->sv_dcntl = INB(nc_dcntl) & 0xa8; 2479 np->sv_ctest3 = INB(nc_ctest3) & 0x01; 2480 np->sv_ctest4 = INB(nc_ctest4) & 0x80; 2481 np->sv_gpcntl = INB(nc_gpcntl); 2482 np->sv_stest1 = INB(nc_stest1); 2483 np->sv_stest2 = INB(nc_stest2) & 0x20; 2484 np->sv_stest4 = INB(nc_stest4); 2485 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */ 2486 np->sv_scntl4 = INB(nc_scntl4); 2487 np->sv_ctest5 = INB(nc_ctest5) & 0x04; 2488 } 2489 else 2490 np->sv_ctest5 = INB(nc_ctest5) & 0x24; 2491 } 2492 2493 /* 2494 * Prepare io register values used by sym_init() according 2495 * to selected and supported features. 2496 */ 2497 static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram) 2498 { 2499 u_char burst_max; 2500 u32 period; 2501 int i; 2502 2503 /* 2504 * Wide ? 2505 */ 2506 np->maxwide = (np->features & FE_WIDE)? 1 : 0; 2507 2508 /* 2509 * Get the frequency of the chip's clock. 2510 */ 2511 if (np->features & FE_QUAD) 2512 np->multiplier = 4; 2513 else if (np->features & FE_DBLR) 2514 np->multiplier = 2; 2515 else 2516 np->multiplier = 1; 2517 2518 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000; 2519 np->clock_khz *= np->multiplier; 2520 2521 if (np->clock_khz != 40000) 2522 sym_getclock(np, np->multiplier); 2523 2524 /* 2525 * Divisor to be used for async (timer pre-scaler). 2526 */ 2527 i = np->clock_divn - 1; 2528 while (--i >= 0) { 2529 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) { 2530 ++i; 2531 break; 2532 } 2533 } 2534 np->rv_scntl3 = i+1; 2535 2536 /* 2537 * The C1010 uses hardwired divisors for async. 2538 * So, we just throw away, the async. divisor.:-) 2539 */ 2540 if (np->features & FE_C10) 2541 np->rv_scntl3 = 0; 2542 2543 /* 2544 * Minimum synchronous period factor supported by the chip. 2545 * Btw, 'period' is in tenths of nanoseconds. 2546 */ 2547 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz; 2548 if (period <= 250) np->minsync = 10; 2549 else if (period <= 303) np->minsync = 11; 2550 else if (period <= 500) np->minsync = 12; 2551 else np->minsync = (period + 40 - 1) / 40; 2552 2553 /* 2554 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2). 2555 */ 2556 if (np->minsync < 25 && 2557 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3))) 2558 np->minsync = 25; 2559 else if (np->minsync < 12 && 2560 !(np->features & (FE_ULTRA2|FE_ULTRA3))) 2561 np->minsync = 12; 2562 2563 /* 2564 * Maximum synchronous period factor supported by the chip. 2565 */ 2566 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz); 2567 np->maxsync = period > 2540 ? 254 : period / 10; 2568 2569 /* 2570 * If chip is a C1010, guess the sync limits in DT mode. 2571 */ 2572 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) { 2573 if (np->clock_khz == 160000) { 2574 np->minsync_dt = 9; 2575 np->maxsync_dt = 50; 2576 np->maxoffs_dt = 62; 2577 } 2578 } 2579 2580 /* 2581 * 64 bit addressing (895A/896/1010) ? 2582 */ 2583 if (np->features & FE_DAC) 2584 #ifdef __LP64__ 2585 np->rv_ccntl1 |= (XTIMOD | EXTIBMV); 2586 #else 2587 np->rv_ccntl1 |= (DDAC); 2588 #endif 2589 2590 /* 2591 * Phase mismatch handled by SCRIPTS (895A/896/1010) ? 2592 */ 2593 if (np->features & FE_NOPM) 2594 np->rv_ccntl0 |= (ENPMJ); 2595 2596 /* 2597 * C1010 Errata. 2598 * In dual channel mode, contention occurs if internal cycles 2599 * are used. Disable internal cycles. 2600 */ 2601 if (np->device_id == PCI_ID_LSI53C1010 && 2602 np->revision_id < 0x2) 2603 np->rv_ccntl0 |= DILS; 2604 2605 /* 2606 * Select burst length (dwords) 2607 */ 2608 burst_max = SYM_SETUP_BURST_ORDER; 2609 if (burst_max == 255) 2610 burst_max = burst_code(np->sv_dmode, np->sv_ctest4, 2611 np->sv_ctest5); 2612 if (burst_max > 7) 2613 burst_max = 7; 2614 if (burst_max > np->maxburst) 2615 burst_max = np->maxburst; 2616 2617 /* 2618 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2. 2619 * This chip and the 860 Rev 1 may wrongly use PCI cache line 2620 * based transactions on LOAD/STORE instructions. So we have 2621 * to prevent these chips from using such PCI transactions in 2622 * this driver. The generic ncr driver that does not use 2623 * LOAD/STORE instructions does not need this work-around. 2624 */ 2625 if ((np->device_id == PCI_ID_SYM53C810 && 2626 np->revision_id >= 0x10 && np->revision_id <= 0x11) || 2627 (np->device_id == PCI_ID_SYM53C860 && 2628 np->revision_id <= 0x1)) 2629 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP); 2630 2631 /* 2632 * Select all supported special features. 2633 * If we are using on-board RAM for scripts, prefetch (PFEN) 2634 * does not help, but burst op fetch (BOF) does. 2635 * Disabling PFEN makes sure BOF will be used. 2636 */ 2637 if (np->features & FE_ERL) 2638 np->rv_dmode |= ERL; /* Enable Read Line */ 2639 if (np->features & FE_BOF) 2640 np->rv_dmode |= BOF; /* Burst Opcode Fetch */ 2641 if (np->features & FE_ERMP) 2642 np->rv_dmode |= ERMP; /* Enable Read Multiple */ 2643 #if 1 2644 if ((np->features & FE_PFEN) && !np->ram_ba) 2645 #else 2646 if (np->features & FE_PFEN) 2647 #endif 2648 np->rv_dcntl |= PFEN; /* Prefetch Enable */ 2649 if (np->features & FE_CLSE) 2650 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */ 2651 if (np->features & FE_WRIE) 2652 np->rv_ctest3 |= WRIE; /* Write and Invalidate */ 2653 if (np->features & FE_DFS) 2654 np->rv_ctest5 |= DFS; /* Dma Fifo Size */ 2655 2656 /* 2657 * Select some other 2658 */ 2659 if (SYM_SETUP_PCI_PARITY) 2660 np->rv_ctest4 |= MPEE; /* Master parity checking */ 2661 if (SYM_SETUP_SCSI_PARITY) 2662 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */ 2663 2664 /* 2665 * Get parity checking, host ID and verbose mode from NVRAM 2666 */ 2667 np->myaddr = 255; 2668 sym_nvram_setup_host (np, nvram); 2669 2670 /* 2671 * Get SCSI addr of host adapter (set by bios?). 2672 */ 2673 if (np->myaddr == 255) { 2674 np->myaddr = INB(nc_scid) & 0x07; 2675 if (!np->myaddr) 2676 np->myaddr = SYM_SETUP_HOST_ID; 2677 } 2678 2679 /* 2680 * Prepare initial io register bits for burst length 2681 */ 2682 sym_init_burst(np, burst_max); 2683 2684 /* 2685 * Set SCSI BUS mode. 2686 * - LVD capable chips (895/895A/896/1010) report the 2687 * current BUS mode through the STEST4 IO register. 2688 * - For previous generation chips (825/825A/875), 2689 * user has to tell us how to check against HVD, 2690 * since a 100% safe algorithm is not possible. 2691 */ 2692 np->scsi_mode = SMODE_SE; 2693 if (np->features & (FE_ULTRA2|FE_ULTRA3)) 2694 np->scsi_mode = (np->sv_stest4 & SMODE); 2695 else if (np->features & FE_DIFF) { 2696 if (SYM_SETUP_SCSI_DIFF == 1) { 2697 if (np->sv_scntl3) { 2698 if (np->sv_stest2 & 0x20) 2699 np->scsi_mode = SMODE_HVD; 2700 } 2701 else if (nvram->type == SYM_SYMBIOS_NVRAM) { 2702 if (!(INB(nc_gpreg) & 0x08)) 2703 np->scsi_mode = SMODE_HVD; 2704 } 2705 } 2706 else if (SYM_SETUP_SCSI_DIFF == 2) 2707 np->scsi_mode = SMODE_HVD; 2708 } 2709 if (np->scsi_mode == SMODE_HVD) 2710 np->rv_stest2 |= 0x20; 2711 2712 /* 2713 * Set LED support from SCRIPTS. 2714 * Ignore this feature for boards known to use a 2715 * specific GPIO wiring and for the 895A, 896 2716 * and 1010 that drive the LED directly. 2717 */ 2718 if ((SYM_SETUP_SCSI_LED || 2719 (nvram->type == SYM_SYMBIOS_NVRAM || 2720 (nvram->type == SYM_TEKRAM_NVRAM && 2721 np->device_id == PCI_ID_SYM53C895))) && 2722 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01)) 2723 np->features |= FE_LED0; 2724 2725 /* 2726 * Set irq mode. 2727 */ 2728 switch(SYM_SETUP_IRQ_MODE & 3) { 2729 case 2: 2730 np->rv_dcntl |= IRQM; 2731 break; 2732 case 1: 2733 np->rv_dcntl |= (np->sv_dcntl & IRQM); 2734 break; 2735 default: 2736 break; 2737 } 2738 2739 /* 2740 * Configure targets according to driver setup. 2741 * If NVRAM present get targets setup from NVRAM. 2742 */ 2743 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 2744 tcb_p tp = &np->target[i]; 2745 2746 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2; 2747 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2; 2748 tp->tinfo.user.period = np->minsync; 2749 if (np->features & FE_ULTRA3) 2750 tp->tinfo.user.period = np->minsync_dt; 2751 tp->tinfo.user.offset = np->maxoffs; 2752 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT; 2753 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 2754 tp->usrtags = SYM_SETUP_MAX_TAG; 2755 2756 sym_nvram_setup_target (np, i, nvram); 2757 2758 /* 2759 * For now, guess PPR/DT support from the period 2760 * and BUS width. 2761 */ 2762 if (np->features & FE_ULTRA3) { 2763 if (tp->tinfo.user.period <= 9 && 2764 tp->tinfo.user.width == BUS_16_BIT) { 2765 tp->tinfo.user.options |= PPR_OPT_DT; 2766 tp->tinfo.user.offset = np->maxoffs_dt; 2767 tp->tinfo.user.spi_version = 3; 2768 } 2769 } 2770 2771 if (!tp->usrtags) 2772 tp->usrflags &= ~SYM_TAGS_ENABLED; 2773 } 2774 2775 /* 2776 * Let user know about the settings. 2777 */ 2778 i = nvram->type; 2779 kprintf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np), 2780 i == SYM_SYMBIOS_NVRAM ? "Symbios" : 2781 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"), 2782 np->myaddr, 2783 (np->features & FE_ULTRA3) ? 80 : 2784 (np->features & FE_ULTRA2) ? 40 : 2785 (np->features & FE_ULTRA) ? 20 : 10, 2786 sym_scsi_bus_mode(np->scsi_mode), 2787 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity"); 2788 /* 2789 * Tell him more on demand. 2790 */ 2791 if (sym_verbose) { 2792 kprintf("%s: %s IRQ line driver%s\n", 2793 sym_name(np), 2794 np->rv_dcntl & IRQM ? "totem pole" : "open drain", 2795 np->ram_ba ? ", using on-chip SRAM" : ""); 2796 kprintf("%s: using %s firmware.\n", sym_name(np), np->fw_name); 2797 if (np->features & FE_NOPM) 2798 kprintf("%s: handling phase mismatch from SCRIPTS.\n", 2799 sym_name(np)); 2800 } 2801 /* 2802 * And still more. 2803 */ 2804 if (sym_verbose > 1) { 2805 kprintf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 2806 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 2807 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl, 2808 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5); 2809 2810 kprintf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 2811 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 2812 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl, 2813 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 2814 } 2815 /* 2816 * Let user be aware of targets that have some disable flags set. 2817 */ 2818 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT"); 2819 if (sym_verbose) 2820 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED, 2821 "SCAN FOR LUNS"); 2822 2823 return 0; 2824 } 2825 2826 /* 2827 * Prepare the next negotiation message if needed. 2828 * 2829 * Fill in the part of message buffer that contains the 2830 * negotiation and the nego_status field of the CCB. 2831 * Returns the size of the message in bytes. 2832 */ 2833 2834 static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr) 2835 { 2836 tcb_p tp = &np->target[cp->target]; 2837 int msglen = 0; 2838 2839 /* 2840 * Early C1010 chips need a work-around for DT 2841 * data transfer to work. 2842 */ 2843 if (!(np->features & FE_U3EN)) 2844 tp->tinfo.goal.options = 0; 2845 /* 2846 * negotiate using PPR ? 2847 */ 2848 if (tp->tinfo.goal.options & PPR_OPT_MASK) 2849 nego = NS_PPR; 2850 /* 2851 * negotiate wide transfers ? 2852 */ 2853 else if (tp->tinfo.current.width != tp->tinfo.goal.width) 2854 nego = NS_WIDE; 2855 /* 2856 * negotiate synchronous transfers? 2857 */ 2858 else if (tp->tinfo.current.period != tp->tinfo.goal.period || 2859 tp->tinfo.current.offset != tp->tinfo.goal.offset) 2860 nego = NS_SYNC; 2861 2862 switch (nego) { 2863 case NS_SYNC: 2864 msgptr[msglen++] = M_EXTENDED; 2865 msgptr[msglen++] = 3; 2866 msgptr[msglen++] = M_X_SYNC_REQ; 2867 msgptr[msglen++] = tp->tinfo.goal.period; 2868 msgptr[msglen++] = tp->tinfo.goal.offset; 2869 break; 2870 case NS_WIDE: 2871 msgptr[msglen++] = M_EXTENDED; 2872 msgptr[msglen++] = 2; 2873 msgptr[msglen++] = M_X_WIDE_REQ; 2874 msgptr[msglen++] = tp->tinfo.goal.width; 2875 break; 2876 case NS_PPR: 2877 msgptr[msglen++] = M_EXTENDED; 2878 msgptr[msglen++] = 6; 2879 msgptr[msglen++] = M_X_PPR_REQ; 2880 msgptr[msglen++] = tp->tinfo.goal.period; 2881 msgptr[msglen++] = 0; 2882 msgptr[msglen++] = tp->tinfo.goal.offset; 2883 msgptr[msglen++] = tp->tinfo.goal.width; 2884 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT; 2885 break; 2886 } 2887 2888 cp->nego_status = nego; 2889 2890 if (nego) { 2891 tp->nego_cp = cp; /* Keep track a nego will be performed */ 2892 if (DEBUG_FLAGS & DEBUG_NEGO) { 2893 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" : 2894 nego == NS_WIDE ? "wide msgout" : 2895 "ppr msgout", msgptr); 2896 } 2897 } 2898 2899 return msglen; 2900 } 2901 2902 /* 2903 * Insert a job into the start queue. 2904 */ 2905 static void sym_put_start_queue(hcb_p np, ccb_p cp) 2906 { 2907 u_short qidx; 2908 2909 #ifdef SYM_CONF_IARB_SUPPORT 2910 /* 2911 * If the previously queued CCB is not yet done, 2912 * set the IARB hint. The SCRIPTS will go with IARB 2913 * for this job when starting the previous one. 2914 * We leave devices a chance to win arbitration by 2915 * not using more than 'iarb_max' consecutive 2916 * immediate arbitrations. 2917 */ 2918 if (np->last_cp && np->iarb_count < np->iarb_max) { 2919 np->last_cp->host_flags |= HF_HINT_IARB; 2920 ++np->iarb_count; 2921 } 2922 else 2923 np->iarb_count = 0; 2924 np->last_cp = cp; 2925 #endif 2926 2927 /* 2928 * Insert first the idle task and then our job. 2929 * The MB should ensure proper ordering. 2930 */ 2931 qidx = np->squeueput + 2; 2932 if (qidx >= MAX_QUEUE*2) qidx = 0; 2933 2934 np->squeue [qidx] = cpu_to_scr(np->idletask_ba); 2935 MEMORY_BARRIER(); 2936 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba); 2937 2938 np->squeueput = qidx; 2939 2940 if (DEBUG_FLAGS & DEBUG_QUEUE) 2941 kprintf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput); 2942 2943 /* 2944 * Script processor may be waiting for reselect. 2945 * Wake it up. 2946 */ 2947 MEMORY_BARRIER(); 2948 OUTB (nc_istat, SIGP|np->istat_sem); 2949 } 2950 2951 2952 /* 2953 * Soft reset the chip. 2954 * 2955 * Raising SRST when the chip is running may cause 2956 * problems on dual function chips (see below). 2957 * On the other hand, LVD devices need some delay 2958 * to settle and report actual BUS mode in STEST4. 2959 */ 2960 static void sym_chip_reset (hcb_p np) 2961 { 2962 OUTB (nc_istat, SRST); 2963 UDELAY (10); 2964 OUTB (nc_istat, 0); 2965 UDELAY(2000); /* For BUS MODE to settle */ 2966 } 2967 2968 /* 2969 * Soft reset the chip. 2970 * 2971 * Some 896 and 876 chip revisions may hang-up if we set 2972 * the SRST (soft reset) bit at the wrong time when SCRIPTS 2973 * are running. 2974 * So, we need to abort the current operation prior to 2975 * soft resetting the chip. 2976 */ 2977 static void sym_soft_reset (hcb_p np) 2978 { 2979 u_char istat; 2980 int i; 2981 2982 OUTB (nc_istat, CABRT); 2983 for (i = 1000000 ; i ; --i) { 2984 istat = INB (nc_istat); 2985 if (istat & SIP) { 2986 INW (nc_sist); 2987 continue; 2988 } 2989 if (istat & DIP) { 2990 OUTB (nc_istat, 0); 2991 INB (nc_dstat); 2992 break; 2993 } 2994 } 2995 if (!i) 2996 kprintf("%s: unable to abort current chip operation.\n", 2997 sym_name(np)); 2998 sym_chip_reset (np); 2999 } 3000 3001 /* 3002 * Start reset process. 3003 * 3004 * The interrupt handler will reinitialize the chip. 3005 */ 3006 static void sym_start_reset(hcb_p np) 3007 { 3008 (void) sym_reset_scsi_bus(np, 1); 3009 } 3010 3011 static int sym_reset_scsi_bus(hcb_p np, int enab_int) 3012 { 3013 u32 term; 3014 int retv = 0; 3015 3016 sym_soft_reset(np); /* Soft reset the chip */ 3017 if (enab_int) 3018 OUTW (nc_sien, RST); 3019 /* 3020 * Enable Tolerant, reset IRQD if present and 3021 * properly set IRQ mode, prior to resetting the bus. 3022 */ 3023 OUTB (nc_stest3, TE); 3024 OUTB (nc_dcntl, (np->rv_dcntl & IRQM)); 3025 OUTB (nc_scntl1, CRST); 3026 UDELAY (200); 3027 3028 if (!SYM_SETUP_SCSI_BUS_CHECK) 3029 goto out; 3030 /* 3031 * Check for no terminators or SCSI bus shorts to ground. 3032 * Read SCSI data bus, data parity bits and control signals. 3033 * We are expecting RESET to be TRUE and other signals to be 3034 * FALSE. 3035 */ 3036 term = INB(nc_sstat0); 3037 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */ 3038 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */ 3039 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */ 3040 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */ 3041 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */ 3042 3043 if (!(np->features & FE_WIDE)) 3044 term &= 0x3ffff; 3045 3046 if (term != (2<<7)) { 3047 kprintf("%s: suspicious SCSI data while resetting the BUS.\n", 3048 sym_name(np)); 3049 kprintf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = " 3050 "0x%lx, expecting 0x%lx\n", 3051 sym_name(np), 3052 (np->features & FE_WIDE) ? "dp1,d15-8," : "", 3053 (u_long)term, (u_long)(2<<7)); 3054 if (SYM_SETUP_SCSI_BUS_CHECK == 1) 3055 retv = 1; 3056 } 3057 out: 3058 OUTB (nc_scntl1, 0); 3059 /* MDELAY(100); */ 3060 return retv; 3061 } 3062 3063 /* 3064 * The chip may have completed jobs. Look at the DONE QUEUE. 3065 * 3066 * On architectures that may reorder LOAD/STORE operations, 3067 * a memory barrier may be needed after the reading of the 3068 * so-called `flag' and prior to dealing with the data. 3069 */ 3070 static int sym_wakeup_done (hcb_p np) 3071 { 3072 ccb_p cp; 3073 int i, n; 3074 u32 dsa; 3075 3076 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 3077 3078 n = 0; 3079 i = np->dqueueget; 3080 while (1) { 3081 dsa = scr_to_cpu(np->dqueue[i]); 3082 if (!dsa) 3083 break; 3084 np->dqueue[i] = 0; 3085 if ((i = i+2) >= MAX_QUEUE*2) 3086 i = 0; 3087 3088 cp = sym_ccb_from_dsa(np, dsa); 3089 if (cp) { 3090 MEMORY_BARRIER(); 3091 sym_complete_ok (np, cp); 3092 ++n; 3093 } 3094 else 3095 kprintf ("%s: bad DSA (%x) in done queue.\n", 3096 sym_name(np), (u_int) dsa); 3097 } 3098 np->dqueueget = i; 3099 3100 return n; 3101 } 3102 3103 /* 3104 * Complete all active CCBs with error. 3105 * Used on CHIP/SCSI RESET. 3106 */ 3107 static void sym_flush_busy_queue (hcb_p np, int cam_status) 3108 { 3109 /* 3110 * Move all active CCBs to the COMP queue 3111 * and flush this queue. 3112 */ 3113 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq); 3114 sym_que_init(&np->busy_ccbq); 3115 sym_flush_comp_queue(np, cam_status); 3116 } 3117 3118 /* 3119 * Start chip. 3120 * 3121 * 'reason' means: 3122 * 0: initialisation. 3123 * 1: SCSI BUS RESET delivered or received. 3124 * 2: SCSI BUS MODE changed. 3125 */ 3126 static void sym_init (hcb_p np, int reason) 3127 { 3128 int i; 3129 u32 phys; 3130 3131 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 3132 3133 /* 3134 * Reset chip if asked, otherwise just clear fifos. 3135 */ 3136 if (reason == 1) 3137 sym_soft_reset(np); 3138 else { 3139 OUTB (nc_stest3, TE|CSF); 3140 OUTONB (nc_ctest3, CLF); 3141 } 3142 3143 /* 3144 * Clear Start Queue 3145 */ 3146 phys = np->squeue_ba; 3147 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3148 np->squeue[i] = cpu_to_scr(np->idletask_ba); 3149 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4); 3150 } 3151 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3152 3153 /* 3154 * Start at first entry. 3155 */ 3156 np->squeueput = 0; 3157 3158 /* 3159 * Clear Done Queue 3160 */ 3161 phys = np->dqueue_ba; 3162 for (i = 0; i < MAX_QUEUE*2; i += 2) { 3163 np->dqueue[i] = 0; 3164 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4); 3165 } 3166 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 3167 3168 /* 3169 * Start at first entry. 3170 */ 3171 np->dqueueget = 0; 3172 3173 /* 3174 * Install patches in scripts. 3175 * This also let point to first position the start 3176 * and done queue pointers used from SCRIPTS. 3177 */ 3178 np->fw_patch(np); 3179 3180 /* 3181 * Wakeup all pending jobs. 3182 */ 3183 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET); 3184 3185 /* 3186 * Init chip. 3187 */ 3188 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */ 3189 UDELAY (2000); /* The 895 needs time for the bus mode to settle */ 3190 3191 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0); 3192 /* full arb., ena parity, par->ATN */ 3193 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */ 3194 3195 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */ 3196 3197 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */ 3198 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */ 3199 OUTB (nc_istat , SIGP ); /* Signal Process */ 3200 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */ 3201 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */ 3202 3203 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */ 3204 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */ 3205 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */ 3206 3207 /* Extended Sreq/Sack filtering not supported on the C10 */ 3208 if (np->features & FE_C10) 3209 OUTB (nc_stest2, np->rv_stest2); 3210 else 3211 OUTB (nc_stest2, EXT|np->rv_stest2); 3212 3213 OUTB (nc_stest3, TE); /* TolerANT enable */ 3214 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */ 3215 3216 /* 3217 * For now, disable AIP generation on C1010-66. 3218 */ 3219 if (np->device_id == PCI_ID_LSI53C1010_2) 3220 OUTB (nc_aipcntl1, DISAIP); 3221 3222 /* 3223 * C10101 Errata. 3224 * Errant SGE's when in narrow. Write bits 4 & 5 of 3225 * STEST1 register to disable SGE. We probably should do 3226 * that from SCRIPTS for each selection/reselection, but 3227 * I just don't want. :) 3228 */ 3229 if (np->device_id == PCI_ID_LSI53C1010 && 3230 /* np->revision_id < 0xff */ 1) 3231 OUTB (nc_stest1, INB(nc_stest1) | 0x30); 3232 3233 /* 3234 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2. 3235 * Disable overlapped arbitration for some dual function devices, 3236 * regardless revision id (kind of post-chip-design feature. ;-)) 3237 */ 3238 if (np->device_id == PCI_ID_SYM53C875) 3239 OUTB (nc_ctest0, (1<<5)); 3240 else if (np->device_id == PCI_ID_SYM53C896) 3241 np->rv_ccntl0 |= DPR; 3242 3243 /* 3244 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing 3245 * and/or hardware phase mismatch, since only such chips 3246 * seem to support those IO registers. 3247 */ 3248 if (np->features & (FE_DAC|FE_NOPM)) { 3249 OUTB (nc_ccntl0, np->rv_ccntl0); 3250 OUTB (nc_ccntl1, np->rv_ccntl1); 3251 } 3252 3253 /* 3254 * If phase mismatch handled by scripts (895A/896/1010), 3255 * set PM jump addresses. 3256 */ 3257 if (np->features & FE_NOPM) { 3258 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle)); 3259 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle)); 3260 } 3261 3262 /* 3263 * Enable GPIO0 pin for writing if LED support from SCRIPTS. 3264 * Also set GPIO5 and clear GPIO6 if hardware LED control. 3265 */ 3266 if (np->features & FE_LED0) 3267 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01); 3268 else if (np->features & FE_LEDC) 3269 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20); 3270 3271 /* 3272 * enable ints 3273 */ 3274 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR); 3275 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID); 3276 3277 /* 3278 * For 895/6 enable SBMC interrupt and save current SCSI bus mode. 3279 * Try to eat the spurious SBMC interrupt that may occur when 3280 * we reset the chip but not the SCSI BUS (at initialization). 3281 */ 3282 if (np->features & (FE_ULTRA2|FE_ULTRA3)) { 3283 OUTONW (nc_sien, SBMC); 3284 if (reason == 0) { 3285 MDELAY(100); 3286 INW (nc_sist); 3287 } 3288 np->scsi_mode = INB (nc_stest4) & SMODE; 3289 } 3290 3291 /* 3292 * Fill in target structure. 3293 * Reinitialize usrsync. 3294 * Reinitialize usrwide. 3295 * Prepare sync negotiation according to actual SCSI bus mode. 3296 */ 3297 for (i=0;i<SYM_CONF_MAX_TARGET;i++) { 3298 tcb_p tp = &np->target[i]; 3299 3300 tp->to_reset = 0; 3301 tp->head.sval = 0; 3302 tp->head.wval = np->rv_scntl3; 3303 tp->head.uval = 0; 3304 3305 tp->tinfo.current.period = 0; 3306 tp->tinfo.current.offset = 0; 3307 tp->tinfo.current.width = BUS_8_BIT; 3308 tp->tinfo.current.options = 0; 3309 } 3310 3311 /* 3312 * Download SCSI SCRIPTS to on-chip RAM if present, 3313 * and start script processor. 3314 */ 3315 if (np->ram_ba) { 3316 if (sym_verbose > 1) 3317 kprintf ("%s: Downloading SCSI SCRIPTS.\n", 3318 sym_name(np)); 3319 if (np->ram_ws == 8192) { 3320 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz); 3321 OUTL (nc_mmws, np->scr_ram_seg); 3322 OUTL (nc_mmrs, np->scr_ram_seg); 3323 OUTL (nc_sfs, np->scr_ram_seg); 3324 phys = SCRIPTB_BA (np, start64); 3325 } 3326 else 3327 phys = SCRIPTA_BA (np, init); 3328 OUTRAM_OFF(0, np->scripta0, np->scripta_sz); 3329 } 3330 else 3331 phys = SCRIPTA_BA (np, init); 3332 3333 np->istat_sem = 0; 3334 3335 OUTL (nc_dsa, np->hcb_ba); 3336 OUTL_DSP (phys); 3337 3338 /* 3339 * Notify the XPT about the RESET condition. 3340 */ 3341 if (reason != 0) 3342 xpt_async(AC_BUS_RESET, np->path, NULL); 3343 } 3344 3345 /* 3346 * Get clock factor and sync divisor for a given 3347 * synchronous factor period. 3348 */ 3349 static int 3350 sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp) 3351 { 3352 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */ 3353 int div = np->clock_divn; /* Number of divisors supported */ 3354 u32 fak; /* Sync factor in sxfer */ 3355 u32 per; /* Period in tenths of ns */ 3356 u32 kpc; /* (per * clk) */ 3357 int ret; 3358 3359 /* 3360 * Compute the synchronous period in tenths of nano-seconds 3361 */ 3362 if (dt && sfac <= 9) per = 125; 3363 else if (sfac <= 10) per = 250; 3364 else if (sfac == 11) per = 303; 3365 else if (sfac == 12) per = 500; 3366 else per = 40 * sfac; 3367 ret = per; 3368 3369 kpc = per * clk; 3370 if (dt) 3371 kpc <<= 1; 3372 3373 /* 3374 * For earliest C10 revision 0, we cannot use extra 3375 * clocks for the setting of the SCSI clocking. 3376 * Note that this limits the lowest sync data transfer 3377 * to 5 Mega-transfers per second and may result in 3378 * using higher clock divisors. 3379 */ 3380 #if 1 3381 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) { 3382 /* 3383 * Look for the lowest clock divisor that allows an 3384 * output speed not faster than the period. 3385 */ 3386 while (div > 0) { 3387 --div; 3388 if (kpc > (div_10M[div] << 2)) { 3389 ++div; 3390 break; 3391 } 3392 } 3393 fak = 0; /* No extra clocks */ 3394 if (div == np->clock_divn) { /* Are we too fast ? */ 3395 ret = -1; 3396 } 3397 *divp = div; 3398 *fakp = fak; 3399 return ret; 3400 } 3401 #endif 3402 3403 /* 3404 * Look for the greatest clock divisor that allows an 3405 * input speed faster than the period. 3406 */ 3407 while (div-- > 0) 3408 if (kpc >= (div_10M[div] << 2)) break; 3409 3410 /* 3411 * Calculate the lowest clock factor that allows an output 3412 * speed not faster than the period, and the max output speed. 3413 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT. 3414 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT. 3415 */ 3416 if (dt) { 3417 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2; 3418 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */ 3419 } 3420 else { 3421 fak = (kpc - 1) / div_10M[div] + 1 - 4; 3422 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */ 3423 } 3424 3425 /* 3426 * Check against our hardware limits, or bugs :). 3427 */ 3428 if (fak < 0) {fak = 0; ret = -1;} 3429 if (fak > 2) {fak = 2; ret = -1;} 3430 3431 /* 3432 * Compute and return sync parameters. 3433 */ 3434 *divp = div; 3435 *fakp = fak; 3436 3437 return ret; 3438 } 3439 3440 /* 3441 * Tell the SCSI layer about the new transfer parameters. 3442 */ 3443 static void 3444 sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid) 3445 { 3446 struct ccb_trans_settings cts; 3447 struct cam_path *path; 3448 int sts; 3449 tcb_p tp = &np->target[target]; 3450 3451 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target, 3452 CAM_LUN_WILDCARD); 3453 if (sts != CAM_REQ_CMP) 3454 return; 3455 3456 bzero(&cts, sizeof(cts)); 3457 3458 #define cts__scsi (cts.proto_specific.scsi) 3459 #define cts__spi (cts.xport_specific.spi) 3460 3461 cts.type = CTS_TYPE_CURRENT_SETTINGS; 3462 cts.protocol = PROTO_SCSI; 3463 cts.transport = XPORT_SPI; 3464 cts.protocol_version = tp->tinfo.current.scsi_version; 3465 cts.transport_version = tp->tinfo.current.spi_version; 3466 3467 cts__spi.valid = spi_valid; 3468 if (spi_valid & CTS_SPI_VALID_SYNC_RATE) 3469 cts__spi.sync_period = tp->tinfo.current.period; 3470 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET) 3471 cts__spi.sync_offset = tp->tinfo.current.offset; 3472 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH) 3473 cts__spi.bus_width = tp->tinfo.current.width; 3474 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS) 3475 cts__spi.ppr_options = tp->tinfo.current.options; 3476 #undef cts__spi 3477 #undef cts__scsi 3478 xpt_setup_ccb(&cts.ccb_h, path, /*priority*/1); 3479 xpt_async(AC_TRANSFER_NEG, path, &cts); 3480 xpt_free_path(path); 3481 } 3482 3483 #define SYM_SPI_VALID_WDTR \ 3484 CTS_SPI_VALID_BUS_WIDTH | \ 3485 CTS_SPI_VALID_SYNC_RATE | \ 3486 CTS_SPI_VALID_SYNC_OFFSET 3487 #define SYM_SPI_VALID_SDTR \ 3488 CTS_SPI_VALID_SYNC_RATE | \ 3489 CTS_SPI_VALID_SYNC_OFFSET 3490 #define SYM_SPI_VALID_PPR \ 3491 CTS_SPI_VALID_PPR_OPTIONS | \ 3492 CTS_SPI_VALID_BUS_WIDTH | \ 3493 CTS_SPI_VALID_SYNC_RATE | \ 3494 CTS_SPI_VALID_SYNC_OFFSET 3495 3496 /* 3497 * We received a WDTR. 3498 * Let everything be aware of the changes. 3499 */ 3500 static void sym_setwide(hcb_p np, ccb_p cp, u_char wide) 3501 { 3502 tcb_p tp = &np->target[cp->target]; 3503 3504 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0); 3505 3506 /* 3507 * Tell the SCSI layer about the new transfer parameters. 3508 */ 3509 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3510 tp->tinfo.current.offset = 0; 3511 tp->tinfo.current.period = 0; 3512 tp->tinfo.current.options = 0; 3513 3514 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR); 3515 } 3516 3517 /* 3518 * We received a SDTR. 3519 * Let everything be aware of the changes. 3520 */ 3521 static void 3522 sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak) 3523 { 3524 tcb_p tp = &np->target[cp->target]; 3525 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0; 3526 3527 sym_settrans(np, cp, 0, ofs, per, wide, div, fak); 3528 3529 /* 3530 * Tell the SCSI layer about the new transfer parameters. 3531 */ 3532 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3533 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3534 tp->tinfo.goal.options = tp->tinfo.current.options = 0; 3535 3536 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR); 3537 } 3538 3539 /* 3540 * We received a PPR. 3541 * Let everything be aware of the changes. 3542 */ 3543 static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3544 u_char per, u_char wide, u_char div, u_char fak) 3545 { 3546 tcb_p tp = &np->target[cp->target]; 3547 3548 sym_settrans(np, cp, dt, ofs, per, wide, div, fak); 3549 3550 /* 3551 * Tell the SCSI layer about the new transfer parameters. 3552 */ 3553 tp->tinfo.goal.width = tp->tinfo.current.width = wide; 3554 tp->tinfo.goal.period = tp->tinfo.current.period = per; 3555 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs; 3556 tp->tinfo.goal.options = tp->tinfo.current.options = dt; 3557 3558 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR); 3559 } 3560 3561 /* 3562 * Switch trans mode for current job and it's target. 3563 */ 3564 static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs, 3565 u_char per, u_char wide, u_char div, u_char fak) 3566 { 3567 SYM_QUEHEAD *qp; 3568 union ccb *ccb; 3569 tcb_p tp; 3570 u_char target = INB (nc_sdid) & 0x0f; 3571 u_char sval, wval, uval; 3572 3573 assert (cp); 3574 if (!cp) return; 3575 ccb = cp->cam_ccb; 3576 assert (ccb); 3577 if (!ccb) return; 3578 assert (target == (cp->target & 0xf)); 3579 tp = &np->target[target]; 3580 3581 sval = tp->head.sval; 3582 wval = tp->head.wval; 3583 uval = tp->head.uval; 3584 3585 #if 0 3586 kprintf("XXXX sval=%x wval=%x uval=%x (%x)\n", 3587 sval, wval, uval, np->rv_scntl3); 3588 #endif 3589 /* 3590 * Set the offset. 3591 */ 3592 if (!(np->features & FE_C10)) 3593 sval = (sval & ~0x1f) | ofs; 3594 else 3595 sval = (sval & ~0x3f) | ofs; 3596 3597 /* 3598 * Set the sync divisor and extra clock factor. 3599 */ 3600 if (ofs != 0) { 3601 wval = (wval & ~0x70) | ((div+1) << 4); 3602 if (!(np->features & FE_C10)) 3603 sval = (sval & ~0xe0) | (fak << 5); 3604 else { 3605 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT); 3606 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT); 3607 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT); 3608 } 3609 } 3610 3611 /* 3612 * Set the bus width. 3613 */ 3614 wval = wval & ~EWS; 3615 if (wide != 0) 3616 wval |= EWS; 3617 3618 /* 3619 * Set misc. ultra enable bits. 3620 */ 3621 if (np->features & FE_C10) { 3622 uval = uval & ~(U3EN|AIPCKEN); 3623 if (dt) { 3624 assert(np->features & FE_U3EN); 3625 uval |= U3EN; 3626 } 3627 } 3628 else { 3629 wval = wval & ~ULTRA; 3630 if (per <= 12) wval |= ULTRA; 3631 } 3632 3633 /* 3634 * Stop there if sync parameters are unchanged. 3635 */ 3636 if (tp->head.sval == sval && 3637 tp->head.wval == wval && 3638 tp->head.uval == uval) 3639 return; 3640 tp->head.sval = sval; 3641 tp->head.wval = wval; 3642 tp->head.uval = uval; 3643 3644 /* 3645 * Disable extended Sreq/Sack filtering if per < 50. 3646 * Not supported on the C1010. 3647 */ 3648 if (per < 50 && !(np->features & FE_C10)) 3649 OUTOFFB (nc_stest2, EXT); 3650 3651 /* 3652 * set actual value and sync_status 3653 */ 3654 OUTB (nc_sxfer, tp->head.sval); 3655 OUTB (nc_scntl3, tp->head.wval); 3656 3657 if (np->features & FE_C10) { 3658 OUTB (nc_scntl4, tp->head.uval); 3659 } 3660 3661 /* 3662 * patch ALL busy ccbs of this target. 3663 */ 3664 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3665 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3666 if (cp->target != target) 3667 continue; 3668 cp->phys.select.sel_scntl3 = tp->head.wval; 3669 cp->phys.select.sel_sxfer = tp->head.sval; 3670 if (np->features & FE_C10) { 3671 cp->phys.select.sel_scntl4 = tp->head.uval; 3672 } 3673 } 3674 } 3675 3676 /* 3677 * log message for real hard errors 3678 * 3679 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc). 3680 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf. 3681 * 3682 * exception register: 3683 * ds: dstat 3684 * si: sist 3685 * 3686 * SCSI bus lines: 3687 * so: control lines as driven by chip. 3688 * si: control lines as seen by chip. 3689 * sd: scsi data lines as seen by chip. 3690 * 3691 * wide/fastmode: 3692 * sxfer: (see the manual) 3693 * scntl3: (see the manual) 3694 * 3695 * current script command: 3696 * dsp: script address (relative to start of script). 3697 * dbc: first word of script command. 3698 * 3699 * First 24 register of the chip: 3700 * r0..rf 3701 */ 3702 static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat) 3703 { 3704 u32 dsp; 3705 int script_ofs; 3706 int script_size; 3707 char *script_name; 3708 u_char *script_base; 3709 int i; 3710 3711 dsp = INL (nc_dsp); 3712 3713 if (dsp > np->scripta_ba && 3714 dsp <= np->scripta_ba + np->scripta_sz) { 3715 script_ofs = dsp - np->scripta_ba; 3716 script_size = np->scripta_sz; 3717 script_base = np->scripta0; 3718 script_name = "scripta"; 3719 } 3720 else if (np->scriptb_ba < dsp && 3721 dsp <= np->scriptb_ba + np->scriptb_sz) { 3722 script_ofs = dsp - np->scriptb_ba; 3723 script_size = np->scriptb_sz; 3724 script_base = np->scriptb0; 3725 script_name = "scriptb"; 3726 } else { 3727 script_ofs = dsp; 3728 script_size = 0; 3729 script_base = NULL; 3730 script_name = "mem"; 3731 } 3732 3733 kprintf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n", 3734 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist, 3735 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), 3736 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer), 3737 (unsigned)INB (nc_scntl3), script_name, script_ofs, 3738 (unsigned)INL (nc_dbc)); 3739 3740 if (((script_ofs & 3) == 0) && 3741 (unsigned)script_ofs < script_size) { 3742 kprintf ("%s: script cmd = %08x\n", sym_name(np), 3743 scr_to_cpu((int) *(u32 *)(script_base + script_ofs))); 3744 } 3745 3746 kprintf ("%s: regdump:", sym_name(np)); 3747 for (i=0; i<24;i++) 3748 kprintf (" %02x", (unsigned)INB_OFF(i)); 3749 kprintf (".\n"); 3750 3751 /* 3752 * PCI BUS error, read the PCI ststus register. 3753 */ 3754 if (dstat & (MDPE|BF)) { 3755 u_short pci_sts; 3756 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2); 3757 if (pci_sts & 0xf900) { 3758 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2); 3759 kprintf("%s: PCI STATUS = 0x%04x\n", 3760 sym_name(np), pci_sts & 0xf900); 3761 } 3762 } 3763 } 3764 3765 /* 3766 * chip interrupt handler 3767 * 3768 * In normal situations, interrupt conditions occur one at 3769 * a time. But when something bad happens on the SCSI BUS, 3770 * the chip may raise several interrupt flags before 3771 * stopping and interrupting the CPU. The additionnal 3772 * interrupt flags are stacked in some extra registers 3773 * after the SIP and/or DIP flag has been raised in the 3774 * ISTAT. After the CPU has read the interrupt condition 3775 * flag from SIST or DSTAT, the chip unstacks the other 3776 * interrupt flags and sets the corresponding bits in 3777 * SIST or DSTAT. Since the chip starts stacking once the 3778 * SIP or DIP flag is set, there is a small window of time 3779 * where the stacking does not occur. 3780 * 3781 * Typically, multiple interrupt conditions may happen in 3782 * the following situations: 3783 * 3784 * - SCSI parity error + Phase mismatch (PAR|MA) 3785 * When a parity error is detected in input phase 3786 * and the device switches to msg-in phase inside a 3787 * block MOV. 3788 * - SCSI parity error + Unexpected disconnect (PAR|UDC) 3789 * When a stupid device does not want to handle the 3790 * recovery of an SCSI parity error. 3791 * - Some combinations of STO, PAR, UDC, ... 3792 * When using non compliant SCSI stuff, when user is 3793 * doing non compliant hot tampering on the BUS, when 3794 * something really bad happens to a device, etc ... 3795 * 3796 * The heuristic suggested by SYMBIOS to handle 3797 * multiple interrupts is to try unstacking all 3798 * interrupts conditions and to handle them on some 3799 * priority based on error severity. 3800 * This will work when the unstacking has been 3801 * successful, but we cannot be 100 % sure of that, 3802 * since the CPU may have been faster to unstack than 3803 * the chip is able to stack. Hmmm ... But it seems that 3804 * such a situation is very unlikely to happen. 3805 * 3806 * If this happen, for example STO caught by the CPU 3807 * then UDC happenning before the CPU have restarted 3808 * the SCRIPTS, the driver may wrongly complete the 3809 * same command on UDC, since the SCRIPTS didn't restart 3810 * and the DSA still points to the same command. 3811 * We avoid this situation by setting the DSA to an 3812 * invalid value when the CCB is completed and before 3813 * restarting the SCRIPTS. 3814 * 3815 * Another issue is that we need some section of our 3816 * recovery procedures to be somehow uninterruptible but 3817 * the SCRIPTS processor does not provides such a 3818 * feature. For this reason, we handle recovery preferently 3819 * from the C code and check against some SCRIPTS critical 3820 * sections from the C code. 3821 * 3822 * Hopefully, the interrupt handling of the driver is now 3823 * able to resist to weird BUS error conditions, but donnot 3824 * ask me for any guarantee that it will never fail. :-) 3825 * Use at your own decision and risk. 3826 */ 3827 3828 static void sym_intr1 (hcb_p np) 3829 { 3830 u_char istat, istatc; 3831 u_char dstat; 3832 u_short sist; 3833 3834 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 3835 3836 /* 3837 * interrupt on the fly ? 3838 * 3839 * A `dummy read' is needed to ensure that the 3840 * clear of the INTF flag reaches the device 3841 * before the scanning of the DONE queue. 3842 */ 3843 istat = INB (nc_istat); 3844 if (istat & INTF) { 3845 OUTB (nc_istat, (istat & SIGP) | INTF | np->istat_sem); 3846 istat = INB (nc_istat); /* DUMMY READ */ 3847 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("F "); 3848 (void)sym_wakeup_done (np); 3849 } 3850 3851 if (!(istat & (SIP|DIP))) 3852 return; 3853 3854 #if 0 /* We should never get this one */ 3855 if (istat & CABRT) 3856 OUTB (nc_istat, CABRT); 3857 #endif 3858 3859 /* 3860 * PAR and MA interrupts may occur at the same time, 3861 * and we need to know of both in order to handle 3862 * this situation properly. We try to unstack SCSI 3863 * interrupts for that reason. BTW, I dislike a LOT 3864 * such a loop inside the interrupt routine. 3865 * Even if DMA interrupt stacking is very unlikely to 3866 * happen, we also try unstacking these ones, since 3867 * this has no performance impact. 3868 */ 3869 sist = 0; 3870 dstat = 0; 3871 istatc = istat; 3872 do { 3873 if (istatc & SIP) 3874 sist |= INW (nc_sist); 3875 if (istatc & DIP) 3876 dstat |= INB (nc_dstat); 3877 istatc = INB (nc_istat); 3878 istat |= istatc; 3879 } while (istatc & (SIP|DIP)); 3880 3881 if (DEBUG_FLAGS & DEBUG_TINY) 3882 kprintf ("<%d|%x:%x|%x:%x>", 3883 (int)INB(nc_scr0), 3884 dstat,sist, 3885 (unsigned)INL(nc_dsp), 3886 (unsigned)INL(nc_dbc)); 3887 /* 3888 * On paper, a memory barrier may be needed here. 3889 * And since we are paranoid ... :) 3890 */ 3891 MEMORY_BARRIER(); 3892 3893 /* 3894 * First, interrupts we want to service cleanly. 3895 * 3896 * Phase mismatch (MA) is the most frequent interrupt 3897 * for chip earlier than the 896 and so we have to service 3898 * it as quickly as possible. 3899 * A SCSI parity error (PAR) may be combined with a phase 3900 * mismatch condition (MA). 3901 * Programmed interrupts (SIR) are used to call the C code 3902 * from SCRIPTS. 3903 * The single step interrupt (SSI) is not used in this 3904 * driver. 3905 */ 3906 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) && 3907 !(dstat & (MDPE|BF|ABRT|IID))) { 3908 if (sist & PAR) sym_int_par (np, sist); 3909 else if (sist & MA) sym_int_ma (np); 3910 else if (dstat & SIR) sym_int_sir (np); 3911 else if (dstat & SSI) OUTONB_STD (); 3912 else goto unknown_int; 3913 return; 3914 } 3915 3916 /* 3917 * Now, interrupts that donnot happen in normal 3918 * situations and that we may need to recover from. 3919 * 3920 * On SCSI RESET (RST), we reset everything. 3921 * On SCSI BUS MODE CHANGE (SBMC), we complete all 3922 * active CCBs with RESET status, prepare all devices 3923 * for negotiating again and restart the SCRIPTS. 3924 * On STO and UDC, we complete the CCB with the corres- 3925 * ponding status and restart the SCRIPTS. 3926 */ 3927 if (sist & RST) { 3928 xpt_print_path(np->path); 3929 kprintf("SCSI BUS reset detected.\n"); 3930 sym_init (np, 1); 3931 return; 3932 } 3933 3934 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 3935 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 3936 3937 if (!(sist & (GEN|HTH|SGE)) && 3938 !(dstat & (MDPE|BF|ABRT|IID))) { 3939 if (sist & SBMC) sym_int_sbmc (np); 3940 else if (sist & STO) sym_int_sto (np); 3941 else if (sist & UDC) sym_int_udc (np); 3942 else goto unknown_int; 3943 return; 3944 } 3945 3946 /* 3947 * Now, interrupts we are not able to recover cleanly. 3948 * 3949 * Log message for hard errors. 3950 * Reset everything. 3951 */ 3952 3953 sym_log_hard_error(np, sist, dstat); 3954 3955 if ((sist & (GEN|HTH|SGE)) || 3956 (dstat & (MDPE|BF|ABRT|IID))) { 3957 sym_start_reset(np); 3958 return; 3959 } 3960 3961 unknown_int: 3962 /* 3963 * We just miss the cause of the interrupt. :( 3964 * Print a message. The timeout will do the real work. 3965 */ 3966 kprintf( "%s: unknown interrupt(s) ignored, " 3967 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n", 3968 sym_name(np), istat, dstat, sist); 3969 } 3970 3971 static void sym_intr(void *arg) 3972 { 3973 hcb_p np = arg; 3974 3975 SYM_LOCK(); 3976 3977 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("["); 3978 sym_intr1((hcb_p) arg); 3979 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("]"); 3980 3981 SYM_UNLOCK(); 3982 } 3983 3984 static void sym_poll(struct cam_sim *sim) 3985 { 3986 sym_intr1(cam_sim_softc(sim)); 3987 } 3988 3989 3990 /* 3991 * generic recovery from scsi interrupt 3992 * 3993 * The doc says that when the chip gets an SCSI interrupt, 3994 * it tries to stop in an orderly fashion, by completing 3995 * an instruction fetch that had started or by flushing 3996 * the DMA fifo for a write to memory that was executing. 3997 * Such a fashion is not enough to know if the instruction 3998 * that was just before the current DSP value has been 3999 * executed or not. 4000 * 4001 * There are some small SCRIPTS sections that deal with 4002 * the start queue and the done queue that may break any 4003 * assomption from the C code if we are interrupted 4004 * inside, so we reset if this happens. Btw, since these 4005 * SCRIPTS sections are executed while the SCRIPTS hasn't 4006 * started SCSI operations, it is very unlikely to happen. 4007 * 4008 * All the driver data structures are supposed to be 4009 * allocated from the same 4 GB memory window, so there 4010 * is a 1 to 1 relationship between DSA and driver data 4011 * structures. Since we are careful :) to invalidate the 4012 * DSA when we complete a command or when the SCRIPTS 4013 * pushes a DSA into a queue, we can trust it when it 4014 * points to a CCB. 4015 */ 4016 static void sym_recover_scsi_int (hcb_p np, u_char hsts) 4017 { 4018 u32 dsp = INL (nc_dsp); 4019 u32 dsa = INL (nc_dsa); 4020 ccb_p cp = sym_ccb_from_dsa(np, dsa); 4021 4022 /* 4023 * If we haven't been interrupted inside the SCRIPTS 4024 * critical pathes, we can safely restart the SCRIPTS 4025 * and trust the DSA value if it matches a CCB. 4026 */ 4027 if ((!(dsp > SCRIPTA_BA (np, getjob_begin) && 4028 dsp < SCRIPTA_BA (np, getjob_end) + 1)) && 4029 (!(dsp > SCRIPTA_BA (np, ungetjob) && 4030 dsp < SCRIPTA_BA (np, reselect) + 1)) && 4031 (!(dsp > SCRIPTB_BA (np, sel_for_abort) && 4032 dsp < SCRIPTB_BA (np, sel_for_abort_1) + 1)) && 4033 (!(dsp > SCRIPTA_BA (np, done) && 4034 dsp < SCRIPTA_BA (np, done_end) + 1))) { 4035 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 4036 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 4037 /* 4038 * If we have a CCB, let the SCRIPTS call us back for 4039 * the handling of the error with SCRATCHA filled with 4040 * STARTPOS. This way, we will be able to freeze the 4041 * device queue and requeue awaiting IOs. 4042 */ 4043 if (cp) { 4044 cp->host_status = hsts; 4045 OUTL_DSP (SCRIPTA_BA (np, complete_error)); 4046 } 4047 /* 4048 * Otherwise just restart the SCRIPTS. 4049 */ 4050 else { 4051 OUTL (nc_dsa, 0xffffff); 4052 OUTL_DSP (SCRIPTA_BA (np, start)); 4053 } 4054 } 4055 else 4056 goto reset_all; 4057 4058 return; 4059 4060 reset_all: 4061 sym_start_reset(np); 4062 } 4063 4064 /* 4065 * chip exception handler for selection timeout 4066 */ 4067 static void sym_int_sto (hcb_p np) 4068 { 4069 u32 dsp = INL (nc_dsp); 4070 4071 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("T"); 4072 4073 if (dsp == SCRIPTA_BA (np, wf_sel_done) + 8) 4074 sym_recover_scsi_int(np, HS_SEL_TIMEOUT); 4075 else 4076 sym_start_reset(np); 4077 } 4078 4079 /* 4080 * chip exception handler for unexpected disconnect 4081 */ 4082 static void sym_int_udc (hcb_p np) 4083 { 4084 kprintf ("%s: unexpected disconnect\n", sym_name(np)); 4085 sym_recover_scsi_int(np, HS_UNEXPECTED); 4086 } 4087 4088 /* 4089 * chip exception handler for SCSI bus mode change 4090 * 4091 * spi2-r12 11.2.3 says a transceiver mode change must 4092 * generate a reset event and a device that detects a reset 4093 * event shall initiate a hard reset. It says also that a 4094 * device that detects a mode change shall set data transfer 4095 * mode to eight bit asynchronous, etc... 4096 * So, just reinitializing all except chip should be enough. 4097 */ 4098 static void sym_int_sbmc (hcb_p np) 4099 { 4100 u_char scsi_mode = INB (nc_stest4) & SMODE; 4101 4102 /* 4103 * Notify user. 4104 */ 4105 xpt_print_path(np->path); 4106 kprintf("SCSI BUS mode change from %s to %s.\n", 4107 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode)); 4108 4109 /* 4110 * Should suspend command processing for a few seconds and 4111 * reinitialize all except the chip. 4112 */ 4113 sym_init (np, 2); 4114 } 4115 4116 /* 4117 * chip exception handler for SCSI parity error. 4118 * 4119 * When the chip detects a SCSI parity error and is 4120 * currently executing a (CH)MOV instruction, it does 4121 * not interrupt immediately, but tries to finish the 4122 * transfer of the current scatter entry before 4123 * interrupting. The following situations may occur: 4124 * 4125 * - The complete scatter entry has been transferred 4126 * without the device having changed phase. 4127 * The chip will then interrupt with the DSP pointing 4128 * to the instruction that follows the MOV. 4129 * 4130 * - A phase mismatch occurs before the MOV finished 4131 * and phase errors are to be handled by the C code. 4132 * The chip will then interrupt with both PAR and MA 4133 * conditions set. 4134 * 4135 * - A phase mismatch occurs before the MOV finished and 4136 * phase errors are to be handled by SCRIPTS. 4137 * The chip will load the DSP with the phase mismatch 4138 * JUMP address and interrupt the host processor. 4139 */ 4140 static void sym_int_par (hcb_p np, u_short sist) 4141 { 4142 u_char hsts = INB (HS_PRT); 4143 u32 dsp = INL (nc_dsp); 4144 u32 dbc = INL (nc_dbc); 4145 u32 dsa = INL (nc_dsa); 4146 u_char sbcl = INB (nc_sbcl); 4147 u_char cmd = dbc >> 24; 4148 int phase = cmd & 7; 4149 ccb_p cp = sym_ccb_from_dsa(np, dsa); 4150 4151 kprintf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n", 4152 sym_name(np), hsts, dbc, sbcl); 4153 4154 /* 4155 * Check that the chip is connected to the SCSI BUS. 4156 */ 4157 if (!(INB (nc_scntl1) & ISCON)) { 4158 sym_recover_scsi_int(np, HS_UNEXPECTED); 4159 return; 4160 } 4161 4162 /* 4163 * If the nexus is not clearly identified, reset the bus. 4164 * We will try to do better later. 4165 */ 4166 if (!cp) 4167 goto reset_all; 4168 4169 /* 4170 * Check instruction was a MOV, direction was INPUT and 4171 * ATN is asserted. 4172 */ 4173 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8)) 4174 goto reset_all; 4175 4176 /* 4177 * Keep track of the parity error. 4178 */ 4179 OUTONB (HF_PRT, HF_EXT_ERR); 4180 cp->xerr_status |= XE_PARITY_ERR; 4181 4182 /* 4183 * Prepare the message to send to the device. 4184 */ 4185 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR; 4186 4187 /* 4188 * If the old phase was DATA IN phase, we have to deal with 4189 * the 3 situations described above. 4190 * For other input phases (MSG IN and STATUS), the device 4191 * must resend the whole thing that failed parity checking 4192 * or signal error. So, jumping to dispatcher should be OK. 4193 */ 4194 if (phase == 1 || phase == 5) { 4195 /* Phase mismatch handled by SCRIPTS */ 4196 if (dsp == SCRIPTB_BA (np, pm_handle)) 4197 OUTL_DSP (dsp); 4198 /* Phase mismatch handled by the C code */ 4199 else if (sist & MA) 4200 sym_int_ma (np); 4201 /* No phase mismatch occurred */ 4202 else { 4203 OUTL (nc_temp, dsp); 4204 OUTL_DSP (SCRIPTA_BA (np, dispatch)); 4205 } 4206 } 4207 else 4208 OUTL_DSP (SCRIPTA_BA (np, clrack)); 4209 return; 4210 4211 reset_all: 4212 sym_start_reset(np); 4213 } 4214 4215 /* 4216 * chip exception handler for phase errors. 4217 * 4218 * We have to construct a new transfer descriptor, 4219 * to transfer the rest of the current block. 4220 */ 4221 static void sym_int_ma (hcb_p np) 4222 { 4223 u32 dbc; 4224 u32 rest; 4225 u32 dsp; 4226 u32 dsa; 4227 u32 nxtdsp; 4228 u32 *vdsp; 4229 u32 oadr, olen; 4230 u32 *tblp; 4231 u32 newcmd; 4232 u_int delta; 4233 u_char cmd; 4234 u_char hflags, hflags0; 4235 struct sym_pmc *pm; 4236 ccb_p cp; 4237 4238 dsp = INL (nc_dsp); 4239 dbc = INL (nc_dbc); 4240 dsa = INL (nc_dsa); 4241 4242 cmd = dbc >> 24; 4243 rest = dbc & 0xffffff; 4244 delta = 0; 4245 4246 /* 4247 * locate matching cp if any. 4248 */ 4249 cp = sym_ccb_from_dsa(np, dsa); 4250 4251 /* 4252 * Donnot take into account dma fifo and various buffers in 4253 * INPUT phase since the chip flushes everything before 4254 * raising the MA interrupt for interrupted INPUT phases. 4255 * For DATA IN phase, we will check for the SWIDE later. 4256 */ 4257 if ((cmd & 7) != 1 && (cmd & 7) != 5) { 4258 u_char ss0, ss2; 4259 4260 if (np->features & FE_DFBC) 4261 delta = INW (nc_dfbc); 4262 else { 4263 u32 dfifo; 4264 4265 /* 4266 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership. 4267 */ 4268 dfifo = INL(nc_dfifo); 4269 4270 /* 4271 * Calculate remaining bytes in DMA fifo. 4272 * (CTEST5 = dfifo >> 16) 4273 */ 4274 if (dfifo & (DFS << 16)) 4275 delta = ((((dfifo >> 8) & 0x300) | 4276 (dfifo & 0xff)) - rest) & 0x3ff; 4277 else 4278 delta = ((dfifo & 0xff) - rest) & 0x7f; 4279 } 4280 4281 /* 4282 * The data in the dma fifo has not been transferred to 4283 * the target -> add the amount to the rest 4284 * and clear the data. 4285 * Check the sstat2 register in case of wide transfer. 4286 */ 4287 rest += delta; 4288 ss0 = INB (nc_sstat0); 4289 if (ss0 & OLF) rest++; 4290 if (!(np->features & FE_C10)) 4291 if (ss0 & ORF) rest++; 4292 if (cp && (cp->phys.select.sel_scntl3 & EWS)) { 4293 ss2 = INB (nc_sstat2); 4294 if (ss2 & OLF1) rest++; 4295 if (!(np->features & FE_C10)) 4296 if (ss2 & ORF1) rest++; 4297 } 4298 4299 /* 4300 * Clear fifos. 4301 */ 4302 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */ 4303 OUTB (nc_stest3, TE|CSF); /* scsi fifo */ 4304 } 4305 4306 /* 4307 * log the information 4308 */ 4309 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) 4310 kprintf ("P%x%x RL=%d D=%d ", cmd&7, INB(nc_sbcl)&7, 4311 (unsigned) rest, (unsigned) delta); 4312 4313 /* 4314 * try to find the interrupted script command, 4315 * and the address at which to continue. 4316 */ 4317 vdsp = NULL; 4318 nxtdsp = 0; 4319 if (dsp > np->scripta_ba && 4320 dsp <= np->scripta_ba + np->scripta_sz) { 4321 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8)); 4322 nxtdsp = dsp; 4323 } 4324 else if (dsp > np->scriptb_ba && 4325 dsp <= np->scriptb_ba + np->scriptb_sz) { 4326 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8)); 4327 nxtdsp = dsp; 4328 } 4329 4330 /* 4331 * log the information 4332 */ 4333 if (DEBUG_FLAGS & DEBUG_PHASE) { 4334 kprintf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ", 4335 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd); 4336 } 4337 4338 if (!vdsp) { 4339 kprintf ("%s: interrupted SCRIPT address not found.\n", 4340 sym_name (np)); 4341 goto reset_all; 4342 } 4343 4344 if (!cp) { 4345 kprintf ("%s: SCSI phase error fixup: CCB already dequeued.\n", 4346 sym_name (np)); 4347 goto reset_all; 4348 } 4349 4350 /* 4351 * get old startaddress and old length. 4352 */ 4353 oadr = scr_to_cpu(vdsp[1]); 4354 4355 if (cmd & 0x10) { /* Table indirect */ 4356 tblp = (u32 *) ((char*) &cp->phys + oadr); 4357 olen = scr_to_cpu(tblp[0]); 4358 oadr = scr_to_cpu(tblp[1]); 4359 } else { 4360 tblp = NULL; 4361 olen = scr_to_cpu(vdsp[0]) & 0xffffff; 4362 } 4363 4364 if (DEBUG_FLAGS & DEBUG_PHASE) { 4365 kprintf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n", 4366 (unsigned) (scr_to_cpu(vdsp[0]) >> 24), 4367 tblp, 4368 (unsigned) olen, 4369 (unsigned) oadr); 4370 } 4371 4372 /* 4373 * check cmd against assumed interrupted script command. 4374 * If dt data phase, the MOVE instruction hasn't bit 4 of 4375 * the phase. 4376 */ 4377 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) { 4378 PRINT_ADDR(cp); 4379 kprintf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n", 4380 (unsigned)cmd, (unsigned)scr_to_cpu(vdsp[0]) >> 24); 4381 4382 goto reset_all; 4383 } 4384 4385 /* 4386 * if old phase not dataphase, leave here. 4387 */ 4388 if (cmd & 2) { 4389 PRINT_ADDR(cp); 4390 kprintf ("phase change %x-%x %d@%08x resid=%d.\n", 4391 cmd&7, INB(nc_sbcl)&7, (unsigned)olen, 4392 (unsigned)oadr, (unsigned)rest); 4393 goto unexpected_phase; 4394 } 4395 4396 /* 4397 * Choose the correct PM save area. 4398 * 4399 * Look at the PM_SAVE SCRIPT if you want to understand 4400 * this stuff. The equivalent code is implemented in 4401 * SCRIPTS for the 895A, 896 and 1010 that are able to 4402 * handle PM from the SCRIPTS processor. 4403 */ 4404 hflags0 = INB (HF_PRT); 4405 hflags = hflags0; 4406 4407 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) { 4408 if (hflags & HF_IN_PM0) 4409 nxtdsp = scr_to_cpu(cp->phys.pm0.ret); 4410 else if (hflags & HF_IN_PM1) 4411 nxtdsp = scr_to_cpu(cp->phys.pm1.ret); 4412 4413 if (hflags & HF_DP_SAVED) 4414 hflags ^= HF_ACT_PM; 4415 } 4416 4417 if (!(hflags & HF_ACT_PM)) { 4418 pm = &cp->phys.pm0; 4419 newcmd = SCRIPTA_BA (np, pm0_data); 4420 } 4421 else { 4422 pm = &cp->phys.pm1; 4423 newcmd = SCRIPTA_BA (np, pm1_data); 4424 } 4425 4426 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED); 4427 if (hflags != hflags0) 4428 OUTB (HF_PRT, hflags); 4429 4430 /* 4431 * fillin the phase mismatch context 4432 */ 4433 pm->sg.addr = cpu_to_scr(oadr + olen - rest); 4434 pm->sg.size = cpu_to_scr(rest); 4435 pm->ret = cpu_to_scr(nxtdsp); 4436 4437 /* 4438 * If we have a SWIDE, 4439 * - prepare the address to write the SWIDE from SCRIPTS, 4440 * - compute the SCRIPTS address to restart from, 4441 * - move current data pointer context by one byte. 4442 */ 4443 nxtdsp = SCRIPTA_BA (np, dispatch); 4444 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) && 4445 (INB (nc_scntl2) & WSR)) { 4446 u32 tmp; 4447 4448 /* 4449 * Set up the table indirect for the MOVE 4450 * of the residual byte and adjust the data 4451 * pointer context. 4452 */ 4453 tmp = scr_to_cpu(pm->sg.addr); 4454 cp->phys.wresid.addr = cpu_to_scr(tmp); 4455 pm->sg.addr = cpu_to_scr(tmp + 1); 4456 tmp = scr_to_cpu(pm->sg.size); 4457 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1); 4458 pm->sg.size = cpu_to_scr(tmp - 1); 4459 4460 /* 4461 * If only the residual byte is to be moved, 4462 * no PM context is needed. 4463 */ 4464 if ((tmp&0xffffff) == 1) 4465 newcmd = pm->ret; 4466 4467 /* 4468 * Prepare the address of SCRIPTS that will 4469 * move the residual byte to memory. 4470 */ 4471 nxtdsp = SCRIPTB_BA (np, wsr_ma_helper); 4472 } 4473 4474 if (DEBUG_FLAGS & DEBUG_PHASE) { 4475 PRINT_ADDR(cp); 4476 kprintf ("PM %x %x %x / %x %x %x.\n", 4477 hflags0, hflags, newcmd, 4478 (unsigned)scr_to_cpu(pm->sg.addr), 4479 (unsigned)scr_to_cpu(pm->sg.size), 4480 (unsigned)scr_to_cpu(pm->ret)); 4481 } 4482 4483 /* 4484 * Restart the SCRIPTS processor. 4485 */ 4486 OUTL (nc_temp, newcmd); 4487 OUTL_DSP (nxtdsp); 4488 return; 4489 4490 /* 4491 * Unexpected phase changes that occurs when the current phase 4492 * is not a DATA IN or DATA OUT phase are due to error conditions. 4493 * Such event may only happen when the SCRIPTS is using a 4494 * multibyte SCSI MOVE. 4495 * 4496 * Phase change Some possible cause 4497 * 4498 * COMMAND --> MSG IN SCSI parity error detected by target. 4499 * COMMAND --> STATUS Bad command or refused by target. 4500 * MSG OUT --> MSG IN Message rejected by target. 4501 * MSG OUT --> COMMAND Bogus target that discards extended 4502 * negotiation messages. 4503 * 4504 * The code below does not care of the new phase and so 4505 * trusts the target. Why to annoy it ? 4506 * If the interrupted phase is COMMAND phase, we restart at 4507 * dispatcher. 4508 * If a target does not get all the messages after selection, 4509 * the code assumes blindly that the target discards extended 4510 * messages and clears the negotiation status. 4511 * If the target does not want all our response to negotiation, 4512 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids 4513 * bloat for such a should_not_happen situation). 4514 * In all other situation, we reset the BUS. 4515 * Are these assumptions reasonnable ? (Wait and see ...) 4516 */ 4517 unexpected_phase: 4518 dsp -= 8; 4519 nxtdsp = 0; 4520 4521 switch (cmd & 7) { 4522 case 2: /* COMMAND phase */ 4523 nxtdsp = SCRIPTA_BA (np, dispatch); 4524 break; 4525 #if 0 4526 case 3: /* STATUS phase */ 4527 nxtdsp = SCRIPTA_BA (np, dispatch); 4528 break; 4529 #endif 4530 case 6: /* MSG OUT phase */ 4531 /* 4532 * If the device may want to use untagged when we want 4533 * tagged, we prepare an IDENTIFY without disc. granted, 4534 * since we will not be able to handle reselect. 4535 * Otherwise, we just don't care. 4536 */ 4537 if (dsp == SCRIPTA_BA (np, send_ident)) { 4538 if (cp->tag != NO_TAG && olen - rest <= 3) { 4539 cp->host_status = HS_BUSY; 4540 np->msgout[0] = M_IDENTIFY | cp->lun; 4541 nxtdsp = SCRIPTB_BA (np, ident_break_atn); 4542 } 4543 else 4544 nxtdsp = SCRIPTB_BA (np, ident_break); 4545 } 4546 else if (dsp == SCRIPTB_BA (np, send_wdtr) || 4547 dsp == SCRIPTB_BA (np, send_sdtr) || 4548 dsp == SCRIPTB_BA (np, send_ppr)) { 4549 nxtdsp = SCRIPTB_BA (np, nego_bad_phase); 4550 } 4551 break; 4552 #if 0 4553 case 7: /* MSG IN phase */ 4554 nxtdsp = SCRIPTA_BA (np, clrack); 4555 break; 4556 #endif 4557 } 4558 4559 if (nxtdsp) { 4560 OUTL_DSP (nxtdsp); 4561 return; 4562 } 4563 4564 reset_all: 4565 sym_start_reset(np); 4566 } 4567 4568 /* 4569 * Dequeue from the START queue all CCBs that match 4570 * a given target/lun/task condition (-1 means all), 4571 * and move them from the BUSY queue to the COMP queue 4572 * with CAM_REQUEUE_REQ status condition. 4573 * This function is used during error handling/recovery. 4574 * It is called with SCRIPTS not running. 4575 */ 4576 static int 4577 sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun, int task) 4578 { 4579 int j; 4580 ccb_p cp; 4581 4582 /* 4583 * Make sure the starting index is within range. 4584 */ 4585 assert((i >= 0) && (i < 2*MAX_QUEUE)); 4586 4587 /* 4588 * Walk until end of START queue and dequeue every job 4589 * that matches the target/lun/task condition. 4590 */ 4591 j = i; 4592 while (i != np->squeueput) { 4593 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i])); 4594 assert(cp); 4595 #ifdef SYM_CONF_IARB_SUPPORT 4596 /* Forget hints for IARB, they may be no longer relevant */ 4597 cp->host_flags &= ~HF_HINT_IARB; 4598 #endif 4599 if ((target == -1 || cp->target == target) && 4600 (lun == -1 || cp->lun == lun) && 4601 (task == -1 || cp->tag == task)) { 4602 sym_set_cam_status(cp->cam_ccb, CAM_REQUEUE_REQ); 4603 sym_remque(&cp->link_ccbq); 4604 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 4605 } 4606 else { 4607 if (i != j) 4608 np->squeue[j] = np->squeue[i]; 4609 if ((j += 2) >= MAX_QUEUE*2) j = 0; 4610 } 4611 if ((i += 2) >= MAX_QUEUE*2) i = 0; 4612 } 4613 if (i != j) /* Copy back the idle task if needed */ 4614 np->squeue[j] = np->squeue[i]; 4615 np->squeueput = j; /* Update our current start queue pointer */ 4616 4617 return (i - j) / 2; 4618 } 4619 4620 /* 4621 * Complete all CCBs queued to the COMP queue. 4622 * 4623 * These CCBs are assumed: 4624 * - Not to be referenced either by devices or 4625 * SCRIPTS-related queues and datas. 4626 * - To have to be completed with an error condition 4627 * or requeued. 4628 * 4629 * The device queue freeze count is incremented 4630 * for each CCB that does not prevent this. 4631 * This function is called when all CCBs involved 4632 * in error handling/recovery have been reaped. 4633 */ 4634 static void 4635 sym_flush_comp_queue(hcb_p np, int cam_status) 4636 { 4637 SYM_QUEHEAD *qp; 4638 ccb_p cp; 4639 4640 while ((qp = sym_remque_head(&np->comp_ccbq)) != NULL) { 4641 union ccb *ccb; 4642 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4643 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4644 /* Leave quiet CCBs waiting for resources */ 4645 if (cp->host_status == HS_WAIT) 4646 continue; 4647 ccb = cp->cam_ccb; 4648 if (cam_status) 4649 sym_set_cam_status(ccb, cam_status); 4650 sym_freeze_cam_ccb(ccb); 4651 sym_xpt_done(np, ccb, cp); 4652 sym_free_ccb(np, cp); 4653 } 4654 } 4655 4656 /* 4657 * chip handler for bad SCSI status condition 4658 * 4659 * In case of bad SCSI status, we unqueue all the tasks 4660 * currently queued to the controller but not yet started 4661 * and then restart the SCRIPTS processor immediately. 4662 * 4663 * QUEUE FULL and BUSY conditions are handled the same way. 4664 * Basically all the not yet started tasks are requeued in 4665 * device queue and the queue is frozen until a completion. 4666 * 4667 * For CHECK CONDITION and COMMAND TERMINATED status, we use 4668 * the CCB of the failed command to prepare a REQUEST SENSE 4669 * SCSI command and queue it to the controller queue. 4670 * 4671 * SCRATCHA is assumed to have been loaded with STARTPOS 4672 * before the SCRIPTS called the C code. 4673 */ 4674 static void sym_sir_bad_scsi_status(hcb_p np, int num, ccb_p cp) 4675 { 4676 tcb_p tp = &np->target[cp->target]; 4677 u32 startp; 4678 u_char s_status = cp->ssss_status; 4679 u_char h_flags = cp->host_flags; 4680 int msglen; 4681 int nego; 4682 int i; 4683 4684 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 4685 4686 /* 4687 * Compute the index of the next job to start from SCRIPTS. 4688 */ 4689 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 4690 4691 /* 4692 * The last CCB queued used for IARB hint may be 4693 * no longer relevant. Forget it. 4694 */ 4695 #ifdef SYM_CONF_IARB_SUPPORT 4696 if (np->last_cp) 4697 np->last_cp = NULL; 4698 #endif 4699 4700 /* 4701 * Now deal with the SCSI status. 4702 */ 4703 switch(s_status) { 4704 case S_BUSY: 4705 case S_QUEUE_FULL: 4706 if (sym_verbose >= 2) { 4707 PRINT_ADDR(cp); 4708 kprintf (s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n"); 4709 } 4710 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */ 4711 sym_complete_error (np, cp); 4712 break; 4713 case S_TERMINATED: 4714 case S_CHECK_COND: 4715 /* 4716 * If we get an SCSI error when requesting sense, give up. 4717 */ 4718 if (h_flags & HF_SENSE) { 4719 sym_complete_error (np, cp); 4720 break; 4721 } 4722 4723 /* 4724 * Dequeue all queued CCBs for that device not yet started, 4725 * and restart the SCRIPTS processor immediately. 4726 */ 4727 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 4728 OUTL_DSP (SCRIPTA_BA (np, start)); 4729 4730 /* 4731 * Save some info of the actual IO. 4732 * Compute the data residual. 4733 */ 4734 cp->sv_scsi_status = cp->ssss_status; 4735 cp->sv_xerr_status = cp->xerr_status; 4736 cp->sv_resid = sym_compute_residual(np, cp); 4737 4738 /* 4739 * Prepare all needed data structures for 4740 * requesting sense data. 4741 */ 4742 4743 /* 4744 * identify message 4745 */ 4746 cp->scsi_smsg2[0] = M_IDENTIFY | cp->lun; 4747 msglen = 1; 4748 4749 /* 4750 * If we are currently using anything different from 4751 * async. 8 bit data transfers with that target, 4752 * start a negotiation, since the device may want 4753 * to report us a UNIT ATTENTION condition due to 4754 * a cause we currently ignore, and we donnot want 4755 * to be stuck with WIDE and/or SYNC data transfer. 4756 * 4757 * cp->nego_status is filled by sym_prepare_nego(). 4758 */ 4759 cp->nego_status = 0; 4760 nego = 0; 4761 if (tp->tinfo.current.options & PPR_OPT_MASK) 4762 nego = NS_PPR; 4763 else if (tp->tinfo.current.width != BUS_8_BIT) 4764 nego = NS_WIDE; 4765 else if (tp->tinfo.current.offset != 0) 4766 nego = NS_SYNC; 4767 if (nego) 4768 msglen += 4769 sym_prepare_nego (np,cp, nego, &cp->scsi_smsg2[msglen]); 4770 /* 4771 * Message table indirect structure. 4772 */ 4773 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg2)); 4774 cp->phys.smsg.size = cpu_to_scr(msglen); 4775 4776 /* 4777 * sense command 4778 */ 4779 cp->phys.cmd.addr = cpu_to_scr(CCB_BA (cp, sensecmd)); 4780 cp->phys.cmd.size = cpu_to_scr(6); 4781 4782 /* 4783 * patch requested size into sense command 4784 */ 4785 cp->sensecmd[0] = 0x03; 4786 cp->sensecmd[1] = cp->lun << 5; 4787 if (tp->tinfo.current.scsi_version > 2 || cp->lun > 7) 4788 cp->sensecmd[1] = 0; 4789 cp->sensecmd[4] = SYM_SNS_BBUF_LEN; 4790 cp->data_len = SYM_SNS_BBUF_LEN; 4791 4792 /* 4793 * sense data 4794 */ 4795 bzero(cp->sns_bbuf, SYM_SNS_BBUF_LEN); 4796 cp->phys.sense.addr = cpu_to_scr(vtobus(cp->sns_bbuf)); 4797 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN); 4798 4799 /* 4800 * requeue the command. 4801 */ 4802 startp = SCRIPTB_BA (np, sdata_in); 4803 4804 cp->phys.head.savep = cpu_to_scr(startp); 4805 cp->phys.head.goalp = cpu_to_scr(startp + 16); 4806 cp->phys.head.lastp = cpu_to_scr(startp); 4807 cp->startp = cpu_to_scr(startp); 4808 4809 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 4810 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 4811 cp->ssss_status = S_ILLEGAL; 4812 cp->host_flags = (HF_SENSE|HF_DATA_IN); 4813 cp->xerr_status = 0; 4814 cp->extra_bytes = 0; 4815 4816 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 4817 4818 /* 4819 * Requeue the command. 4820 */ 4821 sym_put_start_queue(np, cp); 4822 4823 /* 4824 * Give back to upper layer everything we have dequeued. 4825 */ 4826 sym_flush_comp_queue(np, 0); 4827 break; 4828 } 4829 } 4830 4831 /* 4832 * After a device has accepted some management message 4833 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when 4834 * a device signals a UNIT ATTENTION condition, some 4835 * tasks are thrown away by the device. We are required 4836 * to reflect that on our tasks list since the device 4837 * will never complete these tasks. 4838 * 4839 * This function move from the BUSY queue to the COMP 4840 * queue all disconnected CCBs for a given target that 4841 * match the following criteria: 4842 * - lun=-1 means any logical UNIT otherwise a given one. 4843 * - task=-1 means any task, otherwise a given one. 4844 */ 4845 static int 4846 sym_clear_tasks(hcb_p np, int cam_status, int target, int lun, int task) 4847 { 4848 SYM_QUEHEAD qtmp, *qp; 4849 int i = 0; 4850 ccb_p cp; 4851 4852 /* 4853 * Move the entire BUSY queue to our temporary queue. 4854 */ 4855 sym_que_init(&qtmp); 4856 sym_que_splice(&np->busy_ccbq, &qtmp); 4857 sym_que_init(&np->busy_ccbq); 4858 4859 /* 4860 * Put all CCBs that matches our criteria into 4861 * the COMP queue and put back other ones into 4862 * the BUSY queue. 4863 */ 4864 while ((qp = sym_remque_head(&qtmp)) != NULL) { 4865 union ccb *ccb; 4866 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4867 ccb = cp->cam_ccb; 4868 if (cp->host_status != HS_DISCONNECT || 4869 cp->target != target || 4870 (lun != -1 && cp->lun != lun) || 4871 (task != -1 && 4872 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) { 4873 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4874 continue; 4875 } 4876 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 4877 4878 /* Preserve the software timeout condition */ 4879 if (sym_get_cam_status(ccb) != CAM_CMD_TIMEOUT) 4880 sym_set_cam_status(ccb, cam_status); 4881 ++i; 4882 #if 0 4883 kprintf("XXXX TASK @%p CLEARED\n", cp); 4884 #endif 4885 } 4886 return i; 4887 } 4888 4889 /* 4890 * chip handler for TASKS recovery 4891 * 4892 * We cannot safely abort a command, while the SCRIPTS 4893 * processor is running, since we just would be in race 4894 * with it. 4895 * 4896 * As long as we have tasks to abort, we keep the SEM 4897 * bit set in the ISTAT. When this bit is set, the 4898 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED) 4899 * each time it enters the scheduler. 4900 * 4901 * If we have to reset a target, clear tasks of a unit, 4902 * or to perform the abort of a disconnected job, we 4903 * restart the SCRIPTS for selecting the target. Once 4904 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED). 4905 * If it loses arbitration, the SCRIPTS will interrupt again 4906 * the next time it will enter its scheduler, and so on ... 4907 * 4908 * On SIR_TARGET_SELECTED, we scan for the more 4909 * appropriate thing to do: 4910 * 4911 * - If nothing, we just sent a M_ABORT message to the 4912 * target to get rid of the useless SCSI bus ownership. 4913 * According to the specs, no tasks shall be affected. 4914 * - If the target is to be reset, we send it a M_RESET 4915 * message. 4916 * - If a logical UNIT is to be cleared , we send the 4917 * IDENTIFY(lun) + M_ABORT. 4918 * - If an untagged task is to be aborted, we send the 4919 * IDENTIFY(lun) + M_ABORT. 4920 * - If a tagged task is to be aborted, we send the 4921 * IDENTIFY(lun) + task attributes + M_ABORT_TAG. 4922 * 4923 * Once our 'kiss of death' :) message has been accepted 4924 * by the target, the SCRIPTS interrupts again 4925 * (SIR_ABORT_SENT). On this interrupt, we complete 4926 * all the CCBs that should have been aborted by the 4927 * target according to our message. 4928 */ 4929 static void sym_sir_task_recovery(hcb_p np, int num) 4930 { 4931 SYM_QUEHEAD *qp; 4932 ccb_p cp; 4933 tcb_p tp; 4934 int target=-1, lun=-1, task; 4935 int i, k; 4936 4937 switch(num) { 4938 /* 4939 * The SCRIPTS processor stopped before starting 4940 * the next command in order to allow us to perform 4941 * some task recovery. 4942 */ 4943 case SIR_SCRIPT_STOPPED: 4944 /* 4945 * Do we have any target to reset or unit to clear ? 4946 */ 4947 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 4948 tp = &np->target[i]; 4949 if (tp->to_reset || 4950 (tp->lun0p && tp->lun0p->to_clear)) { 4951 target = i; 4952 break; 4953 } 4954 if (!tp->lunmp) 4955 continue; 4956 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 4957 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 4958 target = i; 4959 break; 4960 } 4961 } 4962 if (target != -1) 4963 break; 4964 } 4965 4966 /* 4967 * If not, walk the busy queue for any 4968 * disconnected CCB to be aborted. 4969 */ 4970 if (target == -1) { 4971 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 4972 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq); 4973 if (cp->host_status != HS_DISCONNECT) 4974 continue; 4975 if (cp->to_abort) { 4976 target = cp->target; 4977 break; 4978 } 4979 } 4980 } 4981 4982 /* 4983 * If some target is to be selected, 4984 * prepare and start the selection. 4985 */ 4986 if (target != -1) { 4987 tp = &np->target[target]; 4988 np->abrt_sel.sel_id = target; 4989 np->abrt_sel.sel_scntl3 = tp->head.wval; 4990 np->abrt_sel.sel_sxfer = tp->head.sval; 4991 OUTL(nc_dsa, np->hcb_ba); 4992 OUTL_DSP (SCRIPTB_BA (np, sel_for_abort)); 4993 return; 4994 } 4995 4996 /* 4997 * Now look for a CCB to abort that haven't started yet. 4998 * Btw, the SCRIPTS processor is still stopped, so 4999 * we are not in race. 5000 */ 5001 i = 0; 5002 cp = NULL; 5003 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5004 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5005 if (cp->host_status != HS_BUSY && 5006 cp->host_status != HS_NEGOTIATE) 5007 continue; 5008 if (!cp->to_abort) 5009 continue; 5010 #ifdef SYM_CONF_IARB_SUPPORT 5011 /* 5012 * If we are using IMMEDIATE ARBITRATION, we donnot 5013 * want to cancel the last queued CCB, since the 5014 * SCRIPTS may have anticipated the selection. 5015 */ 5016 if (cp == np->last_cp) { 5017 cp->to_abort = 0; 5018 continue; 5019 } 5020 #endif 5021 i = 1; /* Means we have found some */ 5022 break; 5023 } 5024 if (!i) { 5025 /* 5026 * We are done, so we donnot need 5027 * to synchronize with the SCRIPTS anylonger. 5028 * Remove the SEM flag from the ISTAT. 5029 */ 5030 np->istat_sem = 0; 5031 OUTB (nc_istat, SIGP); 5032 break; 5033 } 5034 /* 5035 * Compute index of next position in the start 5036 * queue the SCRIPTS intends to start and dequeue 5037 * all CCBs for that device that haven't been started. 5038 */ 5039 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5040 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 5041 5042 /* 5043 * Make sure at least our IO to abort has been dequeued. 5044 */ 5045 assert(i && sym_get_cam_status(cp->cam_ccb) == CAM_REQUEUE_REQ); 5046 5047 /* 5048 * Keep track in cam status of the reason of the abort. 5049 */ 5050 if (cp->to_abort == 2) 5051 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5052 else 5053 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 5054 5055 /* 5056 * Complete with error everything that we have dequeued. 5057 */ 5058 sym_flush_comp_queue(np, 0); 5059 break; 5060 /* 5061 * The SCRIPTS processor has selected a target 5062 * we may have some manual recovery to perform for. 5063 */ 5064 case SIR_TARGET_SELECTED: 5065 target = (INB (nc_sdid) & 0xf); 5066 tp = &np->target[target]; 5067 5068 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg)); 5069 5070 /* 5071 * If the target is to be reset, prepare a 5072 * M_RESET message and clear the to_reset flag 5073 * since we donnot expect this operation to fail. 5074 */ 5075 if (tp->to_reset) { 5076 np->abrt_msg[0] = M_RESET; 5077 np->abrt_tbl.size = 1; 5078 tp->to_reset = 0; 5079 break; 5080 } 5081 5082 /* 5083 * Otherwise, look for some logical unit to be cleared. 5084 */ 5085 if (tp->lun0p && tp->lun0p->to_clear) 5086 lun = 0; 5087 else if (tp->lunmp) { 5088 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 5089 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 5090 lun = k; 5091 break; 5092 } 5093 } 5094 } 5095 5096 /* 5097 * If a logical unit is to be cleared, prepare 5098 * an IDENTIFY(lun) + ABORT MESSAGE. 5099 */ 5100 if (lun != -1) { 5101 lcb_p lp = sym_lp(np, tp, lun); 5102 lp->to_clear = 0; /* We donnot expect to fail here */ 5103 np->abrt_msg[0] = M_IDENTIFY | lun; 5104 np->abrt_msg[1] = M_ABORT; 5105 np->abrt_tbl.size = 2; 5106 break; 5107 } 5108 5109 /* 5110 * Otherwise, look for some disconnected job to 5111 * abort for this target. 5112 */ 5113 i = 0; 5114 cp = NULL; 5115 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5116 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5117 if (cp->host_status != HS_DISCONNECT) 5118 continue; 5119 if (cp->target != target) 5120 continue; 5121 if (!cp->to_abort) 5122 continue; 5123 i = 1; /* Means we have some */ 5124 break; 5125 } 5126 5127 /* 5128 * If we have none, probably since the device has 5129 * completed the command before we won abitration, 5130 * send a M_ABORT message without IDENTIFY. 5131 * According to the specs, the device must just 5132 * disconnect the BUS and not abort any task. 5133 */ 5134 if (!i) { 5135 np->abrt_msg[0] = M_ABORT; 5136 np->abrt_tbl.size = 1; 5137 break; 5138 } 5139 5140 /* 5141 * We have some task to abort. 5142 * Set the IDENTIFY(lun) 5143 */ 5144 np->abrt_msg[0] = M_IDENTIFY | cp->lun; 5145 5146 /* 5147 * If we want to abort an untagged command, we 5148 * will send an IDENTIFY + M_ABORT. 5149 * Otherwise (tagged command), we will send 5150 * an IDENTIFY + task attributes + ABORT TAG. 5151 */ 5152 if (cp->tag == NO_TAG) { 5153 np->abrt_msg[1] = M_ABORT; 5154 np->abrt_tbl.size = 2; 5155 } 5156 else { 5157 np->abrt_msg[1] = cp->scsi_smsg[1]; 5158 np->abrt_msg[2] = cp->scsi_smsg[2]; 5159 np->abrt_msg[3] = M_ABORT_TAG; 5160 np->abrt_tbl.size = 4; 5161 } 5162 /* 5163 * Keep track of software timeout condition, since the 5164 * peripheral driver may not count retries on abort 5165 * conditions not due to timeout. 5166 */ 5167 if (cp->to_abort == 2) 5168 sym_set_cam_status(cp->cam_ccb, CAM_CMD_TIMEOUT); 5169 cp->to_abort = 0; /* We donnot expect to fail here */ 5170 break; 5171 5172 /* 5173 * The target has accepted our message and switched 5174 * to BUS FREE phase as we expected. 5175 */ 5176 case SIR_ABORT_SENT: 5177 target = (INB (nc_sdid) & 0xf); 5178 tp = &np->target[target]; 5179 5180 /* 5181 ** If we didn't abort anything, leave here. 5182 */ 5183 if (np->abrt_msg[0] == M_ABORT) 5184 break; 5185 5186 /* 5187 * If we sent a M_RESET, then a hardware reset has 5188 * been performed by the target. 5189 * - Reset everything to async 8 bit 5190 * - Tell ourself to negotiate next time :-) 5191 * - Prepare to clear all disconnected CCBs for 5192 * this target from our task list (lun=task=-1) 5193 */ 5194 lun = -1; 5195 task = -1; 5196 if (np->abrt_msg[0] == M_RESET) { 5197 tp->head.sval = 0; 5198 tp->head.wval = np->rv_scntl3; 5199 tp->head.uval = 0; 5200 tp->tinfo.current.period = 0; 5201 tp->tinfo.current.offset = 0; 5202 tp->tinfo.current.width = BUS_8_BIT; 5203 tp->tinfo.current.options = 0; 5204 } 5205 5206 /* 5207 * Otherwise, check for the LUN and TASK(s) 5208 * concerned by the cancelation. 5209 * If it is not ABORT_TAG then it is CLEAR_QUEUE 5210 * or an ABORT message :-) 5211 */ 5212 else { 5213 lun = np->abrt_msg[0] & 0x3f; 5214 if (np->abrt_msg[1] == M_ABORT_TAG) 5215 task = np->abrt_msg[2]; 5216 } 5217 5218 /* 5219 * Complete all the CCBs the device should have 5220 * aborted due to our 'kiss of death' message. 5221 */ 5222 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 5223 (void) sym_dequeue_from_squeue(np, i, target, lun, -1); 5224 (void) sym_clear_tasks(np, CAM_REQ_ABORTED, target, lun, task); 5225 sym_flush_comp_queue(np, 0); 5226 5227 /* 5228 * If we sent a BDR, make uper layer aware of that. 5229 */ 5230 if (np->abrt_msg[0] == M_RESET) 5231 xpt_async(AC_SENT_BDR, np->path, NULL); 5232 break; 5233 } 5234 5235 /* 5236 * Print to the log the message we intend to send. 5237 */ 5238 if (num == SIR_TARGET_SELECTED) { 5239 PRINT_TARGET(np, target); 5240 sym_printl_hex("control msgout:", np->abrt_msg, 5241 np->abrt_tbl.size); 5242 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size); 5243 } 5244 5245 /* 5246 * Let the SCRIPTS processor continue. 5247 */ 5248 OUTONB_STD (); 5249 } 5250 5251 /* 5252 * Gerard's alchemy:) that deals with with the data 5253 * pointer for both MDP and the residual calculation. 5254 * 5255 * I didn't want to bloat the code by more than 200 5256 * lignes for the handling of both MDP and the residual. 5257 * This has been achieved by using a data pointer 5258 * representation consisting in an index in the data 5259 * array (dp_sg) and a negative offset (dp_ofs) that 5260 * have the following meaning: 5261 * 5262 * - dp_sg = SYM_CONF_MAX_SG 5263 * we are at the end of the data script. 5264 * - dp_sg < SYM_CONF_MAX_SG 5265 * dp_sg points to the next entry of the scatter array 5266 * we want to transfer. 5267 * - dp_ofs < 0 5268 * dp_ofs represents the residual of bytes of the 5269 * previous entry scatter entry we will send first. 5270 * - dp_ofs = 0 5271 * no residual to send first. 5272 * 5273 * The function sym_evaluate_dp() accepts an arbitray 5274 * offset (basically from the MDP message) and returns 5275 * the corresponding values of dp_sg and dp_ofs. 5276 */ 5277 5278 static int sym_evaluate_dp(hcb_p np, ccb_p cp, u32 scr, int *ofs) 5279 { 5280 u32 dp_scr; 5281 int dp_ofs, dp_sg, dp_sgmin; 5282 int tmp; 5283 struct sym_pmc *pm; 5284 5285 /* 5286 * Compute the resulted data pointer in term of a script 5287 * address within some DATA script and a signed byte offset. 5288 */ 5289 dp_scr = scr; 5290 dp_ofs = *ofs; 5291 if (dp_scr == SCRIPTA_BA (np, pm0_data)) 5292 pm = &cp->phys.pm0; 5293 else if (dp_scr == SCRIPTA_BA (np, pm1_data)) 5294 pm = &cp->phys.pm1; 5295 else 5296 pm = NULL; 5297 5298 if (pm) { 5299 dp_scr = scr_to_cpu(pm->ret); 5300 dp_ofs -= scr_to_cpu(pm->sg.size); 5301 } 5302 5303 /* 5304 * If we are auto-sensing, then we are done. 5305 */ 5306 if (cp->host_flags & HF_SENSE) { 5307 *ofs = dp_ofs; 5308 return 0; 5309 } 5310 5311 /* 5312 * Deduce the index of the sg entry. 5313 * Keep track of the index of the first valid entry. 5314 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the 5315 * end of the data. 5316 */ 5317 tmp = scr_to_cpu(cp->phys.head.goalp); 5318 dp_sg = SYM_CONF_MAX_SG; 5319 if (dp_scr != tmp) 5320 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4); 5321 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 5322 5323 /* 5324 * Move to the sg entry the data pointer belongs to. 5325 * 5326 * If we are inside the data area, we expect result to be: 5327 * 5328 * Either, 5329 * dp_ofs = 0 and dp_sg is the index of the sg entry 5330 * the data pointer belongs to (or the end of the data) 5331 * Or, 5332 * dp_ofs < 0 and dp_sg is the index of the sg entry 5333 * the data pointer belongs to + 1. 5334 */ 5335 if (dp_ofs < 0) { 5336 int n; 5337 while (dp_sg > dp_sgmin) { 5338 --dp_sg; 5339 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5340 n = dp_ofs + (tmp & 0xffffff); 5341 if (n > 0) { 5342 ++dp_sg; 5343 break; 5344 } 5345 dp_ofs = n; 5346 } 5347 } 5348 else if (dp_ofs > 0) { 5349 while (dp_sg < SYM_CONF_MAX_SG) { 5350 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5351 dp_ofs -= (tmp & 0xffffff); 5352 ++dp_sg; 5353 if (dp_ofs <= 0) 5354 break; 5355 } 5356 } 5357 5358 /* 5359 * Make sure the data pointer is inside the data area. 5360 * If not, return some error. 5361 */ 5362 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0)) 5363 goto out_err; 5364 else if (dp_sg > SYM_CONF_MAX_SG || 5365 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0)) 5366 goto out_err; 5367 5368 /* 5369 * Save the extreme pointer if needed. 5370 */ 5371 if (dp_sg > cp->ext_sg || 5372 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) { 5373 cp->ext_sg = dp_sg; 5374 cp->ext_ofs = dp_ofs; 5375 } 5376 5377 /* 5378 * Return data. 5379 */ 5380 *ofs = dp_ofs; 5381 return dp_sg; 5382 5383 out_err: 5384 return -1; 5385 } 5386 5387 /* 5388 * chip handler for MODIFY DATA POINTER MESSAGE 5389 * 5390 * We also call this function on IGNORE WIDE RESIDUE 5391 * messages that do not match a SWIDE full condition. 5392 * Btw, we assume in that situation that such a message 5393 * is equivalent to a MODIFY DATA POINTER (offset=-1). 5394 */ 5395 5396 static void sym_modify_dp(hcb_p np, tcb_p tp, ccb_p cp, int ofs) 5397 { 5398 int dp_ofs = ofs; 5399 u32 dp_scr = INL (nc_temp); 5400 u32 dp_ret; 5401 u32 tmp; 5402 u_char hflags; 5403 int dp_sg; 5404 struct sym_pmc *pm; 5405 5406 /* 5407 * Not supported for auto-sense. 5408 */ 5409 if (cp->host_flags & HF_SENSE) 5410 goto out_reject; 5411 5412 /* 5413 * Apply our alchemy:) (see comments in sym_evaluate_dp()), 5414 * to the resulted data pointer. 5415 */ 5416 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs); 5417 if (dp_sg < 0) 5418 goto out_reject; 5419 5420 /* 5421 * And our alchemy:) allows to easily calculate the data 5422 * script address we want to return for the next data phase. 5423 */ 5424 dp_ret = cpu_to_scr(cp->phys.head.goalp); 5425 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4); 5426 5427 /* 5428 * If offset / scatter entry is zero we donnot need 5429 * a context for the new current data pointer. 5430 */ 5431 if (dp_ofs == 0) { 5432 dp_scr = dp_ret; 5433 goto out_ok; 5434 } 5435 5436 /* 5437 * Get a context for the new current data pointer. 5438 */ 5439 hflags = INB (HF_PRT); 5440 5441 if (hflags & HF_DP_SAVED) 5442 hflags ^= HF_ACT_PM; 5443 5444 if (!(hflags & HF_ACT_PM)) { 5445 pm = &cp->phys.pm0; 5446 dp_scr = SCRIPTA_BA (np, pm0_data); 5447 } 5448 else { 5449 pm = &cp->phys.pm1; 5450 dp_scr = SCRIPTA_BA (np, pm1_data); 5451 } 5452 5453 hflags &= ~(HF_DP_SAVED); 5454 5455 OUTB (HF_PRT, hflags); 5456 5457 /* 5458 * Set up the new current data pointer. 5459 * ofs < 0 there, and for the next data phase, we 5460 * want to transfer part of the data of the sg entry 5461 * corresponding to index dp_sg-1 prior to returning 5462 * to the main data script. 5463 */ 5464 pm->ret = cpu_to_scr(dp_ret); 5465 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr); 5466 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs; 5467 pm->sg.addr = cpu_to_scr(tmp); 5468 pm->sg.size = cpu_to_scr(-dp_ofs); 5469 5470 out_ok: 5471 OUTL (nc_temp, dp_scr); 5472 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5473 return; 5474 5475 out_reject: 5476 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5477 } 5478 5479 5480 /* 5481 * chip calculation of the data residual. 5482 * 5483 * As I used to say, the requirement of data residual 5484 * in SCSI is broken, useless and cannot be achieved 5485 * without huge complexity. 5486 * But most OSes and even the official CAM require it. 5487 * When stupidity happens to be so widely spread inside 5488 * a community, it gets hard to convince. 5489 * 5490 * Anyway, I don't care, since I am not going to use 5491 * any software that considers this data residual as 5492 * a relevant information. :) 5493 */ 5494 5495 static int sym_compute_residual(hcb_p np, ccb_p cp) 5496 { 5497 int dp_sg, resid = 0; 5498 int dp_ofs = 0; 5499 5500 /* 5501 * Check for some data lost or just thrown away. 5502 * We are not required to be quite accurate in this 5503 * situation. Btw, if we are odd for output and the 5504 * device claims some more data, it may well happen 5505 * than our residual be zero. :-) 5506 */ 5507 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) { 5508 if (cp->xerr_status & XE_EXTRA_DATA) 5509 resid -= cp->extra_bytes; 5510 if (cp->xerr_status & XE_SODL_UNRUN) 5511 ++resid; 5512 if (cp->xerr_status & XE_SWIDE_OVRUN) 5513 --resid; 5514 } 5515 5516 /* 5517 * If all data has been transferred, 5518 * there is no residual. 5519 */ 5520 if (cp->phys.head.lastp == cp->phys.head.goalp) 5521 return resid; 5522 5523 /* 5524 * If no data transfer occurs, or if the data 5525 * pointer is weird, return full residual. 5526 */ 5527 if (cp->startp == cp->phys.head.lastp || 5528 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp), 5529 &dp_ofs) < 0) { 5530 return cp->data_len; 5531 } 5532 5533 /* 5534 * If we were auto-sensing, then we are done. 5535 */ 5536 if (cp->host_flags & HF_SENSE) { 5537 return -dp_ofs; 5538 } 5539 5540 /* 5541 * We are now full comfortable in the computation 5542 * of the data residual (2's complement). 5543 */ 5544 resid = -cp->ext_ofs; 5545 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) { 5546 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 5547 resid += (tmp & 0xffffff); 5548 } 5549 5550 /* 5551 * Hopefully, the result is not too wrong. 5552 */ 5553 return resid; 5554 } 5555 5556 /* 5557 * Print out the content of a SCSI message. 5558 */ 5559 5560 static int sym_show_msg (u_char * msg) 5561 { 5562 u_char i; 5563 kprintf ("%x",*msg); 5564 if (*msg==M_EXTENDED) { 5565 for (i=1;i<8;i++) { 5566 if (i-1>msg[1]) break; 5567 kprintf ("-%x",msg[i]); 5568 } 5569 return (i+1); 5570 } else if ((*msg & 0xf0) == 0x20) { 5571 kprintf ("-%x",msg[1]); 5572 return (2); 5573 } 5574 return (1); 5575 } 5576 5577 static void sym_print_msg (ccb_p cp, char *label, u_char *msg) 5578 { 5579 PRINT_ADDR(cp); 5580 if (label) 5581 kprintf ("%s: ", label); 5582 5583 (void) sym_show_msg (msg); 5584 kprintf (".\n"); 5585 } 5586 5587 /* 5588 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER. 5589 * 5590 * When we try to negotiate, we append the negotiation message 5591 * to the identify and (maybe) simple tag message. 5592 * The host status field is set to HS_NEGOTIATE to mark this 5593 * situation. 5594 * 5595 * If the target doesn't answer this message immediately 5596 * (as required by the standard), the SIR_NEGO_FAILED interrupt 5597 * will be raised eventually. 5598 * The handler removes the HS_NEGOTIATE status, and sets the 5599 * negotiated value to the default (async / nowide). 5600 * 5601 * If we receive a matching answer immediately, we check it 5602 * for validity, and set the values. 5603 * 5604 * If we receive a Reject message immediately, we assume the 5605 * negotiation has failed, and fall back to standard values. 5606 * 5607 * If we receive a negotiation message while not in HS_NEGOTIATE 5608 * state, it's a target initiated negotiation. We prepare a 5609 * (hopefully) valid answer, set our parameters, and send back 5610 * this answer to the target. 5611 * 5612 * If the target doesn't fetch the answer (no message out phase), 5613 * we assume the negotiation has failed, and fall back to default 5614 * settings (SIR_NEGO_PROTO interrupt). 5615 * 5616 * When we set the values, we adjust them in all ccbs belonging 5617 * to this target, in the controller's register, and in the "phys" 5618 * field of the controller's struct sym_hcb. 5619 */ 5620 5621 /* 5622 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message. 5623 */ 5624 static void sym_sync_nego(hcb_p np, tcb_p tp, ccb_p cp) 5625 { 5626 u_char chg, ofs, per, fak, div; 5627 int req = 1; 5628 5629 /* 5630 * Synchronous request message received. 5631 */ 5632 if (DEBUG_FLAGS & DEBUG_NEGO) { 5633 sym_print_msg(cp, "sync msgin", np->msgin); 5634 } 5635 5636 /* 5637 * request or answer ? 5638 */ 5639 if (INB (HS_PRT) == HS_NEGOTIATE) { 5640 OUTB (HS_PRT, HS_BUSY); 5641 if (cp->nego_status && cp->nego_status != NS_SYNC) 5642 goto reject_it; 5643 req = 0; 5644 } 5645 5646 /* 5647 * get requested values. 5648 */ 5649 chg = 0; 5650 per = np->msgin[3]; 5651 ofs = np->msgin[4]; 5652 5653 /* 5654 * check values against our limits. 5655 */ 5656 if (ofs) { 5657 if (ofs > np->maxoffs) 5658 {chg = 1; ofs = np->maxoffs;} 5659 if (req) { 5660 if (ofs > tp->tinfo.user.offset) 5661 {chg = 1; ofs = tp->tinfo.user.offset;} 5662 } 5663 } 5664 5665 if (ofs) { 5666 if (per < np->minsync) 5667 {chg = 1; per = np->minsync;} 5668 if (req) { 5669 if (per < tp->tinfo.user.period) 5670 {chg = 1; per = tp->tinfo.user.period;} 5671 } 5672 } 5673 5674 div = fak = 0; 5675 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0) 5676 goto reject_it; 5677 5678 if (DEBUG_FLAGS & DEBUG_NEGO) { 5679 PRINT_ADDR(cp); 5680 kprintf ("sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n", 5681 ofs, per, div, fak, chg); 5682 } 5683 5684 /* 5685 * This was an answer message 5686 */ 5687 if (req == 0) { 5688 if (chg) /* Answer wasn't acceptable. */ 5689 goto reject_it; 5690 sym_setsync (np, cp, ofs, per, div, fak); 5691 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5692 return; 5693 } 5694 5695 /* 5696 * It was a request. Set value and 5697 * prepare an answer message 5698 */ 5699 sym_setsync (np, cp, ofs, per, div, fak); 5700 5701 np->msgout[0] = M_EXTENDED; 5702 np->msgout[1] = 3; 5703 np->msgout[2] = M_X_SYNC_REQ; 5704 np->msgout[3] = per; 5705 np->msgout[4] = ofs; 5706 5707 cp->nego_status = NS_SYNC; 5708 5709 if (DEBUG_FLAGS & DEBUG_NEGO) { 5710 sym_print_msg(cp, "sync msgout", np->msgout); 5711 } 5712 5713 np->msgin [0] = M_NOOP; 5714 5715 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 5716 return; 5717 reject_it: 5718 sym_setsync (np, cp, 0, 0, 0, 0); 5719 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5720 } 5721 5722 /* 5723 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message. 5724 */ 5725 static void sym_ppr_nego(hcb_p np, tcb_p tp, ccb_p cp) 5726 { 5727 u_char chg, ofs, per, fak, dt, div, wide; 5728 int req = 1; 5729 5730 /* 5731 * Synchronous request message received. 5732 */ 5733 if (DEBUG_FLAGS & DEBUG_NEGO) { 5734 sym_print_msg(cp, "ppr msgin", np->msgin); 5735 } 5736 5737 /* 5738 * get requested values. 5739 */ 5740 chg = 0; 5741 per = np->msgin[3]; 5742 ofs = np->msgin[5]; 5743 wide = np->msgin[6]; 5744 dt = np->msgin[7] & PPR_OPT_DT; 5745 5746 /* 5747 * request or answer ? 5748 */ 5749 if (INB (HS_PRT) == HS_NEGOTIATE) { 5750 OUTB (HS_PRT, HS_BUSY); 5751 if (cp->nego_status && cp->nego_status != NS_PPR) 5752 goto reject_it; 5753 req = 0; 5754 } 5755 5756 /* 5757 * check values against our limits. 5758 */ 5759 if (wide > np->maxwide) 5760 {chg = 1; wide = np->maxwide;} 5761 if (!wide || !(np->features & FE_ULTRA3)) 5762 dt &= ~PPR_OPT_DT; 5763 if (req) { 5764 if (wide > tp->tinfo.user.width) 5765 {chg = 1; wide = tp->tinfo.user.width;} 5766 } 5767 5768 if (!(np->features & FE_U3EN)) /* Broken U3EN bit not supported */ 5769 dt &= ~PPR_OPT_DT; 5770 5771 if (dt != (np->msgin[7] & PPR_OPT_MASK)) chg = 1; 5772 5773 if (ofs) { 5774 if (dt) { 5775 if (ofs > np->maxoffs_dt) 5776 {chg = 1; ofs = np->maxoffs_dt;} 5777 } 5778 else if (ofs > np->maxoffs) 5779 {chg = 1; ofs = np->maxoffs;} 5780 if (req) { 5781 if (ofs > tp->tinfo.user.offset) 5782 {chg = 1; ofs = tp->tinfo.user.offset;} 5783 } 5784 } 5785 5786 if (ofs) { 5787 if (dt) { 5788 if (per < np->minsync_dt) 5789 {chg = 1; per = np->minsync_dt;} 5790 } 5791 else if (per < np->minsync) 5792 {chg = 1; per = np->minsync;} 5793 if (req) { 5794 if (per < tp->tinfo.user.period) 5795 {chg = 1; per = tp->tinfo.user.period;} 5796 } 5797 } 5798 5799 div = fak = 0; 5800 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0) 5801 goto reject_it; 5802 5803 if (DEBUG_FLAGS & DEBUG_NEGO) { 5804 PRINT_ADDR(cp); 5805 kprintf ("ppr: " 5806 "dt=%x ofs=%d per=%d wide=%d div=%d fak=%d chg=%d.\n", 5807 dt, ofs, per, wide, div, fak, chg); 5808 } 5809 5810 /* 5811 * It was an answer. 5812 */ 5813 if (req == 0) { 5814 if (chg) /* Answer wasn't acceptable */ 5815 goto reject_it; 5816 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 5817 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5818 return; 5819 } 5820 5821 /* 5822 * It was a request. Set value and 5823 * prepare an answer message 5824 */ 5825 sym_setpprot (np, cp, dt, ofs, per, wide, div, fak); 5826 5827 np->msgout[0] = M_EXTENDED; 5828 np->msgout[1] = 6; 5829 np->msgout[2] = M_X_PPR_REQ; 5830 np->msgout[3] = per; 5831 np->msgout[4] = 0; 5832 np->msgout[5] = ofs; 5833 np->msgout[6] = wide; 5834 np->msgout[7] = dt; 5835 5836 cp->nego_status = NS_PPR; 5837 5838 if (DEBUG_FLAGS & DEBUG_NEGO) { 5839 sym_print_msg(cp, "ppr msgout", np->msgout); 5840 } 5841 5842 np->msgin [0] = M_NOOP; 5843 5844 OUTL_DSP (SCRIPTB_BA (np, ppr_resp)); 5845 return; 5846 reject_it: 5847 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 5848 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5849 /* 5850 * If it was a device response that should result in 5851 * ST, we may want to try a legacy negotiation later. 5852 */ 5853 if (!req && !dt) { 5854 tp->tinfo.goal.options = 0; 5855 tp->tinfo.goal.width = wide; 5856 tp->tinfo.goal.period = per; 5857 tp->tinfo.goal.offset = ofs; 5858 } 5859 } 5860 5861 /* 5862 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message. 5863 */ 5864 static void sym_wide_nego(hcb_p np, tcb_p tp, ccb_p cp) 5865 { 5866 u_char chg, wide; 5867 int req = 1; 5868 5869 /* 5870 * Wide request message received. 5871 */ 5872 if (DEBUG_FLAGS & DEBUG_NEGO) { 5873 sym_print_msg(cp, "wide msgin", np->msgin); 5874 } 5875 5876 /* 5877 * Is it a request from the device? 5878 */ 5879 if (INB (HS_PRT) == HS_NEGOTIATE) { 5880 OUTB (HS_PRT, HS_BUSY); 5881 if (cp->nego_status && cp->nego_status != NS_WIDE) 5882 goto reject_it; 5883 req = 0; 5884 } 5885 5886 /* 5887 * get requested values. 5888 */ 5889 chg = 0; 5890 wide = np->msgin[3]; 5891 5892 /* 5893 * check values against driver limits. 5894 */ 5895 if (wide > np->maxwide) 5896 {chg = 1; wide = np->maxwide;} 5897 if (req) { 5898 if (wide > tp->tinfo.user.width) 5899 {chg = 1; wide = tp->tinfo.user.width;} 5900 } 5901 5902 if (DEBUG_FLAGS & DEBUG_NEGO) { 5903 PRINT_ADDR(cp); 5904 kprintf ("wdtr: wide=%d chg=%d.\n", wide, chg); 5905 } 5906 5907 /* 5908 * This was an answer message 5909 */ 5910 if (req == 0) { 5911 if (chg) /* Answer wasn't acceptable. */ 5912 goto reject_it; 5913 sym_setwide (np, cp, wide); 5914 5915 /* 5916 * Negotiate for SYNC immediately after WIDE response. 5917 * This allows to negotiate for both WIDE and SYNC on 5918 * a single SCSI command (Suggested by Justin Gibbs). 5919 */ 5920 if (tp->tinfo.goal.offset) { 5921 np->msgout[0] = M_EXTENDED; 5922 np->msgout[1] = 3; 5923 np->msgout[2] = M_X_SYNC_REQ; 5924 np->msgout[3] = tp->tinfo.goal.period; 5925 np->msgout[4] = tp->tinfo.goal.offset; 5926 5927 if (DEBUG_FLAGS & DEBUG_NEGO) { 5928 sym_print_msg(cp, "sync msgout", np->msgout); 5929 } 5930 5931 cp->nego_status = NS_SYNC; 5932 OUTB (HS_PRT, HS_NEGOTIATE); 5933 OUTL_DSP (SCRIPTB_BA (np, sdtr_resp)); 5934 return; 5935 } 5936 5937 OUTL_DSP (SCRIPTA_BA (np, clrack)); 5938 return; 5939 } 5940 5941 /* 5942 * It was a request, set value and 5943 * prepare an answer message 5944 */ 5945 sym_setwide (np, cp, wide); 5946 5947 np->msgout[0] = M_EXTENDED; 5948 np->msgout[1] = 2; 5949 np->msgout[2] = M_X_WIDE_REQ; 5950 np->msgout[3] = wide; 5951 5952 np->msgin [0] = M_NOOP; 5953 5954 cp->nego_status = NS_WIDE; 5955 5956 if (DEBUG_FLAGS & DEBUG_NEGO) { 5957 sym_print_msg(cp, "wide msgout", np->msgout); 5958 } 5959 5960 OUTL_DSP (SCRIPTB_BA (np, wdtr_resp)); 5961 return; 5962 reject_it: 5963 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 5964 } 5965 5966 /* 5967 * Reset SYNC or WIDE to default settings. 5968 * 5969 * Called when a negotiation does not succeed either 5970 * on rejection or on protocol error. 5971 * 5972 * If it was a PPR that made problems, we may want to 5973 * try a legacy negotiation later. 5974 */ 5975 static void sym_nego_default(hcb_p np, tcb_p tp, ccb_p cp) 5976 { 5977 /* 5978 * any error in negotiation: 5979 * fall back to default mode. 5980 */ 5981 switch (cp->nego_status) { 5982 case NS_PPR: 5983 #if 0 5984 sym_setpprot (np, cp, 0, 0, 0, 0, 0, 0); 5985 #else 5986 tp->tinfo.goal.options = 0; 5987 if (tp->tinfo.goal.period < np->minsync) 5988 tp->tinfo.goal.period = np->minsync; 5989 if (tp->tinfo.goal.offset > np->maxoffs) 5990 tp->tinfo.goal.offset = np->maxoffs; 5991 #endif 5992 break; 5993 case NS_SYNC: 5994 sym_setsync (np, cp, 0, 0, 0, 0); 5995 break; 5996 case NS_WIDE: 5997 sym_setwide (np, cp, 0); 5998 break; 5999 } 6000 np->msgin [0] = M_NOOP; 6001 np->msgout[0] = M_NOOP; 6002 cp->nego_status = 0; 6003 } 6004 6005 /* 6006 * chip handler for MESSAGE REJECT received in response to 6007 * a WIDE or SYNCHRONOUS negotiation. 6008 */ 6009 static void sym_nego_rejected(hcb_p np, tcb_p tp, ccb_p cp) 6010 { 6011 sym_nego_default(np, tp, cp); 6012 OUTB (HS_PRT, HS_BUSY); 6013 } 6014 6015 /* 6016 * chip exception handler for programmed interrupts. 6017 */ 6018 static void sym_int_sir (hcb_p np) 6019 { 6020 u_char num = INB (nc_dsps); 6021 u32 dsa = INL (nc_dsa); 6022 ccb_p cp = sym_ccb_from_dsa(np, dsa); 6023 u_char target = INB (nc_sdid) & 0x0f; 6024 tcb_p tp = &np->target[target]; 6025 int tmp; 6026 6027 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 6028 6029 if (DEBUG_FLAGS & DEBUG_TINY) kprintf ("I#%d", num); 6030 6031 switch (num) { 6032 /* 6033 * Command has been completed with error condition 6034 * or has been auto-sensed. 6035 */ 6036 case SIR_COMPLETE_ERROR: 6037 sym_complete_error(np, cp); 6038 return; 6039 /* 6040 * The C code is currently trying to recover from something. 6041 * Typically, user want to abort some command. 6042 */ 6043 case SIR_SCRIPT_STOPPED: 6044 case SIR_TARGET_SELECTED: 6045 case SIR_ABORT_SENT: 6046 sym_sir_task_recovery(np, num); 6047 return; 6048 /* 6049 * The device didn't go to MSG OUT phase after having 6050 * been selected with ATN. We donnot want to handle 6051 * that. 6052 */ 6053 case SIR_SEL_ATN_NO_MSG_OUT: 6054 kprintf ("%s:%d: No MSG OUT phase after selection with ATN.\n", 6055 sym_name (np), target); 6056 goto out_stuck; 6057 /* 6058 * The device didn't switch to MSG IN phase after 6059 * having reseleted the initiator. 6060 */ 6061 case SIR_RESEL_NO_MSG_IN: 6062 kprintf ("%s:%d: No MSG IN phase after reselection.\n", 6063 sym_name (np), target); 6064 goto out_stuck; 6065 /* 6066 * After reselection, the device sent a message that wasn't 6067 * an IDENTIFY. 6068 */ 6069 case SIR_RESEL_NO_IDENTIFY: 6070 kprintf ("%s:%d: No IDENTIFY after reselection.\n", 6071 sym_name (np), target); 6072 goto out_stuck; 6073 /* 6074 * The device reselected a LUN we donnot know about. 6075 */ 6076 case SIR_RESEL_BAD_LUN: 6077 np->msgout[0] = M_RESET; 6078 goto out; 6079 /* 6080 * The device reselected for an untagged nexus and we 6081 * haven't any. 6082 */ 6083 case SIR_RESEL_BAD_I_T_L: 6084 np->msgout[0] = M_ABORT; 6085 goto out; 6086 /* 6087 * The device reselected for a tagged nexus that we donnot 6088 * have. 6089 */ 6090 case SIR_RESEL_BAD_I_T_L_Q: 6091 np->msgout[0] = M_ABORT_TAG; 6092 goto out; 6093 /* 6094 * The SCRIPTS let us know that the device has grabbed 6095 * our message and will abort the job. 6096 */ 6097 case SIR_RESEL_ABORTED: 6098 np->lastmsg = np->msgout[0]; 6099 np->msgout[0] = M_NOOP; 6100 kprintf ("%s:%d: message %x sent on bad reselection.\n", 6101 sym_name (np), target, np->lastmsg); 6102 goto out; 6103 /* 6104 * The SCRIPTS let us know that a message has been 6105 * successfully sent to the device. 6106 */ 6107 case SIR_MSG_OUT_DONE: 6108 np->lastmsg = np->msgout[0]; 6109 np->msgout[0] = M_NOOP; 6110 /* Should we really care of that */ 6111 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) { 6112 if (cp) { 6113 cp->xerr_status &= ~XE_PARITY_ERR; 6114 if (!cp->xerr_status) 6115 OUTOFFB (HF_PRT, HF_EXT_ERR); 6116 } 6117 } 6118 goto out; 6119 /* 6120 * The device didn't send a GOOD SCSI status. 6121 * We may have some work to do prior to allow 6122 * the SCRIPTS processor to continue. 6123 */ 6124 case SIR_BAD_SCSI_STATUS: 6125 if (!cp) 6126 goto out; 6127 sym_sir_bad_scsi_status(np, num, cp); 6128 return; 6129 /* 6130 * We are asked by the SCRIPTS to prepare a 6131 * REJECT message. 6132 */ 6133 case SIR_REJECT_TO_SEND: 6134 sym_print_msg(cp, "M_REJECT to send for ", np->msgin); 6135 np->msgout[0] = M_REJECT; 6136 goto out; 6137 /* 6138 * We have been ODD at the end of a DATA IN 6139 * transfer and the device didn't send a 6140 * IGNORE WIDE RESIDUE message. 6141 * It is a data overrun condition. 6142 */ 6143 case SIR_SWIDE_OVERRUN: 6144 if (cp) { 6145 OUTONB (HF_PRT, HF_EXT_ERR); 6146 cp->xerr_status |= XE_SWIDE_OVRUN; 6147 } 6148 goto out; 6149 /* 6150 * We have been ODD at the end of a DATA OUT 6151 * transfer. 6152 * It is a data underrun condition. 6153 */ 6154 case SIR_SODL_UNDERRUN: 6155 if (cp) { 6156 OUTONB (HF_PRT, HF_EXT_ERR); 6157 cp->xerr_status |= XE_SODL_UNRUN; 6158 } 6159 goto out; 6160 /* 6161 * The device wants us to tranfer more data than 6162 * expected or in the wrong direction. 6163 * The number of extra bytes is in scratcha. 6164 * It is a data overrun condition. 6165 */ 6166 case SIR_DATA_OVERRUN: 6167 if (cp) { 6168 OUTONB (HF_PRT, HF_EXT_ERR); 6169 cp->xerr_status |= XE_EXTRA_DATA; 6170 cp->extra_bytes += INL (nc_scratcha); 6171 } 6172 goto out; 6173 /* 6174 * The device switched to an illegal phase (4/5). 6175 */ 6176 case SIR_BAD_PHASE: 6177 if (cp) { 6178 OUTONB (HF_PRT, HF_EXT_ERR); 6179 cp->xerr_status |= XE_BAD_PHASE; 6180 } 6181 goto out; 6182 /* 6183 * We received a message. 6184 */ 6185 case SIR_MSG_RECEIVED: 6186 if (!cp) 6187 goto out_stuck; 6188 switch (np->msgin [0]) { 6189 /* 6190 * We received an extended message. 6191 * We handle MODIFY DATA POINTER, SDTR, WDTR 6192 * and reject all other extended messages. 6193 */ 6194 case M_EXTENDED: 6195 switch (np->msgin [2]) { 6196 case M_X_MODIFY_DP: 6197 if (DEBUG_FLAGS & DEBUG_POINTER) 6198 sym_print_msg(cp,"modify DP",np->msgin); 6199 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) + 6200 (np->msgin[5]<<8) + (np->msgin[6]); 6201 sym_modify_dp(np, tp, cp, tmp); 6202 return; 6203 case M_X_SYNC_REQ: 6204 sym_sync_nego(np, tp, cp); 6205 return; 6206 case M_X_PPR_REQ: 6207 sym_ppr_nego(np, tp, cp); 6208 return; 6209 case M_X_WIDE_REQ: 6210 sym_wide_nego(np, tp, cp); 6211 return; 6212 default: 6213 goto out_reject; 6214 } 6215 break; 6216 /* 6217 * We received a 1/2 byte message not handled from SCRIPTS. 6218 * We are only expecting MESSAGE REJECT and IGNORE WIDE 6219 * RESIDUE messages that haven't been anticipated by 6220 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE 6221 * WIDE RESIDUE messages are aliased as MODIFY DP (-1). 6222 */ 6223 case M_IGN_RESIDUE: 6224 if (DEBUG_FLAGS & DEBUG_POINTER) 6225 sym_print_msg(cp,"ign wide residue", np->msgin); 6226 sym_modify_dp(np, tp, cp, -1); 6227 return; 6228 case M_REJECT: 6229 if (INB (HS_PRT) == HS_NEGOTIATE) 6230 sym_nego_rejected(np, tp, cp); 6231 else { 6232 PRINT_ADDR(cp); 6233 kprintf ("M_REJECT received (%x:%x).\n", 6234 scr_to_cpu(np->lastmsg), np->msgout[0]); 6235 } 6236 goto out_clrack; 6237 break; 6238 default: 6239 goto out_reject; 6240 } 6241 break; 6242 /* 6243 * We received an unknown message. 6244 * Ignore all MSG IN phases and reject it. 6245 */ 6246 case SIR_MSG_WEIRD: 6247 sym_print_msg(cp, "WEIRD message received", np->msgin); 6248 OUTL_DSP (SCRIPTB_BA (np, msg_weird)); 6249 return; 6250 /* 6251 * Negotiation failed. 6252 * Target does not send us the reply. 6253 * Remove the HS_NEGOTIATE status. 6254 */ 6255 case SIR_NEGO_FAILED: 6256 OUTB (HS_PRT, HS_BUSY); 6257 /* 6258 * Negotiation failed. 6259 * Target does not want answer message. 6260 */ 6261 case SIR_NEGO_PROTO: 6262 sym_nego_default(np, tp, cp); 6263 goto out; 6264 } 6265 6266 out: 6267 OUTONB_STD (); 6268 return; 6269 out_reject: 6270 OUTL_DSP (SCRIPTB_BA (np, msg_bad)); 6271 return; 6272 out_clrack: 6273 OUTL_DSP (SCRIPTA_BA (np, clrack)); 6274 return; 6275 out_stuck: 6276 return; 6277 } 6278 6279 /* 6280 * Acquire a control block 6281 */ 6282 static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order) 6283 { 6284 tcb_p tp = &np->target[tn]; 6285 lcb_p lp = sym_lp(np, tp, ln); 6286 u_short tag = NO_TAG; 6287 SYM_QUEHEAD *qp; 6288 ccb_p cp = NULL; 6289 6290 /* 6291 * Look for a free CCB 6292 */ 6293 if (sym_que_empty(&np->free_ccbq)) 6294 goto out; 6295 qp = sym_remque_head(&np->free_ccbq); 6296 if (!qp) 6297 goto out; 6298 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 6299 6300 /* 6301 * If the LCB is not yet available and the LUN 6302 * has been probed ok, try to allocate the LCB. 6303 */ 6304 if (!lp && sym_is_bit(tp->lun_map, ln)) { 6305 lp = sym_alloc_lcb(np, tn, ln); 6306 if (!lp) 6307 goto out_free; 6308 } 6309 6310 /* 6311 * If the LCB is not available here, then the 6312 * logical unit is not yet discovered. For those 6313 * ones only accept 1 SCSI IO per logical unit, 6314 * since we cannot allow disconnections. 6315 */ 6316 if (!lp) { 6317 if (!sym_is_bit(tp->busy0_map, ln)) 6318 sym_set_bit(tp->busy0_map, ln); 6319 else 6320 goto out_free; 6321 } else { 6322 /* 6323 * If we have been asked for a tagged command. 6324 */ 6325 if (tag_order) { 6326 /* 6327 * Debugging purpose. 6328 */ 6329 assert(lp->busy_itl == 0); 6330 /* 6331 * Allocate resources for tags if not yet. 6332 */ 6333 if (!lp->cb_tags) { 6334 sym_alloc_lcb_tags(np, tn, ln); 6335 if (!lp->cb_tags) 6336 goto out_free; 6337 } 6338 /* 6339 * Get a tag for this SCSI IO and set up 6340 * the CCB bus address for reselection, 6341 * and count it for this LUN. 6342 * Toggle reselect path to tagged. 6343 */ 6344 if (lp->busy_itlq < SYM_CONF_MAX_TASK) { 6345 tag = lp->cb_tags[lp->ia_tag]; 6346 if (++lp->ia_tag == SYM_CONF_MAX_TASK) 6347 lp->ia_tag = 0; 6348 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba); 6349 ++lp->busy_itlq; 6350 lp->head.resel_sa = 6351 cpu_to_scr(SCRIPTA_BA (np, resel_tag)); 6352 } 6353 else 6354 goto out_free; 6355 } 6356 /* 6357 * This command will not be tagged. 6358 * If we already have either a tagged or untagged 6359 * one, refuse to overlap this untagged one. 6360 */ 6361 else { 6362 /* 6363 * Debugging purpose. 6364 */ 6365 assert(lp->busy_itl == 0 && lp->busy_itlq == 0); 6366 /* 6367 * Count this nexus for this LUN. 6368 * Set up the CCB bus address for reselection. 6369 * Toggle reselect path to untagged. 6370 */ 6371 if (++lp->busy_itl == 1) { 6372 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba); 6373 lp->head.resel_sa = 6374 cpu_to_scr(SCRIPTA_BA (np, resel_no_tag)); 6375 } 6376 else 6377 goto out_free; 6378 } 6379 } 6380 /* 6381 * Put the CCB into the busy queue. 6382 */ 6383 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 6384 6385 /* 6386 * Remember all informations needed to free this CCB. 6387 */ 6388 cp->to_abort = 0; 6389 cp->tag = tag; 6390 cp->target = tn; 6391 cp->lun = ln; 6392 6393 if (DEBUG_FLAGS & DEBUG_TAGS) { 6394 PRINT_LUN(np, tn, ln); 6395 kprintf ("ccb @%p using tag %d.\n", cp, tag); 6396 } 6397 6398 out: 6399 return cp; 6400 out_free: 6401 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6402 return NULL; 6403 } 6404 6405 /* 6406 * Release one control block 6407 */ 6408 static void sym_free_ccb (hcb_p np, ccb_p cp) 6409 { 6410 tcb_p tp = &np->target[cp->target]; 6411 lcb_p lp = sym_lp(np, tp, cp->lun); 6412 6413 if (DEBUG_FLAGS & DEBUG_TAGS) { 6414 PRINT_LUN(np, cp->target, cp->lun); 6415 kprintf ("ccb @%p freeing tag %d.\n", cp, cp->tag); 6416 } 6417 6418 /* 6419 * If LCB available, 6420 */ 6421 if (lp) { 6422 /* 6423 * If tagged, release the tag, set the relect path 6424 */ 6425 if (cp->tag != NO_TAG) { 6426 /* 6427 * Free the tag value. 6428 */ 6429 lp->cb_tags[lp->if_tag] = cp->tag; 6430 if (++lp->if_tag == SYM_CONF_MAX_TASK) 6431 lp->if_tag = 0; 6432 /* 6433 * Make the reselect path invalid, 6434 * and uncount this CCB. 6435 */ 6436 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba); 6437 --lp->busy_itlq; 6438 } else { /* Untagged */ 6439 /* 6440 * Make the reselect path invalid, 6441 * and uncount this CCB. 6442 */ 6443 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6444 --lp->busy_itl; 6445 } 6446 /* 6447 * If no JOB active, make the LUN reselect path invalid. 6448 */ 6449 if (lp->busy_itlq == 0 && lp->busy_itl == 0) 6450 lp->head.resel_sa = 6451 cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6452 } 6453 /* 6454 * Otherwise, we only accept 1 IO per LUN. 6455 * Clear the bit that keeps track of this IO. 6456 */ 6457 else 6458 sym_clr_bit(tp->busy0_map, cp->lun); 6459 6460 /* 6461 * We donnot queue more than 1 ccb per target 6462 * with negotiation at any time. If this ccb was 6463 * used for negotiation, clear this info in the tcb. 6464 */ 6465 if (cp == tp->nego_cp) 6466 tp->nego_cp = NULL; 6467 6468 #ifdef SYM_CONF_IARB_SUPPORT 6469 /* 6470 * If we just complete the last queued CCB, 6471 * clear this info that is no longer relevant. 6472 */ 6473 if (cp == np->last_cp) 6474 np->last_cp = NULL; 6475 #endif 6476 6477 /* 6478 * Unmap user data from DMA map if needed. 6479 */ 6480 if (cp->dmamapped) { 6481 bus_dmamap_unload(np->data_dmat, cp->dmamap); 6482 cp->dmamapped = 0; 6483 } 6484 6485 /* 6486 * Make this CCB available. 6487 */ 6488 cp->cam_ccb = NULL; 6489 cp->host_status = HS_IDLE; 6490 sym_remque(&cp->link_ccbq); 6491 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6492 } 6493 6494 /* 6495 * Allocate a CCB from memory and initialize its fixed part. 6496 */ 6497 static ccb_p sym_alloc_ccb(hcb_p np) 6498 { 6499 ccb_p cp = NULL; 6500 int hcode; 6501 6502 SYM_LOCK_ASSERT(0); 6503 6504 /* 6505 * Prevent from allocating more CCBs than we can 6506 * queue to the controller. 6507 */ 6508 if (np->actccbs >= SYM_CONF_MAX_START) 6509 return NULL; 6510 6511 /* 6512 * Allocate memory for this CCB. 6513 */ 6514 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB"); 6515 if (!cp) 6516 return NULL; 6517 6518 /* 6519 * Allocate a bounce buffer for sense data. 6520 */ 6521 cp->sns_bbuf = sym_calloc_dma(SYM_SNS_BBUF_LEN, "SNS_BBUF"); 6522 if (!cp->sns_bbuf) 6523 goto out_free; 6524 6525 /* 6526 * Allocate a map for the DMA of user data. 6527 */ 6528 if (bus_dmamap_create(np->data_dmat, 0, &cp->dmamap)) 6529 goto out_free; 6530 /* 6531 * Count it. 6532 */ 6533 np->actccbs++; 6534 6535 /* 6536 * Initialize the callout. 6537 */ 6538 callout_init(&cp->ch); 6539 6540 /* 6541 * Compute the bus address of this ccb. 6542 */ 6543 cp->ccb_ba = vtobus(cp); 6544 6545 /* 6546 * Insert this ccb into the hashed list. 6547 */ 6548 hcode = CCB_HASH_CODE(cp->ccb_ba); 6549 cp->link_ccbh = np->ccbh[hcode]; 6550 np->ccbh[hcode] = cp; 6551 6552 /* 6553 * Initialize the start and restart actions. 6554 */ 6555 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 6556 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 6557 6558 /* 6559 * Initilialyze some other fields. 6560 */ 6561 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2])); 6562 6563 /* 6564 * Chain into free ccb queue. 6565 */ 6566 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 6567 6568 return cp; 6569 out_free: 6570 if (cp->sns_bbuf) 6571 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF"); 6572 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 6573 return NULL; 6574 } 6575 6576 /* 6577 * Look up a CCB from a DSA value. 6578 */ 6579 static ccb_p sym_ccb_from_dsa(hcb_p np, u32 dsa) 6580 { 6581 int hcode; 6582 ccb_p cp; 6583 6584 hcode = CCB_HASH_CODE(dsa); 6585 cp = np->ccbh[hcode]; 6586 while (cp) { 6587 if (cp->ccb_ba == dsa) 6588 break; 6589 cp = cp->link_ccbh; 6590 } 6591 6592 return cp; 6593 } 6594 6595 /* 6596 * Target control block initialisation. 6597 * Nothing important to do at the moment. 6598 */ 6599 static void sym_init_tcb (hcb_p np, u_char tn) 6600 { 6601 /* 6602 * Check some alignments required by the chip. 6603 */ 6604 assert (((offsetof(struct sym_reg, nc_sxfer) ^ 6605 offsetof(struct sym_tcb, head.sval)) &3) == 0); 6606 assert (((offsetof(struct sym_reg, nc_scntl3) ^ 6607 offsetof(struct sym_tcb, head.wval)) &3) == 0); 6608 } 6609 6610 /* 6611 * Lun control block allocation and initialization. 6612 */ 6613 static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln) 6614 { 6615 tcb_p tp = &np->target[tn]; 6616 lcb_p lp = sym_lp(np, tp, ln); 6617 6618 /* 6619 * Already done, just return. 6620 */ 6621 if (lp) 6622 return lp; 6623 /* 6624 * Check against some race. 6625 */ 6626 assert(!sym_is_bit(tp->busy0_map, ln)); 6627 6628 /* 6629 * Initialize the target control block if not yet. 6630 */ 6631 sym_init_tcb (np, tn); 6632 6633 /* 6634 * Allocate the LCB bus address array. 6635 * Compute the bus address of this table. 6636 */ 6637 if (ln && !tp->luntbl) { 6638 int i; 6639 6640 tp->luntbl = sym_calloc_dma(256, "LUNTBL"); 6641 if (!tp->luntbl) 6642 goto fail; 6643 for (i = 0 ; i < 64 ; i++) 6644 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 6645 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl)); 6646 } 6647 6648 /* 6649 * Allocate the table of pointers for LUN(s) > 0, if needed. 6650 */ 6651 if (ln && !tp->lunmp) { 6652 tp->lunmp = sym_calloc(SYM_CONF_MAX_LUN * sizeof(lcb_p), 6653 "LUNMP"); 6654 if (!tp->lunmp) 6655 goto fail; 6656 } 6657 6658 /* 6659 * Allocate the lcb. 6660 * Make it available to the chip. 6661 */ 6662 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB"); 6663 if (!lp) 6664 goto fail; 6665 if (ln) { 6666 tp->lunmp[ln] = lp; 6667 tp->luntbl[ln] = cpu_to_scr(vtobus(lp)); 6668 } 6669 else { 6670 tp->lun0p = lp; 6671 tp->head.lun0_sa = cpu_to_scr(vtobus(lp)); 6672 } 6673 6674 /* 6675 * Let the itl task point to error handling. 6676 */ 6677 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 6678 6679 /* 6680 * Set the reselect pattern to our default. :) 6681 */ 6682 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 6683 6684 /* 6685 * Set user capabilities. 6686 */ 6687 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 6688 6689 fail: 6690 return lp; 6691 } 6692 6693 /* 6694 * Allocate LCB resources for tagged command queuing. 6695 */ 6696 static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln) 6697 { 6698 tcb_p tp = &np->target[tn]; 6699 lcb_p lp = sym_lp(np, tp, ln); 6700 int i; 6701 6702 /* 6703 * If LCB not available, try to allocate it. 6704 */ 6705 if (!lp && !(lp = sym_alloc_lcb(np, tn, ln))) 6706 return; 6707 6708 /* 6709 * Allocate the task table and and the tag allocation 6710 * circular buffer. We want both or none. 6711 */ 6712 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6713 if (!lp->itlq_tbl) 6714 return; 6715 lp->cb_tags = sym_calloc(SYM_CONF_MAX_TASK, "CB_TAGS"); 6716 if (!lp->cb_tags) { 6717 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 6718 lp->itlq_tbl = NULL; 6719 return; 6720 } 6721 6722 /* 6723 * Initialize the task table with invalid entries. 6724 */ 6725 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6726 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba); 6727 6728 /* 6729 * Fill up the tag buffer with tag numbers. 6730 */ 6731 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 6732 lp->cb_tags[i] = i; 6733 6734 /* 6735 * Make the task table available to SCRIPTS, 6736 * And accept tagged commands now. 6737 */ 6738 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl)); 6739 } 6740 6741 /* 6742 * Test the pci bus snoop logic :-( 6743 * 6744 * Has to be called with interrupts disabled. 6745 */ 6746 #ifndef SYM_CONF_IOMAPPED 6747 static int sym_regtest (hcb_p np) 6748 { 6749 volatile u32 data; 6750 /* 6751 * chip registers may NOT be cached. 6752 * write 0xffffffff to a read only register area, 6753 * and try to read it back. 6754 */ 6755 data = 0xffffffff; 6756 OUTL_OFF(offsetof(struct sym_reg, nc_dstat), data); 6757 data = INL_OFF(offsetof(struct sym_reg, nc_dstat)); 6758 #if 1 6759 if (data == 0xffffffff) { 6760 #else 6761 if ((data & 0xe2f0fffd) != 0x02000080) { 6762 #endif 6763 kprintf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n", 6764 (unsigned) data); 6765 return (0x10); 6766 } 6767 return (0); 6768 } 6769 #endif 6770 6771 static int sym_snooptest (hcb_p np) 6772 { 6773 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat; 6774 int i, err=0; 6775 #ifndef SYM_CONF_IOMAPPED 6776 err |= sym_regtest (np); 6777 if (err) return (err); 6778 #endif 6779 restart_test: 6780 /* 6781 * Enable Master Parity Checking as we intend 6782 * to enable it for normal operations. 6783 */ 6784 OUTB (nc_ctest4, (np->rv_ctest4 & MPEE)); 6785 /* 6786 * init 6787 */ 6788 pc = SCRIPTB0_BA (np, snooptest); 6789 host_wr = 1; 6790 sym_wr = 2; 6791 /* 6792 * Set memory and register. 6793 */ 6794 np->cache = cpu_to_scr(host_wr); 6795 OUTL (nc_temp, sym_wr); 6796 /* 6797 * Start script (exchange values) 6798 */ 6799 OUTL (nc_dsa, np->hcb_ba); 6800 OUTL_DSP (pc); 6801 /* 6802 * Wait 'til done (with timeout) 6803 */ 6804 for (i=0; i<SYM_SNOOP_TIMEOUT; i++) 6805 if (INB(nc_istat) & (INTF|SIP|DIP)) 6806 break; 6807 if (i>=SYM_SNOOP_TIMEOUT) { 6808 kprintf ("CACHE TEST FAILED: timeout.\n"); 6809 return (0x20); 6810 } 6811 /* 6812 * Check for fatal DMA errors. 6813 */ 6814 dstat = INB (nc_dstat); 6815 #if 1 /* Band aiding for broken hardwares that fail PCI parity */ 6816 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) { 6817 kprintf ("%s: PCI DATA PARITY ERROR DETECTED - " 6818 "DISABLING MASTER DATA PARITY CHECKING.\n", 6819 sym_name(np)); 6820 np->rv_ctest4 &= ~MPEE; 6821 goto restart_test; 6822 } 6823 #endif 6824 if (dstat & (MDPE|BF|IID)) { 6825 kprintf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat); 6826 return (0x80); 6827 } 6828 /* 6829 * Save termination position. 6830 */ 6831 pc = INL (nc_dsp); 6832 /* 6833 * Read memory and register. 6834 */ 6835 host_rd = scr_to_cpu(np->cache); 6836 sym_rd = INL (nc_scratcha); 6837 sym_bk = INL (nc_temp); 6838 6839 /* 6840 * Check termination position. 6841 */ 6842 if (pc != SCRIPTB0_BA (np, snoopend)+8) { 6843 kprintf ("CACHE TEST FAILED: script execution failed.\n"); 6844 kprintf ("start=%08lx, pc=%08lx, end=%08lx\n", 6845 (u_long) SCRIPTB0_BA (np, snooptest), (u_long) pc, 6846 (u_long) SCRIPTB0_BA (np, snoopend) +8); 6847 return (0x40); 6848 } 6849 /* 6850 * Show results. 6851 */ 6852 if (host_wr != sym_rd) { 6853 kprintf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n", 6854 (int) host_wr, (int) sym_rd); 6855 err |= 1; 6856 } 6857 if (host_rd != sym_wr) { 6858 kprintf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n", 6859 (int) sym_wr, (int) host_rd); 6860 err |= 2; 6861 } 6862 if (sym_bk != sym_wr) { 6863 kprintf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n", 6864 (int) sym_wr, (int) sym_bk); 6865 err |= 4; 6866 } 6867 6868 return (err); 6869 } 6870 6871 /* 6872 * Determine the chip's clock frequency. 6873 * 6874 * This is essential for the negotiation of the synchronous 6875 * transfer rate. 6876 * 6877 * Note: we have to return the correct value. 6878 * THERE IS NO SAFE DEFAULT VALUE. 6879 * 6880 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock. 6881 * 53C860 and 53C875 rev. 1 support fast20 transfers but 6882 * do not have a clock doubler and so are provided with a 6883 * 80 MHz clock. All other fast20 boards incorporate a doubler 6884 * and so should be delivered with a 40 MHz clock. 6885 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base 6886 * clock and provide a clock quadrupler (160 Mhz). 6887 */ 6888 6889 /* 6890 * Select SCSI clock frequency 6891 */ 6892 static void sym_selectclock(hcb_p np, u_char scntl3) 6893 { 6894 /* 6895 * If multiplier not present or not selected, leave here. 6896 */ 6897 if (np->multiplier <= 1) { 6898 OUTB(nc_scntl3, scntl3); 6899 return; 6900 } 6901 6902 if (sym_verbose >= 2) 6903 kprintf ("%s: enabling clock multiplier\n", sym_name(np)); 6904 6905 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */ 6906 /* 6907 * Wait for the LCKFRQ bit to be set if supported by the chip. 6908 * Otherwise wait 20 micro-seconds. 6909 */ 6910 if (np->features & FE_LCKFRQ) { 6911 int i = 20; 6912 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0) 6913 UDELAY (20); 6914 if (!i) 6915 kprintf("%s: the chip cannot lock the frequency\n", 6916 sym_name(np)); 6917 } else 6918 UDELAY (20); 6919 OUTB(nc_stest3, HSC); /* Halt the scsi clock */ 6920 OUTB(nc_scntl3, scntl3); 6921 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */ 6922 OUTB(nc_stest3, 0x00); /* Restart scsi clock */ 6923 } 6924 6925 /* 6926 * calculate SCSI clock frequency (in KHz) 6927 */ 6928 static unsigned getfreq (hcb_p np, int gen) 6929 { 6930 unsigned int ms = 0; 6931 unsigned int f; 6932 6933 /* 6934 * Measure GEN timer delay in order 6935 * to calculate SCSI clock frequency 6936 * 6937 * This code will never execute too 6938 * many loop iterations (if DELAY is 6939 * reasonably correct). It could get 6940 * too low a delay (too high a freq.) 6941 * if the CPU is slow executing the 6942 * loop for some reason (an NMI, for 6943 * example). For this reason we will 6944 * if multiple measurements are to be 6945 * performed trust the higher delay 6946 * (lower frequency returned). 6947 */ 6948 OUTW (nc_sien , 0); /* mask all scsi interrupts */ 6949 (void) INW (nc_sist); /* clear pending scsi interrupt */ 6950 OUTB (nc_dien , 0); /* mask all dma interrupts */ 6951 (void) INW (nc_sist); /* another one, just to be sure :) */ 6952 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */ 6953 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6954 OUTB (nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */ 6955 while (!(INW(nc_sist) & GEN) && ms++ < 100000) 6956 UDELAY (1000); /* count ms */ 6957 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6958 /* 6959 * set prescaler to divide by whatever 0 means 6960 * 0 ought to choose divide by 2, but appears 6961 * to set divide by 3.5 mode in my 53c810 ... 6962 */ 6963 OUTB (nc_scntl3, 0); 6964 6965 /* 6966 * adjust for prescaler, and convert into KHz 6967 */ 6968 f = ms ? ((1 << gen) * 4340) / ms : 0; 6969 6970 if (sym_verbose >= 2) 6971 kprintf ("%s: Delay (GEN=%d): %u msec, %u KHz\n", 6972 sym_name(np), gen, ms, f); 6973 6974 return f; 6975 } 6976 6977 static unsigned sym_getfreq (hcb_p np) 6978 { 6979 u_int f1, f2; 6980 int gen = 11; 6981 6982 (void) getfreq (np, gen); /* throw away first result */ 6983 f1 = getfreq (np, gen); 6984 f2 = getfreq (np, gen); 6985 if (f1 > f2) f1 = f2; /* trust lower result */ 6986 return f1; 6987 } 6988 6989 /* 6990 * Get/probe chip SCSI clock frequency 6991 */ 6992 static void sym_getclock (hcb_p np, int mult) 6993 { 6994 unsigned char scntl3 = np->sv_scntl3; 6995 unsigned char stest1 = np->sv_stest1; 6996 unsigned f1; 6997 6998 /* 6999 * For the C10 core, assume 40 MHz. 7000 */ 7001 if (np->features & FE_C10) { 7002 np->multiplier = mult; 7003 np->clock_khz = 40000 * mult; 7004 return; 7005 } 7006 7007 np->multiplier = 1; 7008 f1 = 40000; 7009 /* 7010 * True with 875/895/896/895A with clock multiplier selected 7011 */ 7012 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) { 7013 if (sym_verbose >= 2) 7014 kprintf ("%s: clock multiplier found\n", sym_name(np)); 7015 np->multiplier = mult; 7016 } 7017 7018 /* 7019 * If multiplier not found or scntl3 not 7,5,3, 7020 * reset chip and get frequency from general purpose timer. 7021 * Otherwise trust scntl3 BIOS setting. 7022 */ 7023 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) { 7024 OUTB (nc_stest1, 0); /* make sure doubler is OFF */ 7025 f1 = sym_getfreq (np); 7026 7027 if (sym_verbose) 7028 kprintf ("%s: chip clock is %uKHz\n", sym_name(np), f1); 7029 7030 if (f1 < 45000) f1 = 40000; 7031 else if (f1 < 55000) f1 = 50000; 7032 else f1 = 80000; 7033 7034 if (f1 < 80000 && mult > 1) { 7035 if (sym_verbose >= 2) 7036 kprintf ("%s: clock multiplier assumed\n", 7037 sym_name(np)); 7038 np->multiplier = mult; 7039 } 7040 } else { 7041 if ((scntl3 & 7) == 3) f1 = 40000; 7042 else if ((scntl3 & 7) == 5) f1 = 80000; 7043 else f1 = 160000; 7044 7045 f1 /= np->multiplier; 7046 } 7047 7048 /* 7049 * Compute controller synchronous parameters. 7050 */ 7051 f1 *= np->multiplier; 7052 np->clock_khz = f1; 7053 } 7054 7055 /* 7056 * Get/probe PCI clock frequency 7057 */ 7058 static int sym_getpciclock (hcb_p np) 7059 { 7060 int f = 0; 7061 7062 /* 7063 * For the C1010-33, this doesn't work. 7064 * For the C1010-66, this will be tested when I'll have 7065 * such a beast to play with. 7066 */ 7067 if (!(np->features & FE_C10)) { 7068 OUTB (nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */ 7069 f = (int) sym_getfreq (np); 7070 OUTB (nc_stest1, 0); 7071 } 7072 np->pciclk_khz = f; 7073 7074 return f; 7075 } 7076 7077 /*============= DRIVER ACTION/COMPLETION ====================*/ 7078 7079 /* 7080 * Print something that tells about extended errors. 7081 */ 7082 static void sym_print_xerr(ccb_p cp, int x_status) 7083 { 7084 if (x_status & XE_PARITY_ERR) { 7085 PRINT_ADDR(cp); 7086 kprintf ("unrecovered SCSI parity error.\n"); 7087 } 7088 if (x_status & XE_EXTRA_DATA) { 7089 PRINT_ADDR(cp); 7090 kprintf ("extraneous data discarded.\n"); 7091 } 7092 if (x_status & XE_BAD_PHASE) { 7093 PRINT_ADDR(cp); 7094 kprintf ("illegal scsi phase (4/5).\n"); 7095 } 7096 if (x_status & XE_SODL_UNRUN) { 7097 PRINT_ADDR(cp); 7098 kprintf ("ODD transfer in DATA OUT phase.\n"); 7099 } 7100 if (x_status & XE_SWIDE_OVRUN) { 7101 PRINT_ADDR(cp); 7102 kprintf ("ODD transfer in DATA IN phase.\n"); 7103 } 7104 } 7105 7106 /* 7107 * Choose the more appropriate CAM status if 7108 * the IO encountered an extended error. 7109 */ 7110 static int sym_xerr_cam_status(int cam_status, int x_status) 7111 { 7112 if (x_status) { 7113 if (x_status & XE_PARITY_ERR) 7114 cam_status = CAM_UNCOR_PARITY; 7115 else if (x_status &(XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) 7116 cam_status = CAM_DATA_RUN_ERR; 7117 else if (x_status & XE_BAD_PHASE) 7118 cam_status = CAM_REQ_CMP_ERR; 7119 else 7120 cam_status = CAM_REQ_CMP_ERR; 7121 } 7122 return cam_status; 7123 } 7124 7125 /* 7126 * Complete execution of a SCSI command with extented 7127 * error, SCSI status error, or having been auto-sensed. 7128 * 7129 * The SCRIPTS processor is not running there, so we 7130 * can safely access IO registers and remove JOBs from 7131 * the START queue. 7132 * SCRATCHA is assumed to have been loaded with STARTPOS 7133 * before the SCRIPTS called the C code. 7134 */ 7135 static void sym_complete_error (hcb_p np, ccb_p cp) 7136 { 7137 struct ccb_scsiio *csio; 7138 u_int cam_status; 7139 int i, sense_returned; 7140 7141 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7142 7143 /* 7144 * Paranoid check. :) 7145 */ 7146 if (!cp || !cp->cam_ccb) 7147 return; 7148 7149 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) { 7150 kprintf ("CCB=%lx STAT=%x/%x/%x DEV=%d/%d\n", (unsigned long)cp, 7151 cp->host_status, cp->ssss_status, cp->host_flags, 7152 cp->target, cp->lun); 7153 MDELAY(100); 7154 } 7155 7156 /* 7157 * Get CAM command pointer. 7158 */ 7159 csio = &cp->cam_ccb->csio; 7160 7161 /* 7162 * Check for extended errors. 7163 */ 7164 if (cp->xerr_status) { 7165 if (sym_verbose) 7166 sym_print_xerr(cp, cp->xerr_status); 7167 if (cp->host_status == HS_COMPLETE) 7168 cp->host_status = HS_COMP_ERR; 7169 } 7170 7171 /* 7172 * Calculate the residual. 7173 */ 7174 csio->sense_resid = 0; 7175 csio->resid = sym_compute_residual(np, cp); 7176 7177 if (!SYM_CONF_RESIDUAL_SUPPORT) {/* If user does not want residuals */ 7178 csio->resid = 0; /* throw them away. :) */ 7179 cp->sv_resid = 0; 7180 } 7181 7182 if (cp->host_flags & HF_SENSE) { /* Auto sense */ 7183 csio->scsi_status = cp->sv_scsi_status; /* Restore status */ 7184 csio->sense_resid = csio->resid; /* Swap residuals */ 7185 csio->resid = cp->sv_resid; 7186 cp->sv_resid = 0; 7187 if (sym_verbose && cp->sv_xerr_status) 7188 sym_print_xerr(cp, cp->sv_xerr_status); 7189 if (cp->host_status == HS_COMPLETE && 7190 cp->ssss_status == S_GOOD && 7191 cp->xerr_status == 0) { 7192 cam_status = sym_xerr_cam_status(CAM_SCSI_STATUS_ERROR, 7193 cp->sv_xerr_status); 7194 cam_status |= CAM_AUTOSNS_VALID; 7195 /* 7196 * Bounce back the sense data to user and 7197 * fix the residual. 7198 */ 7199 bzero(&csio->sense_data, sizeof(csio->sense_data)); 7200 sense_returned = SYM_SNS_BBUF_LEN - csio->sense_resid; 7201 if (sense_returned < csio->sense_len) 7202 csio->sense_resid = csio->sense_len - 7203 sense_returned; 7204 else 7205 csio->sense_resid = 0; 7206 bcopy(cp->sns_bbuf, &csio->sense_data, 7207 MIN(csio->sense_len, sense_returned)); 7208 #if 0 7209 /* 7210 * If the device reports a UNIT ATTENTION condition 7211 * due to a RESET condition, we should consider all 7212 * disconnect CCBs for this unit as aborted. 7213 */ 7214 if (1) { 7215 u_char *p; 7216 p = (u_char *) csio->sense_data; 7217 if (p[0]==0x70 && p[2]==0x6 && p[12]==0x29) 7218 sym_clear_tasks(np, CAM_REQ_ABORTED, 7219 cp->target,cp->lun, -1); 7220 } 7221 #endif 7222 } 7223 else 7224 cam_status = CAM_AUTOSENSE_FAIL; 7225 } 7226 else if (cp->host_status == HS_COMPLETE) { /* Bad SCSI status */ 7227 csio->scsi_status = cp->ssss_status; 7228 cam_status = CAM_SCSI_STATUS_ERROR; 7229 } 7230 else if (cp->host_status == HS_SEL_TIMEOUT) /* Selection timeout */ 7231 cam_status = CAM_SEL_TIMEOUT; 7232 else if (cp->host_status == HS_UNEXPECTED) /* Unexpected BUS FREE*/ 7233 cam_status = CAM_UNEXP_BUSFREE; 7234 else { /* Extended error */ 7235 if (sym_verbose) { 7236 PRINT_ADDR(cp); 7237 kprintf ("COMMAND FAILED (%x %x %x).\n", 7238 cp->host_status, cp->ssss_status, 7239 cp->xerr_status); 7240 } 7241 csio->scsi_status = cp->ssss_status; 7242 /* 7243 * Set the most appropriate value for CAM status. 7244 */ 7245 cam_status = sym_xerr_cam_status(CAM_REQ_CMP_ERR, 7246 cp->xerr_status); 7247 } 7248 7249 /* 7250 * Dequeue all queued CCBs for that device 7251 * not yet started by SCRIPTS. 7252 */ 7253 i = (INL (nc_scratcha) - np->squeue_ba) / 4; 7254 (void) sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 7255 7256 /* 7257 * Restart the SCRIPTS processor. 7258 */ 7259 OUTL_DSP (SCRIPTA_BA (np, start)); 7260 7261 /* 7262 * Synchronize DMA map if needed. 7263 */ 7264 if (cp->dmamapped) { 7265 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7266 (cp->dmamapped == SYM_DMA_READ ? 7267 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7268 } 7269 /* 7270 * Add this one to the COMP queue. 7271 * Complete all those commands with either error 7272 * or requeue condition. 7273 */ 7274 sym_set_cam_status((union ccb *) csio, cam_status); 7275 sym_remque(&cp->link_ccbq); 7276 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq); 7277 sym_flush_comp_queue(np, 0); 7278 } 7279 7280 /* 7281 * Complete execution of a successful SCSI command. 7282 * 7283 * Only successful commands go to the DONE queue, 7284 * since we need to have the SCRIPTS processor 7285 * stopped on any error condition. 7286 * The SCRIPTS processor is running while we are 7287 * completing successful commands. 7288 */ 7289 static void sym_complete_ok (hcb_p np, ccb_p cp) 7290 { 7291 struct ccb_scsiio *csio; 7292 tcb_p tp; 7293 lcb_p lp; 7294 7295 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7296 7297 /* 7298 * Paranoid check. :) 7299 */ 7300 if (!cp || !cp->cam_ccb) 7301 return; 7302 assert (cp->host_status == HS_COMPLETE); 7303 7304 /* 7305 * Get command, target and lun pointers. 7306 */ 7307 csio = &cp->cam_ccb->csio; 7308 tp = &np->target[cp->target]; 7309 lp = sym_lp(np, tp, cp->lun); 7310 7311 /* 7312 * Assume device discovered on first success. 7313 */ 7314 if (!lp) 7315 sym_set_bit(tp->lun_map, cp->lun); 7316 7317 /* 7318 * If all data have been transferred, given than no 7319 * extended error did occur, there is no residual. 7320 */ 7321 csio->resid = 0; 7322 if (cp->phys.head.lastp != cp->phys.head.goalp) 7323 csio->resid = sym_compute_residual(np, cp); 7324 7325 /* 7326 * Wrong transfer residuals may be worse than just always 7327 * returning zero. User can disable this feature from 7328 * sym_conf.h. Residual support is enabled by default. 7329 */ 7330 if (!SYM_CONF_RESIDUAL_SUPPORT) 7331 csio->resid = 0; 7332 7333 /* 7334 * Synchronize DMA map if needed. 7335 */ 7336 if (cp->dmamapped) { 7337 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7338 (cp->dmamapped == SYM_DMA_READ ? 7339 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 7340 } 7341 /* 7342 * Set status and complete the command. 7343 */ 7344 csio->scsi_status = cp->ssss_status; 7345 sym_set_cam_status((union ccb *) csio, CAM_REQ_CMP); 7346 sym_xpt_done(np, (union ccb *) csio, cp); 7347 sym_free_ccb(np, cp); 7348 } 7349 7350 /* 7351 * Our callout handler 7352 */ 7353 static void sym_callout(void *arg) 7354 { 7355 union ccb *ccb = (union ccb *) arg; 7356 hcb_p np = ccb->ccb_h.sym_hcb_ptr; 7357 7358 /* 7359 * Check that the CAM CCB is still queued. 7360 */ 7361 if (!np) 7362 return; 7363 7364 SYM_LOCK(); 7365 7366 switch(ccb->ccb_h.func_code) { 7367 case XPT_SCSI_IO: 7368 (void) sym_abort_scsiio(np, ccb, 1); 7369 break; 7370 default: 7371 break; 7372 } 7373 7374 SYM_UNLOCK(); 7375 } 7376 7377 /* 7378 * Abort an SCSI IO. 7379 */ 7380 static int sym_abort_scsiio(hcb_p np, union ccb *ccb, int timed_out) 7381 { 7382 ccb_p cp; 7383 SYM_QUEHEAD *qp; 7384 7385 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7386 7387 /* 7388 * Look up our CCB control block. 7389 */ 7390 cp = NULL; 7391 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 7392 ccb_p cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq); 7393 if (cp2->cam_ccb == ccb) { 7394 cp = cp2; 7395 break; 7396 } 7397 } 7398 if (!cp || cp->host_status == HS_WAIT) 7399 return -1; 7400 7401 /* 7402 * If a previous abort didn't succeed in time, 7403 * perform a BUS reset. 7404 */ 7405 if (cp->to_abort) { 7406 sym_reset_scsi_bus(np, 1); 7407 return 0; 7408 } 7409 7410 /* 7411 * Mark the CCB for abort and allow time for. 7412 */ 7413 cp->to_abort = timed_out ? 2 : 1; 7414 callout_reset(&cp->ch, 10 * hz, sym_callout, (caddr_t) ccb); 7415 7416 /* 7417 * Tell the SCRIPTS processor to stop and synchronize with us. 7418 */ 7419 np->istat_sem = SEM; 7420 OUTB (nc_istat, SIGP|SEM); 7421 return 0; 7422 } 7423 7424 /* 7425 * Reset a SCSI device (all LUNs of a target). 7426 */ 7427 static void sym_reset_dev(hcb_p np, union ccb *ccb) 7428 { 7429 tcb_p tp; 7430 struct ccb_hdr *ccb_h = &ccb->ccb_h; 7431 7432 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7433 7434 if (ccb_h->target_id == np->myaddr || 7435 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7436 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7437 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7438 return; 7439 } 7440 7441 tp = &np->target[ccb_h->target_id]; 7442 7443 tp->to_reset = 1; 7444 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 7445 7446 np->istat_sem = SEM; 7447 OUTB (nc_istat, SIGP|SEM); 7448 } 7449 7450 /* 7451 * SIM action entry point. 7452 */ 7453 static void sym_action(struct cam_sim *sim, union ccb *ccb) 7454 { 7455 hcb_p np; 7456 tcb_p tp; 7457 lcb_p lp; 7458 ccb_p cp; 7459 int tmp; 7460 u_char idmsg, *msgptr; 7461 u_int msglen; 7462 struct ccb_scsiio *csio; 7463 struct ccb_hdr *ccb_h; 7464 7465 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("sym_action\n")); 7466 7467 /* 7468 * Retrieve our controller data structure. 7469 */ 7470 np = (hcb_p) cam_sim_softc(sim); 7471 7472 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7473 7474 /* 7475 * The common case is SCSI IO. 7476 * We deal with other ones elsewhere. 7477 */ 7478 if (ccb->ccb_h.func_code != XPT_SCSI_IO) { 7479 sym_action2(sim, ccb); 7480 return; 7481 } 7482 csio = &ccb->csio; 7483 ccb_h = &csio->ccb_h; 7484 7485 /* 7486 * Work around races. 7487 */ 7488 if ((ccb_h->status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 7489 xpt_done(ccb); 7490 return; 7491 } 7492 7493 /* 7494 * Minimal checkings, so that we will not 7495 * go outside our tables. 7496 */ 7497 if (ccb_h->target_id == np->myaddr || 7498 ccb_h->target_id >= SYM_CONF_MAX_TARGET || 7499 ccb_h->target_lun >= SYM_CONF_MAX_LUN) { 7500 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7501 return; 7502 } 7503 7504 /* 7505 * Retrieve the target and lun descriptors. 7506 */ 7507 tp = &np->target[ccb_h->target_id]; 7508 lp = sym_lp(np, tp, ccb_h->target_lun); 7509 7510 /* 7511 * Complete the 1st INQUIRY command with error 7512 * condition if the device is flagged NOSCAN 7513 * at BOOT in the NVRAM. This may speed up 7514 * the boot and maintain coherency with BIOS 7515 * device numbering. Clearing the flag allows 7516 * user to rescan skipped devices later. 7517 * We also return error for devices not flagged 7518 * for SCAN LUNS in the NVRAM since some mono-lun 7519 * devices behave badly when asked for some non 7520 * zero LUN. Btw, this is an absolute hack.:-) 7521 */ 7522 if (!(ccb_h->flags & CAM_CDB_PHYS) && 7523 (0x12 == ((ccb_h->flags & CAM_CDB_POINTER) ? 7524 csio->cdb_io.cdb_ptr[0] : csio->cdb_io.cdb_bytes[0]))) { 7525 if ((tp->usrflags & SYM_SCAN_BOOT_DISABLED) || 7526 ((tp->usrflags & SYM_SCAN_LUNS_DISABLED) && 7527 ccb_h->target_lun != 0)) { 7528 tp->usrflags &= ~SYM_SCAN_BOOT_DISABLED; 7529 sym_xpt_done2(np, ccb, CAM_DEV_NOT_THERE); 7530 return; 7531 } 7532 } 7533 7534 /* 7535 * Get a control block for this IO. 7536 */ 7537 tmp = ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0); 7538 cp = sym_get_ccb(np, ccb_h->target_id, ccb_h->target_lun, tmp); 7539 if (!cp) { 7540 sym_xpt_done2(np, ccb, CAM_RESRC_UNAVAIL); 7541 return; 7542 } 7543 7544 /* 7545 * Keep track of the IO in our CCB. 7546 */ 7547 cp->cam_ccb = ccb; 7548 7549 /* 7550 * Build the IDENTIFY message. 7551 */ 7552 idmsg = M_IDENTIFY | cp->lun; 7553 if (cp->tag != NO_TAG || (lp && (lp->current_flags & SYM_DISC_ENABLED))) 7554 idmsg |= 0x40; 7555 7556 msgptr = cp->scsi_smsg; 7557 msglen = 0; 7558 msgptr[msglen++] = idmsg; 7559 7560 /* 7561 * Build the tag message if present. 7562 */ 7563 if (cp->tag != NO_TAG) { 7564 u_char order = csio->tag_action; 7565 7566 switch(order) { 7567 case M_ORDERED_TAG: 7568 break; 7569 case M_HEAD_TAG: 7570 break; 7571 default: 7572 order = M_SIMPLE_TAG; 7573 } 7574 msgptr[msglen++] = order; 7575 7576 /* 7577 * For less than 128 tags, actual tags are numbered 7578 * 1,3,5,..2*MAXTAGS+1,since we may have to deal 7579 * with devices that have problems with #TAG 0 or too 7580 * great #TAG numbers. For more tags (up to 256), 7581 * we use directly our tag number. 7582 */ 7583 #if SYM_CONF_MAX_TASK > (512/4) 7584 msgptr[msglen++] = cp->tag; 7585 #else 7586 msgptr[msglen++] = (cp->tag << 1) + 1; 7587 #endif 7588 } 7589 7590 /* 7591 * Build a negotiation message if needed. 7592 * (nego_status is filled by sym_prepare_nego()) 7593 */ 7594 cp->nego_status = 0; 7595 if (tp->tinfo.current.width != tp->tinfo.goal.width || 7596 tp->tinfo.current.period != tp->tinfo.goal.period || 7597 tp->tinfo.current.offset != tp->tinfo.goal.offset || 7598 tp->tinfo.current.options != tp->tinfo.goal.options) { 7599 if (!tp->nego_cp && lp) 7600 msglen += sym_prepare_nego(np, cp, 0, msgptr + msglen); 7601 } 7602 7603 /* 7604 * Fill in our ccb 7605 */ 7606 7607 /* 7608 * Startqueue 7609 */ 7610 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA (np, select)); 7611 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA (np, resel_dsa)); 7612 7613 /* 7614 * select 7615 */ 7616 cp->phys.select.sel_id = cp->target; 7617 cp->phys.select.sel_scntl3 = tp->head.wval; 7618 cp->phys.select.sel_sxfer = tp->head.sval; 7619 cp->phys.select.sel_scntl4 = tp->head.uval; 7620 7621 /* 7622 * message 7623 */ 7624 cp->phys.smsg.addr = cpu_to_scr(CCB_BA (cp, scsi_smsg)); 7625 cp->phys.smsg.size = cpu_to_scr(msglen); 7626 7627 /* 7628 * command 7629 */ 7630 if (sym_setup_cdb(np, csio, cp) < 0) { 7631 sym_xpt_done(np, ccb, cp); 7632 sym_free_ccb(np, cp); 7633 return; 7634 } 7635 7636 /* 7637 * status 7638 */ 7639 #if 0 /* Provision */ 7640 cp->actualquirks = tp->quirks; 7641 #endif 7642 cp->actualquirks = SYM_QUIRK_AUTOSAVE; 7643 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 7644 cp->ssss_status = S_ILLEGAL; 7645 cp->xerr_status = 0; 7646 cp->host_flags = 0; 7647 cp->extra_bytes = 0; 7648 7649 /* 7650 * extreme data pointer. 7651 * shall be positive, so -1 is lower than lowest.:) 7652 */ 7653 cp->ext_sg = -1; 7654 cp->ext_ofs = 0; 7655 7656 /* 7657 * Build the data descriptor block 7658 * and start the IO. 7659 */ 7660 sym_setup_data_and_start(np, csio, cp); 7661 } 7662 7663 /* 7664 * Setup buffers and pointers that address the CDB. 7665 * I bet, physical CDBs will never be used on the planet, 7666 * since they can be bounced without significant overhead. 7667 */ 7668 static int sym_setup_cdb(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 7669 { 7670 struct ccb_hdr *ccb_h; 7671 u32 cmd_ba; 7672 int cmd_len; 7673 7674 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7675 7676 ccb_h = &csio->ccb_h; 7677 7678 /* 7679 * CDB is 16 bytes max. 7680 */ 7681 if (csio->cdb_len > sizeof(cp->cdb_buf)) { 7682 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7683 return -1; 7684 } 7685 cmd_len = csio->cdb_len; 7686 7687 if (ccb_h->flags & CAM_CDB_POINTER) { 7688 /* CDB is a pointer */ 7689 if (!(ccb_h->flags & CAM_CDB_PHYS)) { 7690 /* CDB pointer is virtual */ 7691 bcopy(csio->cdb_io.cdb_ptr, cp->cdb_buf, cmd_len); 7692 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7693 } else { 7694 /* CDB pointer is physical */ 7695 #if 0 7696 cmd_ba = ((u32)csio->cdb_io.cdb_ptr) & 0xffffffff; 7697 #else 7698 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7699 return -1; 7700 #endif 7701 } 7702 } else { 7703 /* CDB is in the CAM ccb (buffer) */ 7704 bcopy(csio->cdb_io.cdb_bytes, cp->cdb_buf, cmd_len); 7705 cmd_ba = CCB_BA (cp, cdb_buf[0]); 7706 } 7707 7708 cp->phys.cmd.addr = cpu_to_scr(cmd_ba); 7709 cp->phys.cmd.size = cpu_to_scr(cmd_len); 7710 7711 return 0; 7712 } 7713 7714 /* 7715 * Set up data pointers used by SCRIPTS. 7716 */ 7717 static __inline void 7718 sym_setup_data_pointers(hcb_p np, ccb_p cp, int dir) 7719 { 7720 u32 lastp, goalp; 7721 7722 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7723 7724 /* 7725 * No segments means no data. 7726 */ 7727 if (!cp->segments) 7728 dir = CAM_DIR_NONE; 7729 7730 /* 7731 * Set the data pointer. 7732 */ 7733 switch(dir) { 7734 case CAM_DIR_OUT: 7735 goalp = SCRIPTA_BA (np, data_out2) + 8; 7736 lastp = goalp - 8 - (cp->segments * (2*4)); 7737 break; 7738 case CAM_DIR_IN: 7739 cp->host_flags |= HF_DATA_IN; 7740 goalp = SCRIPTA_BA (np, data_in2) + 8; 7741 lastp = goalp - 8 - (cp->segments * (2*4)); 7742 break; 7743 case CAM_DIR_NONE: 7744 default: 7745 lastp = goalp = SCRIPTB_BA (np, no_data); 7746 break; 7747 } 7748 7749 cp->phys.head.lastp = cpu_to_scr(lastp); 7750 cp->phys.head.goalp = cpu_to_scr(goalp); 7751 cp->phys.head.savep = cpu_to_scr(lastp); 7752 cp->startp = cp->phys.head.savep; 7753 } 7754 7755 7756 /* 7757 * Call back routine for the DMA map service. 7758 * If bounce buffers are used (why ?), we may sleep and then 7759 * be called there in another context. 7760 */ 7761 static void 7762 sym_execute_ccb(void *arg, bus_dma_segment_t *psegs, int nsegs, int error) 7763 { 7764 ccb_p cp; 7765 hcb_p np; 7766 union ccb *ccb; 7767 7768 cp = (ccb_p) arg; 7769 ccb = cp->cam_ccb; 7770 np = (hcb_p) cp->arg; 7771 7772 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7773 7774 /* 7775 * Deal with weird races. 7776 */ 7777 if (sym_get_cam_status(ccb) != CAM_REQ_INPROG) 7778 goto out_abort; 7779 7780 /* 7781 * Deal with weird errors. 7782 */ 7783 if (error) { 7784 cp->dmamapped = 0; 7785 sym_set_cam_status(cp->cam_ccb, CAM_REQ_ABORTED); 7786 goto out_abort; 7787 } 7788 7789 /* 7790 * Build the data descriptor for the chip. 7791 */ 7792 if (nsegs) { 7793 int retv; 7794 /* 896 rev 1 requires to be careful about boundaries */ 7795 if (np->device_id == PCI_ID_SYM53C896 && np->revision_id <= 1) 7796 retv = sym_scatter_sg_physical(np, cp, psegs, nsegs); 7797 else 7798 retv = sym_fast_scatter_sg_physical(np,cp, psegs,nsegs); 7799 if (retv < 0) { 7800 sym_set_cam_status(cp->cam_ccb, CAM_REQ_TOO_BIG); 7801 goto out_abort; 7802 } 7803 } 7804 7805 /* 7806 * Synchronize the DMA map only if we have 7807 * actually mapped the data. 7808 */ 7809 if (cp->dmamapped) { 7810 bus_dmamap_sync(np->data_dmat, cp->dmamap, 7811 (cp->dmamapped == SYM_DMA_READ ? 7812 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 7813 } 7814 7815 /* 7816 * Set host status to busy state. 7817 * May have been set back to HS_WAIT to avoid a race. 7818 */ 7819 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 7820 7821 /* 7822 * Set data pointers. 7823 */ 7824 sym_setup_data_pointers(np, cp, (ccb->ccb_h.flags & CAM_DIR_MASK)); 7825 7826 /* 7827 * Enqueue this IO in our pending queue. 7828 */ 7829 sym_enqueue_cam_ccb(cp); 7830 7831 /* 7832 * When `#ifed 1', the code below makes the driver 7833 * panic on the first attempt to write to a SCSI device. 7834 * It is the first test we want to do after a driver 7835 * change that does not seem obviously safe. :) 7836 */ 7837 #if 0 7838 switch (cp->cdb_buf[0]) { 7839 case 0x0A: case 0x2A: case 0xAA: 7840 panic("XXXXXXXXXXXXX WRITE NOT YET ALLOWED XXXXXXXXXXXXXX"); 7841 MDELAY(10000); 7842 break; 7843 default: 7844 break; 7845 } 7846 #endif 7847 /* 7848 * Activate this job. 7849 */ 7850 sym_put_start_queue(np, cp); 7851 return; 7852 out_abort: 7853 sym_xpt_done(np, ccb, cp); 7854 sym_free_ccb(np, cp); 7855 } 7856 7857 /* 7858 * How complex it gets to deal with the data in CAM. 7859 * The Bus Dma stuff makes things still more complex. 7860 */ 7861 static void 7862 sym_setup_data_and_start(hcb_p np, struct ccb_scsiio *csio, ccb_p cp) 7863 { 7864 struct ccb_hdr *ccb_h; 7865 int dir, retv; 7866 7867 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7868 7869 ccb_h = &csio->ccb_h; 7870 7871 /* 7872 * Now deal with the data. 7873 */ 7874 cp->data_len = csio->dxfer_len; 7875 cp->arg = np; 7876 7877 /* 7878 * No direction means no data. 7879 */ 7880 dir = (ccb_h->flags & CAM_DIR_MASK); 7881 if (dir == CAM_DIR_NONE) { 7882 sym_execute_ccb(cp, NULL, 0, 0); 7883 return; 7884 } 7885 7886 if (!(ccb_h->flags & CAM_SCATTER_VALID)) { 7887 /* Single buffer */ 7888 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 7889 /* Buffer is virtual */ 7890 cp->dmamapped = (dir == CAM_DIR_IN) ? 7891 SYM_DMA_READ : SYM_DMA_WRITE; 7892 retv = bus_dmamap_load(np->data_dmat, cp->dmamap, 7893 csio->data_ptr, csio->dxfer_len, 7894 sym_execute_ccb, cp, 0); 7895 if (retv == EINPROGRESS) { 7896 cp->host_status = HS_WAIT; 7897 xpt_freeze_simq(np->sim, 1); 7898 csio->ccb_h.status |= CAM_RELEASE_SIMQ; 7899 } 7900 } else { 7901 /* Buffer is physical */ 7902 struct bus_dma_segment seg; 7903 7904 seg.ds_addr = (bus_addr_t) csio->data_ptr; 7905 sym_execute_ccb(cp, &seg, 1, 0); 7906 } 7907 } else { 7908 /* Scatter/gather list */ 7909 struct bus_dma_segment *segs; 7910 7911 if ((ccb_h->flags & CAM_SG_LIST_PHYS) != 0) { 7912 /* The SG list pointer is physical */ 7913 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7914 goto out_abort; 7915 } 7916 7917 if (!(ccb_h->flags & CAM_DATA_PHYS)) { 7918 /* SG buffer pointers are virtual */ 7919 sym_set_cam_status(cp->cam_ccb, CAM_REQ_INVALID); 7920 goto out_abort; 7921 } 7922 7923 /* SG buffer pointers are physical */ 7924 segs = (struct bus_dma_segment *)csio->data_ptr; 7925 sym_execute_ccb(cp, segs, csio->sglist_cnt, 0); 7926 } 7927 return; 7928 out_abort: 7929 sym_xpt_done(np, (union ccb *) csio, cp); 7930 sym_free_ccb(np, cp); 7931 } 7932 7933 /* 7934 * Move the scatter list to our data block. 7935 */ 7936 static int 7937 sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp, 7938 bus_dma_segment_t *psegs, int nsegs) 7939 { 7940 struct sym_tblmove *data; 7941 bus_dma_segment_t *psegs2; 7942 7943 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7944 7945 if (nsegs > SYM_CONF_MAX_SG) 7946 return -1; 7947 7948 data = &cp->phys.data[SYM_CONF_MAX_SG-1]; 7949 psegs2 = &psegs[nsegs-1]; 7950 cp->segments = nsegs; 7951 7952 while (1) { 7953 data->addr = cpu_to_scr(psegs2->ds_addr); 7954 data->size = cpu_to_scr(psegs2->ds_len); 7955 if (DEBUG_FLAGS & DEBUG_SCATTER) { 7956 kprintf ("%s scatter: paddr=%lx len=%ld\n", 7957 sym_name(np), (long) psegs2->ds_addr, 7958 (long) psegs2->ds_len); 7959 } 7960 if (psegs2 != psegs) { 7961 --data; 7962 --psegs2; 7963 continue; 7964 } 7965 break; 7966 } 7967 return 0; 7968 } 7969 7970 7971 /* 7972 * Scatter a SG list with physical addresses into bus addressable chunks. 7973 * We need to ensure 16MB boundaries not to be crossed during DMA of 7974 * each segment, due to some chips being flawed. 7975 */ 7976 #define BOUND_MASK ((1UL<<24)-1) 7977 static int 7978 sym_scatter_sg_physical(hcb_p np, ccb_p cp, bus_dma_segment_t *psegs, int nsegs) 7979 { 7980 u_long ps, pe, pn; 7981 u_long k; 7982 int s, t; 7983 7984 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 7985 7986 s = SYM_CONF_MAX_SG - 1; 7987 t = nsegs - 1; 7988 ps = psegs[t].ds_addr; 7989 pe = ps + psegs[t].ds_len; 7990 7991 while (s >= 0) { 7992 pn = (pe - 1) & ~BOUND_MASK; 7993 if (pn <= ps) 7994 pn = ps; 7995 k = pe - pn; 7996 if (DEBUG_FLAGS & DEBUG_SCATTER) { 7997 kprintf ("%s scatter: paddr=%lx len=%ld\n", 7998 sym_name(np), pn, k); 7999 } 8000 cp->phys.data[s].addr = cpu_to_scr(pn); 8001 cp->phys.data[s].size = cpu_to_scr(k); 8002 --s; 8003 if (pn == ps) { 8004 if (--t < 0) 8005 break; 8006 ps = psegs[t].ds_addr; 8007 pe = ps + psegs[t].ds_len; 8008 } 8009 else 8010 pe = pn; 8011 } 8012 8013 cp->segments = SYM_CONF_MAX_SG - 1 - s; 8014 8015 return t >= 0 ? -1 : 0; 8016 } 8017 #undef BOUND_MASK 8018 8019 /* 8020 * SIM action for non performance critical stuff. 8021 */ 8022 static void sym_action2(struct cam_sim *sim, union ccb *ccb) 8023 { 8024 hcb_p np; 8025 tcb_p tp; 8026 lcb_p lp; 8027 struct ccb_hdr *ccb_h; 8028 8029 /* 8030 * Retrieve our controller data structure. 8031 */ 8032 np = (hcb_p) cam_sim_softc(sim); 8033 8034 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 8035 8036 ccb_h = &ccb->ccb_h; 8037 8038 switch (ccb_h->func_code) { 8039 case XPT_SET_TRAN_SETTINGS: 8040 { 8041 struct ccb_trans_settings *cts; 8042 8043 cts = &ccb->cts; 8044 tp = &np->target[ccb_h->target_id]; 8045 8046 /* 8047 * Update SPI transport settings in TARGET control block. 8048 * Update SCSI device settings in LUN control block. 8049 */ 8050 lp = sym_lp(np, tp, ccb_h->target_lun); 8051 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 8052 sym_update_trans(np, tp, &tp->tinfo.goal, cts); 8053 if (lp) 8054 sym_update_dflags(np, &lp->current_flags, cts); 8055 } 8056 if (cts->type == CTS_TYPE_USER_SETTINGS) { 8057 sym_update_trans(np, tp, &tp->tinfo.user, cts); 8058 if (lp) 8059 sym_update_dflags(np, &lp->user_flags, cts); 8060 } 8061 8062 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8063 break; 8064 } 8065 case XPT_GET_TRAN_SETTINGS: 8066 { 8067 struct ccb_trans_settings *cts; 8068 struct sym_trans *tip; 8069 u_char dflags; 8070 8071 cts = &ccb->cts; 8072 tp = &np->target[ccb_h->target_id]; 8073 lp = sym_lp(np, tp, ccb_h->target_lun); 8074 8075 #define cts__scsi (&cts->proto_specific.scsi) 8076 #define cts__spi (&cts->xport_specific.spi) 8077 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 8078 tip = &tp->tinfo.current; 8079 dflags = lp ? lp->current_flags : 0; 8080 } 8081 else { 8082 tip = &tp->tinfo.user; 8083 dflags = lp ? lp->user_flags : tp->usrflags; 8084 } 8085 8086 cts->protocol = PROTO_SCSI; 8087 cts->transport = XPORT_SPI; 8088 cts->protocol_version = tip->scsi_version; 8089 cts->transport_version = tip->spi_version; 8090 8091 cts__spi->sync_period = tip->period; 8092 cts__spi->sync_offset = tip->offset; 8093 cts__spi->bus_width = tip->width; 8094 cts__spi->ppr_options = tip->options; 8095 8096 cts__spi->valid = CTS_SPI_VALID_SYNC_RATE 8097 | CTS_SPI_VALID_SYNC_OFFSET 8098 | CTS_SPI_VALID_BUS_WIDTH 8099 | CTS_SPI_VALID_PPR_OPTIONS; 8100 8101 cts__spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 8102 if (dflags & SYM_DISC_ENABLED) 8103 cts__spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 8104 cts__spi->valid |= CTS_SPI_VALID_DISC; 8105 8106 cts__scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 8107 if (dflags & SYM_TAGS_ENABLED) 8108 cts__scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 8109 cts__scsi->valid |= CTS_SCSI_VALID_TQ; 8110 #undef cts__spi 8111 #undef cts__scsi 8112 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8113 break; 8114 } 8115 case XPT_CALC_GEOMETRY: 8116 { 8117 cam_calc_geometry(&ccb->ccg, /*extended*/1); 8118 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8119 break; 8120 } 8121 case XPT_PATH_INQ: 8122 { 8123 struct ccb_pathinq *cpi = &ccb->cpi; 8124 cpi->version_num = 1; 8125 cpi->hba_inquiry = PI_MDP_ABLE|PI_SDTR_ABLE|PI_TAG_ABLE; 8126 if ((np->features & FE_WIDE) != 0) 8127 cpi->hba_inquiry |= PI_WIDE_16; 8128 cpi->target_sprt = 0; 8129 cpi->hba_misc = 0; 8130 if (np->usrflags & SYM_SCAN_TARGETS_HILO) 8131 cpi->hba_misc |= PIM_SCANHILO; 8132 if (np->usrflags & SYM_AVOID_BUS_RESET) 8133 cpi->hba_misc |= PIM_NOBUSRESET; 8134 cpi->hba_eng_cnt = 0; 8135 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7; 8136 /* Semantic problem:)LUN number max = max number of LUNs - 1 */ 8137 cpi->max_lun = SYM_CONF_MAX_LUN-1; 8138 if (SYM_SETUP_MAX_LUN < SYM_CONF_MAX_LUN) 8139 cpi->max_lun = SYM_SETUP_MAX_LUN-1; 8140 cpi->bus_id = cam_sim_bus(sim); 8141 cpi->initiator_id = np->myaddr; 8142 cpi->base_transfer_speed = 3300; 8143 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 8144 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN); 8145 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 8146 cpi->unit_number = cam_sim_unit(sim); 8147 8148 cpi->protocol = PROTO_SCSI; 8149 cpi->protocol_version = SCSI_REV_2; 8150 cpi->transport = XPORT_SPI; 8151 cpi->transport_version = 2; 8152 cpi->xport_specific.spi.ppr_options = SID_SPI_CLOCK_ST; 8153 if (np->features & FE_ULTRA3) { 8154 cpi->transport_version = 3; 8155 cpi->xport_specific.spi.ppr_options = 8156 SID_SPI_CLOCK_DT_ST; 8157 } 8158 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8159 break; 8160 } 8161 case XPT_ABORT: 8162 { 8163 union ccb *abort_ccb = ccb->cab.abort_ccb; 8164 switch(abort_ccb->ccb_h.func_code) { 8165 case XPT_SCSI_IO: 8166 if (sym_abort_scsiio(np, abort_ccb, 0) == 0) { 8167 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8168 break; 8169 } 8170 default: 8171 sym_xpt_done2(np, ccb, CAM_UA_ABORT); 8172 break; 8173 } 8174 break; 8175 } 8176 case XPT_RESET_DEV: 8177 { 8178 sym_reset_dev(np, ccb); 8179 break; 8180 } 8181 case XPT_RESET_BUS: 8182 { 8183 sym_reset_scsi_bus(np, 0); 8184 if (sym_verbose) { 8185 xpt_print_path(np->path); 8186 kprintf("SCSI BUS reset delivered.\n"); 8187 } 8188 sym_init (np, 1); 8189 sym_xpt_done2(np, ccb, CAM_REQ_CMP); 8190 break; 8191 } 8192 case XPT_ACCEPT_TARGET_IO: 8193 case XPT_CONT_TARGET_IO: 8194 case XPT_EN_LUN: 8195 case XPT_NOTIFY_ACK: 8196 case XPT_IMMED_NOTIFY: 8197 case XPT_TERM_IO: 8198 default: 8199 sym_xpt_done2(np, ccb, CAM_REQ_INVALID); 8200 break; 8201 } 8202 } 8203 8204 /* 8205 * Asynchronous notification handler. 8206 */ 8207 static void 8208 sym_async(void *cb_arg, u32 code, struct cam_path *path, void *arg) 8209 { 8210 hcb_p np; 8211 struct cam_sim *sim; 8212 u_int tn; 8213 tcb_p tp; 8214 8215 sim = (struct cam_sim *) cb_arg; 8216 np = (hcb_p) cam_sim_softc(sim); 8217 8218 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 8219 8220 switch (code) { 8221 case AC_LOST_DEVICE: 8222 tn = xpt_path_target_id(path); 8223 if (tn >= SYM_CONF_MAX_TARGET) 8224 break; 8225 8226 tp = &np->target[tn]; 8227 8228 tp->to_reset = 0; 8229 tp->head.sval = 0; 8230 tp->head.wval = np->rv_scntl3; 8231 tp->head.uval = 0; 8232 8233 tp->tinfo.current.period = tp->tinfo.goal.period = 0; 8234 tp->tinfo.current.offset = tp->tinfo.goal.offset = 0; 8235 tp->tinfo.current.width = tp->tinfo.goal.width = BUS_8_BIT; 8236 tp->tinfo.current.options = tp->tinfo.goal.options = 0; 8237 8238 break; 8239 default: 8240 break; 8241 } 8242 } 8243 8244 /* 8245 * Update transfer settings of a target. 8246 */ 8247 static void sym_update_trans(hcb_p np, tcb_p tp, struct sym_trans *tip, 8248 struct ccb_trans_settings *cts) 8249 { 8250 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 8251 8252 /* 8253 * Update the infos. 8254 */ 8255 #define cts__spi (&cts->xport_specific.spi) 8256 if ((cts__spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) 8257 tip->width = cts__spi->bus_width; 8258 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) 8259 tip->offset = cts__spi->sync_offset; 8260 if ((cts__spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) 8261 tip->period = cts__spi->sync_period; 8262 if ((cts__spi->valid & CTS_SPI_VALID_PPR_OPTIONS) != 0) 8263 tip->options = (cts__spi->ppr_options & PPR_OPT_DT); 8264 if (cts->protocol_version != PROTO_VERSION_UNSPECIFIED && 8265 cts->protocol_version != PROTO_VERSION_UNKNOWN) 8266 tip->scsi_version = cts->protocol_version; 8267 if (cts->transport_version != XPORT_VERSION_UNSPECIFIED && 8268 cts->transport_version != XPORT_VERSION_UNKNOWN) 8269 tip->spi_version = cts->transport_version; 8270 #undef cts__spi 8271 /* 8272 * Scale against driver configuration limits. 8273 */ 8274 if (tip->width > SYM_SETUP_MAX_WIDE) tip->width = SYM_SETUP_MAX_WIDE; 8275 if (tip->offset > SYM_SETUP_MAX_OFFS) tip->offset = SYM_SETUP_MAX_OFFS; 8276 if (tip->period < SYM_SETUP_MIN_SYNC) tip->period = SYM_SETUP_MIN_SYNC; 8277 8278 /* 8279 * Scale against actual controller BUS width. 8280 */ 8281 if (tip->width > np->maxwide) 8282 tip->width = np->maxwide; 8283 8284 /* 8285 * Only accept DT if controller supports and SYNC/WIDE asked. 8286 */ 8287 if (!((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) || 8288 !(tip->width == BUS_16_BIT && tip->offset)) { 8289 tip->options &= ~PPR_OPT_DT; 8290 } 8291 8292 /* 8293 * Scale period factor and offset against controller limits. 8294 */ 8295 if (tip->options & PPR_OPT_DT) { 8296 if (tip->period < np->minsync_dt) 8297 tip->period = np->minsync_dt; 8298 if (tip->period > np->maxsync_dt) 8299 tip->period = np->maxsync_dt; 8300 if (tip->offset > np->maxoffs_dt) 8301 tip->offset = np->maxoffs_dt; 8302 } 8303 else { 8304 if (tip->period < np->minsync) 8305 tip->period = np->minsync; 8306 if (tip->period > np->maxsync) 8307 tip->period = np->maxsync; 8308 if (tip->offset > np->maxoffs) 8309 tip->offset = np->maxoffs; 8310 } 8311 } 8312 8313 /* 8314 * Update flags for a device (logical unit). 8315 */ 8316 static void 8317 sym_update_dflags(hcb_p np, u_char *flags, struct ccb_trans_settings *cts) 8318 { 8319 SYM_LOCK_ASSERT(LK_EXCLUSIVE); 8320 8321 #define cts__scsi (&cts->proto_specific.scsi) 8322 #define cts__spi (&cts->xport_specific.spi) 8323 if ((cts__spi->valid & CTS_SPI_VALID_DISC) != 0) { 8324 if ((cts__spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) 8325 *flags |= SYM_DISC_ENABLED; 8326 else 8327 *flags &= ~SYM_DISC_ENABLED; 8328 } 8329 8330 if ((cts__scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 8331 if ((cts__scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) 8332 *flags |= SYM_TAGS_ENABLED; 8333 else 8334 *flags &= ~SYM_TAGS_ENABLED; 8335 } 8336 #undef cts__spi 8337 #undef cts__scsi 8338 } 8339 8340 8341 /*============= DRIVER INITIALISATION ==================*/ 8342 8343 8344 static device_method_t sym_pci_methods[] = { 8345 DEVMETHOD(device_probe, sym_pci_probe), 8346 DEVMETHOD(device_attach, sym_pci_attach), 8347 DEVMETHOD_END 8348 }; 8349 8350 static driver_t sym_pci_driver = { 8351 "sym", 8352 sym_pci_methods, 8353 1 /* no softc */ 8354 }; 8355 8356 static devclass_t sym_devclass; 8357 8358 DRIVER_MODULE(sym, pci, sym_pci_driver, sym_devclass, NULL, NULL); 8359 MODULE_VERSION(sym, 1); 8360 MODULE_DEPEND(sym, cam, 1, 1, 1); 8361 MODULE_DEPEND(sym, pci, 1, 1, 1); 8362 8363 8364 static const struct sym_pci_chip sym_pci_dev_table[] = { 8365 {PCI_ID_SYM53C810, 0x0f, "810", 4, 8, 4, 64, 8366 FE_ERL} 8367 , 8368 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8369 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8370 FE_BOF} 8371 , 8372 #else 8373 {PCI_ID_SYM53C810, 0xff, "810a", 4, 8, 4, 1, 8374 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} 8375 , 8376 #endif 8377 {PCI_ID_SYM53C815, 0xff, "815", 4, 8, 4, 64, 8378 FE_BOF|FE_ERL} 8379 , 8380 {PCI_ID_SYM53C825, 0x0f, "825", 6, 8, 4, 64, 8381 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF} 8382 , 8383 {PCI_ID_SYM53C825, 0xff, "825a", 6, 8, 4, 2, 8384 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} 8385 , 8386 {PCI_ID_SYM53C860, 0xff, "860", 4, 8, 5, 1, 8387 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} 8388 , 8389 {PCI_ID_SYM53C875, 0x01, "875", 6, 16, 5, 2, 8390 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8391 FE_RAM|FE_DIFF} 8392 , 8393 {PCI_ID_SYM53C875, 0xff, "875", 6, 16, 5, 2, 8394 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8395 FE_RAM|FE_DIFF} 8396 , 8397 {PCI_ID_SYM53C875_2, 0xff, "875", 6, 16, 5, 2, 8398 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8399 FE_RAM|FE_DIFF} 8400 , 8401 {PCI_ID_SYM53C885, 0xff, "885", 6, 16, 5, 2, 8402 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8403 FE_RAM|FE_DIFF} 8404 , 8405 #ifdef SYM_DEBUG_GENERIC_SUPPORT 8406 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8407 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS| 8408 FE_RAM|FE_LCKFRQ} 8409 , 8410 #else 8411 {PCI_ID_SYM53C895, 0xff, "895", 6, 31, 7, 2, 8412 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8413 FE_RAM|FE_LCKFRQ} 8414 , 8415 #endif 8416 {PCI_ID_SYM53C896, 0xff, "896", 6, 31, 7, 4, 8417 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8418 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8419 , 8420 {PCI_ID_SYM53C895A, 0xff, "895a", 6, 31, 7, 4, 8421 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8422 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 8423 , 8424 {PCI_ID_LSI53C1010, 0x00, "1010-33", 6, 31, 7, 8, 8425 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8426 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8427 FE_C10} 8428 , 8429 {PCI_ID_LSI53C1010, 0xff, "1010-33", 6, 31, 7, 8, 8430 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8431 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 8432 FE_C10|FE_U3EN} 8433 , 8434 {PCI_ID_LSI53C1010_2, 0xff, "1010-66", 6, 31, 7, 8, 8435 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 8436 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC| 8437 FE_C10|FE_U3EN} 8438 , 8439 {PCI_ID_LSI53C1510D, 0xff, "1510d", 6, 31, 7, 4, 8440 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 8441 FE_RAM|FE_IO256|FE_LEDC} 8442 }; 8443 8444 #define sym_pci_num_devs NELEM(sym_pci_dev_table) 8445 8446 /* 8447 * Look up the chip table. 8448 * 8449 * Return a pointer to the chip entry if found, 8450 * zero otherwise. 8451 */ 8452 static const struct sym_pci_chip * 8453 sym_find_pci_chip(device_t dev) 8454 { 8455 const struct sym_pci_chip *chip; 8456 int i; 8457 u_short device_id; 8458 u_char revision; 8459 8460 if (pci_get_vendor(dev) != PCI_VENDOR_NCR) 8461 return NULL; 8462 8463 device_id = pci_get_device(dev); 8464 revision = pci_get_revid(dev); 8465 8466 for (i = 0; i < sym_pci_num_devs; i++) { 8467 chip = &sym_pci_dev_table[i]; 8468 if (device_id != chip->device_id) 8469 continue; 8470 if (revision > chip->revision_id) 8471 continue; 8472 return chip; 8473 } 8474 8475 return NULL; 8476 } 8477 8478 /* 8479 * Tell upper layer if the chip is supported. 8480 */ 8481 static int 8482 sym_pci_probe(device_t dev) 8483 { 8484 const struct sym_pci_chip *chip; 8485 8486 chip = sym_find_pci_chip(dev); 8487 if (chip && sym_find_firmware(chip)) { 8488 device_set_desc(dev, chip->name); 8489 return (chip->lp_probe_bit & SYM_SETUP_LP_PROBE_MAP)? 8490 BUS_PROBE_LOW_PRIORITY : BUS_PROBE_DEFAULT; 8491 } 8492 return ENXIO; 8493 } 8494 8495 /* 8496 * Attach a sym53c8xx device. 8497 */ 8498 static int 8499 sym_pci_attach(device_t dev) 8500 { 8501 const struct sym_pci_chip *chip; 8502 u_short command; 8503 u_char cachelnsz; 8504 struct sym_hcb *np = NULL; 8505 struct sym_nvram nvram; 8506 const struct sym_fw *fw = NULL; 8507 int i; 8508 bus_dma_tag_t bus_dmat; 8509 8510 #if 0 /* XXX swildner */ 8511 bus_dmat = bus_get_dma_tag(dev); 8512 #else 8513 bus_dmat = NULL; 8514 #endif 8515 8516 /* 8517 * Only probed devices should be attached. 8518 * We just enjoy being paranoid. :) 8519 */ 8520 chip = sym_find_pci_chip(dev); 8521 if (chip == NULL || (fw = sym_find_firmware(chip)) == NULL) 8522 return (ENXIO); 8523 8524 /* 8525 * Allocate immediately the host control block, 8526 * since we are only expecting to succeed. :) 8527 * We keep track in the HCB of all the resources that 8528 * are to be released on error. 8529 */ 8530 np = __sym_calloc_dma(bus_dmat, sizeof(*np), "HCB"); 8531 if (np) 8532 np->bus_dmat = bus_dmat; 8533 else 8534 return (ENXIO); 8535 device_set_softc(dev, np); 8536 8537 SYM_LOCK_INIT(); 8538 8539 /* 8540 * Copy some useful infos to the HCB. 8541 */ 8542 np->hcb_ba = vtobus(np); 8543 np->verbose = bootverbose; 8544 np->device = dev; 8545 np->device_id = pci_get_device(dev); 8546 np->revision_id = pci_get_revid(dev); 8547 np->features = chip->features; 8548 np->clock_divn = chip->nr_divisor; 8549 np->maxoffs = chip->offset_max; 8550 np->maxburst = chip->burst_max; 8551 np->scripta_sz = fw->a_size; 8552 np->scriptb_sz = fw->b_size; 8553 np->fw_setup = fw->setup; 8554 np->fw_patch = fw->patch; 8555 np->fw_name = fw->name; 8556 8557 #ifdef __x86_64__ 8558 np->target = sym_calloc_dma(SYM_CONF_MAX_TARGET * sizeof(*(np->target)), 8559 "TARGET"); 8560 if (!np->target) 8561 goto attach_failed; 8562 #endif 8563 8564 /* 8565 * Initialize the CCB free and busy queues. 8566 */ 8567 sym_que_init(&np->free_ccbq); 8568 sym_que_init(&np->busy_ccbq); 8569 sym_que_init(&np->comp_ccbq); 8570 sym_que_init(&np->cam_ccbq); 8571 8572 /* 8573 * Allocate a tag for the DMA of user data. 8574 */ 8575 if (bus_dma_tag_create(np->bus_dmat, 1, (1<<24), 8576 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 8577 NULL, NULL, 8578 BUS_SPACE_MAXSIZE, SYM_CONF_MAX_SG, 8579 (1<<24), 0, 8580 &np->data_dmat)) { 8581 device_printf(dev, "failed to create DMA tag.\n"); 8582 goto attach_failed; 8583 } 8584 /* 8585 * Read and apply some fix-ups to the PCI COMMAND 8586 * register. We want the chip to be enabled for: 8587 * - BUS mastering 8588 * - PCI parity checking (reporting would also be fine) 8589 * - Write And Invalidate. 8590 */ 8591 command = pci_read_config(dev, PCIR_COMMAND, 2); 8592 command |= PCIM_CMD_BUSMASTEREN; 8593 command |= PCIM_CMD_PERRESPEN; 8594 command |= /* PCIM_CMD_MWIEN */ 0x0010; 8595 pci_write_config(dev, PCIR_COMMAND, command, 2); 8596 8597 /* 8598 * Let the device know about the cache line size, 8599 * if it doesn't yet. 8600 */ 8601 cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 8602 if (!cachelnsz) { 8603 cachelnsz = 8; 8604 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1); 8605 } 8606 8607 /* 8608 * Alloc/get/map/retrieve everything that deals with MMIO. 8609 */ 8610 if ((command & PCIM_CMD_MEMEN) != 0) { 8611 int regs_id = SYM_PCI_MMIO; 8612 np->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 8613 ®s_id, RF_ACTIVE); 8614 } 8615 if (!np->mmio_res) { 8616 device_printf(dev, "failed to allocate MMIO resources\n"); 8617 goto attach_failed; 8618 } 8619 np->mmio_ba = rman_get_start(np->mmio_res); 8620 8621 /* 8622 * Allocate the IRQ. 8623 */ 8624 i = 0; 8625 np->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, 8626 RF_ACTIVE | RF_SHAREABLE); 8627 if (!np->irq_res) { 8628 device_printf(dev, "failed to allocate IRQ resource\n"); 8629 goto attach_failed; 8630 } 8631 8632 #ifdef SYM_CONF_IOMAPPED 8633 /* 8634 * User want us to use normal IO with PCI. 8635 * Alloc/get/map/retrieve everything that deals with IO. 8636 */ 8637 if ((command & PCI_COMMAND_IO_ENABLE) != 0) { 8638 int regs_id = SYM_PCI_IO; 8639 np->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 8640 ®s_id, RF_ACTIVE); 8641 } 8642 if (!np->io_res) { 8643 device_printf(dev, "failed to allocate IO resources\n"); 8644 goto attach_failed; 8645 } 8646 8647 #endif /* SYM_CONF_IOMAPPED */ 8648 8649 /* 8650 * If the chip has RAM. 8651 * Alloc/get/map/retrieve the corresponding resources. 8652 */ 8653 if ((np->features & (FE_RAM|FE_RAM8K)) && 8654 (command & PCIM_CMD_MEMEN) != 0) { 8655 int regs_id = SYM_PCI_RAM; 8656 if (np->features & FE_64BIT) 8657 regs_id = SYM_PCI_RAM64; 8658 np->ram_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 8659 ®s_id, RF_ACTIVE); 8660 if (!np->ram_res) { 8661 device_printf(dev,"failed to allocate RAM resources\n"); 8662 goto attach_failed; 8663 } 8664 np->ram_id = regs_id; 8665 np->ram_ba = rman_get_start(np->ram_res); 8666 } 8667 8668 /* 8669 * Save setting of some IO registers, so we will 8670 * be able to probe specific implementations. 8671 */ 8672 sym_save_initial_setting (np); 8673 8674 /* 8675 * Reset the chip now, since it has been reported 8676 * that SCSI clock calibration may not work properly 8677 * if the chip is currently active. 8678 */ 8679 sym_chip_reset (np); 8680 8681 /* 8682 * Try to read the user set-up. 8683 */ 8684 (void) sym_read_nvram(np, &nvram); 8685 8686 /* 8687 * Prepare controller and devices settings, according 8688 * to chip features, user set-up and driver set-up. 8689 */ 8690 (void) sym_prepare_setting(np, &nvram); 8691 8692 /* 8693 * Check the PCI clock frequency. 8694 * Must be performed after prepare_setting since it destroys 8695 * STEST1 that is used to probe for the clock doubler. 8696 */ 8697 i = sym_getpciclock(np); 8698 if (i > 37000) 8699 device_printf(dev, "PCI BUS clock seems too high: %u KHz.\n",i); 8700 8701 /* 8702 * Allocate the start queue. 8703 */ 8704 np->squeue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE"); 8705 if (!np->squeue) 8706 goto attach_failed; 8707 np->squeue_ba = vtobus(np->squeue); 8708 8709 /* 8710 * Allocate the done queue. 8711 */ 8712 np->dqueue = (u32 *) sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE"); 8713 if (!np->dqueue) 8714 goto attach_failed; 8715 np->dqueue_ba = vtobus(np->dqueue); 8716 8717 /* 8718 * Allocate the target bus address array. 8719 */ 8720 np->targtbl = (u32 *) sym_calloc_dma(256, "TARGTBL"); 8721 if (!np->targtbl) 8722 goto attach_failed; 8723 np->targtbl_ba = vtobus(np->targtbl); 8724 8725 /* 8726 * Allocate SCRIPTS areas. 8727 */ 8728 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0"); 8729 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0"); 8730 if (!np->scripta0 || !np->scriptb0) 8731 goto attach_failed; 8732 8733 /* 8734 * Allocate the CCBs. We need at least ONE. 8735 */ 8736 for (i = 0; sym_alloc_ccb(np) != NULL; i++) 8737 ; 8738 if (i < 1) 8739 goto attach_failed; 8740 8741 /* 8742 * Calculate BUS addresses where we are going 8743 * to load the SCRIPTS. 8744 */ 8745 np->scripta_ba = vtobus(np->scripta0); 8746 np->scriptb_ba = vtobus(np->scriptb0); 8747 np->scriptb0_ba = np->scriptb_ba; 8748 8749 if (np->ram_ba) { 8750 np->scripta_ba = np->ram_ba; 8751 if (np->features & FE_RAM8K) { 8752 np->ram_ws = 8192; 8753 np->scriptb_ba = np->scripta_ba + 4096; 8754 #ifdef __LP64__ 8755 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32); 8756 #endif 8757 } 8758 else 8759 np->ram_ws = 4096; 8760 } 8761 8762 /* 8763 * Copy scripts to controller instance. 8764 */ 8765 bcopy(fw->a_base, np->scripta0, np->scripta_sz); 8766 bcopy(fw->b_base, np->scriptb0, np->scriptb_sz); 8767 8768 /* 8769 * Setup variable parts in scripts and compute 8770 * scripts bus addresses used from the C code. 8771 */ 8772 np->fw_setup(np, fw); 8773 8774 /* 8775 * Bind SCRIPTS with physical addresses usable by the 8776 * SCRIPTS processor (as seen from the BUS = BUS addresses). 8777 */ 8778 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz); 8779 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz); 8780 8781 #ifdef SYM_CONF_IARB_SUPPORT 8782 /* 8783 * If user wants IARB to be set when we win arbitration 8784 * and have other jobs, compute the max number of consecutive 8785 * settings of IARB hints before we leave devices a chance to 8786 * arbitrate for reselection. 8787 */ 8788 #ifdef SYM_SETUP_IARB_MAX 8789 np->iarb_max = SYM_SETUP_IARB_MAX; 8790 #else 8791 np->iarb_max = 4; 8792 #endif 8793 #endif 8794 8795 /* 8796 * Prepare the idle and invalid task actions. 8797 */ 8798 np->idletask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8799 np->idletask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8800 np->idletask_ba = vtobus(&np->idletask); 8801 8802 np->notask.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8803 np->notask.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8804 np->notask_ba = vtobus(&np->notask); 8805 8806 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8807 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA (np, bad_i_t_l)); 8808 np->bad_itl_ba = vtobus(&np->bad_itl); 8809 8810 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA (np, idle)); 8811 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA (np,bad_i_t_l_q)); 8812 np->bad_itlq_ba = vtobus(&np->bad_itlq); 8813 8814 /* 8815 * Allocate and prepare the lun JUMP table that is used 8816 * for a target prior the probing of devices (bad lun table). 8817 * A private table will be allocated for the target on the 8818 * first INQUIRY response received. 8819 */ 8820 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL"); 8821 if (!np->badluntbl) 8822 goto attach_failed; 8823 8824 np->badlun_sa = cpu_to_scr(SCRIPTB_BA (np, resel_bad_lun)); 8825 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */ 8826 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 8827 8828 /* 8829 * Prepare the bus address array that contains the bus 8830 * address of each target control block. 8831 * For now, assume all logical units are wrong. :) 8832 */ 8833 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 8834 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i])); 8835 np->target[i].head.luntbl_sa = 8836 cpu_to_scr(vtobus(np->badluntbl)); 8837 np->target[i].head.lun0_sa = 8838 cpu_to_scr(vtobus(&np->badlun_sa)); 8839 } 8840 8841 /* 8842 * Now check the cache handling of the pci chipset. 8843 */ 8844 if (sym_snooptest (np)) { 8845 device_printf(dev, "CACHE INCORRECTLY CONFIGURED.\n"); 8846 goto attach_failed; 8847 } 8848 8849 /* 8850 * Now deal with CAM. 8851 * Hopefully, we will succeed with that one.:) 8852 */ 8853 if (!sym_cam_attach(np)) 8854 goto attach_failed; 8855 8856 /* 8857 * Sigh! we are done. 8858 */ 8859 return 0; 8860 8861 /* 8862 * We have failed. 8863 * We will try to free all the resources we have 8864 * allocated, but if we are a boot device, this 8865 * will not help that much.;) 8866 */ 8867 attach_failed: 8868 if (np) 8869 sym_pci_free(np); 8870 return ENXIO; 8871 } 8872 8873 /* 8874 * Free everything that have been allocated for this device. 8875 */ 8876 static void sym_pci_free(hcb_p np) 8877 { 8878 SYM_QUEHEAD *qp; 8879 ccb_p cp; 8880 tcb_p tp; 8881 lcb_p lp; 8882 int target, lun; 8883 8884 /* 8885 * First free CAM resources. 8886 */ 8887 sym_cam_free(np); 8888 8889 /* 8890 * Now every should be quiet for us to 8891 * free other resources. 8892 */ 8893 if (np->ram_res) 8894 bus_release_resource(np->device, SYS_RES_MEMORY, 8895 np->ram_id, np->ram_res); 8896 if (np->mmio_res) 8897 bus_release_resource(np->device, SYS_RES_MEMORY, 8898 SYM_PCI_MMIO, np->mmio_res); 8899 if (np->io_res) 8900 bus_release_resource(np->device, SYS_RES_IOPORT, 8901 SYM_PCI_IO, np->io_res); 8902 if (np->irq_res) 8903 bus_release_resource(np->device, SYS_RES_IRQ, 8904 0, np->irq_res); 8905 8906 if (np->scriptb0) 8907 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0"); 8908 if (np->scripta0) 8909 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0"); 8910 if (np->squeue) 8911 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE"); 8912 if (np->dqueue) 8913 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE"); 8914 8915 while ((qp = sym_remque_head(&np->free_ccbq)) != NULL) { 8916 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 8917 bus_dmamap_destroy(np->data_dmat, cp->dmamap); 8918 sym_mfree_dma(cp->sns_bbuf, SYM_SNS_BBUF_LEN, "SNS_BBUF"); 8919 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 8920 } 8921 8922 if (np->badluntbl) 8923 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL"); 8924 8925 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) { 8926 tp = &np->target[target]; 8927 for (lun = 0 ; lun < SYM_CONF_MAX_LUN ; lun++) { 8928 lp = sym_lp(np, tp, lun); 8929 if (!lp) 8930 continue; 8931 if (lp->itlq_tbl) 8932 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, 8933 "ITLQ_TBL"); 8934 if (lp->cb_tags) 8935 sym_mfree(lp->cb_tags, SYM_CONF_MAX_TASK, 8936 "CB_TAGS"); 8937 sym_mfree_dma(lp, sizeof(*lp), "LCB"); 8938 } 8939 #if SYM_CONF_MAX_LUN > 1 8940 if (tp->lunmp) 8941 sym_mfree(tp->lunmp, SYM_CONF_MAX_LUN*sizeof(lcb_p), 8942 "LUNMP"); 8943 #endif 8944 } 8945 #ifdef __x86_64__ 8946 if (np->target) 8947 sym_mfree_dma(np->target, 8948 SYM_CONF_MAX_TARGET * sizeof(*(np->target)), "TARGET"); 8949 #endif 8950 if (np->targtbl) 8951 sym_mfree_dma(np->targtbl, 256, "TARGTBL"); 8952 if (np->data_dmat) 8953 bus_dma_tag_destroy(np->data_dmat); 8954 #if 0 /* XXX swildner */ 8955 if (SYM_LOCK_INITIALIZED() != 0) 8956 #endif 8957 SYM_LOCK_DESTROY(); 8958 device_set_softc(np->device, NULL); 8959 sym_mfree_dma(np, sizeof(*np), "HCB"); 8960 } 8961 8962 /* 8963 * Allocate CAM resources and register a bus to CAM. 8964 */ 8965 static int sym_cam_attach(hcb_p np) 8966 { 8967 struct cam_devq *devq = NULL; 8968 struct cam_sim *sim = NULL; 8969 struct cam_path *path = NULL; 8970 int err; 8971 8972 /* 8973 * Establish our interrupt handler. 8974 */ 8975 err = bus_setup_intr(np->device, np->irq_res, 8976 INTR_MPSAFE, 8977 sym_intr, np, &np->intr, NULL); 8978 if (err) { 8979 device_printf(np->device, "bus_setup_intr() failed: %d\n", 8980 err); 8981 goto fail; 8982 } 8983 8984 /* 8985 * Create the device queue for our sym SIM. 8986 */ 8987 devq = cam_simq_alloc(SYM_CONF_MAX_START); 8988 if (!devq) 8989 goto fail; 8990 8991 /* 8992 * Construct our SIM entry. 8993 */ 8994 sim = cam_sim_alloc(sym_action, sym_poll, "sym", np, 8995 device_get_unit(np->device), 8996 &np->lock, 1, SYM_SETUP_MAX_TAG, devq); 8997 cam_simq_release(devq); 8998 if (!sim) 8999 goto fail; 9000 9001 SYM_LOCK(); 9002 9003 if (xpt_bus_register(sim, 0) != CAM_SUCCESS) 9004 goto fail; 9005 np->sim = sim; 9006 9007 if (xpt_create_path(&path, 0, 9008 cam_sim_path(np->sim), CAM_TARGET_WILDCARD, 9009 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 9010 goto fail; 9011 } 9012 np->path = path; 9013 9014 /* 9015 * Establish our async notification handler. 9016 */ 9017 if (xpt_register_async(AC_LOST_DEVICE, sym_async, sim, path) != 9018 CAM_REQ_CMP) 9019 goto fail; 9020 9021 /* 9022 * Start the chip now, without resetting the BUS, since 9023 * it seems that this must stay under control of CAM. 9024 * With LVD/SE capable chips and BUS in SE mode, we may 9025 * get a spurious SMBC interrupt. 9026 */ 9027 sym_init (np, 0); 9028 9029 SYM_UNLOCK(); 9030 9031 return 1; 9032 fail: 9033 if (sim) 9034 cam_sim_free(sim); 9035 9036 SYM_UNLOCK(); 9037 9038 sym_cam_free(np); 9039 9040 return 0; 9041 } 9042 9043 /* 9044 * Free everything that deals with CAM. 9045 */ 9046 static void sym_cam_free(hcb_p np) 9047 { 9048 SYM_LOCK_ASSERT(0); 9049 9050 if (np->intr) { 9051 bus_teardown_intr(np->device, np->irq_res, np->intr); 9052 np->intr = NULL; 9053 } 9054 9055 SYM_LOCK(); 9056 9057 if (np->sim) { 9058 xpt_bus_deregister(cam_sim_path(np->sim)); 9059 cam_sim_free(np->sim); 9060 np->sim = NULL; 9061 } 9062 if (np->path) { 9063 xpt_free_path(np->path); 9064 np->path = NULL; 9065 } 9066 9067 SYM_UNLOCK(); 9068 } 9069 9070 /*============ OPTIONNAL NVRAM SUPPORT =================*/ 9071 9072 /* 9073 * Get host setup from NVRAM. 9074 */ 9075 static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram) 9076 { 9077 #ifdef SYM_CONF_NVRAM_SUPPORT 9078 /* 9079 * Get parity checking, host ID, verbose mode 9080 * and miscellaneous host flags from NVRAM. 9081 */ 9082 switch(nvram->type) { 9083 case SYM_SYMBIOS_NVRAM: 9084 if (!(nvram->data.Symbios.flags & SYMBIOS_PARITY_ENABLE)) 9085 np->rv_scntl0 &= ~0x0a; 9086 np->myaddr = nvram->data.Symbios.host_id & 0x0f; 9087 if (nvram->data.Symbios.flags & SYMBIOS_VERBOSE_MSGS) 9088 np->verbose += 1; 9089 if (nvram->data.Symbios.flags1 & SYMBIOS_SCAN_HI_LO) 9090 np->usrflags |= SYM_SCAN_TARGETS_HILO; 9091 if (nvram->data.Symbios.flags2 & SYMBIOS_AVOID_BUS_RESET) 9092 np->usrflags |= SYM_AVOID_BUS_RESET; 9093 break; 9094 case SYM_TEKRAM_NVRAM: 9095 np->myaddr = nvram->data.Tekram.host_id & 0x0f; 9096 break; 9097 default: 9098 break; 9099 } 9100 #endif 9101 } 9102 9103 /* 9104 * Get target setup from NVRAM. 9105 */ 9106 #ifdef SYM_CONF_NVRAM_SUPPORT 9107 static void sym_Symbios_setup_target(hcb_p np,int target, Symbios_nvram *nvram); 9108 static void sym_Tekram_setup_target(hcb_p np,int target, Tekram_nvram *nvram); 9109 #endif 9110 9111 static void 9112 sym_nvram_setup_target (hcb_p np, int target, struct sym_nvram *nvp) 9113 { 9114 #ifdef SYM_CONF_NVRAM_SUPPORT 9115 switch(nvp->type) { 9116 case SYM_SYMBIOS_NVRAM: 9117 sym_Symbios_setup_target (np, target, &nvp->data.Symbios); 9118 break; 9119 case SYM_TEKRAM_NVRAM: 9120 sym_Tekram_setup_target (np, target, &nvp->data.Tekram); 9121 break; 9122 default: 9123 break; 9124 } 9125 #endif 9126 } 9127 9128 #ifdef SYM_CONF_NVRAM_SUPPORT 9129 /* 9130 * Get target set-up from Symbios format NVRAM. 9131 */ 9132 static void 9133 sym_Symbios_setup_target(hcb_p np, int target, Symbios_nvram *nvram) 9134 { 9135 tcb_p tp = &np->target[target]; 9136 Symbios_target *tn = &nvram->target[target]; 9137 9138 tp->tinfo.user.period = tn->sync_period ? (tn->sync_period + 3) / 4 : 0; 9139 tp->tinfo.user.width = tn->bus_width == 0x10 ? BUS_16_BIT : BUS_8_BIT; 9140 tp->usrtags = 9141 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? SYM_SETUP_MAX_TAG : 0; 9142 9143 if (!(tn->flags & SYMBIOS_DISCONNECT_ENABLE)) 9144 tp->usrflags &= ~SYM_DISC_ENABLED; 9145 if (!(tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME)) 9146 tp->usrflags |= SYM_SCAN_BOOT_DISABLED; 9147 if (!(tn->flags & SYMBIOS_SCAN_LUNS)) 9148 tp->usrflags |= SYM_SCAN_LUNS_DISABLED; 9149 } 9150 9151 /* 9152 * Get target set-up from Tekram format NVRAM. 9153 */ 9154 static void 9155 sym_Tekram_setup_target(hcb_p np, int target, Tekram_nvram *nvram) 9156 { 9157 tcb_p tp = &np->target[target]; 9158 struct Tekram_target *tn = &nvram->target[target]; 9159 int i; 9160 9161 if (tn->flags & TEKRAM_SYNC_NEGO) { 9162 i = tn->sync_index & 0xf; 9163 tp->tinfo.user.period = Tekram_sync[i]; 9164 } 9165 9166 tp->tinfo.user.width = 9167 (tn->flags & TEKRAM_WIDE_NEGO) ? BUS_16_BIT : BUS_8_BIT; 9168 9169 if (tn->flags & TEKRAM_TAGGED_COMMANDS) { 9170 tp->usrtags = 2 << nvram->max_tags_index; 9171 } 9172 9173 if (tn->flags & TEKRAM_DISCONNECT_ENABLE) 9174 tp->usrflags |= SYM_DISC_ENABLED; 9175 9176 /* If any device does not support parity, we will not use this option */ 9177 if (!(tn->flags & TEKRAM_PARITY_CHECK)) 9178 np->rv_scntl0 &= ~0x0a; /* SCSI parity checking disabled */ 9179 } 9180 9181 #ifdef SYM_CONF_DEBUG_NVRAM 9182 /* 9183 * Dump Symbios format NVRAM for debugging purpose. 9184 */ 9185 static void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram) 9186 { 9187 int i; 9188 9189 /* display Symbios nvram host data */ 9190 kprintf("%s: HOST ID=%d%s%s%s%s%s%s\n", 9191 sym_name(np), nvram->host_id & 0x0f, 9192 (nvram->flags & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9193 (nvram->flags & SYMBIOS_PARITY_ENABLE) ? " PARITY" :"", 9194 (nvram->flags & SYMBIOS_VERBOSE_MSGS) ? " VERBOSE" :"", 9195 (nvram->flags & SYMBIOS_CHS_MAPPING) ? " CHS_ALT" :"", 9196 (nvram->flags2 & SYMBIOS_AVOID_BUS_RESET)?" NO_RESET" :"", 9197 (nvram->flags1 & SYMBIOS_SCAN_HI_LO) ? " HI_LO" :""); 9198 9199 /* display Symbios nvram drive data */ 9200 for (i = 0 ; i < 15 ; i++) { 9201 struct Symbios_target *tn = &nvram->target[i]; 9202 kprintf("%s-%d:%s%s%s%s WIDTH=%d SYNC=%d TMO=%d\n", 9203 sym_name(np), i, 9204 (tn->flags & SYMBIOS_DISCONNECT_ENABLE) ? " DISC" : "", 9205 (tn->flags & SYMBIOS_SCAN_AT_BOOT_TIME) ? " SCAN_BOOT" : "", 9206 (tn->flags & SYMBIOS_SCAN_LUNS) ? " SCAN_LUNS" : "", 9207 (tn->flags & SYMBIOS_QUEUE_TAGS_ENABLED)? " TCQ" : "", 9208 tn->bus_width, 9209 tn->sync_period / 4, 9210 tn->timeout); 9211 } 9212 } 9213 9214 /* 9215 * Dump TEKRAM format NVRAM for debugging purpose. 9216 */ 9217 static const u_char Tekram_boot_delay[7] = {3, 5, 10, 20, 30, 60, 120}; 9218 static void sym_display_Tekram_nvram(hcb_p np, Tekram_nvram *nvram) 9219 { 9220 int i, tags, boot_delay; 9221 char *rem; 9222 9223 /* display Tekram nvram host data */ 9224 tags = 2 << nvram->max_tags_index; 9225 boot_delay = 0; 9226 if (nvram->boot_delay_index < 6) 9227 boot_delay = Tekram_boot_delay[nvram->boot_delay_index]; 9228 switch((nvram->flags & TEKRAM_REMOVABLE_FLAGS) >> 6) { 9229 default: 9230 case 0: rem = ""; break; 9231 case 1: rem = " REMOVABLE=boot device"; break; 9232 case 2: rem = " REMOVABLE=all"; break; 9233 } 9234 9235 kprintf("%s: HOST ID=%d%s%s%s%s%s%s%s%s%s BOOT DELAY=%d tags=%d\n", 9236 sym_name(np), nvram->host_id & 0x0f, 9237 (nvram->flags1 & SYMBIOS_SCAM_ENABLE) ? " SCAM" :"", 9238 (nvram->flags & TEKRAM_MORE_THAN_2_DRIVES) ? " >2DRIVES" :"", 9239 (nvram->flags & TEKRAM_DRIVES_SUP_1GB) ? " >1GB" :"", 9240 (nvram->flags & TEKRAM_RESET_ON_POWER_ON) ? " RESET" :"", 9241 (nvram->flags & TEKRAM_ACTIVE_NEGATION) ? " ACT_NEG" :"", 9242 (nvram->flags & TEKRAM_IMMEDIATE_SEEK) ? " IMM_SEEK" :"", 9243 (nvram->flags & TEKRAM_SCAN_LUNS) ? " SCAN_LUNS" :"", 9244 (nvram->flags1 & TEKRAM_F2_F6_ENABLED) ? " F2_F6" :"", 9245 rem, boot_delay, tags); 9246 9247 /* display Tekram nvram drive data */ 9248 for (i = 0; i <= 15; i++) { 9249 int sync, j; 9250 struct Tekram_target *tn = &nvram->target[i]; 9251 j = tn->sync_index & 0xf; 9252 sync = Tekram_sync[j]; 9253 kprintf("%s-%d:%s%s%s%s%s%s PERIOD=%d\n", 9254 sym_name(np), i, 9255 (tn->flags & TEKRAM_PARITY_CHECK) ? " PARITY" : "", 9256 (tn->flags & TEKRAM_SYNC_NEGO) ? " SYNC" : "", 9257 (tn->flags & TEKRAM_DISCONNECT_ENABLE) ? " DISC" : "", 9258 (tn->flags & TEKRAM_START_CMD) ? " START" : "", 9259 (tn->flags & TEKRAM_TAGGED_COMMANDS) ? " TCQ" : "", 9260 (tn->flags & TEKRAM_WIDE_NEGO) ? " WIDE" : "", 9261 sync); 9262 } 9263 } 9264 #endif /* SYM_CONF_DEBUG_NVRAM */ 9265 #endif /* SYM_CONF_NVRAM_SUPPORT */ 9266 9267 9268 /* 9269 * Try reading Symbios or Tekram NVRAM 9270 */ 9271 #ifdef SYM_CONF_NVRAM_SUPPORT 9272 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram); 9273 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram); 9274 #endif 9275 9276 static int sym_read_nvram(hcb_p np, struct sym_nvram *nvp) 9277 { 9278 #ifdef SYM_CONF_NVRAM_SUPPORT 9279 /* 9280 * Try to read SYMBIOS nvram. 9281 * Try to read TEKRAM nvram if Symbios nvram not found. 9282 */ 9283 if (SYM_SETUP_SYMBIOS_NVRAM && 9284 !sym_read_Symbios_nvram (np, &nvp->data.Symbios)) { 9285 nvp->type = SYM_SYMBIOS_NVRAM; 9286 #ifdef SYM_CONF_DEBUG_NVRAM 9287 sym_display_Symbios_nvram(np, &nvp->data.Symbios); 9288 #endif 9289 } 9290 else if (SYM_SETUP_TEKRAM_NVRAM && 9291 !sym_read_Tekram_nvram (np, &nvp->data.Tekram)) { 9292 nvp->type = SYM_TEKRAM_NVRAM; 9293 #ifdef SYM_CONF_DEBUG_NVRAM 9294 sym_display_Tekram_nvram(np, &nvp->data.Tekram); 9295 #endif 9296 } 9297 else 9298 nvp->type = 0; 9299 #else 9300 nvp->type = 0; 9301 #endif 9302 return nvp->type; 9303 } 9304 9305 9306 #ifdef SYM_CONF_NVRAM_SUPPORT 9307 /* 9308 * 24C16 EEPROM reading. 9309 * 9310 * GPOI0 - data in/data out 9311 * GPIO1 - clock 9312 * Symbios NVRAM wiring now also used by Tekram. 9313 */ 9314 9315 #define SET_BIT 0 9316 #define CLR_BIT 1 9317 #define SET_CLK 2 9318 #define CLR_CLK 3 9319 9320 /* 9321 * Set/clear data/clock bit in GPIO0 9322 */ 9323 static void S24C16_set_bit(hcb_p np, u_char write_bit, u_char *gpreg, 9324 int bit_mode) 9325 { 9326 UDELAY (5); 9327 switch (bit_mode){ 9328 case SET_BIT: 9329 *gpreg |= write_bit; 9330 break; 9331 case CLR_BIT: 9332 *gpreg &= 0xfe; 9333 break; 9334 case SET_CLK: 9335 *gpreg |= 0x02; 9336 break; 9337 case CLR_CLK: 9338 *gpreg &= 0xfd; 9339 break; 9340 9341 } 9342 OUTB (nc_gpreg, *gpreg); 9343 UDELAY (5); 9344 } 9345 9346 /* 9347 * Send START condition to NVRAM to wake it up. 9348 */ 9349 static void S24C16_start(hcb_p np, u_char *gpreg) 9350 { 9351 S24C16_set_bit(np, 1, gpreg, SET_BIT); 9352 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9353 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 9354 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 9355 } 9356 9357 /* 9358 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZzzzz!! 9359 */ 9360 static void S24C16_stop(hcb_p np, u_char *gpreg) 9361 { 9362 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9363 S24C16_set_bit(np, 1, gpreg, SET_BIT); 9364 } 9365 9366 /* 9367 * Read or write a bit to the NVRAM, 9368 * read if GPIO0 input else write if GPIO0 output 9369 */ 9370 static void S24C16_do_bit(hcb_p np, u_char *read_bit, u_char write_bit, 9371 u_char *gpreg) 9372 { 9373 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); 9374 S24C16_set_bit(np, 0, gpreg, SET_CLK); 9375 if (read_bit) 9376 *read_bit = INB (nc_gpreg); 9377 S24C16_set_bit(np, 0, gpreg, CLR_CLK); 9378 S24C16_set_bit(np, 0, gpreg, CLR_BIT); 9379 } 9380 9381 /* 9382 * Output an ACK to the NVRAM after reading, 9383 * change GPIO0 to output and when done back to an input 9384 */ 9385 static void S24C16_write_ack(hcb_p np, u_char write_bit, u_char *gpreg, 9386 u_char *gpcntl) 9387 { 9388 OUTB (nc_gpcntl, *gpcntl & 0xfe); 9389 S24C16_do_bit(np, 0, write_bit, gpreg); 9390 OUTB (nc_gpcntl, *gpcntl); 9391 } 9392 9393 /* 9394 * Input an ACK from NVRAM after writing, 9395 * change GPIO0 to input and when done back to an output 9396 */ 9397 static void S24C16_read_ack(hcb_p np, u_char *read_bit, u_char *gpreg, 9398 u_char *gpcntl) 9399 { 9400 OUTB (nc_gpcntl, *gpcntl | 0x01); 9401 S24C16_do_bit(np, read_bit, 1, gpreg); 9402 OUTB (nc_gpcntl, *gpcntl); 9403 } 9404 9405 /* 9406 * WRITE a byte to the NVRAM and then get an ACK to see it was accepted OK, 9407 * GPIO0 must already be set as an output 9408 */ 9409 static void S24C16_write_byte(hcb_p np, u_char *ack_data, u_char write_data, 9410 u_char *gpreg, u_char *gpcntl) 9411 { 9412 int x; 9413 9414 for (x = 0; x < 8; x++) 9415 S24C16_do_bit(np, 0, (write_data >> (7 - x)) & 0x01, gpreg); 9416 9417 S24C16_read_ack(np, ack_data, gpreg, gpcntl); 9418 } 9419 9420 /* 9421 * READ a byte from the NVRAM and then send an ACK to say we have got it, 9422 * GPIO0 must already be set as an input 9423 */ 9424 static void S24C16_read_byte(hcb_p np, u_char *read_data, u_char ack_data, 9425 u_char *gpreg, u_char *gpcntl) 9426 { 9427 int x; 9428 u_char read_bit; 9429 9430 *read_data = 0; 9431 for (x = 0; x < 8; x++) { 9432 S24C16_do_bit(np, &read_bit, 1, gpreg); 9433 *read_data |= ((read_bit & 0x01) << (7 - x)); 9434 } 9435 9436 S24C16_write_ack(np, ack_data, gpreg, gpcntl); 9437 } 9438 9439 /* 9440 * Read 'len' bytes starting at 'offset'. 9441 */ 9442 static int sym_read_S24C16_nvram (hcb_p np, int offset, u_char *data, int len) 9443 { 9444 u_char gpcntl, gpreg; 9445 u_char old_gpcntl, old_gpreg; 9446 u_char ack_data; 9447 int retv = 1; 9448 int x; 9449 9450 /* save current state of GPCNTL and GPREG */ 9451 old_gpreg = INB (nc_gpreg); 9452 old_gpcntl = INB (nc_gpcntl); 9453 gpcntl = old_gpcntl & 0x1c; 9454 9455 /* set up GPREG & GPCNTL to set GPIO0 and GPIO1 in to known state */ 9456 OUTB (nc_gpreg, old_gpreg); 9457 OUTB (nc_gpcntl, gpcntl); 9458 9459 /* this is to set NVRAM into a known state with GPIO0/1 both low */ 9460 gpreg = old_gpreg; 9461 S24C16_set_bit(np, 0, &gpreg, CLR_CLK); 9462 S24C16_set_bit(np, 0, &gpreg, CLR_BIT); 9463 9464 /* now set NVRAM inactive with GPIO0/1 both high */ 9465 S24C16_stop(np, &gpreg); 9466 9467 /* activate NVRAM */ 9468 S24C16_start(np, &gpreg); 9469 9470 /* write device code and random address MSB */ 9471 S24C16_write_byte(np, &ack_data, 9472 0xa0 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 9473 if (ack_data & 0x01) 9474 goto out; 9475 9476 /* write random address LSB */ 9477 S24C16_write_byte(np, &ack_data, 9478 offset & 0xff, &gpreg, &gpcntl); 9479 if (ack_data & 0x01) 9480 goto out; 9481 9482 /* regenerate START state to set up for reading */ 9483 S24C16_start(np, &gpreg); 9484 9485 /* rewrite device code and address MSB with read bit set (lsb = 0x01) */ 9486 S24C16_write_byte(np, &ack_data, 9487 0xa1 | ((offset >> 7) & 0x0e), &gpreg, &gpcntl); 9488 if (ack_data & 0x01) 9489 goto out; 9490 9491 /* now set up GPIO0 for inputting data */ 9492 gpcntl |= 0x01; 9493 OUTB (nc_gpcntl, gpcntl); 9494 9495 /* input all requested data - only part of total NVRAM */ 9496 for (x = 0; x < len; x++) 9497 S24C16_read_byte(np, &data[x], (x == (len-1)), &gpreg, &gpcntl); 9498 9499 /* finally put NVRAM back in inactive mode */ 9500 gpcntl &= 0xfe; 9501 OUTB (nc_gpcntl, gpcntl); 9502 S24C16_stop(np, &gpreg); 9503 retv = 0; 9504 out: 9505 /* return GPIO0/1 to original states after having accessed NVRAM */ 9506 OUTB (nc_gpcntl, old_gpcntl); 9507 OUTB (nc_gpreg, old_gpreg); 9508 9509 return retv; 9510 } 9511 9512 #undef SET_BIT /* 0 */ 9513 #undef CLR_BIT /* 1 */ 9514 #undef SET_CLK /* 2 */ 9515 #undef CLR_CLK /* 3 */ 9516 9517 /* 9518 * Try reading Symbios NVRAM. 9519 * Return 0 if OK. 9520 */ 9521 static int sym_read_Symbios_nvram (hcb_p np, Symbios_nvram *nvram) 9522 { 9523 static u_char Symbios_trailer[6] = {0xfe, 0xfe, 0, 0, 0, 0}; 9524 u_char *data = (u_char *) nvram; 9525 int len = sizeof(*nvram); 9526 u_short csum; 9527 int x; 9528 9529 /* probe the 24c16 and read the SYMBIOS 24c16 area */ 9530 if (sym_read_S24C16_nvram (np, SYMBIOS_NVRAM_ADDRESS, data, len)) 9531 return 1; 9532 9533 /* check valid NVRAM signature, verify byte count and checksum */ 9534 if (nvram->type != 0 || 9535 bcmp(nvram->trailer, Symbios_trailer, 6) || 9536 nvram->byte_count != len - 12) 9537 return 1; 9538 9539 /* verify checksum */ 9540 for (x = 6, csum = 0; x < len - 6; x++) 9541 csum += data[x]; 9542 if (csum != nvram->checksum) 9543 return 1; 9544 9545 return 0; 9546 } 9547 9548 /* 9549 * 93C46 EEPROM reading. 9550 * 9551 * GPOI0 - data in 9552 * GPIO1 - data out 9553 * GPIO2 - clock 9554 * GPIO4 - chip select 9555 * 9556 * Used by Tekram. 9557 */ 9558 9559 /* 9560 * Pulse clock bit in GPIO0 9561 */ 9562 static void T93C46_Clk(hcb_p np, u_char *gpreg) 9563 { 9564 OUTB (nc_gpreg, *gpreg | 0x04); 9565 UDELAY (2); 9566 OUTB (nc_gpreg, *gpreg); 9567 } 9568 9569 /* 9570 * Read bit from NVRAM 9571 */ 9572 static void T93C46_Read_Bit(hcb_p np, u_char *read_bit, u_char *gpreg) 9573 { 9574 UDELAY (2); 9575 T93C46_Clk(np, gpreg); 9576 *read_bit = INB (nc_gpreg); 9577 } 9578 9579 /* 9580 * Write bit to GPIO0 9581 */ 9582 static void T93C46_Write_Bit(hcb_p np, u_char write_bit, u_char *gpreg) 9583 { 9584 if (write_bit & 0x01) 9585 *gpreg |= 0x02; 9586 else 9587 *gpreg &= 0xfd; 9588 9589 *gpreg |= 0x10; 9590 9591 OUTB (nc_gpreg, *gpreg); 9592 UDELAY (2); 9593 9594 T93C46_Clk(np, gpreg); 9595 } 9596 9597 /* 9598 * Send STOP condition to NVRAM - puts NVRAM to sleep... ZZZzzz!! 9599 */ 9600 static void T93C46_Stop(hcb_p np, u_char *gpreg) 9601 { 9602 *gpreg &= 0xef; 9603 OUTB (nc_gpreg, *gpreg); 9604 UDELAY (2); 9605 9606 T93C46_Clk(np, gpreg); 9607 } 9608 9609 /* 9610 * Send read command and address to NVRAM 9611 */ 9612 static void T93C46_Send_Command(hcb_p np, u_short write_data, 9613 u_char *read_bit, u_char *gpreg) 9614 { 9615 int x; 9616 9617 /* send 9 bits, start bit (1), command (2), address (6) */ 9618 for (x = 0; x < 9; x++) 9619 T93C46_Write_Bit(np, (u_char) (write_data >> (8 - x)), gpreg); 9620 9621 *read_bit = INB (nc_gpreg); 9622 } 9623 9624 /* 9625 * READ 2 bytes from the NVRAM 9626 */ 9627 static void T93C46_Read_Word(hcb_p np, u_short *nvram_data, u_char *gpreg) 9628 { 9629 int x; 9630 u_char read_bit; 9631 9632 *nvram_data = 0; 9633 for (x = 0; x < 16; x++) { 9634 T93C46_Read_Bit(np, &read_bit, gpreg); 9635 9636 if (read_bit & 0x01) 9637 *nvram_data |= (0x01 << (15 - x)); 9638 else 9639 *nvram_data &= ~(0x01 << (15 - x)); 9640 } 9641 } 9642 9643 /* 9644 * Read Tekram NvRAM data. 9645 */ 9646 static int T93C46_Read_Data(hcb_p np, u_short *data,int len,u_char *gpreg) 9647 { 9648 u_char read_bit; 9649 int x; 9650 9651 for (x = 0; x < len; x++) { 9652 9653 /* output read command and address */ 9654 T93C46_Send_Command(np, 0x180 | x, &read_bit, gpreg); 9655 if (read_bit & 0x01) 9656 return 1; /* Bad */ 9657 T93C46_Read_Word(np, &data[x], gpreg); 9658 T93C46_Stop(np, gpreg); 9659 } 9660 9661 return 0; 9662 } 9663 9664 /* 9665 * Try reading 93C46 Tekram NVRAM. 9666 */ 9667 static int sym_read_T93C46_nvram (hcb_p np, Tekram_nvram *nvram) 9668 { 9669 u_char gpcntl, gpreg; 9670 u_char old_gpcntl, old_gpreg; 9671 int retv = 1; 9672 9673 /* save current state of GPCNTL and GPREG */ 9674 old_gpreg = INB (nc_gpreg); 9675 old_gpcntl = INB (nc_gpcntl); 9676 9677 /* set up GPREG & GPCNTL to set GPIO0/1/2/4 in to known state, 0 in, 9678 1/2/4 out */ 9679 gpreg = old_gpreg & 0xe9; 9680 OUTB (nc_gpreg, gpreg); 9681 gpcntl = (old_gpcntl & 0xe9) | 0x09; 9682 OUTB (nc_gpcntl, gpcntl); 9683 9684 /* input all of NVRAM, 64 words */ 9685 retv = T93C46_Read_Data(np, (u_short *) nvram, 9686 sizeof(*nvram) / sizeof(short), &gpreg); 9687 9688 /* return GPIO0/1/2/4 to original states after having accessed NVRAM */ 9689 OUTB (nc_gpcntl, old_gpcntl); 9690 OUTB (nc_gpreg, old_gpreg); 9691 9692 return retv; 9693 } 9694 9695 /* 9696 * Try reading Tekram NVRAM. 9697 * Return 0 if OK. 9698 */ 9699 static int sym_read_Tekram_nvram (hcb_p np, Tekram_nvram *nvram) 9700 { 9701 u_char *data = (u_char *) nvram; 9702 int len = sizeof(*nvram); 9703 u_short csum; 9704 int x; 9705 9706 switch (np->device_id) { 9707 case PCI_ID_SYM53C885: 9708 case PCI_ID_SYM53C895: 9709 case PCI_ID_SYM53C896: 9710 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 9711 data, len); 9712 break; 9713 case PCI_ID_SYM53C875: 9714 x = sym_read_S24C16_nvram(np, TEKRAM_24C16_NVRAM_ADDRESS, 9715 data, len); 9716 if (!x) 9717 break; 9718 default: 9719 x = sym_read_T93C46_nvram(np, nvram); 9720 break; 9721 } 9722 if (x) 9723 return 1; 9724 9725 /* verify checksum */ 9726 for (x = 0, csum = 0; x < len - 1; x += 2) 9727 csum += data[x] + (data[x+1] << 8); 9728 if (csum != 0x1234) 9729 return 1; 9730 9731 return 0; 9732 } 9733 9734 #endif /* SYM_CONF_NVRAM_SUPPORT */ 9735