1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 /**
30 * DOC: Interrupt Handling
31 *
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
37 *
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
40 *
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
43 */
44
45 #include <linux/irq.h>
46 #include <drm/drmP.h>
47 #include <drm/drm_crtc_helper.h>
48 #include <drm/amdgpu_drm.h>
49 #include "amdgpu.h"
50 #include "amdgpu_ih.h"
51 #include "atom.h"
52 #include "amdgpu_connectors.h"
53 #include "amdgpu_trace.h"
54
55 #include <linux/pm_runtime.h>
56
57 #ifdef CONFIG_DRM_AMD_DC
58 #include "amdgpu_dm_irq.h"
59 #endif
60
61 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
62
63 /**
64 * amdgpu_hotplug_work_func - work handler for display hotplug event
65 *
66 * @work: work struct pointer
67 *
68 * This is the hotplug event work handler (all ASICs).
69 * The work gets scheduled from the IRQ handler if there
70 * was a hotplug interrupt. It walks through the connector table
71 * and calls hotplug handler for each connector. After this, it sends
72 * a DRM hotplug event to alert userspace.
73 *
74 * This design approach is required in order to defer hotplug event handling
75 * from the IRQ handler to a work handler because hotplug handler has to use
76 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
77 * sleep).
78 */
amdgpu_hotplug_work_func(struct work_struct * work)79 static void amdgpu_hotplug_work_func(struct work_struct *work)
80 {
81 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
82 hotplug_work);
83 struct drm_device *dev = adev->ddev;
84 struct drm_mode_config *mode_config = &dev->mode_config;
85 struct drm_connector *connector;
86
87 mutex_lock(&mode_config->mutex);
88 list_for_each_entry(connector, &mode_config->connector_list, head)
89 amdgpu_connector_hotplug(connector);
90 mutex_unlock(&mode_config->mutex);
91 /* Just fire off a uevent and let userspace tell us what to do */
92 drm_helper_hpd_irq_event(dev);
93 }
94
95 /**
96 * amdgpu_irq_reset_work_func - execute GPU reset
97 *
98 * @work: work struct pointer
99 *
100 * Execute scheduled GPU reset (Cayman+).
101 * This function is called when the IRQ handler thinks we need a GPU reset.
102 */
amdgpu_irq_reset_work_func(struct work_struct * work)103 static void amdgpu_irq_reset_work_func(struct work_struct *work)
104 {
105 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
106 reset_work);
107
108 if (!amdgpu_sriov_vf(adev))
109 amdgpu_device_gpu_recover(adev, NULL, false);
110 }
111
112 /**
113 * amdgpu_irq_disable_all - disable *all* interrupts
114 *
115 * @adev: amdgpu device pointer
116 *
117 * Disable all types of interrupts from all sources.
118 */
amdgpu_irq_disable_all(struct amdgpu_device * adev)119 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
120 {
121 unsigned long irqflags;
122 unsigned i, j, k;
123 int r;
124
125 spin_lock_irqsave(&adev->irq.lock, irqflags);
126 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
127 if (!adev->irq.client[i].sources)
128 continue;
129
130 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
131 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
132
133 if (!src || !src->funcs->set || !src->num_types)
134 continue;
135
136 for (k = 0; k < src->num_types; ++k) {
137 atomic_set(&src->enabled_types[k], 0);
138 r = src->funcs->set(adev, src, k,
139 AMDGPU_IRQ_STATE_DISABLE);
140 if (r)
141 DRM_ERROR("error disabling interrupt (%d)\n",
142 r);
143 }
144 }
145 }
146 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
147 }
148
149 /**
150 * amdgpu_irq_handler - IRQ handler
151 *
152 * @irq: IRQ number (unused)
153 * @arg: pointer to DRM device
154 *
155 * IRQ handler for amdgpu driver (all ASICs).
156 *
157 * Returns:
158 * result of handling the IRQ, as defined by &irqreturn_t
159 */
amdgpu_irq_handler(int irq,void * arg)160 irqreturn_t amdgpu_irq_handler(int irq, void *arg)
161 {
162 struct drm_device *dev = (struct drm_device *) arg;
163 struct amdgpu_device *adev = dev->dev_private;
164 irqreturn_t ret;
165
166 ret = amdgpu_ih_process(adev);
167 if (ret == IRQ_HANDLED)
168 pm_runtime_mark_last_busy(dev->dev);
169 return ret;
170 }
171
172 /**
173 * amdgpu_msi_ok - check whether MSI functionality is enabled
174 *
175 * @adev: amdgpu device pointer (unused)
176 *
177 * Checks whether MSI functionality has been disabled via module parameter
178 * (all ASICs).
179 *
180 * Returns:
181 * *true* if MSIs are allowed to be enabled or *false* otherwise
182 */
amdgpu_msi_ok(struct amdgpu_device * adev)183 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
184 {
185 if (amdgpu_msi == 1)
186 return true;
187 else if (amdgpu_msi == 0)
188 return false;
189
190 return true;
191 }
192
193 /**
194 * amdgpu_irq_init - initialize interrupt handling
195 *
196 * @adev: amdgpu device pointer
197 *
198 * Sets up work functions for hotplug and reset interrupts, enables MSI
199 * functionality, initializes vblank, hotplug and reset interrupt handling.
200 *
201 * Returns:
202 * 0 on success or error code on failure
203 */
amdgpu_irq_init(struct amdgpu_device * adev)204 int amdgpu_irq_init(struct amdgpu_device *adev)
205 {
206 int r = 0;
207
208 lockinit(&adev->irq.lock, "agail", 0, LK_CANRECURSE);
209
210 /* Enable MSI if not disabled by module parameter */
211 #ifndef __DragonFly__
212 adev->irq.msi_enabled = false;
213 #else
214 adev->irq.msi_enabled = (adev->ddev->pdev->_irq_type == PCI_INTR_TYPE_MSI);
215 #endif
216
217 if (amdgpu_msi_ok(adev)) {
218 #ifndef __DragonFly__
219 int ret = pci_enable_msi(adev->pdev);
220 if (!ret) {
221 adev->irq.msi_enabled = true;
222 dev_dbg(adev->dev, "amdgpu: using MSI.\n");
223 }
224 #endif
225 }
226
227 if (!amdgpu_device_has_dc_support(adev)) {
228 if (!adev->enable_virtual_display)
229 /* Disable vblank IRQs aggressively for power-saving */
230 /* XXX: can this be enabled for DC? */
231 adev->ddev->vblank_disable_immediate = true;
232
233 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
234 if (r)
235 return r;
236
237 /* Pre-DCE11 */
238 INIT_WORK(&adev->hotplug_work,
239 amdgpu_hotplug_work_func);
240 }
241
242 INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
243
244 adev->irq.installed = true;
245 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
246 if (r) {
247 adev->irq.installed = false;
248 if (!amdgpu_device_has_dc_support(adev))
249 flush_work(&adev->hotplug_work);
250 cancel_work_sync(&adev->reset_work);
251 return r;
252 }
253 adev->ddev->max_vblank_count = 0x00ffffff;
254
255 DRM_DEBUG("amdgpu: irq initialized.\n");
256 return 0;
257 }
258
259 /**
260 * amdgpu_irq_fini - shut down interrupt handling
261 *
262 * @adev: amdgpu device pointer
263 *
264 * Tears down work functions for hotplug and reset interrupts, disables MSI
265 * functionality, shuts down vblank, hotplug and reset interrupt handling,
266 * turns off interrupts from all sources (all ASICs).
267 */
amdgpu_irq_fini(struct amdgpu_device * adev)268 void amdgpu_irq_fini(struct amdgpu_device *adev)
269 {
270 unsigned i, j;
271
272 if (adev->irq.installed) {
273 drm_irq_uninstall(adev->ddev);
274 adev->irq.installed = false;
275 #ifndef __DragonFly__
276 if (adev->irq.msi_enabled)
277 pci_disable_msi(adev->pdev);
278 #endif
279 if (!amdgpu_device_has_dc_support(adev))
280 flush_work(&adev->hotplug_work);
281 cancel_work_sync(&adev->reset_work);
282 }
283
284 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
285 if (!adev->irq.client[i].sources)
286 continue;
287
288 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
289 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
290
291 if (!src)
292 continue;
293
294 kfree(src->enabled_types);
295 src->enabled_types = NULL;
296 if (src->data) {
297 kfree(src->data);
298 kfree(src);
299 adev->irq.client[i].sources[j] = NULL;
300 }
301 }
302 kfree(adev->irq.client[i].sources);
303 adev->irq.client[i].sources = NULL;
304 }
305 }
306
307 /**
308 * amdgpu_irq_add_id - register IRQ source
309 *
310 * @adev: amdgpu device pointer
311 * @client_id: client id
312 * @src_id: source id
313 * @source: IRQ source pointer
314 *
315 * Registers IRQ source on a client.
316 *
317 * Returns:
318 * 0 on success or error code otherwise
319 */
amdgpu_irq_add_id(struct amdgpu_device * adev,unsigned client_id,unsigned src_id,struct amdgpu_irq_src * source)320 int amdgpu_irq_add_id(struct amdgpu_device *adev,
321 unsigned client_id, unsigned src_id,
322 struct amdgpu_irq_src *source)
323 {
324 if (client_id >= AMDGPU_IH_CLIENTID_MAX)
325 return -EINVAL;
326
327 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
328 return -EINVAL;
329
330 if (!source->funcs)
331 return -EINVAL;
332
333 if (!adev->irq.client[client_id].sources) {
334 adev->irq.client[client_id].sources =
335 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
336 sizeof(struct amdgpu_irq_src *),
337 GFP_KERNEL);
338 if (!adev->irq.client[client_id].sources)
339 return -ENOMEM;
340 }
341
342 if (adev->irq.client[client_id].sources[src_id] != NULL)
343 return -EINVAL;
344
345 if (source->num_types && !source->enabled_types) {
346 atomic_t *types;
347
348 types = kcalloc(source->num_types, sizeof(atomic_t),
349 GFP_KERNEL);
350 if (!types)
351 return -ENOMEM;
352
353 source->enabled_types = types;
354 }
355
356 adev->irq.client[client_id].sources[src_id] = source;
357 return 0;
358 }
359
360 /**
361 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
362 *
363 * @adev: amdgpu device pointer
364 * @entry: interrupt vector pointer
365 *
366 * Dispatches IRQ to IP blocks.
367 */
amdgpu_irq_dispatch(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)368 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
369 struct amdgpu_iv_entry *entry)
370 {
371 unsigned client_id = entry->client_id;
372 unsigned src_id = entry->src_id;
373 struct amdgpu_irq_src *src;
374 int r;
375
376 #if 0
377 trace_amdgpu_iv(entry);
378 #endif
379
380 if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
381 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
382 return;
383 }
384
385 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
386 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
387 return;
388 }
389
390 if (adev->irq.virq[src_id]) {
391 #if 0
392 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
393 #endif
394 } else {
395 if (!adev->irq.client[client_id].sources) {
396 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
397 client_id, src_id);
398 return;
399 }
400
401 src = adev->irq.client[client_id].sources[src_id];
402 if (!src) {
403 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
404 return;
405 }
406
407 r = src->funcs->process(adev, src, entry);
408 if (r)
409 DRM_ERROR("error processing interrupt (%d)\n", r);
410 }
411 }
412
413 /**
414 * amdgpu_irq_update - update hardware interrupt state
415 *
416 * @adev: amdgpu device pointer
417 * @src: interrupt source pointer
418 * @type: type of interrupt
419 *
420 * Updates interrupt state for the specific source (all ASICs).
421 */
amdgpu_irq_update(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)422 int amdgpu_irq_update(struct amdgpu_device *adev,
423 struct amdgpu_irq_src *src, unsigned type)
424 {
425 unsigned long irqflags;
426 enum amdgpu_interrupt_state state;
427 int r;
428
429 spin_lock_irqsave(&adev->irq.lock, irqflags);
430
431 /* We need to determine after taking the lock, otherwise
432 we might disable just enabled interrupts again */
433 if (amdgpu_irq_enabled(adev, src, type))
434 state = AMDGPU_IRQ_STATE_ENABLE;
435 else
436 state = AMDGPU_IRQ_STATE_DISABLE;
437
438 r = src->funcs->set(adev, src, type, state);
439 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
440 return r;
441 }
442
443 /**
444 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
445 *
446 * @adev: amdgpu device pointer
447 *
448 * Updates state of all types of interrupts on all sources on resume after
449 * reset.
450 */
amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device * adev)451 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
452 {
453 int i, j, k;
454
455 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
456 if (!adev->irq.client[i].sources)
457 continue;
458
459 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
460 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
461
462 if (!src || !src->funcs || !src->funcs->set)
463 continue;
464 for (k = 0; k < src->num_types; k++)
465 amdgpu_irq_update(adev, src, k);
466 }
467 }
468 }
469
470 /**
471 * amdgpu_irq_get - enable interrupt
472 *
473 * @adev: amdgpu device pointer
474 * @src: interrupt source pointer
475 * @type: type of interrupt
476 *
477 * Enables specified type of interrupt on the specified source (all ASICs).
478 *
479 * Returns:
480 * 0 on success or error code otherwise
481 */
amdgpu_irq_get(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)482 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
483 unsigned type)
484 {
485 if (!adev->ddev->irq_enabled)
486 return -ENOENT;
487
488 if (type >= src->num_types)
489 return -EINVAL;
490
491 if (!src->enabled_types || !src->funcs->set)
492 return -EINVAL;
493
494 if (atomic_inc_return(&src->enabled_types[type]) == 1)
495 return amdgpu_irq_update(adev, src, type);
496
497 return 0;
498 }
499
500 /**
501 * amdgpu_irq_put - disable interrupt
502 *
503 * @adev: amdgpu device pointer
504 * @src: interrupt source pointer
505 * @type: type of interrupt
506 *
507 * Enables specified type of interrupt on the specified source (all ASICs).
508 *
509 * Returns:
510 * 0 on success or error code otherwise
511 */
amdgpu_irq_put(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)512 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
513 unsigned type)
514 {
515 if (!adev->ddev->irq_enabled)
516 return -ENOENT;
517
518 if (type >= src->num_types)
519 return -EINVAL;
520
521 if (!src->enabled_types || !src->funcs->set)
522 return -EINVAL;
523
524 if (atomic_dec_and_test(&src->enabled_types[type]))
525 return amdgpu_irq_update(adev, src, type);
526
527 return 0;
528 }
529
530 /**
531 * amdgpu_irq_enabled - check whether interrupt is enabled or not
532 *
533 * @adev: amdgpu device pointer
534 * @src: interrupt source pointer
535 * @type: type of interrupt
536 *
537 * Checks whether the given type of interrupt is enabled on the given source.
538 *
539 * Returns:
540 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
541 * invalid parameters
542 */
amdgpu_irq_enabled(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type)543 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
544 unsigned type)
545 {
546 if (!adev->ddev->irq_enabled)
547 return false;
548
549 if (type >= src->num_types)
550 return false;
551
552 if (!src->enabled_types || !src->funcs->set)
553 return false;
554
555 return !!atomic_read(&src->enabled_types[type]);
556 }
557
558 #if 0
559 /* XXX: Generic IRQ handling */
560 static void amdgpu_irq_mask(struct irq_data *irqd)
561 {
562 /* XXX */
563 }
564
565 static void amdgpu_irq_unmask(struct irq_data *irqd)
566 {
567 /* XXX */
568 }
569
570 /* amdgpu hardware interrupt chip descriptor */
571 static struct irq_chip amdgpu_irq_chip = {
572 .name = "amdgpu-ih",
573 .irq_mask = amdgpu_irq_mask,
574 .irq_unmask = amdgpu_irq_unmask,
575 };
576
577 /**
578 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
579 *
580 * @d: amdgpu IRQ domain pointer (unused)
581 * @irq: virtual IRQ number
582 * @hwirq: hardware irq number
583 *
584 * Current implementation assigns simple interrupt handler to the given virtual
585 * IRQ.
586 *
587 * Returns:
588 * 0 on success or error code otherwise
589 */
590 static int amdgpu_irqdomain_map(struct irq_domain *d,
591 unsigned int irq, irq_hw_number_t hwirq)
592 {
593 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
594 return -EPERM;
595
596 irq_set_chip_and_handler(irq,
597 &amdgpu_irq_chip, handle_simple_irq);
598 return 0;
599 }
600
601 /* Implementation of methods for amdgpu IRQ domain */
602 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
603 .map = amdgpu_irqdomain_map,
604 };
605 #endif
606
607 /**
608 * amdgpu_irq_add_domain - create a linear IRQ domain
609 *
610 * @adev: amdgpu device pointer
611 *
612 * Creates an IRQ domain for GPU interrupt sources
613 * that may be driven by another driver (e.g., ACP).
614 *
615 * Returns:
616 * 0 on success or error code otherwise
617 */
amdgpu_irq_add_domain(struct amdgpu_device * adev)618 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
619 {
620 #if 0
621 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
622 &amdgpu_hw_irqdomain_ops, adev);
623 if (!adev->irq.domain) {
624 DRM_ERROR("GPU irq add domain failed\n");
625 return -ENODEV;
626 }
627 #endif
628
629 return 0;
630 }
631
632 /**
633 * amdgpu_irq_remove_domain - remove the IRQ domain
634 *
635 * @adev: amdgpu device pointer
636 *
637 * Removes the IRQ domain for GPU interrupt sources
638 * that may be driven by another driver (e.g., ACP).
639 */
amdgpu_irq_remove_domain(struct amdgpu_device * adev)640 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
641 {
642 #if 0
643 if (adev->irq.domain) {
644 irq_domain_remove(adev->irq.domain);
645 adev->irq.domain = NULL;
646 }
647 #endif
648 }
649
650 /**
651 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
652 *
653 * @adev: amdgpu device pointer
654 * @src_id: IH source id
655 *
656 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
657 * Use this for components that generate a GPU interrupt, but are driven
658 * by a different driver (e.g., ACP).
659 *
660 * Returns:
661 * Linux IRQ
662 */
amdgpu_irq_create_mapping(struct amdgpu_device * adev,unsigned src_id)663 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
664 {
665 #if 0
666 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
667
668 return adev->irq.virq[src_id];
669 #endif
670 return 0;
671 }
672