1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2014 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef __AMDGPU_UVD_H__ 25*b843c749SSergey Zigachev #define __AMDGPU_UVD_H__ 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #define AMDGPU_DEFAULT_UVD_HANDLES 10 28*b843c749SSergey Zigachev #define AMDGPU_MAX_UVD_HANDLES 40 29*b843c749SSergey Zigachev #define AMDGPU_UVD_STACK_SIZE (200*1024) 30*b843c749SSergey Zigachev #define AMDGPU_UVD_HEAP_SIZE (256*1024) 31*b843c749SSergey Zigachev #define AMDGPU_UVD_SESSION_SIZE (50*1024) 32*b843c749SSergey Zigachev #define AMDGPU_UVD_FIRMWARE_OFFSET 256 33*b843c749SSergey Zigachev 34*b843c749SSergey Zigachev #define AMDGPU_MAX_UVD_INSTANCES 2 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev #define AMDGPU_UVD_FIRMWARE_SIZE(adev) \ 37*b843c749SSergey Zigachev (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \ 38*b843c749SSergey Zigachev 8) - AMDGPU_UVD_FIRMWARE_OFFSET) 39*b843c749SSergey Zigachev 40*b843c749SSergey Zigachev struct amdgpu_uvd_inst { 41*b843c749SSergey Zigachev struct amdgpu_bo *vcpu_bo; 42*b843c749SSergey Zigachev void *cpu_addr; 43*b843c749SSergey Zigachev uint64_t gpu_addr; 44*b843c749SSergey Zigachev void *saved_bo; 45*b843c749SSergey Zigachev struct amdgpu_ring ring; 46*b843c749SSergey Zigachev struct amdgpu_ring ring_enc[AMDGPU_MAX_UVD_ENC_RINGS]; 47*b843c749SSergey Zigachev struct amdgpu_irq_src irq; 48*b843c749SSergey Zigachev uint32_t srbm_soft_reset; 49*b843c749SSergey Zigachev }; 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev #define AMDGPU_UVD_HARVEST_UVD0 (1 << 0) 52*b843c749SSergey Zigachev #define AMDGPU_UVD_HARVEST_UVD1 (1 << 1) 53*b843c749SSergey Zigachev 54*b843c749SSergey Zigachev struct amdgpu_uvd { 55*b843c749SSergey Zigachev const struct firmware *fw; /* UVD firmware */ 56*b843c749SSergey Zigachev unsigned fw_version; 57*b843c749SSergey Zigachev unsigned max_handles; 58*b843c749SSergey Zigachev unsigned num_enc_rings; 59*b843c749SSergey Zigachev uint8_t num_uvd_inst; 60*b843c749SSergey Zigachev bool address_64_bit; 61*b843c749SSergey Zigachev bool use_ctx_buf; 62*b843c749SSergey Zigachev struct amdgpu_uvd_inst inst[AMDGPU_MAX_UVD_INSTANCES]; 63*b843c749SSergey Zigachev struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 64*b843c749SSergey Zigachev atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 65*b843c749SSergey Zigachev struct drm_sched_entity entity; 66*b843c749SSergey Zigachev struct delayed_work idle_work; 67*b843c749SSergey Zigachev unsigned harvest_config; 68*b843c749SSergey Zigachev }; 69*b843c749SSergey Zigachev 70*b843c749SSergey Zigachev int amdgpu_uvd_sw_init(struct amdgpu_device *adev); 71*b843c749SSergey Zigachev int amdgpu_uvd_sw_fini(struct amdgpu_device *adev); 72*b843c749SSergey Zigachev int amdgpu_uvd_entity_init(struct amdgpu_device *adev); 73*b843c749SSergey Zigachev int amdgpu_uvd_suspend(struct amdgpu_device *adev); 74*b843c749SSergey Zigachev int amdgpu_uvd_resume(struct amdgpu_device *adev); 75*b843c749SSergey Zigachev int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 76*b843c749SSergey Zigachev struct dma_fence **fence); 77*b843c749SSergey Zigachev int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 78*b843c749SSergey Zigachev bool direct, struct dma_fence **fence); 79*b843c749SSergey Zigachev void amdgpu_uvd_free_handles(struct amdgpu_device *adev, 80*b843c749SSergey Zigachev struct drm_file *filp); 81*b843c749SSergey Zigachev int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx); 82*b843c749SSergey Zigachev void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring); 83*b843c749SSergey Zigachev void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring); 84*b843c749SSergey Zigachev int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout); 85*b843c749SSergey Zigachev uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev); 86*b843c749SSergey Zigachev 87*b843c749SSergey Zigachev #endif 88