1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2013-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev /*
27*b843c749SSergey Zigachev * Pre-requisites: headers required by header of this unit
28*b843c749SSergey Zigachev */
29*b843c749SSergey Zigachev
30*b843c749SSergey Zigachev #include "hw_translate_dce120.h"
31*b843c749SSergey Zigachev
32*b843c749SSergey Zigachev #include "dm_services.h"
33*b843c749SSergey Zigachev #include "include/gpio_types.h"
34*b843c749SSergey Zigachev #include "../hw_translate.h"
35*b843c749SSergey Zigachev
36*b843c749SSergey Zigachev #include "dce/dce_12_0_offset.h"
37*b843c749SSergey Zigachev #include "dce/dce_12_0_sh_mask.h"
38*b843c749SSergey Zigachev #include "soc15_hw_ip.h"
39*b843c749SSergey Zigachev #include "vega10_ip_offset.h"
40*b843c749SSergey Zigachev
41*b843c749SSergey Zigachev /* begin *********************
42*b843c749SSergey Zigachev * macros to expend register list macro defined in HW object header file */
43*b843c749SSergey Zigachev
44*b843c749SSergey Zigachev #define BASE_INNER(seg) \
45*b843c749SSergey Zigachev DCE_BASE__INST0_SEG ## seg
46*b843c749SSergey Zigachev
47*b843c749SSergey Zigachev /* compile time expand base address. */
48*b843c749SSergey Zigachev #define BASE(seg) \
49*b843c749SSergey Zigachev BASE_INNER(seg)
50*b843c749SSergey Zigachev
51*b843c749SSergey Zigachev #define REG(reg_name)\
52*b843c749SSergey Zigachev BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
53*b843c749SSergey Zigachev
54*b843c749SSergey Zigachev #define REGI(reg_name, block, id)\
55*b843c749SSergey Zigachev BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
56*b843c749SSergey Zigachev mm ## block ## id ## _ ## reg_name
57*b843c749SSergey Zigachev
58*b843c749SSergey Zigachev /* macros to expend register list macro defined in HW object header file
59*b843c749SSergey Zigachev * end *********************/
60*b843c749SSergey Zigachev
offset_to_id(uint32_t offset,uint32_t mask,enum gpio_id * id,uint32_t * en)61*b843c749SSergey Zigachev static bool offset_to_id(
62*b843c749SSergey Zigachev uint32_t offset,
63*b843c749SSergey Zigachev uint32_t mask,
64*b843c749SSergey Zigachev enum gpio_id *id,
65*b843c749SSergey Zigachev uint32_t *en)
66*b843c749SSergey Zigachev {
67*b843c749SSergey Zigachev switch (offset) {
68*b843c749SSergey Zigachev /* GENERIC */
69*b843c749SSergey Zigachev case REG(DC_GPIO_GENERIC_A):
70*b843c749SSergey Zigachev *id = GPIO_ID_GENERIC;
71*b843c749SSergey Zigachev switch (mask) {
72*b843c749SSergey Zigachev case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
73*b843c749SSergey Zigachev *en = GPIO_GENERIC_A;
74*b843c749SSergey Zigachev return true;
75*b843c749SSergey Zigachev case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
76*b843c749SSergey Zigachev *en = GPIO_GENERIC_B;
77*b843c749SSergey Zigachev return true;
78*b843c749SSergey Zigachev case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
79*b843c749SSergey Zigachev *en = GPIO_GENERIC_C;
80*b843c749SSergey Zigachev return true;
81*b843c749SSergey Zigachev case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
82*b843c749SSergey Zigachev *en = GPIO_GENERIC_D;
83*b843c749SSergey Zigachev return true;
84*b843c749SSergey Zigachev case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
85*b843c749SSergey Zigachev *en = GPIO_GENERIC_E;
86*b843c749SSergey Zigachev return true;
87*b843c749SSergey Zigachev case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
88*b843c749SSergey Zigachev *en = GPIO_GENERIC_F;
89*b843c749SSergey Zigachev return true;
90*b843c749SSergey Zigachev case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
91*b843c749SSergey Zigachev *en = GPIO_GENERIC_G;
92*b843c749SSergey Zigachev return true;
93*b843c749SSergey Zigachev default:
94*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
95*b843c749SSergey Zigachev return false;
96*b843c749SSergey Zigachev }
97*b843c749SSergey Zigachev break;
98*b843c749SSergey Zigachev /* HPD */
99*b843c749SSergey Zigachev case REG(DC_GPIO_HPD_A):
100*b843c749SSergey Zigachev *id = GPIO_ID_HPD;
101*b843c749SSergey Zigachev switch (mask) {
102*b843c749SSergey Zigachev case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
103*b843c749SSergey Zigachev *en = GPIO_HPD_1;
104*b843c749SSergey Zigachev return true;
105*b843c749SSergey Zigachev case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
106*b843c749SSergey Zigachev *en = GPIO_HPD_2;
107*b843c749SSergey Zigachev return true;
108*b843c749SSergey Zigachev case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
109*b843c749SSergey Zigachev *en = GPIO_HPD_3;
110*b843c749SSergey Zigachev return true;
111*b843c749SSergey Zigachev case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
112*b843c749SSergey Zigachev *en = GPIO_HPD_4;
113*b843c749SSergey Zigachev return true;
114*b843c749SSergey Zigachev case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
115*b843c749SSergey Zigachev *en = GPIO_HPD_5;
116*b843c749SSergey Zigachev return true;
117*b843c749SSergey Zigachev case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
118*b843c749SSergey Zigachev *en = GPIO_HPD_6;
119*b843c749SSergey Zigachev return true;
120*b843c749SSergey Zigachev default:
121*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
122*b843c749SSergey Zigachev return false;
123*b843c749SSergey Zigachev }
124*b843c749SSergey Zigachev break;
125*b843c749SSergey Zigachev /* SYNCA */
126*b843c749SSergey Zigachev case REG(DC_GPIO_SYNCA_A):
127*b843c749SSergey Zigachev *id = GPIO_ID_SYNC;
128*b843c749SSergey Zigachev switch (mask) {
129*b843c749SSergey Zigachev case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
130*b843c749SSergey Zigachev *en = GPIO_SYNC_HSYNC_A;
131*b843c749SSergey Zigachev return true;
132*b843c749SSergey Zigachev case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
133*b843c749SSergey Zigachev *en = GPIO_SYNC_VSYNC_A;
134*b843c749SSergey Zigachev return true;
135*b843c749SSergey Zigachev default:
136*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
137*b843c749SSergey Zigachev return false;
138*b843c749SSergey Zigachev }
139*b843c749SSergey Zigachev break;
140*b843c749SSergey Zigachev /* REG(DC_GPIO_GENLK_MASK */
141*b843c749SSergey Zigachev case REG(DC_GPIO_GENLK_A):
142*b843c749SSergey Zigachev *id = GPIO_ID_GSL;
143*b843c749SSergey Zigachev switch (mask) {
144*b843c749SSergey Zigachev case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
145*b843c749SSergey Zigachev *en = GPIO_GSL_GENLOCK_CLOCK;
146*b843c749SSergey Zigachev return true;
147*b843c749SSergey Zigachev case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
148*b843c749SSergey Zigachev *en = GPIO_GSL_GENLOCK_VSYNC;
149*b843c749SSergey Zigachev return true;
150*b843c749SSergey Zigachev case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
151*b843c749SSergey Zigachev *en = GPIO_GSL_SWAPLOCK_A;
152*b843c749SSergey Zigachev return true;
153*b843c749SSergey Zigachev case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
154*b843c749SSergey Zigachev *en = GPIO_GSL_SWAPLOCK_B;
155*b843c749SSergey Zigachev return true;
156*b843c749SSergey Zigachev default:
157*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
158*b843c749SSergey Zigachev return false;
159*b843c749SSergey Zigachev }
160*b843c749SSergey Zigachev break;
161*b843c749SSergey Zigachev /* DDC */
162*b843c749SSergey Zigachev /* we don't care about the GPIO_ID for DDC
163*b843c749SSergey Zigachev * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
164*b843c749SSergey Zigachev * directly in the create method */
165*b843c749SSergey Zigachev case REG(DC_GPIO_DDC1_A):
166*b843c749SSergey Zigachev *en = GPIO_DDC_LINE_DDC1;
167*b843c749SSergey Zigachev return true;
168*b843c749SSergey Zigachev case REG(DC_GPIO_DDC2_A):
169*b843c749SSergey Zigachev *en = GPIO_DDC_LINE_DDC2;
170*b843c749SSergey Zigachev return true;
171*b843c749SSergey Zigachev case REG(DC_GPIO_DDC3_A):
172*b843c749SSergey Zigachev *en = GPIO_DDC_LINE_DDC3;
173*b843c749SSergey Zigachev return true;
174*b843c749SSergey Zigachev case REG(DC_GPIO_DDC4_A):
175*b843c749SSergey Zigachev *en = GPIO_DDC_LINE_DDC4;
176*b843c749SSergey Zigachev return true;
177*b843c749SSergey Zigachev case REG(DC_GPIO_DDC5_A):
178*b843c749SSergey Zigachev *en = GPIO_DDC_LINE_DDC5;
179*b843c749SSergey Zigachev return true;
180*b843c749SSergey Zigachev case REG(DC_GPIO_DDC6_A):
181*b843c749SSergey Zigachev *en = GPIO_DDC_LINE_DDC6;
182*b843c749SSergey Zigachev return true;
183*b843c749SSergey Zigachev case REG(DC_GPIO_DDCVGA_A):
184*b843c749SSergey Zigachev *en = GPIO_DDC_LINE_DDC_VGA;
185*b843c749SSergey Zigachev return true;
186*b843c749SSergey Zigachev /* GPIO_I2CPAD */
187*b843c749SSergey Zigachev case REG(DC_GPIO_I2CPAD_A):
188*b843c749SSergey Zigachev *en = GPIO_DDC_LINE_I2C_PAD;
189*b843c749SSergey Zigachev return true;
190*b843c749SSergey Zigachev /* Not implemented */
191*b843c749SSergey Zigachev case REG(DC_GPIO_PWRSEQ_A):
192*b843c749SSergey Zigachev case REG(DC_GPIO_PAD_STRENGTH_1):
193*b843c749SSergey Zigachev case REG(DC_GPIO_PAD_STRENGTH_2):
194*b843c749SSergey Zigachev case REG(DC_GPIO_DEBUG):
195*b843c749SSergey Zigachev return false;
196*b843c749SSergey Zigachev /* UNEXPECTED */
197*b843c749SSergey Zigachev default:
198*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
199*b843c749SSergey Zigachev return false;
200*b843c749SSergey Zigachev }
201*b843c749SSergey Zigachev }
202*b843c749SSergey Zigachev
id_to_offset(enum gpio_id id,uint32_t en,struct gpio_pin_info * info)203*b843c749SSergey Zigachev static bool id_to_offset(
204*b843c749SSergey Zigachev enum gpio_id id,
205*b843c749SSergey Zigachev uint32_t en,
206*b843c749SSergey Zigachev struct gpio_pin_info *info)
207*b843c749SSergey Zigachev {
208*b843c749SSergey Zigachev bool result = true;
209*b843c749SSergey Zigachev
210*b843c749SSergey Zigachev switch (id) {
211*b843c749SSergey Zigachev case GPIO_ID_DDC_DATA:
212*b843c749SSergey Zigachev info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
213*b843c749SSergey Zigachev switch (en) {
214*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC1:
215*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC1_A);
216*b843c749SSergey Zigachev break;
217*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC2:
218*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC2_A);
219*b843c749SSergey Zigachev break;
220*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC3:
221*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC3_A);
222*b843c749SSergey Zigachev break;
223*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC4:
224*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC4_A);
225*b843c749SSergey Zigachev break;
226*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC5:
227*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC5_A);
228*b843c749SSergey Zigachev break;
229*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC6:
230*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC6_A);
231*b843c749SSergey Zigachev break;
232*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC_VGA:
233*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDCVGA_A);
234*b843c749SSergey Zigachev break;
235*b843c749SSergey Zigachev case GPIO_DDC_LINE_I2C_PAD:
236*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_I2CPAD_A);
237*b843c749SSergey Zigachev break;
238*b843c749SSergey Zigachev default:
239*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
240*b843c749SSergey Zigachev result = false;
241*b843c749SSergey Zigachev }
242*b843c749SSergey Zigachev break;
243*b843c749SSergey Zigachev case GPIO_ID_DDC_CLOCK:
244*b843c749SSergey Zigachev info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
245*b843c749SSergey Zigachev switch (en) {
246*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC1:
247*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC1_A);
248*b843c749SSergey Zigachev break;
249*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC2:
250*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC2_A);
251*b843c749SSergey Zigachev break;
252*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC3:
253*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC3_A);
254*b843c749SSergey Zigachev break;
255*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC4:
256*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC4_A);
257*b843c749SSergey Zigachev break;
258*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC5:
259*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC5_A);
260*b843c749SSergey Zigachev break;
261*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC6:
262*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDC6_A);
263*b843c749SSergey Zigachev break;
264*b843c749SSergey Zigachev case GPIO_DDC_LINE_DDC_VGA:
265*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_DDCVGA_A);
266*b843c749SSergey Zigachev break;
267*b843c749SSergey Zigachev case GPIO_DDC_LINE_I2C_PAD:
268*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_I2CPAD_A);
269*b843c749SSergey Zigachev break;
270*b843c749SSergey Zigachev default:
271*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
272*b843c749SSergey Zigachev result = false;
273*b843c749SSergey Zigachev }
274*b843c749SSergey Zigachev break;
275*b843c749SSergey Zigachev case GPIO_ID_GENERIC:
276*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_GENERIC_A);
277*b843c749SSergey Zigachev switch (en) {
278*b843c749SSergey Zigachev case GPIO_GENERIC_A:
279*b843c749SSergey Zigachev info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
280*b843c749SSergey Zigachev break;
281*b843c749SSergey Zigachev case GPIO_GENERIC_B:
282*b843c749SSergey Zigachev info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
283*b843c749SSergey Zigachev break;
284*b843c749SSergey Zigachev case GPIO_GENERIC_C:
285*b843c749SSergey Zigachev info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
286*b843c749SSergey Zigachev break;
287*b843c749SSergey Zigachev case GPIO_GENERIC_D:
288*b843c749SSergey Zigachev info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
289*b843c749SSergey Zigachev break;
290*b843c749SSergey Zigachev case GPIO_GENERIC_E:
291*b843c749SSergey Zigachev info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
292*b843c749SSergey Zigachev break;
293*b843c749SSergey Zigachev case GPIO_GENERIC_F:
294*b843c749SSergey Zigachev info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
295*b843c749SSergey Zigachev break;
296*b843c749SSergey Zigachev case GPIO_GENERIC_G:
297*b843c749SSergey Zigachev info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
298*b843c749SSergey Zigachev break;
299*b843c749SSergey Zigachev default:
300*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
301*b843c749SSergey Zigachev result = false;
302*b843c749SSergey Zigachev }
303*b843c749SSergey Zigachev break;
304*b843c749SSergey Zigachev case GPIO_ID_HPD:
305*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_HPD_A);
306*b843c749SSergey Zigachev switch (en) {
307*b843c749SSergey Zigachev case GPIO_HPD_1:
308*b843c749SSergey Zigachev info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
309*b843c749SSergey Zigachev break;
310*b843c749SSergey Zigachev case GPIO_HPD_2:
311*b843c749SSergey Zigachev info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
312*b843c749SSergey Zigachev break;
313*b843c749SSergey Zigachev case GPIO_HPD_3:
314*b843c749SSergey Zigachev info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
315*b843c749SSergey Zigachev break;
316*b843c749SSergey Zigachev case GPIO_HPD_4:
317*b843c749SSergey Zigachev info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
318*b843c749SSergey Zigachev break;
319*b843c749SSergey Zigachev case GPIO_HPD_5:
320*b843c749SSergey Zigachev info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
321*b843c749SSergey Zigachev break;
322*b843c749SSergey Zigachev case GPIO_HPD_6:
323*b843c749SSergey Zigachev info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
324*b843c749SSergey Zigachev break;
325*b843c749SSergey Zigachev default:
326*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
327*b843c749SSergey Zigachev result = false;
328*b843c749SSergey Zigachev }
329*b843c749SSergey Zigachev break;
330*b843c749SSergey Zigachev case GPIO_ID_SYNC:
331*b843c749SSergey Zigachev switch (en) {
332*b843c749SSergey Zigachev case GPIO_SYNC_HSYNC_A:
333*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_SYNCA_A);
334*b843c749SSergey Zigachev info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
335*b843c749SSergey Zigachev break;
336*b843c749SSergey Zigachev case GPIO_SYNC_VSYNC_A:
337*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_SYNCA_A);
338*b843c749SSergey Zigachev info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
339*b843c749SSergey Zigachev break;
340*b843c749SSergey Zigachev case GPIO_SYNC_HSYNC_B:
341*b843c749SSergey Zigachev case GPIO_SYNC_VSYNC_B:
342*b843c749SSergey Zigachev default:
343*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
344*b843c749SSergey Zigachev result = false;
345*b843c749SSergey Zigachev }
346*b843c749SSergey Zigachev break;
347*b843c749SSergey Zigachev case GPIO_ID_GSL:
348*b843c749SSergey Zigachev switch (en) {
349*b843c749SSergey Zigachev case GPIO_GSL_GENLOCK_CLOCK:
350*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_GENLK_A);
351*b843c749SSergey Zigachev info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
352*b843c749SSergey Zigachev break;
353*b843c749SSergey Zigachev case GPIO_GSL_GENLOCK_VSYNC:
354*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_GENLK_A);
355*b843c749SSergey Zigachev info->mask =
356*b843c749SSergey Zigachev DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
357*b843c749SSergey Zigachev break;
358*b843c749SSergey Zigachev case GPIO_GSL_SWAPLOCK_A:
359*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_GENLK_A);
360*b843c749SSergey Zigachev info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
361*b843c749SSergey Zigachev break;
362*b843c749SSergey Zigachev case GPIO_GSL_SWAPLOCK_B:
363*b843c749SSergey Zigachev info->offset = REG(DC_GPIO_GENLK_A);
364*b843c749SSergey Zigachev info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
365*b843c749SSergey Zigachev break;
366*b843c749SSergey Zigachev default:
367*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
368*b843c749SSergey Zigachev result = false;
369*b843c749SSergey Zigachev }
370*b843c749SSergey Zigachev break;
371*b843c749SSergey Zigachev case GPIO_ID_VIP_PAD:
372*b843c749SSergey Zigachev default:
373*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
374*b843c749SSergey Zigachev result = false;
375*b843c749SSergey Zigachev }
376*b843c749SSergey Zigachev
377*b843c749SSergey Zigachev if (result) {
378*b843c749SSergey Zigachev info->offset_y = info->offset + 2;
379*b843c749SSergey Zigachev info->offset_en = info->offset + 1;
380*b843c749SSergey Zigachev info->offset_mask = info->offset - 1;
381*b843c749SSergey Zigachev
382*b843c749SSergey Zigachev info->mask_y = info->mask;
383*b843c749SSergey Zigachev info->mask_en = info->mask;
384*b843c749SSergey Zigachev info->mask_mask = info->mask;
385*b843c749SSergey Zigachev }
386*b843c749SSergey Zigachev
387*b843c749SSergey Zigachev return result;
388*b843c749SSergey Zigachev }
389*b843c749SSergey Zigachev
390*b843c749SSergey Zigachev /* function table */
391*b843c749SSergey Zigachev static const struct hw_translate_funcs funcs = {
392*b843c749SSergey Zigachev .offset_to_id = offset_to_id,
393*b843c749SSergey Zigachev .id_to_offset = id_to_offset,
394*b843c749SSergey Zigachev };
395*b843c749SSergey Zigachev
396*b843c749SSergey Zigachev /*
397*b843c749SSergey Zigachev * dal_hw_translate_dce120_init
398*b843c749SSergey Zigachev *
399*b843c749SSergey Zigachev * @brief
400*b843c749SSergey Zigachev * Initialize Hw translate function pointers.
401*b843c749SSergey Zigachev *
402*b843c749SSergey Zigachev * @param
403*b843c749SSergey Zigachev * struct hw_translate *tr - [out] struct of function pointers
404*b843c749SSergey Zigachev *
405*b843c749SSergey Zigachev */
dal_hw_translate_dce120_init(struct hw_translate * tr)406*b843c749SSergey Zigachev void dal_hw_translate_dce120_init(struct hw_translate *tr)
407*b843c749SSergey Zigachev {
408*b843c749SSergey Zigachev tr->funcs = &funcs;
409*b843c749SSergey Zigachev }
410