1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef __DC_CLOCK_SOURCE_H__ 27*b843c749SSergey Zigachev #define __DC_CLOCK_SOURCE_H__ 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #include "dc_types.h" 30*b843c749SSergey Zigachev #include "include/grph_object_id.h" 31*b843c749SSergey Zigachev #include "include/bios_parser_types.h" 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev struct clock_source; 34*b843c749SSergey Zigachev 35*b843c749SSergey Zigachev struct spread_spectrum_data { 36*b843c749SSergey Zigachev uint32_t percentage; /*> In unit of 0.01% or 0.001%*/ 37*b843c749SSergey Zigachev uint32_t percentage_divider; /*> 100 or 1000 */ 38*b843c749SSergey Zigachev uint32_t freq_range_khz; 39*b843c749SSergey Zigachev uint32_t modulation_freq_hz; 40*b843c749SSergey Zigachev 41*b843c749SSergey Zigachev struct spread_spectrum_flags flags; 42*b843c749SSergey Zigachev }; 43*b843c749SSergey Zigachev 44*b843c749SSergey Zigachev struct delta_sigma_data { 45*b843c749SSergey Zigachev uint32_t feedback_amount; 46*b843c749SSergey Zigachev uint32_t nfrac_amount; 47*b843c749SSergey Zigachev uint32_t ds_frac_size; 48*b843c749SSergey Zigachev uint32_t ds_frac_amount; 49*b843c749SSergey Zigachev }; 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev /** 52*b843c749SSergey Zigachev * Pixel Clock Parameters structure 53*b843c749SSergey Zigachev * These parameters are required as input 54*b843c749SSergey Zigachev * when calculating Pixel Clock Dividers for requested Pixel Clock 55*b843c749SSergey Zigachev */ 56*b843c749SSergey Zigachev struct pixel_clk_flags { 57*b843c749SSergey Zigachev uint32_t ENABLE_SS:1; 58*b843c749SSergey Zigachev uint32_t DISPLAY_BLANKED:1; 59*b843c749SSergey Zigachev uint32_t PROGRAM_PIXEL_CLOCK:1; 60*b843c749SSergey Zigachev uint32_t PROGRAM_ID_CLOCK:1; 61*b843c749SSergey Zigachev uint32_t SUPPORT_YCBCR420:1; 62*b843c749SSergey Zigachev }; 63*b843c749SSergey Zigachev 64*b843c749SSergey Zigachev /** 65*b843c749SSergey Zigachev * Display Port HW De spread of Reference Clock related Parameters structure 66*b843c749SSergey Zigachev * Store it once at boot for later usage 67*b843c749SSergey Zigachev */ 68*b843c749SSergey Zigachev struct csdp_ref_clk_ds_params { 69*b843c749SSergey Zigachev bool hw_dso_n_dp_ref_clk; 70*b843c749SSergey Zigachev /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/ 71*b843c749SSergey Zigachev uint32_t avg_dp_ref_clk_khz; 72*b843c749SSergey Zigachev /* Average DP Reference clock (in KHz)*/ 73*b843c749SSergey Zigachev uint32_t ss_percentage_on_dp_ref_clk; 74*b843c749SSergey Zigachev /* DP Reference clock SS percentage 75*b843c749SSergey Zigachev * (not to be mixed with DP IDCLK SS from PLL Settings)*/ 76*b843c749SSergey Zigachev uint32_t ss_percentage_divider; 77*b843c749SSergey Zigachev /* DP Reference clock SS percentage divider */ 78*b843c749SSergey Zigachev }; 79*b843c749SSergey Zigachev 80*b843c749SSergey Zigachev struct pixel_clk_params { 81*b843c749SSergey Zigachev uint32_t requested_pix_clk; /* in KHz */ 82*b843c749SSergey Zigachev /*> Requested Pixel Clock 83*b843c749SSergey Zigachev * (based on Video Timing standard used for requested mode)*/ 84*b843c749SSergey Zigachev uint32_t requested_sym_clk; /* in KHz */ 85*b843c749SSergey Zigachev /*> Requested Sym Clock (relevant only for display port)*/ 86*b843c749SSergey Zigachev uint32_t dp_ref_clk; /* in KHz */ 87*b843c749SSergey Zigachev /*> DP reference clock - calculated only for DP signal for specific cases*/ 88*b843c749SSergey Zigachev struct graphics_object_id encoder_object_id; 89*b843c749SSergey Zigachev /*> Encoder object Id - needed by VBIOS Exec table*/ 90*b843c749SSergey Zigachev enum signal_type signal_type; 91*b843c749SSergey Zigachev /*> signalType -> Encoder Mode - needed by VBIOS Exec table*/ 92*b843c749SSergey Zigachev enum controller_id controller_id; 93*b843c749SSergey Zigachev /*> ControllerId - which controller using this PLL*/ 94*b843c749SSergey Zigachev enum dc_color_depth color_depth; 95*b843c749SSergey Zigachev struct csdp_ref_clk_ds_params de_spread_params; 96*b843c749SSergey Zigachev /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/ 97*b843c749SSergey Zigachev enum dc_pixel_encoding pixel_encoding; 98*b843c749SSergey Zigachev struct pixel_clk_flags flags; 99*b843c749SSergey Zigachev }; 100*b843c749SSergey Zigachev 101*b843c749SSergey Zigachev /** 102*b843c749SSergey Zigachev * Pixel Clock Dividers structure with desired Pixel Clock 103*b843c749SSergey Zigachev * (adjusted after VBIOS exec table), 104*b843c749SSergey Zigachev * with actually calculated Clock and reference Crystal frequency 105*b843c749SSergey Zigachev */ 106*b843c749SSergey Zigachev struct pll_settings { 107*b843c749SSergey Zigachev uint32_t actual_pix_clk; 108*b843c749SSergey Zigachev uint32_t adjusted_pix_clk; 109*b843c749SSergey Zigachev uint32_t calculated_pix_clk; 110*b843c749SSergey Zigachev uint32_t vco_freq; 111*b843c749SSergey Zigachev uint32_t reference_freq; 112*b843c749SSergey Zigachev uint32_t reference_divider; 113*b843c749SSergey Zigachev uint32_t feedback_divider; 114*b843c749SSergey Zigachev uint32_t fract_feedback_divider; 115*b843c749SSergey Zigachev uint32_t pix_clk_post_divider; 116*b843c749SSergey Zigachev uint32_t ss_percentage; 117*b843c749SSergey Zigachev bool use_external_clk; 118*b843c749SSergey Zigachev }; 119*b843c749SSergey Zigachev 120*b843c749SSergey Zigachev struct calc_pll_clock_source_init_data { 121*b843c749SSergey Zigachev struct dc_bios *bp; 122*b843c749SSergey Zigachev uint32_t min_pix_clk_pll_post_divider; 123*b843c749SSergey Zigachev uint32_t max_pix_clk_pll_post_divider; 124*b843c749SSergey Zigachev uint32_t min_pll_ref_divider; 125*b843c749SSergey Zigachev uint32_t max_pll_ref_divider; 126*b843c749SSergey Zigachev uint32_t min_override_input_pxl_clk_pll_freq_khz; 127*b843c749SSergey Zigachev /* if not 0, override the firmware info */ 128*b843c749SSergey Zigachev 129*b843c749SSergey Zigachev uint32_t max_override_input_pxl_clk_pll_freq_khz; 130*b843c749SSergey Zigachev /* if not 0, override the firmware info */ 131*b843c749SSergey Zigachev 132*b843c749SSergey Zigachev uint32_t num_fract_fb_divider_decimal_point; 133*b843c749SSergey Zigachev /* number of decimal point for fractional feedback divider value */ 134*b843c749SSergey Zigachev 135*b843c749SSergey Zigachev uint32_t num_fract_fb_divider_decimal_point_precision; 136*b843c749SSergey Zigachev /* number of decimal point to round off for fractional feedback divider value*/ 137*b843c749SSergey Zigachev struct dc_context *ctx; 138*b843c749SSergey Zigachev 139*b843c749SSergey Zigachev }; 140*b843c749SSergey Zigachev 141*b843c749SSergey Zigachev struct calc_pll_clock_source { 142*b843c749SSergey Zigachev uint32_t ref_freq_khz; 143*b843c749SSergey Zigachev uint32_t min_pix_clock_pll_post_divider; 144*b843c749SSergey Zigachev uint32_t max_pix_clock_pll_post_divider; 145*b843c749SSergey Zigachev uint32_t min_pll_ref_divider; 146*b843c749SSergey Zigachev uint32_t max_pll_ref_divider; 147*b843c749SSergey Zigachev 148*b843c749SSergey Zigachev uint32_t max_vco_khz; 149*b843c749SSergey Zigachev uint32_t min_vco_khz; 150*b843c749SSergey Zigachev uint32_t min_pll_input_freq_khz; 151*b843c749SSergey Zigachev uint32_t max_pll_input_freq_khz; 152*b843c749SSergey Zigachev 153*b843c749SSergey Zigachev uint32_t fract_fb_divider_decimal_points_num; 154*b843c749SSergey Zigachev uint32_t fract_fb_divider_factor; 155*b843c749SSergey Zigachev uint32_t fract_fb_divider_precision; 156*b843c749SSergey Zigachev uint32_t fract_fb_divider_precision_factor; 157*b843c749SSergey Zigachev struct dc_context *ctx; 158*b843c749SSergey Zigachev }; 159*b843c749SSergey Zigachev 160*b843c749SSergey Zigachev struct clock_source_funcs { 161*b843c749SSergey Zigachev bool (*cs_power_down)( 162*b843c749SSergey Zigachev struct clock_source *); 163*b843c749SSergey Zigachev bool (*program_pix_clk)(struct clock_source *, 164*b843c749SSergey Zigachev struct pixel_clk_params *, struct pll_settings *); 165*b843c749SSergey Zigachev uint32_t (*get_pix_clk_dividers)( 166*b843c749SSergey Zigachev struct clock_source *, 167*b843c749SSergey Zigachev struct pixel_clk_params *, 168*b843c749SSergey Zigachev struct pll_settings *); 169*b843c749SSergey Zigachev uint32_t (*get_pix_rate_in_hz)( 170*b843c749SSergey Zigachev struct clock_source *, 171*b843c749SSergey Zigachev struct pixel_clk_params *, 172*b843c749SSergey Zigachev struct pll_settings *); 173*b843c749SSergey Zigachev }; 174*b843c749SSergey Zigachev 175*b843c749SSergey Zigachev struct clock_source { 176*b843c749SSergey Zigachev const struct clock_source_funcs *funcs; 177*b843c749SSergey Zigachev struct dc_context *ctx; 178*b843c749SSergey Zigachev enum clock_source_id id; 179*b843c749SSergey Zigachev bool dp_clk_src; 180*b843c749SSergey Zigachev }; 181*b843c749SSergey Zigachev 182*b843c749SSergey Zigachev #endif 183