1b843c749SSergey Zigachev /*
2b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc.
3b843c749SSergey Zigachev *
4b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10b843c749SSergey Zigachev *
11b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13b843c749SSergey Zigachev *
14b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21b843c749SSergey Zigachev *
22b843c749SSergey Zigachev */
23b843c749SSergey Zigachev
24b843c749SSergey Zigachev #include "hwmgr.h"
25b843c749SSergey Zigachev #include "vega10_hwmgr.h"
26b843c749SSergey Zigachev #include "vega10_powertune.h"
27b843c749SSergey Zigachev #include "vega10_ppsmc.h"
28b843c749SSergey Zigachev #include "vega10_inc.h"
29b843c749SSergey Zigachev #include "pp_debug.h"
30b843c749SSergey Zigachev #include "soc15_common.h"
31b843c749SSergey Zigachev
32b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] =
33b843c749SSergey Zigachev {
34b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
35b843c749SSergey Zigachev * Offset Mask Shift Value
36b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
37b843c749SSergey Zigachev */
38b843c749SSergey Zigachev /* DIDT_SQ */
39b843c749SSergey Zigachev { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853 },
40b843c749SSergey Zigachev { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153 },
41b843c749SSergey Zigachev
42b843c749SSergey Zigachev /* DIDT_TD */
43b843c749SSergey Zigachev { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde },
44b843c749SSergey Zigachev { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde },
45b843c749SSergey Zigachev
46b843c749SSergey Zigachev /* DIDT_TCP */
47b843c749SSergey Zigachev { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde },
48b843c749SSergey Zigachev { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde },
49b843c749SSergey Zigachev
50b843c749SSergey Zigachev /* DIDT_DB */
51b843c749SSergey Zigachev { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde },
52b843c749SSergey Zigachev { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde },
53b843c749SSergey Zigachev
54b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
55b843c749SSergey Zigachev };
56b843c749SSergey Zigachev
57b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] =
58b843c749SSergey Zigachev {
59b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
60b843c749SSergey Zigachev * Offset Mask Shift Value
61b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
62b843c749SSergey Zigachev */
63b843c749SSergey Zigachev /*DIDT_SQ_CTRL3 */
64b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
65b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
66b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK, DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
67b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
68b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
69b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
70b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
71b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
72b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
73b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK, DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
74b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
75b843c749SSergey Zigachev { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
76b843c749SSergey Zigachev
77b843c749SSergey Zigachev /*DIDT_TCP_CTRL3 */
78b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
79b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
80b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK, DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
81b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
82b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
83b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
84b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
85b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
86b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
87b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
88b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
89b843c749SSergey Zigachev { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
90b843c749SSergey Zigachev
91b843c749SSergey Zigachev /*DIDT_TD_CTRL3 */
92b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
93b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
94b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__THROTTLE_POLICY_MASK, DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
95b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
96b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
97b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
98b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
99b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
100b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
101b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
102b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
103b843c749SSergey Zigachev { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
104b843c749SSergey Zigachev
105b843c749SSergey Zigachev /*DIDT_DB_CTRL3 */
106b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
107b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
108b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__THROTTLE_POLICY_MASK, DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
109b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
110b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
111b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
112b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
113b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
114b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
115b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK, DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
116b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
117b843c749SSergey Zigachev { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
118b843c749SSergey Zigachev
119b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
120b843c749SSergey Zigachev };
121b843c749SSergey Zigachev
122b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] =
123b843c749SSergey Zigachev {
124b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
125b843c749SSergey Zigachev * Offset Mask Shift Value
126b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
127b843c749SSergey Zigachev */
128b843c749SSergey Zigachev /* DIDT_SQ */
129b843c749SSergey Zigachev { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853 },
130b843c749SSergey Zigachev { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
131b843c749SSergey Zigachev { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000 },
132b843c749SSergey Zigachev
133b843c749SSergey Zigachev /* DIDT_TD */
134b843c749SSergey Zigachev { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff },
135b843c749SSergey Zigachev { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
136b843c749SSergey Zigachev { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
137b843c749SSergey Zigachev
138b843c749SSergey Zigachev /* DIDT_TCP */
139b843c749SSergey Zigachev { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde },
140b843c749SSergey Zigachev { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
141b843c749SSergey Zigachev { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
142b843c749SSergey Zigachev
143b843c749SSergey Zigachev /* DIDT_DB */
144b843c749SSergey Zigachev { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK, DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde },
145b843c749SSergey Zigachev { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
146b843c749SSergey Zigachev { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
147b843c749SSergey Zigachev
148b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
149b843c749SSergey Zigachev };
150b843c749SSergey Zigachev
151b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] =
152b843c749SSergey Zigachev {
153b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
154b843c749SSergey Zigachev * Offset Mask Shift Value
155b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
156b843c749SSergey Zigachev */
157b843c749SSergey Zigachev /* DIDT_SQ */
158b843c749SSergey Zigachev { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000 },
159b843c749SSergey Zigachev { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff },
160b843c749SSergey Zigachev /* DIDT_TD */
161b843c749SSergey Zigachev { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000 },
162b843c749SSergey Zigachev { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff },
163b843c749SSergey Zigachev /* DIDT_TCP */
164b843c749SSergey Zigachev { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000 },
165b843c749SSergey Zigachev { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff },
166b843c749SSergey Zigachev /* DIDT_DB */
167b843c749SSergey Zigachev { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MIN_POWER_MASK, DIDT_DB_CTRL1__MIN_POWER__SHIFT, 0x0000 },
168b843c749SSergey Zigachev { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MAX_POWER_MASK, DIDT_DB_CTRL1__MAX_POWER__SHIFT, 0xffff },
169b843c749SSergey Zigachev
170b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
171b843c749SSergey Zigachev };
172b843c749SSergey Zigachev
173b843c749SSergey Zigachev
174b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] =
175b843c749SSergey Zigachev {
176b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
177b843c749SSergey Zigachev * Offset Mask Shift Value
178b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
179b843c749SSergey Zigachev */
180b843c749SSergey Zigachev /* DIDT_SQ */
181b843c749SSergey Zigachev { ixDIDT_SQ_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B363B1A },
182b843c749SSergey Zigachev { ixDIDT_SQ_WEIGHT4_7, 0xFFFFFFFF, 0, 0x270B2432 },
183b843c749SSergey Zigachev { ixDIDT_SQ_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000018 },
184b843c749SSergey Zigachev
185b843c749SSergey Zigachev /* DIDT_TD */
186b843c749SSergey Zigachev { ixDIDT_TD_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B1D220F },
187b843c749SSergey Zigachev { ixDIDT_TD_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00007558 },
188b843c749SSergey Zigachev { ixDIDT_TD_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 },
189b843c749SSergey Zigachev
190b843c749SSergey Zigachev /* DIDT_TCP */
191b843c749SSergey Zigachev { ixDIDT_TCP_WEIGHT0_3, 0xFFFFFFFF, 0, 0x5ACE160D },
192b843c749SSergey Zigachev { ixDIDT_TCP_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00000000 },
193b843c749SSergey Zigachev { ixDIDT_TCP_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 },
194b843c749SSergey Zigachev
195b843c749SSergey Zigachev /* DIDT_DB */
196b843c749SSergey Zigachev { ixDIDT_DB_WEIGHT0_3, 0xFFFFFFFF, 0, 0x0E152A0F },
197b843c749SSergey Zigachev { ixDIDT_DB_WEIGHT4_7, 0xFFFFFFFF, 0, 0x09061813 },
198b843c749SSergey Zigachev { ixDIDT_DB_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000013 },
199b843c749SSergey Zigachev
200b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
201b843c749SSergey Zigachev };
202b843c749SSergey Zigachev
203b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] =
204b843c749SSergey Zigachev {
205b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
206b843c749SSergey Zigachev * Offset Mask Shift Value
207b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
208b843c749SSergey Zigachev */
209b843c749SSergey Zigachev /* DIDT_SQ */
210b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
211b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
212b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
213b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
214b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
215b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
216b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
217b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
218b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
219b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
220b843c749SSergey Zigachev { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
221b843c749SSergey Zigachev /* DIDT_TD */
222b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
223b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
224b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
225b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
226b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
227b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
228b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
229b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
230b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
231b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
232b843c749SSergey Zigachev { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
233b843c749SSergey Zigachev /* DIDT_TCP */
234b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
235b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
236b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
237b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
238b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
239b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
240b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
241b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
242b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
243b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
244b843c749SSergey Zigachev { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
245b843c749SSergey Zigachev /* DIDT_DB */
246b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
247b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
248b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
249b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
250b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
251b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
252b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
253b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
254b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
255b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
256b843c749SSergey Zigachev { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
257b843c749SSergey Zigachev
258b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
259b843c749SSergey Zigachev };
260b843c749SSergey Zigachev
261b843c749SSergey Zigachev
262b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] =
263b843c749SSergey Zigachev {
264b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
265b843c749SSergey Zigachev * Offset Mask Shift Value
266b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
267b843c749SSergey Zigachev */
268b843c749SSergey Zigachev /* DIDT_SQ */
269b843c749SSergey Zigachev { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 },
270b843c749SSergey Zigachev { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 },
271b843c749SSergey Zigachev { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
272b843c749SSergey Zigachev { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
273b843c749SSergey Zigachev
274b843c749SSergey Zigachev /* DIDT_TD */
275b843c749SSergey Zigachev { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 },
276b843c749SSergey Zigachev { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 },
277b843c749SSergey Zigachev { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
278b843c749SSergey Zigachev { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
279b843c749SSergey Zigachev
280b843c749SSergey Zigachev /* DIDT_TCP */
281b843c749SSergey Zigachev { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 },
282b843c749SSergey Zigachev { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 },
283b843c749SSergey Zigachev { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
284b843c749SSergey Zigachev { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
285b843c749SSergey Zigachev
286b843c749SSergey Zigachev /* DIDT_DB */
287b843c749SSergey Zigachev { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 },
288b843c749SSergey Zigachev { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 },
289b843c749SSergey Zigachev { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
290b843c749SSergey Zigachev { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
291b843c749SSergey Zigachev
292b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
293b843c749SSergey Zigachev };
294b843c749SSergey Zigachev
295b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] =
296b843c749SSergey Zigachev {
297b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
298b843c749SSergey Zigachev * Offset Mask Shift Value
299b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
300b843c749SSergey Zigachev */
301b843c749SSergey Zigachev /* DIDT_SQ_STALL_PATTERN_1_2 */
302b843c749SSergey Zigachev { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
303b843c749SSergey Zigachev { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
304b843c749SSergey Zigachev
305b843c749SSergey Zigachev /* DIDT_SQ_STALL_PATTERN_3_4 */
306b843c749SSergey Zigachev { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
307b843c749SSergey Zigachev { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
308b843c749SSergey Zigachev
309b843c749SSergey Zigachev /* DIDT_SQ_STALL_PATTERN_5_6 */
310b843c749SSergey Zigachev { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
311b843c749SSergey Zigachev { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
312b843c749SSergey Zigachev
313b843c749SSergey Zigachev /* DIDT_SQ_STALL_PATTERN_7 */
314b843c749SSergey Zigachev { ixDIDT_SQ_STALL_PATTERN_7, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
315b843c749SSergey Zigachev
316b843c749SSergey Zigachev /* DIDT_TCP_STALL_PATTERN_1_2 */
317b843c749SSergey Zigachev { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
318b843c749SSergey Zigachev { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
319b843c749SSergey Zigachev
320b843c749SSergey Zigachev /* DIDT_TCP_STALL_PATTERN_3_4 */
321b843c749SSergey Zigachev { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
322b843c749SSergey Zigachev { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
323b843c749SSergey Zigachev
324b843c749SSergey Zigachev /* DIDT_TCP_STALL_PATTERN_5_6 */
325b843c749SSergey Zigachev { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
326b843c749SSergey Zigachev { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
327b843c749SSergey Zigachev
328b843c749SSergey Zigachev /* DIDT_TCP_STALL_PATTERN_7 */
329b843c749SSergey Zigachev { ixDIDT_TCP_STALL_PATTERN_7, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
330b843c749SSergey Zigachev
331b843c749SSergey Zigachev /* DIDT_TD_STALL_PATTERN_1_2 */
332b843c749SSergey Zigachev { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
333b843c749SSergey Zigachev { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
334b843c749SSergey Zigachev
335b843c749SSergey Zigachev /* DIDT_TD_STALL_PATTERN_3_4 */
336b843c749SSergey Zigachev { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
337b843c749SSergey Zigachev { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
338b843c749SSergey Zigachev
339b843c749SSergey Zigachev /* DIDT_TD_STALL_PATTERN_5_6 */
340b843c749SSergey Zigachev { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
341b843c749SSergey Zigachev { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
342b843c749SSergey Zigachev
343b843c749SSergey Zigachev /* DIDT_TD_STALL_PATTERN_7 */
344b843c749SSergey Zigachev { ixDIDT_TD_STALL_PATTERN_7, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
345b843c749SSergey Zigachev
346b843c749SSergey Zigachev /* DIDT_DB_STALL_PATTERN_1_2 */
347b843c749SSergey Zigachev { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
348b843c749SSergey Zigachev { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
349b843c749SSergey Zigachev
350b843c749SSergey Zigachev /* DIDT_DB_STALL_PATTERN_3_4 */
351b843c749SSergey Zigachev { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
352b843c749SSergey Zigachev { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
353b843c749SSergey Zigachev
354b843c749SSergey Zigachev /* DIDT_DB_STALL_PATTERN_5_6 */
355b843c749SSergey Zigachev { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
356b843c749SSergey Zigachev { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
357b843c749SSergey Zigachev
358b843c749SSergey Zigachev /* DIDT_DB_STALL_PATTERN_7 */
359b843c749SSergey Zigachev { ixDIDT_DB_STALL_PATTERN_7, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
360b843c749SSergey Zigachev
361b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
362b843c749SSergey Zigachev };
363b843c749SSergey Zigachev
364b843c749SSergey Zigachev static const struct vega10_didt_config_reg SELCacConfig_Vega10[] =
365b843c749SSergey Zigachev {
366b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
367b843c749SSergey Zigachev * Offset Mask Shift Value
368b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
369b843c749SSergey Zigachev */
370b843c749SSergey Zigachev /* SQ */
371b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060021 },
372b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860021 },
373b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060021 },
374b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860021 },
375b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060021 },
376b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860021 },
377b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060021 },
378b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860021 },
379b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060021 },
380b843c749SSergey Zigachev /* TD */
381b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0020 },
382b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0020 },
383b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0020 },
384b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0020 },
385b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0020 },
386b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x028E0020 },
387b843c749SSergey Zigachev /* TCP */
388b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x001c0020 },
389b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x009c0020 },
390b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x011c0020 },
391b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x019c0020 },
392b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x021c0020 },
393b843c749SSergey Zigachev /* DB */
394b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00200008 },
395b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00820008 },
396b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01020008 },
397b843c749SSergey Zigachev { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01820008 },
398b843c749SSergey Zigachev
399b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
400b843c749SSergey Zigachev };
401b843c749SSergey Zigachev
402b843c749SSergey Zigachev
403b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] =
404b843c749SSergey Zigachev {
405b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
406b843c749SSergey Zigachev * Offset Mask Shift Value
407b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
408b843c749SSergey Zigachev */
409b843c749SSergey Zigachev /* SQ */
410b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00030001 },
411b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x000F0007 },
412b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x003F001F },
413b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x0000007F },
414b843c749SSergey Zigachev /* TD */
415b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
416b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
417b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
418b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
419b843c749SSergey Zigachev /* TCP */
420b843c749SSergey Zigachev { ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
421b843c749SSergey Zigachev { ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
422b843c749SSergey Zigachev { ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
423b843c749SSergey Zigachev { ixDIDT_TCP_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
424b843c749SSergey Zigachev /* DB */
425b843c749SSergey Zigachev { ixDIDT_DB_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
426b843c749SSergey Zigachev { ixDIDT_DB_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
427b843c749SSergey Zigachev { ixDIDT_DB_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
428b843c749SSergey Zigachev { ixDIDT_DB_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
429b843c749SSergey Zigachev
430b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
431b843c749SSergey Zigachev };
432b843c749SSergey Zigachev
433b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] =
434b843c749SSergey Zigachev {
435b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
436b843c749SSergey Zigachev * Offset Mask Shift Value
437b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
438b843c749SSergey Zigachev */
439b843c749SSergey Zigachev /* SQ */
440b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 },
441b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
442b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
443b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
444b843c749SSergey Zigachev /* TD */
445b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 },
446b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
447b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
448b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
449b843c749SSergey Zigachev
450b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
451b843c749SSergey Zigachev };
452b843c749SSergey Zigachev
453b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] =
454b843c749SSergey Zigachev {
455b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
456b843c749SSergey Zigachev * Offset Mask Shift Value
457b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
458b843c749SSergey Zigachev */
459b843c749SSergey Zigachev /* SQ */
460b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
461b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
462b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
463b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
464b843c749SSergey Zigachev /* TD */
465b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
466b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
467b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
468b843c749SSergey Zigachev { ixDIDT_TD_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
469b843c749SSergey Zigachev /* TCP */
470b843c749SSergey Zigachev { ixDIDT_TCP_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
471b843c749SSergey Zigachev { ixDIDT_TCP_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
472b843c749SSergey Zigachev { ixDIDT_TCP_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
473b843c749SSergey Zigachev { ixDIDT_TCP_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
474b843c749SSergey Zigachev /* DB */
475b843c749SSergey Zigachev { ixDIDT_DB_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
476b843c749SSergey Zigachev
477b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
478b843c749SSergey Zigachev };
479b843c749SSergey Zigachev
480b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] =
481b843c749SSergey Zigachev {
482b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
483b843c749SSergey Zigachev * Offset Mask Shift Value
484b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
485b843c749SSergey Zigachev */
486b843c749SSergey Zigachev { ixDIDT_SQ_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0x0000010E },
487b843c749SSergey Zigachev { ixDIDT_TD_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
488b843c749SSergey Zigachev { ixDIDT_TCP_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
489b843c749SSergey Zigachev { ixDIDT_DB_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
490b843c749SSergey Zigachev
491b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
492b843c749SSergey Zigachev };
493b843c749SSergey Zigachev
494b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] =
495b843c749SSergey Zigachev {
496b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
497b843c749SSergey Zigachev * Offset Mask Shift Value
498b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
499b843c749SSergey Zigachev */
500b843c749SSergey Zigachev /* SQ */
501b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
502b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
503b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
504b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
505b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
506b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 },
507b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
508b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
509b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
510b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
511b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
512b843c749SSergey Zigachev
513b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
514b843c749SSergey Zigachev };
515b843c749SSergey Zigachev
516b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] =
517b843c749SSergey Zigachev {
518b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
519b843c749SSergey Zigachev * Offset Mask Shift Value
520b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
521b843c749SSergey Zigachev */
522b843c749SSergey Zigachev /* SQ */
523b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
524b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
525b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
526b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
527b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0004 },
528b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0006 },
529b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
530b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
531b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
532b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
533b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
534b843c749SSergey Zigachev
535b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
536b843c749SSergey Zigachev };
537b843c749SSergey Zigachev
538b843c749SSergey Zigachev static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] =
539b843c749SSergey Zigachev {
540b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
541b843c749SSergey Zigachev * Offset Mask Shift Value
542b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
543b843c749SSergey Zigachev */
544b843c749SSergey Zigachev /* SQ */
545b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
546b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
547b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
548b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 },
549b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 },
550b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000C },
551b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
552b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
553b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
554b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
555b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
556b843c749SSergey Zigachev
557b843c749SSergey Zigachev /* TD */
558b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
559b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
560b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
561b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 },
562b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 },
563b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E },
564b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
565b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
566b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
567b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
568b843c749SSergey Zigachev { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
569b843c749SSergey Zigachev
570b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
571b843c749SSergey Zigachev };
572b843c749SSergey Zigachev
573b843c749SSergey Zigachev static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] =
574b843c749SSergey Zigachev {
575b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
576b843c749SSergey Zigachev * Offset Mask Shift Value
577b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
578b843c749SSergey Zigachev */
579b843c749SSergey Zigachev { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT, 0x0000 },
580b843c749SSergey Zigachev { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT, 0x0000 },
581b843c749SSergey Zigachev { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT, 0x0000 },
582b843c749SSergey Zigachev { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT, 0x0000 },
583b843c749SSergey Zigachev { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT, 0x0000 },
584b843c749SSergey Zigachev
585b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
586b843c749SSergey Zigachev };
587b843c749SSergey Zigachev
588b843c749SSergey Zigachev static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] =
589b843c749SSergey Zigachev {
590b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
591b843c749SSergey Zigachev * Offset Mask Shift Value
592b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
593b843c749SSergey Zigachev */
594b843c749SSergey Zigachev { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK, GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
595b843c749SSergey Zigachev { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__PHASE_OFFSET_MASK, GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
596b843c749SSergey Zigachev { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_SW_RST_MASK, GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT, 0x0000 },
597b843c749SSergey Zigachev { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
598b843c749SSergey Zigachev { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
599b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
600b843c749SSergey Zigachev };
601b843c749SSergey Zigachev
602b843c749SSergey Zigachev
603b843c749SSergey Zigachev static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[] =
604b843c749SSergey Zigachev {
605b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
606b843c749SSergey Zigachev * Offset Mask Shift Value
607b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
608b843c749SSergey Zigachev */
609b843c749SSergey Zigachev /* SQ EDC STALL PATTERNs */
610b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT, 0x0101 },
611b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT, 0x0101 },
612b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT, 0x1111 },
613b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT, 0x1111 },
614b843c749SSergey Zigachev
615b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT, 0x1515 },
616b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT, 0x1515 },
617b843c749SSergey Zigachev
618b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_PATTERN_7, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT, 0x5555 },
619b843c749SSergey Zigachev
620b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
621b843c749SSergey Zigachev };
622b843c749SSergey Zigachev
623b843c749SSergey Zigachev static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] =
624b843c749SSergey Zigachev {
625b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
626b843c749SSergey Zigachev * Offset Mask Shift Value
627b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
628b843c749SSergey Zigachev */
629b843c749SSergey Zigachev /* SQ EDC STALL DELAYs */
630b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT, 0x0000 },
631b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT, 0x0000 },
632b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT, 0x0000 },
633b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT, 0x0000 },
634b843c749SSergey Zigachev
635b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT, 0x0000 },
636b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT, 0x0000 },
637b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT, 0x0000 },
638b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT, 0x0000 },
639b843c749SSergey Zigachev
640b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT, 0x0000 },
641b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT, 0x0000 },
642b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 },
643b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 },
644b843c749SSergey Zigachev
645b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 },
646b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 },
647b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 },
648b843c749SSergey Zigachev { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 },
649b843c749SSergey Zigachev
650b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
651b843c749SSergey Zigachev };
652b843c749SSergey Zigachev
653*78973132SSergey Zigachev #if 0
654b843c749SSergey Zigachev static const struct vega10_didt_config_reg PSMSEEDCThresholdConfig_Vega10[] =
655b843c749SSergey Zigachev {
656b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
657b843c749SSergey Zigachev * Offset Mask Shift Value
658b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
659b843c749SSergey Zigachev */
660b843c749SSergey Zigachev /* SQ EDC THRESHOLD */
661b843c749SSergey Zigachev { ixDIDT_SQ_EDC_THRESHOLD, DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK, DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT, 0x0000 },
662b843c749SSergey Zigachev
663b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
664b843c749SSergey Zigachev };
665*78973132SSergey Zigachev #endif
666b843c749SSergey Zigachev
667b843c749SSergey Zigachev static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] =
668b843c749SSergey Zigachev {
669b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
670b843c749SSergey Zigachev * Offset Mask Shift Value
671b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
672b843c749SSergey Zigachev */
673b843c749SSergey Zigachev /* SQ EDC CTRL */
674b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
675b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
676b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
677b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
678b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
679b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 },
680b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
681b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
682b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
683b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
684b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
685b843c749SSergey Zigachev
686b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
687b843c749SSergey Zigachev };
688b843c749SSergey Zigachev
689b843c749SSergey Zigachev static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] =
690b843c749SSergey Zigachev {
691b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
692b843c749SSergey Zigachev * Offset Mask Shift Value
693b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
694b843c749SSergey Zigachev */
695b843c749SSergey Zigachev /* SQ EDC CTRL */
696b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
697b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
698b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
699b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
700b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
701b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E },
702b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
703b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0001 },
704b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0003 },
705b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
706b843c749SSergey Zigachev { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
707b843c749SSergey Zigachev
708b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
709b843c749SSergey Zigachev };
710b843c749SSergey Zigachev
711*78973132SSergey Zigachev #if 0
712b843c749SSergey Zigachev static const struct vega10_didt_config_reg PSMGCEDCThresholdConfig_vega10[] =
713b843c749SSergey Zigachev {
714b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
715b843c749SSergey Zigachev * Offset Mask Shift Value
716b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
717b843c749SSergey Zigachev */
718b843c749SSergey Zigachev { mmGC_EDC_THRESHOLD, GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK, GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT, 0x0000000 },
719b843c749SSergey Zigachev
720b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
721b843c749SSergey Zigachev };
722*78973132SSergey Zigachev #endif
723b843c749SSergey Zigachev
724b843c749SSergey Zigachev static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] =
725b843c749SSergey Zigachev {
726b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
727b843c749SSergey Zigachev * Offset Mask Shift Value
728b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
729b843c749SSergey Zigachev */
730b843c749SSergey Zigachev { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT, 0x0001 },
731b843c749SSergey Zigachev { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT, 0x0384 },
732b843c749SSergey Zigachev { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT, 0x0001 },
733b843c749SSergey Zigachev { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK, GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT, 0x0001 },
734b843c749SSergey Zigachev { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT, 0x0001 },
735b843c749SSergey Zigachev
736b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
737b843c749SSergey Zigachev };
738b843c749SSergey Zigachev
739b843c749SSergey Zigachev static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] =
740b843c749SSergey Zigachev {
741b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
742b843c749SSergey Zigachev * Offset Mask Shift Value
743b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
744b843c749SSergey Zigachev */
745b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
746b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
747b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
748b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
749b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
750b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
751b843c749SSergey Zigachev
752b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
753b843c749SSergey Zigachev };
754b843c749SSergey Zigachev
755b843c749SSergey Zigachev static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] =
756b843c749SSergey Zigachev {
757b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
758b843c749SSergey Zigachev * Offset Mask Shift Value
759b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
760b843c749SSergey Zigachev */
761b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
762b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
763b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
764b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
765b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
766b843c749SSergey Zigachev { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
767b843c749SSergey Zigachev
768b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
769b843c749SSergey Zigachev };
770b843c749SSergey Zigachev
771b843c749SSergey Zigachev static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[]=
772b843c749SSergey Zigachev {
773b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
774b843c749SSergey Zigachev * Offset Mask Shift Value
775b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
776b843c749SSergey Zigachev */
777b843c749SSergey Zigachev { 0x16A02, 0xFFFFFFFF, 0x0, 0x0000005F },
778b843c749SSergey Zigachev { 0x16A05, 0xFFFFFFFF, 0x0, 0x00000001 },
779b843c749SSergey Zigachev { 0x16A06, 0x00000001, 0x0, 0x02000000 },
780b843c749SSergey Zigachev { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 },
781b843c749SSergey Zigachev
782b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
783b843c749SSergey Zigachev };
784b843c749SSergey Zigachev
785b843c749SSergey Zigachev static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] =
786b843c749SSergey Zigachev {
787b843c749SSergey Zigachev /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
788b843c749SSergey Zigachev * Offset Mask Shift Value
789b843c749SSergey Zigachev * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
790b843c749SSergey Zigachev */
791b843c749SSergey Zigachev { 0x16A05, 0xFFFFFFFF, 0x18, 0x00000001 },
792b843c749SSergey Zigachev { 0x16A05, 0xFFFFFFFF, 0x8, 0x00000003 },
793b843c749SSergey Zigachev { 0x16A05, 0xFFFFFFFF, 0xa, 0x00000006 },
794b843c749SSergey Zigachev { 0x16A05, 0xFFFFFFFF, 0x7, 0x00000000 },
795b843c749SSergey Zigachev { 0x16A06, 0xFFFFFFFF, 0x18, 0x00000001 },
796b843c749SSergey Zigachev { 0x16A06, 0xFFFFFFFF, 0x19, 0x00000001 },
797b843c749SSergey Zigachev { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 },
798b843c749SSergey Zigachev
799b843c749SSergey Zigachev { 0xFFFFFFFF } /* End of list */
800b843c749SSergey Zigachev };
801b843c749SSergey Zigachev
vega10_program_didt_config_registers(struct pp_hwmgr * hwmgr,const struct vega10_didt_config_reg * config_regs,enum vega10_didt_config_reg_type reg_type)802b843c749SSergey Zigachev static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type)
803b843c749SSergey Zigachev {
804b843c749SSergey Zigachev uint32_t data;
805b843c749SSergey Zigachev
806b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);
807b843c749SSergey Zigachev
808b843c749SSergey Zigachev while (config_regs->offset != 0xFFFFFFFF) {
809b843c749SSergey Zigachev switch (reg_type) {
810b843c749SSergey Zigachev case VEGA10_CONFIGREG_DIDT:
811b843c749SSergey Zigachev data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
812b843c749SSergey Zigachev data &= ~config_regs->mask;
813b843c749SSergey Zigachev data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
814b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
815b843c749SSergey Zigachev break;
816b843c749SSergey Zigachev case VEGA10_CONFIGREG_GCCAC:
817b843c749SSergey Zigachev data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
818b843c749SSergey Zigachev data &= ~config_regs->mask;
819b843c749SSergey Zigachev data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
820b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
821b843c749SSergey Zigachev break;
822b843c749SSergey Zigachev case VEGA10_CONFIGREG_SECAC:
823b843c749SSergey Zigachev data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset);
824b843c749SSergey Zigachev data &= ~config_regs->mask;
825b843c749SSergey Zigachev data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
826b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data);
827b843c749SSergey Zigachev break;
828b843c749SSergey Zigachev default:
829b843c749SSergey Zigachev return -EINVAL;
830b843c749SSergey Zigachev }
831b843c749SSergey Zigachev
832b843c749SSergey Zigachev config_regs++;
833b843c749SSergey Zigachev }
834b843c749SSergey Zigachev
835b843c749SSergey Zigachev return 0;
836b843c749SSergey Zigachev }
837b843c749SSergey Zigachev
vega10_program_gc_didt_config_registers(struct pp_hwmgr * hwmgr,const struct vega10_didt_config_reg * config_regs)838b843c749SSergey Zigachev static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs)
839b843c749SSergey Zigachev {
840b843c749SSergey Zigachev uint32_t data;
841b843c749SSergey Zigachev
842b843c749SSergey Zigachev while (config_regs->offset != 0xFFFFFFFF) {
843b843c749SSergey Zigachev data = cgs_read_register(hwmgr->device, config_regs->offset);
844b843c749SSergey Zigachev data &= ~config_regs->mask;
845b843c749SSergey Zigachev data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
846b843c749SSergey Zigachev cgs_write_register(hwmgr->device, config_regs->offset, data);
847b843c749SSergey Zigachev config_regs++;
848b843c749SSergey Zigachev }
849b843c749SSergey Zigachev
850b843c749SSergey Zigachev return 0;
851b843c749SSergey Zigachev }
852b843c749SSergey Zigachev
vega10_didt_set_mask(struct pp_hwmgr * hwmgr,const bool enable)853b843c749SSergey Zigachev static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
854b843c749SSergey Zigachev {
855b843c749SSergey Zigachev uint32_t data;
856b843c749SSergey Zigachev uint32_t en = (enable ? 1 : 0);
857b843c749SSergey Zigachev uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
858b843c749SSergey Zigachev
859b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
860b843c749SSergey Zigachev CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
861b843c749SSergey Zigachev DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
862b843c749SSergey Zigachev didt_block_info &= ~SQ_Enable_MASK;
863b843c749SSergey Zigachev didt_block_info |= en << SQ_Enable_SHIFT;
864b843c749SSergey Zigachev }
865b843c749SSergey Zigachev
866b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
867b843c749SSergey Zigachev CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
868b843c749SSergey Zigachev DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
869b843c749SSergey Zigachev didt_block_info &= ~DB_Enable_MASK;
870b843c749SSergey Zigachev didt_block_info |= en << DB_Enable_SHIFT;
871b843c749SSergey Zigachev }
872b843c749SSergey Zigachev
873b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
874b843c749SSergey Zigachev CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
875b843c749SSergey Zigachev DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
876b843c749SSergey Zigachev didt_block_info &= ~TD_Enable_MASK;
877b843c749SSergey Zigachev didt_block_info |= en << TD_Enable_SHIFT;
878b843c749SSergey Zigachev }
879b843c749SSergey Zigachev
880b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
881b843c749SSergey Zigachev CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
882b843c749SSergey Zigachev DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
883b843c749SSergey Zigachev didt_block_info &= ~TCP_Enable_MASK;
884b843c749SSergey Zigachev didt_block_info |= en << TCP_Enable_SHIFT;
885b843c749SSergey Zigachev }
886b843c749SSergey Zigachev
887b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
888b843c749SSergey Zigachev CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
889b843c749SSergey Zigachev DIDT_DBR_CTRL0, DIDT_CTRL_EN, en);
890b843c749SSergey Zigachev }
891b843c749SSergey Zigachev
892b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
893b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
894b843c749SSergey Zigachev data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
895b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
896b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
897b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
898b843c749SSergey Zigachev }
899b843c749SSergey Zigachev
900b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
901b843c749SSergey Zigachev data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
902b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
903b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
904b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
905b843c749SSergey Zigachev }
906b843c749SSergey Zigachev
907b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
908b843c749SSergey Zigachev data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
909b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
910b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
911b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
912b843c749SSergey Zigachev }
913b843c749SSergey Zigachev
914b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
915b843c749SSergey Zigachev data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
916b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
917b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
918b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
919b843c749SSergey Zigachev }
920b843c749SSergey Zigachev
921b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
922b843c749SSergey Zigachev data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
923b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
924b843c749SSergey Zigachev data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
925b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
926b843c749SSergey Zigachev }
927b843c749SSergey Zigachev }
928b843c749SSergey Zigachev
929b843c749SSergey Zigachev /* For Vega10, SMC does not support any mask yet. */
930b843c749SSergey Zigachev if (enable)
931b843c749SSergey Zigachev smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
932b843c749SSergey Zigachev
933b843c749SSergey Zigachev }
934b843c749SSergey Zigachev
vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr * hwmgr)935b843c749SSergey Zigachev static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
936b843c749SSergey Zigachev {
937b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
938b843c749SSergey Zigachev int result;
939b843c749SSergey Zigachev uint32_t num_se = 0, count, data;
940b843c749SSergey Zigachev
941b843c749SSergey Zigachev num_se = adev->gfx.config.max_shader_engines;
942b843c749SSergey Zigachev
943b843c749SSergey Zigachev adev->gfx.rlc.funcs->enter_safe_mode(adev);
944b843c749SSergey Zigachev
945b843c749SSergey Zigachev mutex_lock(&adev->grbm_idx_mutex);
946b843c749SSergey Zigachev for (count = 0; count < num_se; count++) {
947b843c749SSergey Zigachev data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
948b843c749SSergey Zigachev WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
949b843c749SSergey Zigachev
950b843c749SSergey Zigachev result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
951b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
952b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
953b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT);
954b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT);
955b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
956b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
957b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC);
958b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
959b843c749SSergey Zigachev
960b843c749SSergey Zigachev if (0 != result)
961b843c749SSergey Zigachev break;
962b843c749SSergey Zigachev }
963b843c749SSergey Zigachev WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
964b843c749SSergey Zigachev mutex_unlock(&adev->grbm_idx_mutex);
965b843c749SSergey Zigachev
966b843c749SSergey Zigachev vega10_didt_set_mask(hwmgr, true);
967b843c749SSergey Zigachev
968b843c749SSergey Zigachev adev->gfx.rlc.funcs->exit_safe_mode(adev);
969b843c749SSergey Zigachev
970b843c749SSergey Zigachev return 0;
971b843c749SSergey Zigachev }
972b843c749SSergey Zigachev
vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr * hwmgr)973b843c749SSergey Zigachev static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
974b843c749SSergey Zigachev {
975b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
976b843c749SSergey Zigachev
977b843c749SSergey Zigachev adev->gfx.rlc.funcs->enter_safe_mode(adev);
978b843c749SSergey Zigachev
979b843c749SSergey Zigachev vega10_didt_set_mask(hwmgr, false);
980b843c749SSergey Zigachev
981b843c749SSergey Zigachev adev->gfx.rlc.funcs->exit_safe_mode(adev);
982b843c749SSergey Zigachev
983b843c749SSergey Zigachev return 0;
984b843c749SSergey Zigachev }
985b843c749SSergey Zigachev
vega10_enable_psm_gc_didt_config(struct pp_hwmgr * hwmgr)986b843c749SSergey Zigachev static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
987b843c749SSergey Zigachev {
988b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
989b843c749SSergey Zigachev int result;
990b843c749SSergey Zigachev uint32_t num_se = 0, count, data;
991b843c749SSergey Zigachev
992b843c749SSergey Zigachev num_se = adev->gfx.config.max_shader_engines;
993b843c749SSergey Zigachev
994b843c749SSergey Zigachev adev->gfx.rlc.funcs->enter_safe_mode(adev);
995b843c749SSergey Zigachev
996b843c749SSergey Zigachev mutex_lock(&adev->grbm_idx_mutex);
997b843c749SSergey Zigachev for (count = 0; count < num_se; count++) {
998b843c749SSergey Zigachev data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
999b843c749SSergey Zigachev WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1000b843c749SSergey Zigachev
1001b843c749SSergey Zigachev result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
1002b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
1003b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
1004b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
1005b843c749SSergey Zigachev if (0 != result)
1006b843c749SSergey Zigachev break;
1007b843c749SSergey Zigachev }
1008b843c749SSergey Zigachev WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1009b843c749SSergey Zigachev mutex_unlock(&adev->grbm_idx_mutex);
1010b843c749SSergey Zigachev
1011b843c749SSergey Zigachev vega10_didt_set_mask(hwmgr, true);
1012b843c749SSergey Zigachev
1013b843c749SSergey Zigachev adev->gfx.rlc.funcs->exit_safe_mode(adev);
1014b843c749SSergey Zigachev
1015b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
1016b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_GCEDC))
1017b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
1018b843c749SSergey Zigachev
1019b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_PSM))
1020b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
1021b843c749SSergey Zigachev
1022b843c749SSergey Zigachev return 0;
1023b843c749SSergey Zigachev }
1024b843c749SSergey Zigachev
vega10_disable_psm_gc_didt_config(struct pp_hwmgr * hwmgr)1025b843c749SSergey Zigachev static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
1026b843c749SSergey Zigachev {
1027b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
1028b843c749SSergey Zigachev uint32_t data;
1029b843c749SSergey Zigachev
1030b843c749SSergey Zigachev adev->gfx.rlc.funcs->enter_safe_mode(adev);
1031b843c749SSergey Zigachev
1032b843c749SSergey Zigachev vega10_didt_set_mask(hwmgr, false);
1033b843c749SSergey Zigachev
1034b843c749SSergey Zigachev adev->gfx.rlc.funcs->exit_safe_mode(adev);
1035b843c749SSergey Zigachev
1036b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1037b843c749SSergey Zigachev data = 0x00000000;
1038b843c749SSergey Zigachev cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
1039b843c749SSergey Zigachev }
1040b843c749SSergey Zigachev
1041b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_PSM))
1042b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1043b843c749SSergey Zigachev
1044b843c749SSergey Zigachev return 0;
1045b843c749SSergey Zigachev }
1046b843c749SSergey Zigachev
vega10_enable_se_edc_config(struct pp_hwmgr * hwmgr)1047b843c749SSergey Zigachev static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
1048b843c749SSergey Zigachev {
1049b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
1050b843c749SSergey Zigachev int result;
1051b843c749SSergey Zigachev uint32_t num_se = 0, count, data;
1052b843c749SSergey Zigachev
1053b843c749SSergey Zigachev num_se = adev->gfx.config.max_shader_engines;
1054b843c749SSergey Zigachev
1055b843c749SSergey Zigachev adev->gfx.rlc.funcs->enter_safe_mode(adev);
1056b843c749SSergey Zigachev
1057b843c749SSergey Zigachev mutex_lock(&adev->grbm_idx_mutex);
1058b843c749SSergey Zigachev for (count = 0; count < num_se; count++) {
1059b843c749SSergey Zigachev data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1060b843c749SSergey Zigachev WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1061b843c749SSergey Zigachev result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1062b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1063b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1064b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1065b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1066b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1067b843c749SSergey Zigachev
1068b843c749SSergey Zigachev if (0 != result)
1069b843c749SSergey Zigachev break;
1070b843c749SSergey Zigachev }
1071b843c749SSergey Zigachev WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1072b843c749SSergey Zigachev mutex_unlock(&adev->grbm_idx_mutex);
1073b843c749SSergey Zigachev
1074b843c749SSergey Zigachev vega10_didt_set_mask(hwmgr, true);
1075b843c749SSergey Zigachev
1076b843c749SSergey Zigachev adev->gfx.rlc.funcs->exit_safe_mode(adev);
1077b843c749SSergey Zigachev
1078b843c749SSergey Zigachev return 0;
1079b843c749SSergey Zigachev }
1080b843c749SSergey Zigachev
vega10_disable_se_edc_config(struct pp_hwmgr * hwmgr)1081b843c749SSergey Zigachev static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr)
1082b843c749SSergey Zigachev {
1083b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
1084b843c749SSergey Zigachev
1085b843c749SSergey Zigachev adev->gfx.rlc.funcs->enter_safe_mode(adev);
1086b843c749SSergey Zigachev
1087b843c749SSergey Zigachev vega10_didt_set_mask(hwmgr, false);
1088b843c749SSergey Zigachev
1089b843c749SSergey Zigachev adev->gfx.rlc.funcs->exit_safe_mode(adev);
1090b843c749SSergey Zigachev
1091b843c749SSergey Zigachev return 0;
1092b843c749SSergey Zigachev }
1093b843c749SSergey Zigachev
vega10_enable_psm_gc_edc_config(struct pp_hwmgr * hwmgr)1094b843c749SSergey Zigachev static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1095b843c749SSergey Zigachev {
1096b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
1097b843c749SSergey Zigachev int result = 0;
1098b843c749SSergey Zigachev uint32_t num_se = 0;
1099b843c749SSergey Zigachev uint32_t count, data;
1100b843c749SSergey Zigachev
1101b843c749SSergey Zigachev num_se = adev->gfx.config.max_shader_engines;
1102b843c749SSergey Zigachev
1103b843c749SSergey Zigachev adev->gfx.rlc.funcs->enter_safe_mode(adev);
1104b843c749SSergey Zigachev
1105b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1106b843c749SSergey Zigachev
1107b843c749SSergey Zigachev mutex_lock(&adev->grbm_idx_mutex);
1108b843c749SSergey Zigachev for (count = 0; count < num_se; count++) {
1109b843c749SSergey Zigachev data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1110b843c749SSergey Zigachev WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1111b843c749SSergey Zigachev result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1112b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1113b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1114b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1115b843c749SSergey Zigachev
1116b843c749SSergey Zigachev if (0 != result)
1117b843c749SSergey Zigachev break;
1118b843c749SSergey Zigachev }
1119b843c749SSergey Zigachev WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1120b843c749SSergey Zigachev mutex_unlock(&adev->grbm_idx_mutex);
1121b843c749SSergey Zigachev
1122b843c749SSergey Zigachev vega10_didt_set_mask(hwmgr, true);
1123b843c749SSergey Zigachev
1124b843c749SSergey Zigachev adev->gfx.rlc.funcs->exit_safe_mode(adev);
1125b843c749SSergey Zigachev
1126b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
1127b843c749SSergey Zigachev
1128b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1129b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
1130b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
1131b843c749SSergey Zigachev }
1132b843c749SSergey Zigachev
1133b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_PSM))
1134b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
1135b843c749SSergey Zigachev
1136b843c749SSergey Zigachev return 0;
1137b843c749SSergey Zigachev }
1138b843c749SSergey Zigachev
vega10_disable_psm_gc_edc_config(struct pp_hwmgr * hwmgr)1139b843c749SSergey Zigachev static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1140b843c749SSergey Zigachev {
1141b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
1142b843c749SSergey Zigachev uint32_t data;
1143b843c749SSergey Zigachev
1144b843c749SSergey Zigachev adev->gfx.rlc.funcs->enter_safe_mode(adev);
1145b843c749SSergey Zigachev
1146b843c749SSergey Zigachev vega10_didt_set_mask(hwmgr, false);
1147b843c749SSergey Zigachev
1148b843c749SSergey Zigachev adev->gfx.rlc.funcs->exit_safe_mode(adev);
1149b843c749SSergey Zigachev
1150b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1151b843c749SSergey Zigachev data = 0x00000000;
1152b843c749SSergey Zigachev cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
1153b843c749SSergey Zigachev }
1154b843c749SSergey Zigachev
1155b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_PSM))
1156b843c749SSergey Zigachev vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1157b843c749SSergey Zigachev
1158b843c749SSergey Zigachev return 0;
1159b843c749SSergey Zigachev }
1160b843c749SSergey Zigachev
vega10_enable_se_edc_force_stall_config(struct pp_hwmgr * hwmgr)1161b843c749SSergey Zigachev static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1162b843c749SSergey Zigachev {
1163b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
1164b843c749SSergey Zigachev int result;
1165b843c749SSergey Zigachev
1166b843c749SSergey Zigachev adev->gfx.rlc.funcs->enter_safe_mode(adev);
1167b843c749SSergey Zigachev
1168b843c749SSergey Zigachev mutex_lock(&adev->grbm_idx_mutex);
1169b843c749SSergey Zigachev WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1170b843c749SSergey Zigachev mutex_unlock(&adev->grbm_idx_mutex);
1171b843c749SSergey Zigachev
1172b843c749SSergey Zigachev result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1173b843c749SSergey Zigachev result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1174b843c749SSergey Zigachev if (0 != result)
1175b843c749SSergey Zigachev return result;
1176b843c749SSergey Zigachev
1177b843c749SSergey Zigachev vega10_didt_set_mask(hwmgr, false);
1178b843c749SSergey Zigachev
1179b843c749SSergey Zigachev adev->gfx.rlc.funcs->exit_safe_mode(adev);
1180b843c749SSergey Zigachev
1181b843c749SSergey Zigachev return 0;
1182b843c749SSergey Zigachev }
1183b843c749SSergey Zigachev
vega10_disable_se_edc_force_stall_config(struct pp_hwmgr * hwmgr)1184b843c749SSergey Zigachev static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1185b843c749SSergey Zigachev {
1186b843c749SSergey Zigachev int result;
1187b843c749SSergey Zigachev
1188b843c749SSergey Zigachev result = vega10_disable_se_edc_config(hwmgr);
1189b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);
1190b843c749SSergey Zigachev
1191b843c749SSergey Zigachev return 0;
1192b843c749SSergey Zigachev }
1193b843c749SSergey Zigachev
vega10_enable_didt_config(struct pp_hwmgr * hwmgr)1194b843c749SSergey Zigachev int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
1195b843c749SSergey Zigachev {
1196b843c749SSergey Zigachev int result = 0;
1197b843c749SSergey Zigachev struct vega10_hwmgr *data = hwmgr->backend;
1198b843c749SSergey Zigachev
1199b843c749SSergey Zigachev if (data->smu_features[GNLD_DIDT].supported) {
1200b843c749SSergey Zigachev if (data->smu_features[GNLD_DIDT].enabled)
1201b843c749SSergey Zigachev PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n");
1202b843c749SSergey Zigachev
1203b843c749SSergey Zigachev switch (data->registry_data.didt_mode) {
1204b843c749SSergey Zigachev case 0:
1205b843c749SSergey Zigachev result = vega10_enable_cac_driving_se_didt_config(hwmgr);
1206b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);
1207b843c749SSergey Zigachev break;
1208b843c749SSergey Zigachev case 2:
1209b843c749SSergey Zigachev result = vega10_enable_psm_gc_didt_config(hwmgr);
1210b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);
1211b843c749SSergey Zigachev break;
1212b843c749SSergey Zigachev case 3:
1213b843c749SSergey Zigachev result = vega10_enable_se_edc_config(hwmgr);
1214b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);
1215b843c749SSergey Zigachev break;
1216b843c749SSergey Zigachev case 1:
1217b843c749SSergey Zigachev case 4:
1218b843c749SSergey Zigachev case 5:
1219b843c749SSergey Zigachev result = vega10_enable_psm_gc_edc_config(hwmgr);
1220b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);
1221b843c749SSergey Zigachev break;
1222b843c749SSergey Zigachev case 6:
1223b843c749SSergey Zigachev result = vega10_enable_se_edc_force_stall_config(hwmgr);
1224b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);
1225b843c749SSergey Zigachev break;
1226b843c749SSergey Zigachev default:
1227b843c749SSergey Zigachev result = -EINVAL;
1228b843c749SSergey Zigachev break;
1229b843c749SSergey Zigachev }
1230b843c749SSergey Zigachev
1231b843c749SSergey Zigachev if (0 == result) {
1232b843c749SSergey Zigachev result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1233b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
1234b843c749SSergey Zigachev data->smu_features[GNLD_DIDT].enabled = true;
1235b843c749SSergey Zigachev }
1236b843c749SSergey Zigachev }
1237b843c749SSergey Zigachev
1238b843c749SSergey Zigachev return result;
1239b843c749SSergey Zigachev }
1240b843c749SSergey Zigachev
vega10_disable_didt_config(struct pp_hwmgr * hwmgr)1241b843c749SSergey Zigachev int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
1242b843c749SSergey Zigachev {
1243b843c749SSergey Zigachev int result = 0;
1244b843c749SSergey Zigachev struct vega10_hwmgr *data = hwmgr->backend;
1245b843c749SSergey Zigachev
1246b843c749SSergey Zigachev if (data->smu_features[GNLD_DIDT].supported) {
1247b843c749SSergey Zigachev if (!data->smu_features[GNLD_DIDT].enabled)
1248b843c749SSergey Zigachev PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n");
1249b843c749SSergey Zigachev
1250b843c749SSergey Zigachev switch (data->registry_data.didt_mode) {
1251b843c749SSergey Zigachev case 0:
1252b843c749SSergey Zigachev result = vega10_disable_cac_driving_se_didt_config(hwmgr);
1253b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);
1254b843c749SSergey Zigachev break;
1255b843c749SSergey Zigachev case 2:
1256b843c749SSergey Zigachev result = vega10_disable_psm_gc_didt_config(hwmgr);
1257b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result);
1258b843c749SSergey Zigachev break;
1259b843c749SSergey Zigachev case 3:
1260b843c749SSergey Zigachev result = vega10_disable_se_edc_config(hwmgr);
1261b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result);
1262b843c749SSergey Zigachev break;
1263b843c749SSergey Zigachev case 1:
1264b843c749SSergey Zigachev case 4:
1265b843c749SSergey Zigachev case 5:
1266b843c749SSergey Zigachev result = vega10_disable_psm_gc_edc_config(hwmgr);
1267b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result);
1268b843c749SSergey Zigachev break;
1269b843c749SSergey Zigachev case 6:
1270b843c749SSergey Zigachev result = vega10_disable_se_edc_force_stall_config(hwmgr);
1271b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result);
1272b843c749SSergey Zigachev break;
1273b843c749SSergey Zigachev default:
1274b843c749SSergey Zigachev result = -EINVAL;
1275b843c749SSergey Zigachev break;
1276b843c749SSergey Zigachev }
1277b843c749SSergey Zigachev
1278b843c749SSergey Zigachev if (0 == result) {
1279b843c749SSergey Zigachev result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1280b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
1281b843c749SSergey Zigachev data->smu_features[GNLD_DIDT].enabled = false;
1282b843c749SSergey Zigachev }
1283b843c749SSergey Zigachev }
1284b843c749SSergey Zigachev
1285b843c749SSergey Zigachev return result;
1286b843c749SSergey Zigachev }
1287b843c749SSergey Zigachev
vega10_initialize_power_tune_defaults(struct pp_hwmgr * hwmgr)1288b843c749SSergey Zigachev void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1289b843c749SSergey Zigachev {
1290b843c749SSergey Zigachev struct vega10_hwmgr *data = hwmgr->backend;
1291b843c749SSergey Zigachev struct phm_ppt_v2_information *table_info =
1292b843c749SSergey Zigachev (struct phm_ppt_v2_information *)(hwmgr->pptable);
1293b843c749SSergey Zigachev struct phm_tdp_table *tdp_table = table_info->tdp_table;
1294b843c749SSergey Zigachev PPTable_t *table = &(data->smc_state_table.pp_table);
1295b843c749SSergey Zigachev
1296b843c749SSergey Zigachev table->SocketPowerLimit = cpu_to_le16(
1297b843c749SSergey Zigachev tdp_table->usMaximumPowerDeliveryLimit);
1298b843c749SSergey Zigachev table->TdcLimit = cpu_to_le16(tdp_table->usTDC);
1299b843c749SSergey Zigachev table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit);
1300b843c749SSergey Zigachev table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge);
1301b843c749SSergey Zigachev table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot);
1302b843c749SSergey Zigachev table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM);
1303b843c749SSergey Zigachev table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc);
1304b843c749SSergey Zigachev table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd);
1305b843c749SSergey Zigachev table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1);
1306b843c749SSergey Zigachev table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2);
1307b843c749SSergey Zigachev table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx);
1308b843c749SSergey Zigachev table->LoadLineResistance =
1309b843c749SSergey Zigachev hwmgr->platform_descriptor.LoadLineSlope * 256;
1310b843c749SSergey Zigachev table->FitLimit = 0; /* Not used for Vega10 */
1311b843c749SSergey Zigachev
1312b843c749SSergey Zigachev table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address;
1313b843c749SSergey Zigachev table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address;
1314b843c749SSergey Zigachev table->Vr_I2C_address = tdp_table->ucVr_I2C_address;
1315b843c749SSergey Zigachev table->Plx_I2C_address = tdp_table->ucPlx_I2C_address;
1316b843c749SSergey Zigachev
1317b843c749SSergey Zigachev table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line;
1318b843c749SSergey Zigachev table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA;
1319b843c749SSergey Zigachev
1320b843c749SSergey Zigachev table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line;
1321b843c749SSergey Zigachev table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA;
1322b843c749SSergey Zigachev
1323b843c749SSergey Zigachev table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line;
1324b843c749SSergey Zigachev table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA;
1325b843c749SSergey Zigachev }
1326b843c749SSergey Zigachev
vega10_set_power_limit(struct pp_hwmgr * hwmgr,uint32_t n)1327b843c749SSergey Zigachev int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1328b843c749SSergey Zigachev {
1329b843c749SSergey Zigachev struct vega10_hwmgr *data = hwmgr->backend;
1330b843c749SSergey Zigachev
1331b843c749SSergey Zigachev if (data->registry_data.enable_pkg_pwr_tracking_feature)
1332b843c749SSergey Zigachev smum_send_msg_to_smc_with_parameter(hwmgr,
1333b843c749SSergey Zigachev PPSMC_MSG_SetPptLimit, n);
1334b843c749SSergey Zigachev
1335b843c749SSergey Zigachev return 0;
1336b843c749SSergey Zigachev }
1337b843c749SSergey Zigachev
vega10_enable_power_containment(struct pp_hwmgr * hwmgr)1338b843c749SSergey Zigachev int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
1339b843c749SSergey Zigachev {
1340b843c749SSergey Zigachev struct vega10_hwmgr *data = hwmgr->backend;
1341b843c749SSergey Zigachev struct phm_ppt_v2_information *table_info =
1342b843c749SSergey Zigachev (struct phm_ppt_v2_information *)(hwmgr->pptable);
1343b843c749SSergey Zigachev struct phm_tdp_table *tdp_table = table_info->tdp_table;
1344b843c749SSergey Zigachev int result = 0;
1345b843c749SSergey Zigachev
1346b843c749SSergey Zigachev hwmgr->default_power_limit = hwmgr->power_limit =
1347b843c749SSergey Zigachev (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
1348b843c749SSergey Zigachev
1349b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1350b843c749SSergey Zigachev if (data->smu_features[GNLD_PPT].supported)
1351b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1352b843c749SSergey Zigachev true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1353b843c749SSergey Zigachev "Attempt to enable PPT feature Failed!",
1354b843c749SSergey Zigachev data->smu_features[GNLD_PPT].supported = false);
1355b843c749SSergey Zigachev
1356b843c749SSergey Zigachev if (data->smu_features[GNLD_TDC].supported)
1357b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1358b843c749SSergey Zigachev true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1359b843c749SSergey Zigachev "Attempt to enable PPT feature Failed!",
1360b843c749SSergey Zigachev data->smu_features[GNLD_TDC].supported = false);
1361b843c749SSergey Zigachev
1362b843c749SSergey Zigachev result = vega10_set_power_limit(hwmgr, hwmgr->power_limit);
1363b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1364b843c749SSergey Zigachev "Failed to set Default Power Limit in SMC!",
1365b843c749SSergey Zigachev return result);
1366b843c749SSergey Zigachev }
1367b843c749SSergey Zigachev
1368b843c749SSergey Zigachev return result;
1369b843c749SSergey Zigachev }
1370b843c749SSergey Zigachev
vega10_disable_power_containment(struct pp_hwmgr * hwmgr)1371b843c749SSergey Zigachev int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
1372b843c749SSergey Zigachev {
1373b843c749SSergey Zigachev struct vega10_hwmgr *data = hwmgr->backend;
1374b843c749SSergey Zigachev
1375b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1376b843c749SSergey Zigachev if (data->smu_features[GNLD_PPT].supported)
1377b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1378b843c749SSergey Zigachev false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1379b843c749SSergey Zigachev "Attempt to disable PPT feature Failed!",
1380b843c749SSergey Zigachev data->smu_features[GNLD_PPT].supported = false);
1381b843c749SSergey Zigachev
1382b843c749SSergey Zigachev if (data->smu_features[GNLD_TDC].supported)
1383b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1384b843c749SSergey Zigachev false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1385b843c749SSergey Zigachev "Attempt to disable PPT feature Failed!",
1386b843c749SSergey Zigachev data->smu_features[GNLD_TDC].supported = false);
1387b843c749SSergey Zigachev }
1388b843c749SSergey Zigachev
1389b843c749SSergey Zigachev return 0;
1390b843c749SSergey Zigachev }
1391b843c749SSergey Zigachev
vega10_set_overdrive_target_percentage(struct pp_hwmgr * hwmgr,uint32_t adjust_percent)1392b843c749SSergey Zigachev static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
1393b843c749SSergey Zigachev uint32_t adjust_percent)
1394b843c749SSergey Zigachev {
1395b843c749SSergey Zigachev smum_send_msg_to_smc_with_parameter(hwmgr,
1396b843c749SSergey Zigachev PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
1397b843c749SSergey Zigachev }
1398b843c749SSergey Zigachev
vega10_power_control_set_level(struct pp_hwmgr * hwmgr)1399b843c749SSergey Zigachev int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
1400b843c749SSergey Zigachev {
1401b843c749SSergey Zigachev int adjust_percent;
1402b843c749SSergey Zigachev
1403b843c749SSergey Zigachev if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1404b843c749SSergey Zigachev adjust_percent =
1405b843c749SSergey Zigachev hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
1406b843c749SSergey Zigachev hwmgr->platform_descriptor.TDPAdjustment :
1407b843c749SSergey Zigachev (-1 * hwmgr->platform_descriptor.TDPAdjustment);
1408b843c749SSergey Zigachev vega10_set_overdrive_target_percentage(hwmgr,
1409b843c749SSergey Zigachev (uint32_t)adjust_percent);
1410b843c749SSergey Zigachev }
1411b843c749SSergey Zigachev return 0;
1412b843c749SSergey Zigachev }
1413