1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2013 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef SMU7_DISCRETE_H 25*b843c749SSergey Zigachev #define SMU7_DISCRETE_H 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include "smu7.h" 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #pragma pack(push, 1) 30*b843c749SSergey Zigachev 31*b843c749SSergey Zigachev #define SMU7_DTE_ITERATIONS 5 32*b843c749SSergey Zigachev #define SMU7_DTE_SOURCES 3 33*b843c749SSergey Zigachev #define SMU7_DTE_SINKS 1 34*b843c749SSergey Zigachev #define SMU7_NUM_CPU_TES 0 35*b843c749SSergey Zigachev #define SMU7_NUM_GPU_TES 1 36*b843c749SSergey Zigachev #define SMU7_NUM_NON_TES 2 37*b843c749SSergey Zigachev 38*b843c749SSergey Zigachev struct SMU7_SoftRegisters 39*b843c749SSergey Zigachev { 40*b843c749SSergey Zigachev uint32_t RefClockFrequency; 41*b843c749SSergey Zigachev uint32_t PmTimerP; 42*b843c749SSergey Zigachev uint32_t FeatureEnables; 43*b843c749SSergey Zigachev uint32_t PreVBlankGap; 44*b843c749SSergey Zigachev uint32_t VBlankTimeout; 45*b843c749SSergey Zigachev uint32_t TrainTimeGap; 46*b843c749SSergey Zigachev 47*b843c749SSergey Zigachev uint32_t MvddSwitchTime; 48*b843c749SSergey Zigachev uint32_t LongestAcpiTrainTime; 49*b843c749SSergey Zigachev uint32_t AcpiDelay; 50*b843c749SSergey Zigachev uint32_t G5TrainTime; 51*b843c749SSergey Zigachev uint32_t DelayMpllPwron; 52*b843c749SSergey Zigachev uint32_t VoltageChangeTimeout; 53*b843c749SSergey Zigachev uint32_t HandshakeDisables; 54*b843c749SSergey Zigachev 55*b843c749SSergey Zigachev uint8_t DisplayPhy1Config; 56*b843c749SSergey Zigachev uint8_t DisplayPhy2Config; 57*b843c749SSergey Zigachev uint8_t DisplayPhy3Config; 58*b843c749SSergey Zigachev uint8_t DisplayPhy4Config; 59*b843c749SSergey Zigachev 60*b843c749SSergey Zigachev uint8_t DisplayPhy5Config; 61*b843c749SSergey Zigachev uint8_t DisplayPhy6Config; 62*b843c749SSergey Zigachev uint8_t DisplayPhy7Config; 63*b843c749SSergey Zigachev uint8_t DisplayPhy8Config; 64*b843c749SSergey Zigachev 65*b843c749SSergey Zigachev uint32_t AverageGraphicsA; 66*b843c749SSergey Zigachev uint32_t AverageMemoryA; 67*b843c749SSergey Zigachev uint32_t AverageGioA; 68*b843c749SSergey Zigachev 69*b843c749SSergey Zigachev uint8_t SClkDpmEnabledLevels; 70*b843c749SSergey Zigachev uint8_t MClkDpmEnabledLevels; 71*b843c749SSergey Zigachev uint8_t LClkDpmEnabledLevels; 72*b843c749SSergey Zigachev uint8_t PCIeDpmEnabledLevels; 73*b843c749SSergey Zigachev 74*b843c749SSergey Zigachev uint8_t UVDDpmEnabledLevels; 75*b843c749SSergey Zigachev uint8_t SAMUDpmEnabledLevels; 76*b843c749SSergey Zigachev uint8_t ACPDpmEnabledLevels; 77*b843c749SSergey Zigachev uint8_t VCEDpmEnabledLevels; 78*b843c749SSergey Zigachev 79*b843c749SSergey Zigachev uint32_t DRAM_LOG_ADDR_H; 80*b843c749SSergey Zigachev uint32_t DRAM_LOG_ADDR_L; 81*b843c749SSergey Zigachev uint32_t DRAM_LOG_PHY_ADDR_H; 82*b843c749SSergey Zigachev uint32_t DRAM_LOG_PHY_ADDR_L; 83*b843c749SSergey Zigachev uint32_t DRAM_LOG_BUFF_SIZE; 84*b843c749SSergey Zigachev uint32_t UlvEnterC; 85*b843c749SSergey Zigachev uint32_t UlvTime; 86*b843c749SSergey Zigachev uint32_t Reserved[3]; 87*b843c749SSergey Zigachev 88*b843c749SSergey Zigachev }; 89*b843c749SSergey Zigachev 90*b843c749SSergey Zigachev typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; 91*b843c749SSergey Zigachev 92*b843c749SSergey Zigachev struct SMU7_Discrete_VoltageLevel 93*b843c749SSergey Zigachev { 94*b843c749SSergey Zigachev uint16_t Voltage; 95*b843c749SSergey Zigachev uint16_t StdVoltageHiSidd; 96*b843c749SSergey Zigachev uint16_t StdVoltageLoSidd; 97*b843c749SSergey Zigachev uint8_t Smio; 98*b843c749SSergey Zigachev uint8_t padding; 99*b843c749SSergey Zigachev }; 100*b843c749SSergey Zigachev 101*b843c749SSergey Zigachev typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel; 102*b843c749SSergey Zigachev 103*b843c749SSergey Zigachev struct SMU7_Discrete_GraphicsLevel 104*b843c749SSergey Zigachev { 105*b843c749SSergey Zigachev uint32_t Flags; 106*b843c749SSergey Zigachev uint32_t MinVddc; 107*b843c749SSergey Zigachev uint32_t MinVddcPhases; 108*b843c749SSergey Zigachev 109*b843c749SSergey Zigachev uint32_t SclkFrequency; 110*b843c749SSergey Zigachev 111*b843c749SSergey Zigachev uint8_t padding1[2]; 112*b843c749SSergey Zigachev uint16_t ActivityLevel; 113*b843c749SSergey Zigachev 114*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl3; 115*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl4; 116*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum; 117*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum2; 118*b843c749SSergey Zigachev uint32_t CcPwrDynRm; 119*b843c749SSergey Zigachev uint32_t CcPwrDynRm1; 120*b843c749SSergey Zigachev uint8_t SclkDid; 121*b843c749SSergey Zigachev uint8_t DisplayWatermark; 122*b843c749SSergey Zigachev uint8_t EnabledForActivity; 123*b843c749SSergey Zigachev uint8_t EnabledForThrottle; 124*b843c749SSergey Zigachev uint8_t UpH; 125*b843c749SSergey Zigachev uint8_t DownH; 126*b843c749SSergey Zigachev uint8_t VoltageDownH; 127*b843c749SSergey Zigachev uint8_t PowerThrottle; 128*b843c749SSergey Zigachev uint8_t DeepSleepDivId; 129*b843c749SSergey Zigachev uint8_t padding[3]; 130*b843c749SSergey Zigachev }; 131*b843c749SSergey Zigachev 132*b843c749SSergey Zigachev typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel; 133*b843c749SSergey Zigachev 134*b843c749SSergey Zigachev struct SMU7_Discrete_ACPILevel 135*b843c749SSergey Zigachev { 136*b843c749SSergey Zigachev uint32_t Flags; 137*b843c749SSergey Zigachev uint32_t MinVddc; 138*b843c749SSergey Zigachev uint32_t MinVddcPhases; 139*b843c749SSergey Zigachev uint32_t SclkFrequency; 140*b843c749SSergey Zigachev uint8_t SclkDid; 141*b843c749SSergey Zigachev uint8_t DisplayWatermark; 142*b843c749SSergey Zigachev uint8_t DeepSleepDivId; 143*b843c749SSergey Zigachev uint8_t padding; 144*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl; 145*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl2; 146*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl3; 147*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl4; 148*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum; 149*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum2; 150*b843c749SSergey Zigachev uint32_t CcPwrDynRm; 151*b843c749SSergey Zigachev uint32_t CcPwrDynRm1; 152*b843c749SSergey Zigachev }; 153*b843c749SSergey Zigachev 154*b843c749SSergey Zigachev typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel; 155*b843c749SSergey Zigachev 156*b843c749SSergey Zigachev struct SMU7_Discrete_Ulv 157*b843c749SSergey Zigachev { 158*b843c749SSergey Zigachev uint32_t CcPwrDynRm; 159*b843c749SSergey Zigachev uint32_t CcPwrDynRm1; 160*b843c749SSergey Zigachev uint16_t VddcOffset; 161*b843c749SSergey Zigachev uint8_t VddcOffsetVid; 162*b843c749SSergey Zigachev uint8_t VddcPhase; 163*b843c749SSergey Zigachev uint32_t Reserved; 164*b843c749SSergey Zigachev }; 165*b843c749SSergey Zigachev 166*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv; 167*b843c749SSergey Zigachev 168*b843c749SSergey Zigachev struct SMU7_Discrete_MemoryLevel 169*b843c749SSergey Zigachev { 170*b843c749SSergey Zigachev uint32_t MinVddc; 171*b843c749SSergey Zigachev uint32_t MinVddcPhases; 172*b843c749SSergey Zigachev uint32_t MinVddci; 173*b843c749SSergey Zigachev uint32_t MinMvdd; 174*b843c749SSergey Zigachev 175*b843c749SSergey Zigachev uint32_t MclkFrequency; 176*b843c749SSergey Zigachev 177*b843c749SSergey Zigachev uint8_t EdcReadEnable; 178*b843c749SSergey Zigachev uint8_t EdcWriteEnable; 179*b843c749SSergey Zigachev uint8_t RttEnable; 180*b843c749SSergey Zigachev uint8_t StutterEnable; 181*b843c749SSergey Zigachev 182*b843c749SSergey Zigachev uint8_t StrobeEnable; 183*b843c749SSergey Zigachev uint8_t StrobeRatio; 184*b843c749SSergey Zigachev uint8_t EnabledForThrottle; 185*b843c749SSergey Zigachev uint8_t EnabledForActivity; 186*b843c749SSergey Zigachev 187*b843c749SSergey Zigachev uint8_t UpH; 188*b843c749SSergey Zigachev uint8_t DownH; 189*b843c749SSergey Zigachev uint8_t VoltageDownH; 190*b843c749SSergey Zigachev uint8_t padding; 191*b843c749SSergey Zigachev 192*b843c749SSergey Zigachev uint16_t ActivityLevel; 193*b843c749SSergey Zigachev uint8_t DisplayWatermark; 194*b843c749SSergey Zigachev uint8_t padding1; 195*b843c749SSergey Zigachev 196*b843c749SSergey Zigachev uint32_t MpllFuncCntl; 197*b843c749SSergey Zigachev uint32_t MpllFuncCntl_1; 198*b843c749SSergey Zigachev uint32_t MpllFuncCntl_2; 199*b843c749SSergey Zigachev uint32_t MpllAdFuncCntl; 200*b843c749SSergey Zigachev uint32_t MpllDqFuncCntl; 201*b843c749SSergey Zigachev uint32_t MclkPwrmgtCntl; 202*b843c749SSergey Zigachev uint32_t DllCntl; 203*b843c749SSergey Zigachev uint32_t MpllSs1; 204*b843c749SSergey Zigachev uint32_t MpllSs2; 205*b843c749SSergey Zigachev }; 206*b843c749SSergey Zigachev 207*b843c749SSergey Zigachev typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel; 208*b843c749SSergey Zigachev 209*b843c749SSergey Zigachev struct SMU7_Discrete_LinkLevel 210*b843c749SSergey Zigachev { 211*b843c749SSergey Zigachev uint8_t PcieGenSpeed; 212*b843c749SSergey Zigachev uint8_t PcieLaneCount; 213*b843c749SSergey Zigachev uint8_t EnabledForActivity; 214*b843c749SSergey Zigachev uint8_t Padding; 215*b843c749SSergey Zigachev uint32_t DownT; 216*b843c749SSergey Zigachev uint32_t UpT; 217*b843c749SSergey Zigachev uint32_t Reserved; 218*b843c749SSergey Zigachev }; 219*b843c749SSergey Zigachev 220*b843c749SSergey Zigachev typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel; 221*b843c749SSergey Zigachev 222*b843c749SSergey Zigachev 223*b843c749SSergey Zigachev struct SMU7_Discrete_MCArbDramTimingTableEntry 224*b843c749SSergey Zigachev { 225*b843c749SSergey Zigachev uint32_t McArbDramTiming; 226*b843c749SSergey Zigachev uint32_t McArbDramTiming2; 227*b843c749SSergey Zigachev uint8_t McArbBurstTime; 228*b843c749SSergey Zigachev uint8_t padding[3]; 229*b843c749SSergey Zigachev }; 230*b843c749SSergey Zigachev 231*b843c749SSergey Zigachev typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry; 232*b843c749SSergey Zigachev 233*b843c749SSergey Zigachev struct SMU7_Discrete_MCArbDramTimingTable 234*b843c749SSergey Zigachev { 235*b843c749SSergey Zigachev SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 236*b843c749SSergey Zigachev }; 237*b843c749SSergey Zigachev 238*b843c749SSergey Zigachev typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable; 239*b843c749SSergey Zigachev 240*b843c749SSergey Zigachev struct SMU7_Discrete_UvdLevel 241*b843c749SSergey Zigachev { 242*b843c749SSergey Zigachev uint32_t VclkFrequency; 243*b843c749SSergey Zigachev uint32_t DclkFrequency; 244*b843c749SSergey Zigachev uint16_t MinVddc; 245*b843c749SSergey Zigachev uint8_t MinVddcPhases; 246*b843c749SSergey Zigachev uint8_t VclkDivider; 247*b843c749SSergey Zigachev uint8_t DclkDivider; 248*b843c749SSergey Zigachev uint8_t padding[3]; 249*b843c749SSergey Zigachev }; 250*b843c749SSergey Zigachev 251*b843c749SSergey Zigachev typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel; 252*b843c749SSergey Zigachev 253*b843c749SSergey Zigachev struct SMU7_Discrete_ExtClkLevel 254*b843c749SSergey Zigachev { 255*b843c749SSergey Zigachev uint32_t Frequency; 256*b843c749SSergey Zigachev uint16_t MinVoltage; 257*b843c749SSergey Zigachev uint8_t MinPhases; 258*b843c749SSergey Zigachev uint8_t Divider; 259*b843c749SSergey Zigachev }; 260*b843c749SSergey Zigachev 261*b843c749SSergey Zigachev typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel; 262*b843c749SSergey Zigachev 263*b843c749SSergey Zigachev struct SMU7_Discrete_StateInfo 264*b843c749SSergey Zigachev { 265*b843c749SSergey Zigachev uint32_t SclkFrequency; 266*b843c749SSergey Zigachev uint32_t MclkFrequency; 267*b843c749SSergey Zigachev uint32_t VclkFrequency; 268*b843c749SSergey Zigachev uint32_t DclkFrequency; 269*b843c749SSergey Zigachev uint32_t SamclkFrequency; 270*b843c749SSergey Zigachev uint32_t AclkFrequency; 271*b843c749SSergey Zigachev uint32_t EclkFrequency; 272*b843c749SSergey Zigachev uint16_t MvddVoltage; 273*b843c749SSergey Zigachev uint16_t padding16; 274*b843c749SSergey Zigachev uint8_t DisplayWatermark; 275*b843c749SSergey Zigachev uint8_t McArbIndex; 276*b843c749SSergey Zigachev uint8_t McRegIndex; 277*b843c749SSergey Zigachev uint8_t SeqIndex; 278*b843c749SSergey Zigachev uint8_t SclkDid; 279*b843c749SSergey Zigachev int8_t SclkIndex; 280*b843c749SSergey Zigachev int8_t MclkIndex; 281*b843c749SSergey Zigachev uint8_t PCIeGen; 282*b843c749SSergey Zigachev 283*b843c749SSergey Zigachev }; 284*b843c749SSergey Zigachev 285*b843c749SSergey Zigachev typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo; 286*b843c749SSergey Zigachev 287*b843c749SSergey Zigachev 288*b843c749SSergey Zigachev struct SMU7_Discrete_DpmTable 289*b843c749SSergey Zigachev { 290*b843c749SSergey Zigachev SMU7_PIDController GraphicsPIDController; 291*b843c749SSergey Zigachev SMU7_PIDController MemoryPIDController; 292*b843c749SSergey Zigachev SMU7_PIDController LinkPIDController; 293*b843c749SSergey Zigachev 294*b843c749SSergey Zigachev uint32_t SystemFlags; 295*b843c749SSergey Zigachev 296*b843c749SSergey Zigachev 297*b843c749SSergey Zigachev uint32_t SmioMaskVddcVid; 298*b843c749SSergey Zigachev uint32_t SmioMaskVddcPhase; 299*b843c749SSergey Zigachev uint32_t SmioMaskVddciVid; 300*b843c749SSergey Zigachev uint32_t SmioMaskMvddVid; 301*b843c749SSergey Zigachev 302*b843c749SSergey Zigachev uint32_t VddcLevelCount; 303*b843c749SSergey Zigachev uint32_t VddciLevelCount; 304*b843c749SSergey Zigachev uint32_t MvddLevelCount; 305*b843c749SSergey Zigachev 306*b843c749SSergey Zigachev SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC]; 307*b843c749SSergey Zigachev // SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC]; 308*b843c749SSergey Zigachev SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI]; 309*b843c749SSergey Zigachev SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD]; 310*b843c749SSergey Zigachev 311*b843c749SSergey Zigachev uint8_t GraphicsDpmLevelCount; 312*b843c749SSergey Zigachev uint8_t MemoryDpmLevelCount; 313*b843c749SSergey Zigachev uint8_t LinkLevelCount; 314*b843c749SSergey Zigachev uint8_t UvdLevelCount; 315*b843c749SSergey Zigachev uint8_t VceLevelCount; 316*b843c749SSergey Zigachev uint8_t AcpLevelCount; 317*b843c749SSergey Zigachev uint8_t SamuLevelCount; 318*b843c749SSergey Zigachev uint8_t MasterDeepSleepControl; 319*b843c749SSergey Zigachev uint32_t VRConfig; 320*b843c749SSergey Zigachev uint32_t Reserved[4]; 321*b843c749SSergey Zigachev // uint32_t SamuDefaultLevel; 322*b843c749SSergey Zigachev 323*b843c749SSergey Zigachev SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; 324*b843c749SSergey Zigachev SMU7_Discrete_MemoryLevel MemoryACPILevel; 325*b843c749SSergey Zigachev SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; 326*b843c749SSergey Zigachev SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; 327*b843c749SSergey Zigachev SMU7_Discrete_ACPILevel ACPILevel; 328*b843c749SSergey Zigachev SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; 329*b843c749SSergey Zigachev SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; 330*b843c749SSergey Zigachev SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; 331*b843c749SSergey Zigachev SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; 332*b843c749SSergey Zigachev SMU7_Discrete_Ulv Ulv; 333*b843c749SSergey Zigachev 334*b843c749SSergey Zigachev uint32_t SclkStepSize; 335*b843c749SSergey Zigachev uint32_t Smio [SMU7_MAX_ENTRIES_SMIO]; 336*b843c749SSergey Zigachev 337*b843c749SSergey Zigachev uint8_t UvdBootLevel; 338*b843c749SSergey Zigachev uint8_t VceBootLevel; 339*b843c749SSergey Zigachev uint8_t AcpBootLevel; 340*b843c749SSergey Zigachev uint8_t SamuBootLevel; 341*b843c749SSergey Zigachev 342*b843c749SSergey Zigachev uint8_t UVDInterval; 343*b843c749SSergey Zigachev uint8_t VCEInterval; 344*b843c749SSergey Zigachev uint8_t ACPInterval; 345*b843c749SSergey Zigachev uint8_t SAMUInterval; 346*b843c749SSergey Zigachev 347*b843c749SSergey Zigachev uint8_t GraphicsBootLevel; 348*b843c749SSergey Zigachev uint8_t GraphicsVoltageChangeEnable; 349*b843c749SSergey Zigachev uint8_t GraphicsThermThrottleEnable; 350*b843c749SSergey Zigachev uint8_t GraphicsInterval; 351*b843c749SSergey Zigachev 352*b843c749SSergey Zigachev uint8_t VoltageInterval; 353*b843c749SSergey Zigachev uint8_t ThermalInterval; 354*b843c749SSergey Zigachev uint16_t TemperatureLimitHigh; 355*b843c749SSergey Zigachev 356*b843c749SSergey Zigachev uint16_t TemperatureLimitLow; 357*b843c749SSergey Zigachev uint8_t MemoryBootLevel; 358*b843c749SSergey Zigachev uint8_t MemoryVoltageChangeEnable; 359*b843c749SSergey Zigachev 360*b843c749SSergey Zigachev uint8_t MemoryInterval; 361*b843c749SSergey Zigachev uint8_t MemoryThermThrottleEnable; 362*b843c749SSergey Zigachev uint16_t VddcVddciDelta; 363*b843c749SSergey Zigachev 364*b843c749SSergey Zigachev uint16_t VoltageResponseTime; 365*b843c749SSergey Zigachev uint16_t PhaseResponseTime; 366*b843c749SSergey Zigachev 367*b843c749SSergey Zigachev uint8_t PCIeBootLinkLevel; 368*b843c749SSergey Zigachev uint8_t PCIeGenInterval; 369*b843c749SSergey Zigachev uint8_t DTEInterval; 370*b843c749SSergey Zigachev uint8_t DTEMode; 371*b843c749SSergey Zigachev 372*b843c749SSergey Zigachev uint8_t SVI2Enable; 373*b843c749SSergey Zigachev uint8_t VRHotGpio; 374*b843c749SSergey Zigachev uint8_t AcDcGpio; 375*b843c749SSergey Zigachev uint8_t ThermGpio; 376*b843c749SSergey Zigachev 377*b843c749SSergey Zigachev uint16_t PPM_PkgPwrLimit; 378*b843c749SSergey Zigachev uint16_t PPM_TemperatureLimit; 379*b843c749SSergey Zigachev 380*b843c749SSergey Zigachev uint16_t DefaultTdp; 381*b843c749SSergey Zigachev uint16_t TargetTdp; 382*b843c749SSergey Zigachev 383*b843c749SSergey Zigachev uint16_t FpsHighT; 384*b843c749SSergey Zigachev uint16_t FpsLowT; 385*b843c749SSergey Zigachev 386*b843c749SSergey Zigachev uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; 387*b843c749SSergey Zigachev uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; 388*b843c749SSergey Zigachev 389*b843c749SSergey Zigachev uint8_t DTEAmbientTempBase; 390*b843c749SSergey Zigachev uint8_t DTETjOffset; 391*b843c749SSergey Zigachev uint8_t GpuTjMax; 392*b843c749SSergey Zigachev uint8_t GpuTjHyst; 393*b843c749SSergey Zigachev 394*b843c749SSergey Zigachev uint16_t BootVddc; 395*b843c749SSergey Zigachev uint16_t BootVddci; 396*b843c749SSergey Zigachev 397*b843c749SSergey Zigachev uint16_t BootMVdd; 398*b843c749SSergey Zigachev uint16_t padding; 399*b843c749SSergey Zigachev 400*b843c749SSergey Zigachev uint32_t BAPM_TEMP_GRADIENT; 401*b843c749SSergey Zigachev 402*b843c749SSergey Zigachev uint32_t LowSclkInterruptT; 403*b843c749SSergey Zigachev }; 404*b843c749SSergey Zigachev 405*b843c749SSergey Zigachev typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable; 406*b843c749SSergey Zigachev 407*b843c749SSergey Zigachev #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 408*b843c749SSergey Zigachev #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY 409*b843c749SSergey Zigachev 410*b843c749SSergey Zigachev struct SMU7_Discrete_MCRegisterAddress 411*b843c749SSergey Zigachev { 412*b843c749SSergey Zigachev uint16_t s0; 413*b843c749SSergey Zigachev uint16_t s1; 414*b843c749SSergey Zigachev }; 415*b843c749SSergey Zigachev 416*b843c749SSergey Zigachev typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress; 417*b843c749SSergey Zigachev 418*b843c749SSergey Zigachev struct SMU7_Discrete_MCRegisterSet 419*b843c749SSergey Zigachev { 420*b843c749SSergey Zigachev uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 421*b843c749SSergey Zigachev }; 422*b843c749SSergey Zigachev 423*b843c749SSergey Zigachev typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet; 424*b843c749SSergey Zigachev 425*b843c749SSergey Zigachev struct SMU7_Discrete_MCRegisters 426*b843c749SSergey Zigachev { 427*b843c749SSergey Zigachev uint8_t last; 428*b843c749SSergey Zigachev uint8_t reserved[3]; 429*b843c749SSergey Zigachev SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 430*b843c749SSergey Zigachev SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; 431*b843c749SSergey Zigachev }; 432*b843c749SSergey Zigachev 433*b843c749SSergey Zigachev typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters; 434*b843c749SSergey Zigachev 435*b843c749SSergey Zigachev struct SMU7_Discrete_FanTable 436*b843c749SSergey Zigachev { 437*b843c749SSergey Zigachev uint16_t FdoMode; 438*b843c749SSergey Zigachev int16_t TempMin; 439*b843c749SSergey Zigachev int16_t TempMed; 440*b843c749SSergey Zigachev int16_t TempMax; 441*b843c749SSergey Zigachev int16_t Slope1; 442*b843c749SSergey Zigachev int16_t Slope2; 443*b843c749SSergey Zigachev int16_t FdoMin; 444*b843c749SSergey Zigachev int16_t HystUp; 445*b843c749SSergey Zigachev int16_t HystDown; 446*b843c749SSergey Zigachev int16_t HystSlope; 447*b843c749SSergey Zigachev int16_t TempRespLim; 448*b843c749SSergey Zigachev int16_t TempCurr; 449*b843c749SSergey Zigachev int16_t SlopeCurr; 450*b843c749SSergey Zigachev int16_t PwmCurr; 451*b843c749SSergey Zigachev uint32_t RefreshPeriod; 452*b843c749SSergey Zigachev int16_t FdoMax; 453*b843c749SSergey Zigachev uint8_t TempSrc; 454*b843c749SSergey Zigachev int8_t Padding; 455*b843c749SSergey Zigachev }; 456*b843c749SSergey Zigachev 457*b843c749SSergey Zigachev typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable; 458*b843c749SSergey Zigachev 459*b843c749SSergey Zigachev 460*b843c749SSergey Zigachev struct SMU7_Discrete_PmFuses { 461*b843c749SSergey Zigachev // dw0-dw1 462*b843c749SSergey Zigachev uint8_t BapmVddCVidHiSidd[8]; 463*b843c749SSergey Zigachev 464*b843c749SSergey Zigachev // dw2-dw3 465*b843c749SSergey Zigachev uint8_t BapmVddCVidLoSidd[8]; 466*b843c749SSergey Zigachev 467*b843c749SSergey Zigachev // dw4-dw5 468*b843c749SSergey Zigachev uint8_t VddCVid[8]; 469*b843c749SSergey Zigachev 470*b843c749SSergey Zigachev // dw6 471*b843c749SSergey Zigachev uint8_t SviLoadLineEn; 472*b843c749SSergey Zigachev uint8_t SviLoadLineVddC; 473*b843c749SSergey Zigachev uint8_t SviLoadLineTrimVddC; 474*b843c749SSergey Zigachev uint8_t SviLoadLineOffsetVddC; 475*b843c749SSergey Zigachev 476*b843c749SSergey Zigachev // dw7 477*b843c749SSergey Zigachev uint16_t TDC_VDDC_PkgLimit; 478*b843c749SSergey Zigachev uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 479*b843c749SSergey Zigachev uint8_t TDC_MAWt; 480*b843c749SSergey Zigachev 481*b843c749SSergey Zigachev // dw8 482*b843c749SSergey Zigachev uint8_t TdcWaterfallCtl; 483*b843c749SSergey Zigachev uint8_t LPMLTemperatureMin; 484*b843c749SSergey Zigachev uint8_t LPMLTemperatureMax; 485*b843c749SSergey Zigachev uint8_t Reserved; 486*b843c749SSergey Zigachev 487*b843c749SSergey Zigachev // dw9-dw10 488*b843c749SSergey Zigachev uint8_t BapmVddCVidHiSidd2[8]; 489*b843c749SSergey Zigachev 490*b843c749SSergey Zigachev // dw11-dw12 491*b843c749SSergey Zigachev int16_t FuzzyFan_ErrorSetDelta; 492*b843c749SSergey Zigachev int16_t FuzzyFan_ErrorRateSetDelta; 493*b843c749SSergey Zigachev int16_t FuzzyFan_PwmSetDelta; 494*b843c749SSergey Zigachev uint16_t CalcMeasPowerBlend; 495*b843c749SSergey Zigachev 496*b843c749SSergey Zigachev // dw13-dw16 497*b843c749SSergey Zigachev uint8_t GnbLPML[16]; 498*b843c749SSergey Zigachev 499*b843c749SSergey Zigachev // dw17 500*b843c749SSergey Zigachev uint8_t GnbLPMLMaxVid; 501*b843c749SSergey Zigachev uint8_t GnbLPMLMinVid; 502*b843c749SSergey Zigachev uint8_t Reserved1[2]; 503*b843c749SSergey Zigachev 504*b843c749SSergey Zigachev // dw18 505*b843c749SSergey Zigachev uint16_t BapmVddCBaseLeakageHiSidd; 506*b843c749SSergey Zigachev uint16_t BapmVddCBaseLeakageLoSidd; 507*b843c749SSergey Zigachev }; 508*b843c749SSergey Zigachev 509*b843c749SSergey Zigachev typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses; 510*b843c749SSergey Zigachev 511*b843c749SSergey Zigachev 512*b843c749SSergey Zigachev #pragma pack(pop) 513*b843c749SSergey Zigachev 514*b843c749SSergey Zigachev #endif 515*b843c749SSergey Zigachev 516