1 /* 2 * Copyright © 2009 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/delay.h> 26 #include <linux/init.h> 27 #include <linux/errno.h> 28 #include <linux/sched.h> 29 #include <linux/i2c.h> 30 #include <linux/seq_file.h> 31 #include <drm/drm_dp_helper.h> 32 #include <drm/drmP.h> 33 34 #include "drm_crtc_helper_internal.h" 35 36 /** 37 * DOC: dp helpers 38 * 39 * These functions contain some common logic and helpers at various abstraction 40 * levels to deal with Display Port sink devices and related things like DP aux 41 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 42 * blocks, ... 43 */ 44 45 /* Helpers for DP link training */ 46 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 47 { 48 return link_status[r - DP_LANE0_1_STATUS]; 49 } 50 51 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 52 int lane) 53 { 54 int i = DP_LANE0_1_STATUS + (lane >> 1); 55 int s = (lane & 1) * 4; 56 u8 l = dp_link_status(link_status, i); 57 return (l >> s) & 0xf; 58 } 59 60 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 61 int lane_count) 62 { 63 u8 lane_align; 64 u8 lane_status; 65 int lane; 66 67 lane_align = dp_link_status(link_status, 68 DP_LANE_ALIGN_STATUS_UPDATED); 69 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 70 return false; 71 for (lane = 0; lane < lane_count; lane++) { 72 lane_status = dp_get_lane_status(link_status, lane); 73 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 74 return false; 75 } 76 return true; 77 } 78 EXPORT_SYMBOL(drm_dp_channel_eq_ok); 79 80 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 81 int lane_count) 82 { 83 int lane; 84 u8 lane_status; 85 86 for (lane = 0; lane < lane_count; lane++) { 87 lane_status = dp_get_lane_status(link_status, lane); 88 if ((lane_status & DP_LANE_CR_DONE) == 0) 89 return false; 90 } 91 return true; 92 } 93 EXPORT_SYMBOL(drm_dp_clock_recovery_ok); 94 95 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 96 int lane) 97 { 98 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 99 int s = ((lane & 1) ? 100 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 101 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 102 u8 l = dp_link_status(link_status, i); 103 104 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 105 } 106 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); 107 108 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 109 int lane) 110 { 111 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 112 int s = ((lane & 1) ? 113 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 114 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 115 u8 l = dp_link_status(link_status, i); 116 117 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 118 } 119 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); 120 121 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { 122 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) 123 udelay(100); 124 else 125 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); 126 } 127 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); 128 129 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { 130 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) 131 udelay(400); 132 else 133 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); 134 } 135 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); 136 137 u8 drm_dp_link_rate_to_bw_code(int link_rate) 138 { 139 switch (link_rate) { 140 case 162000: 141 default: 142 return DP_LINK_BW_1_62; 143 case 270000: 144 return DP_LINK_BW_2_7; 145 case 540000: 146 return DP_LINK_BW_5_4; 147 } 148 } 149 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); 150 151 int drm_dp_bw_code_to_link_rate(u8 link_bw) 152 { 153 switch (link_bw) { 154 case DP_LINK_BW_1_62: 155 default: 156 return 162000; 157 case DP_LINK_BW_2_7: 158 return 270000; 159 case DP_LINK_BW_5_4: 160 return 540000; 161 } 162 } 163 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); 164 165 #define AUX_RETRY_INTERVAL 500 /* us */ 166 167 /** 168 * DOC: dp helpers 169 * 170 * The DisplayPort AUX channel is an abstraction to allow generic, driver- 171 * independent access to AUX functionality. Drivers can take advantage of 172 * this by filling in the fields of the drm_dp_aux structure. 173 * 174 * Transactions are described using a hardware-independent drm_dp_aux_msg 175 * structure, which is passed into a driver's .transfer() implementation. 176 * Both native and I2C-over-AUX transactions are supported. 177 */ 178 179 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 180 unsigned int offset, void *buffer, size_t size) 181 { 182 struct drm_dp_aux_msg msg; 183 unsigned int retry, native_reply; 184 int err = 0, ret = 0; 185 186 memset(&msg, 0, sizeof(msg)); 187 msg.address = offset; 188 msg.request = request; 189 msg.buffer = buffer; 190 msg.size = size; 191 192 mutex_lock(&aux->hw_mutex); 193 194 /* 195 * The specification doesn't give any recommendation on how often to 196 * retry native transactions. We used to retry 7 times like for 197 * aux i2c transactions but real world devices this wasn't 198 * sufficient, bump to 32 which makes Dell 4k monitors happier. 199 */ 200 for (retry = 0; retry < 32; retry++) { 201 if (ret != 0 && ret != -ETIMEDOUT) { 202 usleep_range(AUX_RETRY_INTERVAL, 203 AUX_RETRY_INTERVAL + 100); 204 } 205 206 ret = aux->transfer(aux, &msg); 207 208 if (ret >= 0) { 209 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 210 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 211 if (ret == size) 212 goto unlock; 213 214 ret = -EPROTO; 215 } else 216 ret = -EIO; 217 } 218 219 /* 220 * We want the error we return to be the error we received on 221 * the first transaction, since we may get a different error the 222 * next time we retry 223 */ 224 if (!err) 225 err = ret; 226 } 227 228 DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err); 229 ret = err; 230 231 unlock: 232 mutex_unlock(&aux->hw_mutex); 233 return ret; 234 } 235 236 /** 237 * drm_dp_dpcd_read() - read a series of bytes from the DPCD 238 * @aux: DisplayPort AUX channel 239 * @offset: address of the (first) register to read 240 * @buffer: buffer to store the register values 241 * @size: number of bytes in @buffer 242 * 243 * Returns the number of bytes transferred on success, or a negative error 244 * code on failure. -EIO is returned if the request was NAKed by the sink or 245 * if the retry count was exceeded. If not all bytes were transferred, this 246 * function returns -EPROTO. Errors from the underlying AUX channel transfer 247 * function, with the exception of -EBUSY (which causes the transaction to 248 * be retried), are propagated to the caller. 249 */ 250 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 251 void *buffer, size_t size) 252 { 253 int ret; 254 255 /* 256 * HP ZR24w corrupts the first DPCD access after entering power save 257 * mode. Eg. on a read, the entire buffer will be filled with the same 258 * byte. Do a throw away read to avoid corrupting anything we care 259 * about. Afterwards things will work correctly until the monitor 260 * gets woken up and subsequently re-enters power save mode. 261 * 262 * The user pressing any button on the monitor is enough to wake it 263 * up, so there is no particularly good place to do the workaround. 264 * We just have to do it before any DPCD access and hope that the 265 * monitor doesn't power down exactly after the throw away read. 266 */ 267 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer, 268 1); 269 if (ret != 1) 270 return ret; 271 272 return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer, 273 size); 274 } 275 EXPORT_SYMBOL(drm_dp_dpcd_read); 276 277 /** 278 * drm_dp_dpcd_write() - write a series of bytes to the DPCD 279 * @aux: DisplayPort AUX channel 280 * @offset: address of the (first) register to write 281 * @buffer: buffer containing the values to write 282 * @size: number of bytes in @buffer 283 * 284 * Returns the number of bytes transferred on success, or a negative error 285 * code on failure. -EIO is returned if the request was NAKed by the sink or 286 * if the retry count was exceeded. If not all bytes were transferred, this 287 * function returns -EPROTO. Errors from the underlying AUX channel transfer 288 * function, with the exception of -EBUSY (which causes the transaction to 289 * be retried), are propagated to the caller. 290 */ 291 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 292 void *buffer, size_t size) 293 { 294 return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, 295 size); 296 } 297 EXPORT_SYMBOL(drm_dp_dpcd_write); 298 299 /** 300 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) 301 * @aux: DisplayPort AUX channel 302 * @status: buffer to store the link status in (must be at least 6 bytes) 303 * 304 * Returns the number of bytes transferred on success or a negative error 305 * code on failure. 306 */ 307 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 308 u8 status[DP_LINK_STATUS_SIZE]) 309 { 310 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 311 DP_LINK_STATUS_SIZE); 312 } 313 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); 314 315 /** 316 * drm_dp_link_probe() - probe a DisplayPort link for capabilities 317 * @aux: DisplayPort AUX channel 318 * @link: pointer to structure in which to return link capabilities 319 * 320 * The structure filled in by this function can usually be passed directly 321 * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and 322 * configure the link based on the link's capabilities. 323 * 324 * Returns 0 on success or a negative error code on failure. 325 */ 326 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) 327 { 328 u8 values[3]; 329 int err; 330 331 memset(link, 0, sizeof(*link)); 332 333 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values)); 334 if (err < 0) 335 return err; 336 337 link->revision = values[0]; 338 link->rate = drm_dp_bw_code_to_link_rate(values[1]); 339 link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; 340 341 if (values[2] & DP_ENHANCED_FRAME_CAP) 342 link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; 343 344 return 0; 345 } 346 EXPORT_SYMBOL(drm_dp_link_probe); 347 348 /** 349 * drm_dp_link_power_up() - power up a DisplayPort link 350 * @aux: DisplayPort AUX channel 351 * @link: pointer to a structure containing the link configuration 352 * 353 * Returns 0 on success or a negative error code on failure. 354 */ 355 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link) 356 { 357 u8 value; 358 int err; 359 360 /* DP_SET_POWER register is only available on DPCD v1.1 and later */ 361 if (link->revision < 0x11) 362 return 0; 363 364 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value); 365 if (err < 0) 366 return err; 367 368 value &= ~DP_SET_POWER_MASK; 369 value |= DP_SET_POWER_D0; 370 371 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value); 372 if (err < 0) 373 return err; 374 375 /* 376 * According to the DP 1.1 specification, a "Sink Device must exit the 377 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink 378 * Control Field" (register 0x600). 379 */ 380 usleep_range(1000, 2000); 381 382 return 0; 383 } 384 EXPORT_SYMBOL(drm_dp_link_power_up); 385 386 /** 387 * drm_dp_link_power_down() - power down a DisplayPort link 388 * @aux: DisplayPort AUX channel 389 * @link: pointer to a structure containing the link configuration 390 * 391 * Returns 0 on success or a negative error code on failure. 392 */ 393 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link) 394 { 395 u8 value; 396 int err; 397 398 /* DP_SET_POWER register is only available on DPCD v1.1 and later */ 399 if (link->revision < 0x11) 400 return 0; 401 402 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value); 403 if (err < 0) 404 return err; 405 406 value &= ~DP_SET_POWER_MASK; 407 value |= DP_SET_POWER_D3; 408 409 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value); 410 if (err < 0) 411 return err; 412 413 return 0; 414 } 415 EXPORT_SYMBOL(drm_dp_link_power_down); 416 417 /** 418 * drm_dp_link_configure() - configure a DisplayPort link 419 * @aux: DisplayPort AUX channel 420 * @link: pointer to a structure containing the link configuration 421 * 422 * Returns 0 on success or a negative error code on failure. 423 */ 424 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) 425 { 426 u8 values[2]; 427 int err; 428 429 values[0] = drm_dp_link_rate_to_bw_code(link->rate); 430 values[1] = link->num_lanes; 431 432 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 433 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 434 435 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); 436 if (err < 0) 437 return err; 438 439 return 0; 440 } 441 EXPORT_SYMBOL(drm_dp_link_configure); 442 443 /** 444 * drm_dp_downstream_max_clock() - extract branch device max 445 * pixel rate for legacy VGA 446 * converter or max TMDS clock 447 * rate for others 448 * @dpcd: DisplayPort configuration data 449 * @port_cap: port capabilities 450 * 451 * Returns max clock in kHz on success or 0 if max clock not defined 452 */ 453 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 454 const u8 port_cap[4]) 455 { 456 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 457 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 458 DP_DETAILED_CAP_INFO_AVAILABLE; 459 460 if (!detailed_cap_info) 461 return 0; 462 463 switch (type) { 464 case DP_DS_PORT_TYPE_VGA: 465 return port_cap[1] * 8 * 1000; 466 case DP_DS_PORT_TYPE_DVI: 467 case DP_DS_PORT_TYPE_HDMI: 468 case DP_DS_PORT_TYPE_DP_DUALMODE: 469 return port_cap[1] * 2500; 470 default: 471 return 0; 472 } 473 } 474 EXPORT_SYMBOL(drm_dp_downstream_max_clock); 475 476 /** 477 * drm_dp_downstream_max_bpc() - extract branch device max 478 * bits per component 479 * @dpcd: DisplayPort configuration data 480 * @port_cap: port capabilities 481 * 482 * Returns max bpc on success or 0 if max bpc not defined 483 */ 484 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 485 const u8 port_cap[4]) 486 { 487 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 488 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 489 DP_DETAILED_CAP_INFO_AVAILABLE; 490 int bpc; 491 492 if (!detailed_cap_info) 493 return 0; 494 495 switch (type) { 496 case DP_DS_PORT_TYPE_VGA: 497 case DP_DS_PORT_TYPE_DVI: 498 case DP_DS_PORT_TYPE_HDMI: 499 case DP_DS_PORT_TYPE_DP_DUALMODE: 500 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK; 501 502 switch (bpc) { 503 case DP_DS_8BPC: 504 return 8; 505 case DP_DS_10BPC: 506 return 10; 507 case DP_DS_12BPC: 508 return 12; 509 case DP_DS_16BPC: 510 return 16; 511 } 512 default: 513 return 0; 514 } 515 } 516 EXPORT_SYMBOL(drm_dp_downstream_max_bpc); 517 518 /** 519 * drm_dp_downstream_id() - identify branch device 520 * @aux: DisplayPort AUX channel 521 * @id: DisplayPort branch device id 522 * 523 * Returns branch device id on success or NULL on failure 524 */ 525 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) 526 { 527 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); 528 } 529 EXPORT_SYMBOL(drm_dp_downstream_id); 530 531 /** 532 * drm_dp_downstream_debug() - debug DP branch devices 533 * @m: pointer for debugfs file 534 * @dpcd: DisplayPort configuration data 535 * @port_cap: port capabilities 536 * @aux: DisplayPort AUX channel 537 * 538 */ 539 void drm_dp_downstream_debug(struct seq_file *m, 540 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 541 const u8 port_cap[4], struct drm_dp_aux *aux) 542 { 543 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 544 DP_DETAILED_CAP_INFO_AVAILABLE; 545 int clk; 546 int bpc; 547 char id[6]; 548 int len; 549 uint8_t rev[2]; 550 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 551 bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 552 DP_DWN_STRM_PORT_PRESENT; 553 554 seq_printf(m, "\tDP branch device present: %s\n", 555 branch_device ? "yes" : "no"); 556 557 if (!branch_device) 558 return; 559 560 switch (type) { 561 case DP_DS_PORT_TYPE_DP: 562 seq_puts(m, "\t\tType: DisplayPort\n"); 563 break; 564 case DP_DS_PORT_TYPE_VGA: 565 seq_puts(m, "\t\tType: VGA\n"); 566 break; 567 case DP_DS_PORT_TYPE_DVI: 568 seq_puts(m, "\t\tType: DVI\n"); 569 break; 570 case DP_DS_PORT_TYPE_HDMI: 571 seq_puts(m, "\t\tType: HDMI\n"); 572 break; 573 case DP_DS_PORT_TYPE_NON_EDID: 574 seq_puts(m, "\t\tType: others without EDID support\n"); 575 break; 576 case DP_DS_PORT_TYPE_DP_DUALMODE: 577 seq_puts(m, "\t\tType: DP++\n"); 578 break; 579 case DP_DS_PORT_TYPE_WIRELESS: 580 seq_puts(m, "\t\tType: Wireless\n"); 581 break; 582 default: 583 seq_puts(m, "\t\tType: N/A\n"); 584 } 585 586 drm_dp_downstream_id(aux, id); 587 seq_printf(m, "\t\tID: %s\n", id); 588 589 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); 590 if (len > 0) 591 seq_printf(m, "\t\tHW: %d.%d\n", 592 (rev[0] & 0xf0) >> 4, rev[0] & 0xf); 593 594 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, &rev, 2); 595 if (len > 0) 596 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); 597 598 if (detailed_cap_info) { 599 clk = drm_dp_downstream_max_clock(dpcd, port_cap); 600 601 if (clk > 0) { 602 if (type == DP_DS_PORT_TYPE_VGA) 603 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 604 else 605 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 606 } 607 608 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap); 609 610 if (bpc > 0) 611 seq_printf(m, "\t\tMax bpc: %d\n", bpc); 612 } 613 } 614 EXPORT_SYMBOL(drm_dp_downstream_debug); 615 616 /* 617 * I2C-over-AUX implementation 618 */ 619 620 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) 621 { 622 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 623 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 624 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 625 I2C_FUNC_10BIT_ADDR; 626 } 627 628 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 629 { 630 /* 631 * In case of i2c defer or short i2c ack reply to a write, 632 * we need to switch to WRITE_STATUS_UPDATE to drain the 633 * rest of the message 634 */ 635 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 636 msg->request &= DP_AUX_I2C_MOT; 637 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 638 } 639 } 640 641 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ 642 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ 643 #define AUX_STOP_LEN 4 644 #define AUX_CMD_LEN 4 645 #define AUX_ADDRESS_LEN 20 646 #define AUX_REPLY_PAD_LEN 4 647 #define AUX_LENGTH_LEN 8 648 649 /* 650 * Calculate the duration of the AUX request/reply in usec. Gives the 651 * "best" case estimate, ie. successful while as short as possible. 652 */ 653 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) 654 { 655 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 656 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; 657 658 if ((msg->request & DP_AUX_I2C_READ) == 0) 659 len += msg->size * 8; 660 661 return len; 662 } 663 664 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) 665 { 666 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 667 AUX_CMD_LEN + AUX_REPLY_PAD_LEN; 668 669 /* 670 * For read we expect what was asked. For writes there will 671 * be 0 or 1 data bytes. Assume 0 for the "best" case. 672 */ 673 if (msg->request & DP_AUX_I2C_READ) 674 len += msg->size * 8; 675 676 return len; 677 } 678 679 #define I2C_START_LEN 1 680 #define I2C_STOP_LEN 1 681 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ 682 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ 683 684 /* 685 * Calculate the length of the i2c transfer in usec, assuming 686 * the i2c bus speed is as specified. Gives the the "worst" 687 * case estimate, ie. successful while as long as possible. 688 * Doesn't account the the "MOT" bit, and instead assumes each 689 * message includes a START, ADDRESS and STOP. Neither does it 690 * account for additional random variables such as clock stretching. 691 */ 692 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, 693 int i2c_speed_khz) 694 { 695 /* AUX bitrate is 1MHz, i2c bitrate as specified */ 696 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + 697 msg->size * I2C_DATA_LEN + 698 I2C_STOP_LEN) * 1000, i2c_speed_khz); 699 } 700 701 /* 702 * Deterine how many retries should be attempted to successfully transfer 703 * the specified message, based on the estimated durations of the 704 * i2c and AUX transfers. 705 */ 706 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, 707 int i2c_speed_khz) 708 { 709 int aux_time_us = drm_dp_aux_req_duration(msg) + 710 drm_dp_aux_reply_duration(msg); 711 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); 712 713 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); 714 } 715 716 /* 717 * FIXME currently assumes 10 kHz as some real world devices seem 718 * to require it. We should query/set the speed via DPCD if supported. 719 */ 720 static int dp_aux_i2c_speed_khz __read_mostly = 10; 721 MODULE_PARM_DESC(dp_aux_i2c_speed_khz, 722 "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); 723 724 /* 725 * Transfer a single I2C-over-AUX message and handle various error conditions, 726 * retrying the transaction as appropriate. It is assumed that the 727 * aux->transfer function does not modify anything in the msg other than the 728 * reply field. 729 * 730 * Returns bytes transferred on success, or a negative error code on failure. 731 */ 732 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 733 { 734 unsigned int retry, defer_i2c; 735 int ret; 736 /* 737 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 738 * is required to retry at least seven times upon receiving AUX_DEFER 739 * before giving up the AUX transaction. 740 * 741 * We also try to account for the i2c bus speed. 742 */ 743 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); 744 745 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { 746 ret = aux->transfer(aux, msg); 747 if (ret < 0) { 748 if (ret == -EBUSY) 749 continue; 750 751 /* 752 * While timeouts can be errors, they're usually normal 753 * behavior (for instance, when a driver tries to 754 * communicate with a non-existant DisplayPort device). 755 * Avoid spamming the kernel log with timeout errors. 756 */ 757 if (ret == -ETIMEDOUT) 758 DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n"); 759 else 760 DRM_DEBUG_KMS("transaction failed: %d\n", ret); 761 762 return ret; 763 } 764 765 766 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 767 case DP_AUX_NATIVE_REPLY_ACK: 768 /* 769 * For I2C-over-AUX transactions this isn't enough, we 770 * need to check for the I2C ACK reply. 771 */ 772 break; 773 774 case DP_AUX_NATIVE_REPLY_NACK: 775 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size); 776 return -EREMOTEIO; 777 778 case DP_AUX_NATIVE_REPLY_DEFER: 779 DRM_DEBUG_KMS("native defer\n"); 780 /* 781 * We could check for I2C bit rate capabilities and if 782 * available adjust this interval. We could also be 783 * more careful with DP-to-legacy adapters where a 784 * long legacy cable may force very low I2C bit rates. 785 * 786 * For now just defer for long enough to hopefully be 787 * safe for all use-cases. 788 */ 789 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 790 continue; 791 792 default: 793 DRM_ERROR("invalid native reply %#04x\n", msg->reply); 794 return -EREMOTEIO; 795 } 796 797 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 798 case DP_AUX_I2C_REPLY_ACK: 799 /* 800 * Both native ACK and I2C ACK replies received. We 801 * can assume the transfer was successful. 802 */ 803 if (ret != msg->size) 804 drm_dp_i2c_msg_write_status_update(msg); 805 return ret; 806 807 case DP_AUX_I2C_REPLY_NACK: 808 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu\n", ret, msg->size); 809 aux->i2c_nack_count++; 810 return -EREMOTEIO; 811 812 case DP_AUX_I2C_REPLY_DEFER: 813 DRM_DEBUG_KMS("I2C defer\n"); 814 /* DP Compliance Test 4.2.2.5 Requirement: 815 * Must have at least 7 retries for I2C defers on the 816 * transaction to pass this test 817 */ 818 aux->i2c_defer_count++; 819 if (defer_i2c < 7) 820 defer_i2c++; 821 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 822 drm_dp_i2c_msg_write_status_update(msg); 823 824 continue; 825 826 default: 827 DRM_ERROR("invalid I2C reply %#04x\n", msg->reply); 828 return -EREMOTEIO; 829 } 830 } 831 832 DRM_DEBUG_KMS("too many retries, giving up\n"); 833 return -EREMOTEIO; 834 } 835 836 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 837 const struct i2c_msg *i2c_msg) 838 { 839 msg->request = (i2c_msg->flags & I2C_M_RD) ? 840 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 841 msg->request |= DP_AUX_I2C_MOT; 842 } 843 844 /* 845 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 846 * 847 * Returns an error code on failure, or a recommended transfer size on success. 848 */ 849 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) 850 { 851 int err, ret = orig_msg->size; 852 struct drm_dp_aux_msg msg = *orig_msg; 853 854 while (msg.size > 0) { 855 err = drm_dp_i2c_do_msg(aux, &msg); 856 if (err <= 0) 857 return err == 0 ? -EPROTO : err; 858 859 if (err < msg.size && err < ret) { 860 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n", 861 msg.size, err); 862 ret = err; 863 } 864 865 msg.size -= err; 866 msg.buffer += err; 867 } 868 869 return ret; 870 } 871 872 /* 873 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX 874 * packets to be as large as possible. If not, the I2C transactions never 875 * succeed. Hence the default is maximum. 876 */ 877 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; 878 MODULE_PARM_DESC(dp_aux_i2c_transfer_size, 879 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); 880 881 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, 882 int num) 883 { 884 struct drm_dp_aux *aux = adapter->algo_data; 885 unsigned int i, j; 886 unsigned transfer_size; 887 struct drm_dp_aux_msg msg; 888 int err = 0; 889 890 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); 891 892 memset(&msg, 0, sizeof(msg)); 893 894 for (i = 0; i < num; i++) { 895 msg.address = msgs[i].addr; 896 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 897 /* Send a bare address packet to start the transaction. 898 * Zero sized messages specify an address only (bare 899 * address) transaction. 900 */ 901 msg.buffer = NULL; 902 msg.size = 0; 903 err = drm_dp_i2c_do_msg(aux, &msg); 904 905 /* 906 * Reset msg.request in case in case it got 907 * changed into a WRITE_STATUS_UPDATE. 908 */ 909 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 910 911 if (err < 0) 912 break; 913 /* We want each transaction to be as large as possible, but 914 * we'll go to smaller sizes if the hardware gives us a 915 * short reply. 916 */ 917 transfer_size = dp_aux_i2c_transfer_size; 918 for (j = 0; j < msgs[i].len; j += msg.size) { 919 msg.buffer = msgs[i].buf + j; 920 msg.size = min(transfer_size, msgs[i].len - j); 921 922 err = drm_dp_i2c_drain_msg(aux, &msg); 923 924 /* 925 * Reset msg.request in case in case it got 926 * changed into a WRITE_STATUS_UPDATE. 927 */ 928 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 929 930 if (err < 0) 931 break; 932 transfer_size = err; 933 } 934 if (err < 0) 935 break; 936 } 937 if (err >= 0) 938 err = num; 939 /* Send a bare address packet to close out the transaction. 940 * Zero sized messages specify an address only (bare 941 * address) transaction. 942 */ 943 msg.request &= ~DP_AUX_I2C_MOT; 944 msg.buffer = NULL; 945 msg.size = 0; 946 (void)drm_dp_i2c_do_msg(aux, &msg); 947 948 return err; 949 } 950 951 static const struct i2c_algorithm drm_dp_i2c_algo = { 952 .functionality = drm_dp_i2c_functionality, 953 .master_xfer = drm_dp_i2c_xfer, 954 }; 955 956 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) 957 { 958 return container_of(i2c, struct drm_dp_aux, ddc); 959 } 960 961 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 962 { 963 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); 964 } 965 966 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 967 { 968 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); 969 } 970 971 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 972 { 973 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); 974 } 975 976 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { 977 .lock_bus = lock_bus, 978 .trylock_bus = trylock_bus, 979 .unlock_bus = unlock_bus, 980 }; 981 982 /** 983 * drm_dp_aux_init() - minimally initialise an aux channel 984 * @aux: DisplayPort AUX channel 985 * 986 * If you need to use the drm_dp_aux's i2c adapter prior to registering it 987 * with the outside world, call drm_dp_aux_init() first. You must still 988 * call drm_dp_aux_register() once the connector has been registered to 989 * allow userspace access to the auxiliary DP channel. 990 */ 991 void drm_dp_aux_init(struct drm_dp_aux *aux) 992 { 993 lockinit(&aux->hw_mutex, "ahwm", 0, LK_CANRECURSE); 994 995 aux->ddc.algo = &drm_dp_i2c_algo; 996 aux->ddc.algo_data = aux; 997 aux->ddc.retries = 3; 998 999 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; 1000 } 1001 EXPORT_SYMBOL(drm_dp_aux_init); 1002 1003 /** 1004 * drm_dp_aux_register() - initialise and register aux channel 1005 * @aux: DisplayPort AUX channel 1006 * 1007 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. 1008 * 1009 * Returns 0 on success or a negative error code on failure. 1010 */ 1011 int drm_dp_aux_register(struct drm_dp_aux *aux) 1012 { 1013 int ret; 1014 1015 if (!aux->ddc.algo) 1016 drm_dp_aux_init(aux); 1017 1018 #if 0 1019 aux->ddc.class = I2C_CLASS_DDC; 1020 aux->ddc.owner = THIS_MODULE; 1021 #endif 1022 aux->ddc.dev.parent = aux->dev; 1023 #if 0 1024 aux->ddc.dev.of_node = aux->dev->of_node; 1025 #endif 1026 1027 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), 1028 sizeof(aux->ddc.name)); 1029 1030 ret = drm_dp_aux_register_devnode(aux); 1031 if (ret) 1032 return ret; 1033 1034 ret = i2c_add_adapter(&aux->ddc); 1035 if (ret) { 1036 drm_dp_aux_unregister_devnode(aux); 1037 return ret; 1038 } 1039 1040 return 0; 1041 } 1042 EXPORT_SYMBOL(drm_dp_aux_register); 1043 1044 /** 1045 * drm_dp_aux_unregister() - unregister an AUX adapter 1046 * @aux: DisplayPort AUX channel 1047 */ 1048 void drm_dp_aux_unregister(struct drm_dp_aux *aux) 1049 { 1050 drm_dp_aux_unregister_devnode(aux); 1051 i2c_del_adapter(&aux->ddc); 1052 } 1053 EXPORT_SYMBOL(drm_dp_aux_unregister); 1054 1055 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) 1056 1057 /** 1058 * drm_dp_psr_setup_time() - PSR setup in time usec 1059 * @psr_cap: PSR capabilities from DPCD 1060 * 1061 * Returns: 1062 * PSR setup time for the panel in microseconds, negative 1063 * error code on failure. 1064 */ 1065 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) 1066 { 1067 static const u16 psr_setup_time_us[] = { 1068 PSR_SETUP_TIME(330), 1069 PSR_SETUP_TIME(275), 1070 PSR_SETUP_TIME(165), 1071 PSR_SETUP_TIME(110), 1072 PSR_SETUP_TIME(55), 1073 PSR_SETUP_TIME(0), 1074 }; 1075 int i; 1076 1077 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; 1078 if (i >= ARRAY_SIZE(psr_setup_time_us)) 1079 return -EINVAL; 1080 1081 return psr_setup_time_us[i]; 1082 } 1083 EXPORT_SYMBOL(drm_dp_psr_setup_time); 1084 1085 #undef PSR_SETUP_TIME 1086