1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <drm/drmP.h> 31 #include <drm/i915_drm.h> 32 #include "i915_drv.h" 33 #include <drm/drm_pciids.h> 34 #include "intel_drv.h" 35 36 #include <linux/module.h> 37 #include <drm/drm_crtc_helper.h> 38 39 static struct drm_driver driver; 40 41 #define GEN_DEFAULT_PIPEOFFSETS \ 42 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 43 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 44 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 45 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 46 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 47 48 #define GEN_CHV_PIPEOFFSETS \ 49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 50 CHV_PIPE_C_OFFSET }, \ 51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 52 CHV_TRANSCODER_C_OFFSET, }, \ 53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 54 CHV_PALETTE_C_OFFSET } 55 56 #define CURSOR_OFFSETS \ 57 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 58 59 #define IVB_CURSOR_OFFSETS \ 60 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 61 62 static const struct intel_device_info intel_i830_info = { 63 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, 64 .has_overlay = 1, .overlay_needs_physical = 1, 65 .ring_mask = RENDER_RING, 66 GEN_DEFAULT_PIPEOFFSETS, 67 CURSOR_OFFSETS, 68 }; 69 70 static const struct intel_device_info intel_845g_info = { 71 .gen = 2, .num_pipes = 1, 72 .has_overlay = 1, .overlay_needs_physical = 1, 73 .ring_mask = RENDER_RING, 74 GEN_DEFAULT_PIPEOFFSETS, 75 CURSOR_OFFSETS, 76 }; 77 78 static const struct intel_device_info intel_i85x_info = { 79 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, 80 .cursor_needs_physical = 1, 81 .has_overlay = 1, .overlay_needs_physical = 1, 82 .has_fbc = 1, 83 .ring_mask = RENDER_RING, 84 GEN_DEFAULT_PIPEOFFSETS, 85 CURSOR_OFFSETS, 86 }; 87 88 static const struct intel_device_info intel_i865g_info = { 89 .gen = 2, .num_pipes = 1, 90 .has_overlay = 1, .overlay_needs_physical = 1, 91 .ring_mask = RENDER_RING, 92 GEN_DEFAULT_PIPEOFFSETS, 93 CURSOR_OFFSETS, 94 }; 95 96 static const struct intel_device_info intel_i915g_info = { 97 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, 98 .has_overlay = 1, .overlay_needs_physical = 1, 99 .ring_mask = RENDER_RING, 100 GEN_DEFAULT_PIPEOFFSETS, 101 CURSOR_OFFSETS, 102 }; 103 static const struct intel_device_info intel_i915gm_info = { 104 .gen = 3, .is_mobile = 1, .num_pipes = 2, 105 .cursor_needs_physical = 1, 106 .has_overlay = 1, .overlay_needs_physical = 1, 107 .supports_tv = 1, 108 .has_fbc = 1, 109 .ring_mask = RENDER_RING, 110 GEN_DEFAULT_PIPEOFFSETS, 111 CURSOR_OFFSETS, 112 }; 113 static const struct intel_device_info intel_i945g_info = { 114 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, 115 .has_overlay = 1, .overlay_needs_physical = 1, 116 .ring_mask = RENDER_RING, 117 GEN_DEFAULT_PIPEOFFSETS, 118 CURSOR_OFFSETS, 119 }; 120 static const struct intel_device_info intel_i945gm_info = { 121 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, 122 .has_hotplug = 1, .cursor_needs_physical = 1, 123 .has_overlay = 1, .overlay_needs_physical = 1, 124 .supports_tv = 1, 125 .has_fbc = 1, 126 .ring_mask = RENDER_RING, 127 GEN_DEFAULT_PIPEOFFSETS, 128 CURSOR_OFFSETS, 129 }; 130 131 static const struct intel_device_info intel_i965g_info = { 132 .gen = 4, .is_broadwater = 1, .num_pipes = 2, 133 .has_hotplug = 1, 134 .has_overlay = 1, 135 .ring_mask = RENDER_RING, 136 GEN_DEFAULT_PIPEOFFSETS, 137 CURSOR_OFFSETS, 138 }; 139 140 static const struct intel_device_info intel_i965gm_info = { 141 .gen = 4, .is_crestline = 1, .num_pipes = 2, 142 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, 143 .has_overlay = 1, 144 .supports_tv = 1, 145 .ring_mask = RENDER_RING, 146 GEN_DEFAULT_PIPEOFFSETS, 147 CURSOR_OFFSETS, 148 }; 149 150 static const struct intel_device_info intel_g33_info = { 151 .gen = 3, .is_g33 = 1, .num_pipes = 2, 152 .need_gfx_hws = 1, .has_hotplug = 1, 153 .has_overlay = 1, 154 .ring_mask = RENDER_RING, 155 GEN_DEFAULT_PIPEOFFSETS, 156 CURSOR_OFFSETS, 157 }; 158 159 static const struct intel_device_info intel_g45_info = { 160 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, 161 .has_pipe_cxsr = 1, .has_hotplug = 1, 162 .ring_mask = RENDER_RING | BSD_RING, 163 GEN_DEFAULT_PIPEOFFSETS, 164 CURSOR_OFFSETS, 165 }; 166 167 static const struct intel_device_info intel_gm45_info = { 168 .gen = 4, .is_g4x = 1, .num_pipes = 2, 169 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, 170 .has_pipe_cxsr = 1, .has_hotplug = 1, 171 .supports_tv = 1, 172 .ring_mask = RENDER_RING | BSD_RING, 173 GEN_DEFAULT_PIPEOFFSETS, 174 CURSOR_OFFSETS, 175 }; 176 177 static const struct intel_device_info intel_pineview_info = { 178 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, 179 .need_gfx_hws = 1, .has_hotplug = 1, 180 .has_overlay = 1, 181 GEN_DEFAULT_PIPEOFFSETS, 182 CURSOR_OFFSETS, 183 }; 184 185 static const struct intel_device_info intel_ironlake_d_info = { 186 .gen = 5, .num_pipes = 2, 187 .need_gfx_hws = 1, .has_hotplug = 1, 188 .ring_mask = RENDER_RING | BSD_RING, 189 GEN_DEFAULT_PIPEOFFSETS, 190 CURSOR_OFFSETS, 191 }; 192 193 static const struct intel_device_info intel_ironlake_m_info = { 194 .gen = 5, .is_mobile = 1, .num_pipes = 2, 195 .need_gfx_hws = 1, .has_hotplug = 1, 196 .has_fbc = 1, 197 .ring_mask = RENDER_RING | BSD_RING, 198 GEN_DEFAULT_PIPEOFFSETS, 199 CURSOR_OFFSETS, 200 }; 201 202 static const struct intel_device_info intel_sandybridge_d_info = { 203 .gen = 6, .num_pipes = 2, 204 .need_gfx_hws = 1, .has_hotplug = 1, 205 .has_fbc = 1, 206 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 207 .has_llc = 1, 208 GEN_DEFAULT_PIPEOFFSETS, 209 CURSOR_OFFSETS, 210 }; 211 212 static const struct intel_device_info intel_sandybridge_m_info = { 213 .gen = 6, .is_mobile = 1, .num_pipes = 2, 214 .need_gfx_hws = 1, .has_hotplug = 1, 215 .has_fbc = 1, 216 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 217 .has_llc = 1, 218 GEN_DEFAULT_PIPEOFFSETS, 219 CURSOR_OFFSETS, 220 }; 221 222 #define GEN7_FEATURES \ 223 .gen = 7, .num_pipes = 3, \ 224 .need_gfx_hws = 1, .has_hotplug = 1, \ 225 .has_fbc = 1, \ 226 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 227 .has_llc = 1 228 229 static const struct intel_device_info intel_ivybridge_d_info = { 230 GEN7_FEATURES, 231 .is_ivybridge = 1, 232 GEN_DEFAULT_PIPEOFFSETS, 233 IVB_CURSOR_OFFSETS, 234 }; 235 236 static const struct intel_device_info intel_ivybridge_m_info = { 237 GEN7_FEATURES, 238 .is_ivybridge = 1, 239 .is_mobile = 1, 240 GEN_DEFAULT_PIPEOFFSETS, 241 IVB_CURSOR_OFFSETS, 242 }; 243 244 static const struct intel_device_info intel_ivybridge_q_info = { 245 GEN7_FEATURES, 246 .is_ivybridge = 1, 247 .num_pipes = 0, /* legal, last one wins */ 248 GEN_DEFAULT_PIPEOFFSETS, 249 IVB_CURSOR_OFFSETS, 250 }; 251 252 static const struct intel_device_info intel_valleyview_m_info = { 253 GEN7_FEATURES, 254 .is_mobile = 1, 255 .num_pipes = 2, 256 .is_valleyview = 1, 257 .display_mmio_offset = VLV_DISPLAY_BASE, 258 .has_fbc = 0, /* legal, last one wins */ 259 .has_llc = 0, /* legal, last one wins */ 260 GEN_DEFAULT_PIPEOFFSETS, 261 CURSOR_OFFSETS, 262 }; 263 264 static const struct intel_device_info intel_valleyview_d_info = { 265 GEN7_FEATURES, 266 .num_pipes = 2, 267 .is_valleyview = 1, 268 .display_mmio_offset = VLV_DISPLAY_BASE, 269 .has_fbc = 0, /* legal, last one wins */ 270 .has_llc = 0, /* legal, last one wins */ 271 GEN_DEFAULT_PIPEOFFSETS, 272 CURSOR_OFFSETS, 273 }; 274 275 static const struct intel_device_info intel_haswell_d_info = { 276 GEN7_FEATURES, 277 .is_haswell = 1, 278 .has_ddi = 1, 279 .has_fpga_dbg = 1, 280 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 281 GEN_DEFAULT_PIPEOFFSETS, 282 IVB_CURSOR_OFFSETS, 283 }; 284 285 static const struct intel_device_info intel_haswell_m_info = { 286 GEN7_FEATURES, 287 .is_haswell = 1, 288 .is_mobile = 1, 289 .has_ddi = 1, 290 .has_fpga_dbg = 1, 291 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 292 GEN_DEFAULT_PIPEOFFSETS, 293 IVB_CURSOR_OFFSETS, 294 }; 295 296 static const struct intel_device_info intel_broadwell_d_info = { 297 .gen = 8, .num_pipes = 3, 298 .need_gfx_hws = 1, .has_hotplug = 1, 299 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 300 .has_llc = 1, 301 .has_ddi = 1, 302 .has_fpga_dbg = 1, 303 .has_fbc = 1, 304 GEN_DEFAULT_PIPEOFFSETS, 305 IVB_CURSOR_OFFSETS, 306 }; 307 308 static const struct intel_device_info intel_broadwell_m_info = { 309 .gen = 8, .is_mobile = 1, .num_pipes = 3, 310 .need_gfx_hws = 1, .has_hotplug = 1, 311 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 312 .has_llc = 1, 313 .has_ddi = 1, 314 .has_fpga_dbg = 1, 315 .has_fbc = 1, 316 GEN_DEFAULT_PIPEOFFSETS, 317 IVB_CURSOR_OFFSETS, 318 }; 319 320 static const struct intel_device_info intel_broadwell_gt3d_info = { 321 .gen = 8, .num_pipes = 3, 322 .need_gfx_hws = 1, .has_hotplug = 1, 323 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 324 .has_llc = 1, 325 .has_ddi = 1, 326 .has_fpga_dbg = 1, 327 .has_fbc = 1, 328 GEN_DEFAULT_PIPEOFFSETS, 329 IVB_CURSOR_OFFSETS, 330 }; 331 332 static const struct intel_device_info intel_broadwell_gt3m_info = { 333 .gen = 8, .is_mobile = 1, .num_pipes = 3, 334 .need_gfx_hws = 1, .has_hotplug = 1, 335 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 336 .has_llc = 1, 337 .has_ddi = 1, 338 .has_fpga_dbg = 1, 339 .has_fbc = 1, 340 GEN_DEFAULT_PIPEOFFSETS, 341 IVB_CURSOR_OFFSETS, 342 }; 343 344 static const struct intel_device_info intel_cherryview_info = { 345 .gen = 8, .num_pipes = 3, 346 .need_gfx_hws = 1, .has_hotplug = 1, 347 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 348 .is_valleyview = 1, 349 .display_mmio_offset = VLV_DISPLAY_BASE, 350 GEN_CHV_PIPEOFFSETS, 351 CURSOR_OFFSETS, 352 }; 353 354 static const struct intel_device_info intel_skylake_info = { 355 .is_preliminary = 1, 356 .is_skylake = 1, 357 .gen = 9, .num_pipes = 3, 358 .need_gfx_hws = 1, .has_hotplug = 1, 359 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 360 .has_llc = 1, 361 .has_ddi = 1, 362 .has_fbc = 1, 363 GEN_DEFAULT_PIPEOFFSETS, 364 IVB_CURSOR_OFFSETS, 365 }; 366 367 static const struct intel_device_info intel_skylake_gt3_info = { 368 .is_preliminary = 1, 369 .is_skylake = 1, 370 .gen = 9, .num_pipes = 3, 371 .need_gfx_hws = 1, .has_hotplug = 1, 372 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 373 .has_llc = 1, 374 .has_ddi = 1, 375 .has_fbc = 1, 376 GEN_DEFAULT_PIPEOFFSETS, 377 IVB_CURSOR_OFFSETS, 378 }; 379 380 static const struct intel_device_info intel_broxton_info = { 381 .is_preliminary = 1, 382 .gen = 9, 383 .need_gfx_hws = 1, .has_hotplug = 1, 384 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 385 .num_pipes = 3, 386 .has_ddi = 1, 387 .has_fbc = 1, 388 GEN_DEFAULT_PIPEOFFSETS, 389 IVB_CURSOR_OFFSETS, 390 }; 391 392 /* 393 * Make sure any device matches here are from most specific to most 394 * general. For example, since the Quanta match is based on the subsystem 395 * and subvendor IDs, we need it to come before the more general IVB 396 * PCI ID matches, otherwise we'll use the wrong info struct above. 397 */ 398 #define INTEL_PCI_IDS \ 399 INTEL_I830_IDS(&intel_i830_info), \ 400 INTEL_I845G_IDS(&intel_845g_info), \ 401 INTEL_I85X_IDS(&intel_i85x_info), \ 402 INTEL_I865G_IDS(&intel_i865g_info), \ 403 INTEL_I915G_IDS(&intel_i915g_info), \ 404 INTEL_I915GM_IDS(&intel_i915gm_info), \ 405 INTEL_I945G_IDS(&intel_i945g_info), \ 406 INTEL_I945GM_IDS(&intel_i945gm_info), \ 407 INTEL_I965G_IDS(&intel_i965g_info), \ 408 INTEL_G33_IDS(&intel_g33_info), \ 409 INTEL_I965GM_IDS(&intel_i965gm_info), \ 410 INTEL_GM45_IDS(&intel_gm45_info), \ 411 INTEL_G45_IDS(&intel_g45_info), \ 412 INTEL_PINEVIEW_IDS(&intel_pineview_info), \ 413 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ 414 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ 415 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ 416 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ 417 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ 418 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ 419 INTEL_HSW_D_IDS(&intel_haswell_d_info), \ 420 INTEL_HSW_M_IDS(&intel_haswell_m_info), \ 421 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ 422 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ 423 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ 424 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ 425 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ 426 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \ 427 INTEL_CHV_IDS(&intel_cherryview_info), \ 428 INTEL_SKL_GT1_IDS(&intel_skylake_info), \ 429 INTEL_SKL_GT2_IDS(&intel_skylake_info), \ 430 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \ 431 INTEL_BXT_IDS(&intel_broxton_info) 432 433 static const struct pci_device_id pciidlist[] = { /* aka */ 434 INTEL_PCI_IDS, 435 {0, 0} 436 }; 437 438 #define PCI_VENDOR_INTEL 0x8086 439 440 void intel_detect_pch(struct drm_device *dev) 441 { 442 struct drm_i915_private *dev_priv = dev->dev_private; 443 struct device *pch = NULL; 444 struct pci_devinfo *di; 445 446 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting 447 * (which really amounts to a PCH but no South Display). 448 */ 449 if (INTEL_INFO(dev)->num_pipes == 0) { 450 dev_priv->pch_type = PCH_NOP; 451 return; 452 } 453 454 /* XXX The ISA bridge probe causes some old Core2 machines to hang */ 455 if (INTEL_INFO(dev)->gen < 5) 456 return; 457 458 /* 459 * The reason to probe ISA bridge instead of Dev31:Fun0 is to 460 * make graphics device passthrough work easy for VMM, that only 461 * need to expose ISA bridge to let driver know the real hardware 462 * underneath. This is a requirement from virtualization team. 463 * 464 * In some virtualized environments (e.g. XEN), there is irrelevant 465 * ISA bridge in the system. To work reliably, we should scan trhough 466 * all the ISA bridge devices and check for the first match, instead 467 * of only checking the first one. 468 */ 469 di = NULL; 470 471 while ((pch = pci_iterate_class(&di, PCIC_BRIDGE, PCIS_BRIDGE_ISA))) { 472 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) { 473 unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK; 474 dev_priv->pch_id = id; 475 476 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { 477 dev_priv->pch_type = PCH_IBX; 478 DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); 479 WARN_ON(!IS_GEN5(dev)); 480 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { 481 dev_priv->pch_type = PCH_CPT; 482 DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 483 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 484 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { 485 /* PantherPoint is CPT compatible */ 486 dev_priv->pch_type = PCH_CPT; 487 DRM_DEBUG_KMS("Found PantherPoint PCH\n"); 488 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 489 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 490 dev_priv->pch_type = PCH_LPT; 491 DRM_DEBUG_KMS("Found LynxPoint PCH\n"); 492 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); 493 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); 494 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 495 dev_priv->pch_type = PCH_LPT; 496 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); 497 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); 498 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); 499 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { 500 dev_priv->pch_type = PCH_SPT; 501 DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); 502 WARN_ON(!IS_SKYLAKE(dev)); 503 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { 504 dev_priv->pch_type = PCH_SPT; 505 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); 506 WARN_ON(!IS_SKYLAKE(dev)); 507 } else 508 continue; 509 510 break; 511 } 512 } 513 if (!pch) 514 DRM_DEBUG_KMS("No PCH found.\n"); 515 516 #if 0 517 pci_dev_put(pch); 518 #endif 519 } 520 521 bool i915_semaphore_is_enabled(struct drm_device *dev) 522 { 523 if (INTEL_INFO(dev)->gen < 6) 524 return false; 525 526 if (i915.semaphores >= 0) 527 return i915.semaphores; 528 529 /* TODO: make semaphores and Execlists play nicely together */ 530 if (i915.enable_execlists) 531 return false; 532 533 /* Until we get further testing... */ 534 if (IS_GEN8(dev)) 535 return false; 536 537 #ifdef CONFIG_INTEL_IOMMU 538 /* Enable semaphores on SNB when IO remapping is off */ 539 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) 540 return false; 541 #endif 542 543 return true; 544 } 545 546 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) 547 { 548 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 549 550 dev_priv->long_hpd_port_mask = 0; 551 dev_priv->short_hpd_port_mask = 0; 552 dev_priv->hpd_event_bits = 0; 553 554 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 555 556 cancel_work_sync(&dev_priv->dig_port_work); 557 cancel_work_sync(&dev_priv->hotplug_work); 558 cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work); 559 } 560 561 #ifdef __DragonFly__ 562 #define IS_BUILTIN(blah) 0 563 #endif 564 565 void i915_firmware_load_error_print(const char *fw_path, int err) 566 { 567 DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err); 568 569 /* 570 * If the reason is not known assume -ENOENT since that's the most 571 * usual failure mode. 572 */ 573 if (!err) 574 err = -ENOENT; 575 576 if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT)) 577 return; 578 579 DRM_ERROR( 580 "The driver is built-in, so to load the firmware you need to\n" 581 "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n" 582 "in your initrd/initramfs image.\n"); 583 } 584 585 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 586 { 587 struct drm_device *dev = dev_priv->dev; 588 struct drm_encoder *encoder; 589 590 drm_modeset_lock_all(dev); 591 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 592 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 593 594 if (intel_encoder->suspend) 595 intel_encoder->suspend(intel_encoder); 596 } 597 drm_modeset_unlock_all(dev); 598 } 599 600 601 static int intel_suspend_complete(struct drm_i915_private *dev_priv); 602 static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 603 bool rpm_resume); 604 static int skl_resume_prepare(struct drm_i915_private *dev_priv); 605 static int bxt_resume_prepare(struct drm_i915_private *dev_priv); 606 607 608 static int i915_drm_suspend(struct drm_device *dev) 609 { 610 struct drm_i915_private *dev_priv = dev->dev_private; 611 struct drm_crtc *crtc; 612 pci_power_t opregion_target_state; 613 int error; 614 615 /* ignore lid events during suspend */ 616 mutex_lock(&dev_priv->modeset_restore_lock); 617 dev_priv->modeset_restore = MODESET_SUSPENDED; 618 mutex_unlock(&dev_priv->modeset_restore_lock); 619 620 /* We do a lot of poking in a lot of registers, make sure they work 621 * properly. */ 622 intel_display_set_init_power(dev_priv, true); 623 624 drm_kms_helper_poll_disable(dev); 625 626 #if 0 627 pci_save_state(dev->pdev); 628 #endif 629 630 error = i915_gem_suspend(dev); 631 if (error) { 632 dev_err(dev->pdev->dev, 633 "GEM idle failed, resume might fail\n"); 634 return error; 635 } 636 637 intel_suspend_gt_powersave(dev); 638 639 /* 640 * Disable CRTCs directly since we want to preserve sw state 641 * for _thaw. Also, power gate the CRTC power wells. 642 */ 643 drm_modeset_lock_all(dev); 644 for_each_crtc(dev, crtc) 645 intel_crtc_control(crtc, false); 646 drm_modeset_unlock_all(dev); 647 648 #if 0 649 intel_dp_mst_suspend(dev); 650 #endif 651 652 intel_runtime_pm_disable_interrupts(dev_priv); 653 intel_hpd_cancel_work(dev_priv); 654 655 intel_suspend_encoders(dev_priv); 656 657 intel_suspend_hw(dev); 658 659 i915_gem_suspend_gtt_mappings(dev); 660 661 i915_save_state(dev); 662 663 opregion_target_state = PCI_D3cold; 664 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 665 if (acpi_target_system_state() < ACPI_STATE_S3) 666 opregion_target_state = PCI_D1; 667 #endif 668 intel_opregion_notify_adapter(dev, opregion_target_state); 669 670 intel_uncore_forcewake_reset(dev, false); 671 intel_opregion_fini(dev); 672 673 #if 0 674 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 675 #endif 676 677 dev_priv->suspend_count++; 678 679 intel_display_set_init_power(dev_priv, false); 680 681 return 0; 682 } 683 684 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) 685 { 686 struct drm_i915_private *dev_priv = drm_dev->dev_private; 687 int ret; 688 689 ret = intel_suspend_complete(dev_priv); 690 691 if (ret) { 692 DRM_ERROR("Suspend complete failed: %d\n", ret); 693 694 return ret; 695 } 696 697 #if 0 698 pci_disable_device(drm_dev->pdev); 699 /* 700 * During hibernation on some GEN4 platforms the BIOS may try to access 701 * the device even though it's already in D3 and hang the machine. So 702 * leave the device in D0 on those platforms and hope the BIOS will 703 * power down the device properly. Platforms where this was seen: 704 * Lenovo Thinkpad X301, X61s 705 */ 706 if (!(hibernation && 707 drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO && 708 INTEL_INFO(dev_priv)->gen == 4)) 709 pci_set_power_state(drm_dev->pdev, PCI_D3hot); 710 #endif 711 712 return 0; 713 } 714 715 int i915_suspend_legacy(device_t kdev) 716 { 717 struct drm_device *dev = device_get_softc(kdev); 718 int error; 719 720 if (!dev || !dev->dev_private) { 721 DRM_ERROR("dev: %p\n", dev); 722 DRM_ERROR("DRM not initialized, aborting suspend.\n"); 723 return -ENODEV; 724 } 725 726 #if 0 727 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && 728 state.event != PM_EVENT_FREEZE)) 729 return -EINVAL; 730 #endif 731 732 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 733 return 0; 734 735 error = i915_drm_suspend(dev); 736 if (error) 737 return error; 738 739 return i915_drm_suspend_late(dev, false); 740 } 741 742 static int i915_drm_resume(struct drm_device *dev) 743 { 744 struct drm_i915_private *dev_priv = dev->dev_private; 745 746 mutex_lock(&dev->struct_mutex); 747 i915_gem_restore_gtt_mappings(dev); 748 mutex_unlock(&dev->struct_mutex); 749 750 i915_restore_state(dev); 751 intel_opregion_setup(dev); 752 753 intel_init_pch_refclk(dev); 754 drm_mode_config_reset(dev); 755 756 /* 757 * Interrupts have to be enabled before any batches are run. If not the 758 * GPU will hang. i915_gem_init_hw() will initiate batches to 759 * update/restore the context. 760 * 761 * Modeset enabling in intel_modeset_init_hw() also needs working 762 * interrupts. 763 */ 764 intel_runtime_pm_enable_interrupts(dev_priv); 765 766 mutex_lock(&dev->struct_mutex); 767 if (i915_gem_init_hw(dev)) { 768 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); 769 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); 770 } 771 mutex_unlock(&dev->struct_mutex); 772 773 intel_modeset_init_hw(dev); 774 775 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 776 if (dev_priv->display.hpd_irq_setup) 777 dev_priv->display.hpd_irq_setup(dev); 778 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 779 780 drm_modeset_lock_all(dev); 781 intel_modeset_setup_hw_state(dev, true); 782 drm_modeset_unlock_all(dev); 783 784 intel_dp_mst_resume(dev); 785 786 /* 787 * ... but also need to make sure that hotplug processing 788 * doesn't cause havoc. Like in the driver load code we don't 789 * bother with the tiny race here where we might loose hotplug 790 * notifications. 791 * */ 792 intel_hpd_init(dev_priv); 793 /* Config may have changed between suspend and resume */ 794 drm_helper_hpd_irq_event(dev); 795 796 intel_opregion_init(dev); 797 798 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 799 800 mutex_lock(&dev_priv->modeset_restore_lock); 801 dev_priv->modeset_restore = MODESET_DONE; 802 mutex_unlock(&dev_priv->modeset_restore_lock); 803 804 #if 0 805 intel_opregion_notify_adapter(dev, PCI_D0); 806 #endif 807 808 drm_kms_helper_poll_enable(dev); 809 810 return 0; 811 } 812 813 static int i915_drm_resume_early(struct drm_device *dev) 814 { 815 struct drm_i915_private *dev_priv = dev->dev_private; 816 int ret = 0; 817 818 /* 819 * We have a resume ordering issue with the snd-hda driver also 820 * requiring our device to be power up. Due to the lack of a 821 * parent/child relationship we currently solve this with an early 822 * resume hook. 823 * 824 * FIXME: This should be solved with a special hdmi sink device or 825 * similar so that power domains can be employed. 826 */ 827 #if 0 828 if (pci_enable_device(dev->pdev)) 829 return -EIO; 830 831 pci_set_master(dev->pdev); 832 #endif 833 834 if (IS_VALLEYVIEW(dev_priv)) 835 ret = vlv_resume_prepare(dev_priv, false); 836 if (ret) 837 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", 838 ret); 839 840 intel_uncore_early_sanitize(dev, true); 841 842 if (IS_BROXTON(dev)) 843 ret = bxt_resume_prepare(dev_priv); 844 else if (IS_SKYLAKE(dev_priv)) 845 ret = skl_resume_prepare(dev_priv); 846 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 847 hsw_disable_pc8(dev_priv); 848 849 intel_uncore_sanitize(dev); 850 intel_power_domains_init_hw(dev_priv); 851 852 return ret; 853 } 854 855 int i915_resume_legacy(struct drm_device *dev) 856 { 857 int ret; 858 859 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 860 return 0; 861 862 ret = i915_drm_resume_early(dev); 863 if (ret) 864 return ret; 865 866 return i915_drm_resume(dev); 867 } 868 869 /* XXX Hack for the old *BSD drm code base 870 * The device id field is set at probe time */ 871 static drm_pci_id_list_t i915_attach_list[] = { 872 {0x8086, 0, 0, "Intel i915 GPU"}, 873 {0, 0, 0, NULL} 874 }; 875 876 struct intel_device_info * 877 i915_get_device_id(int device) 878 { 879 const struct pci_device_id *did; 880 881 for (did = &pciidlist[0]; did->device != 0; did++) { 882 if (did->device != device) 883 continue; 884 return (struct intel_device_info *)did->driver_data; 885 } 886 return (NULL); 887 } 888 889 extern devclass_t drm_devclass; 890 891 /** 892 * i915_reset - reset chip after a hang 893 * @dev: drm device to reset 894 * 895 * Reset the chip. Useful if a hang is detected. Returns zero on successful 896 * reset or otherwise an error code. 897 * 898 * Procedure is fairly simple: 899 * - reset the chip using the reset reg 900 * - re-init context state 901 * - re-init hardware status page 902 * - re-init ring buffer 903 * - re-init interrupt state 904 * - re-init display 905 */ 906 int i915_reset(struct drm_device *dev) 907 { 908 struct drm_i915_private *dev_priv = dev->dev_private; 909 bool simulated; 910 int ret; 911 912 if (!i915.reset) 913 return 0; 914 915 intel_reset_gt_powersave(dev); 916 917 mutex_lock(&dev->struct_mutex); 918 919 i915_gem_reset(dev); 920 921 simulated = dev_priv->gpu_error.stop_rings != 0; 922 923 ret = intel_gpu_reset(dev); 924 925 /* Also reset the gpu hangman. */ 926 if (simulated) { 927 DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); 928 dev_priv->gpu_error.stop_rings = 0; 929 if (ret == -ENODEV) { 930 DRM_INFO("Reset not implemented, but ignoring " 931 "error for simulated gpu hangs\n"); 932 ret = 0; 933 } 934 } 935 936 if (i915_stop_ring_allow_warn(dev_priv)) 937 pr_notice("drm/i915: Resetting chip after gpu hang\n"); 938 939 if (ret) { 940 DRM_ERROR("Failed to reset chip: %i\n", ret); 941 mutex_unlock(&dev->struct_mutex); 942 return ret; 943 } 944 945 intel_overlay_reset(dev_priv); 946 947 /* Ok, now get things going again... */ 948 949 /* 950 * Everything depends on having the GTT running, so we need to start 951 * there. Fortunately we don't need to do this unless we reset the 952 * chip at a PCI level. 953 * 954 * Next we need to restore the context, but we don't use those 955 * yet either... 956 * 957 * Ring buffer needs to be re-initialized in the KMS case, or if X 958 * was running at the time of the reset (i.e. we weren't VT 959 * switched away). 960 */ 961 962 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ 963 dev_priv->gpu_error.reload_in_reset = true; 964 965 ret = i915_gem_init_hw(dev); 966 967 dev_priv->gpu_error.reload_in_reset = false; 968 969 mutex_unlock(&dev->struct_mutex); 970 if (ret) { 971 DRM_ERROR("Failed hw init on reset %d\n", ret); 972 return ret; 973 } 974 975 /* 976 * rps/rc6 re-init is necessary to restore state lost after the 977 * reset and the re-install of gt irqs. Skip for ironlake per 978 * previous concerns that it doesn't respond well to some forms 979 * of re-init after reset. 980 */ 981 if (INTEL_INFO(dev)->gen > 5) 982 intel_enable_gt_powersave(dev); 983 984 return 0; 985 } 986 987 static int i915_pci_probe(device_t kdev) 988 { 989 int device, i = 0; 990 991 if (pci_get_class(kdev) != PCIC_DISPLAY) 992 return ENXIO; 993 994 if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL) 995 return ENXIO; 996 997 device = pci_get_device(kdev); 998 999 driver.driver_features &= ~(DRIVER_USE_AGP); 1000 1001 for (i = 0; pciidlist[i].device != 0; i++) { 1002 if (pciidlist[i].device == device) { 1003 i915_attach_list[0].device = device; 1004 return 0; 1005 } 1006 } 1007 1008 return ENXIO; 1009 } 1010 1011 #if 0 1012 static void 1013 i915_pci_remove(struct pci_dev *pdev) 1014 { 1015 struct drm_device *dev = pci_get_drvdata(pdev); 1016 1017 drm_put_dev(dev); 1018 } 1019 1020 static int i915_pm_suspend(struct device *dev) 1021 { 1022 struct pci_dev *pdev = to_pci_dev(dev); 1023 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1024 1025 if (!drm_dev || !drm_dev->dev_private) { 1026 dev_err(dev, "DRM not initialized, aborting suspend.\n"); 1027 return -ENODEV; 1028 } 1029 1030 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1031 return 0; 1032 1033 return i915_drm_suspend(drm_dev); 1034 } 1035 1036 static int i915_pm_suspend_late(struct device *dev) 1037 { 1038 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1039 1040 /* 1041 * We have a suspend ordering issue with the snd-hda driver also 1042 * requiring our device to be power up. Due to the lack of a 1043 * parent/child relationship we currently solve this with an late 1044 * suspend hook. 1045 * 1046 * FIXME: This should be solved with a special hdmi sink device or 1047 * similar so that power domains can be employed. 1048 */ 1049 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1050 return 0; 1051 1052 return i915_drm_suspend_late(drm_dev, false); 1053 } 1054 1055 static int i915_pm_poweroff_late(struct device *dev) 1056 { 1057 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1058 1059 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1060 return 0; 1061 1062 return i915_drm_suspend_late(drm_dev, true); 1063 } 1064 1065 static int i915_pm_resume_early(struct device *dev) 1066 { 1067 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1068 1069 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1070 return 0; 1071 1072 return i915_drm_resume_early(drm_dev); 1073 } 1074 1075 static int i915_pm_resume(struct device *dev) 1076 { 1077 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1078 1079 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1080 return 0; 1081 1082 return i915_drm_resume(drm_dev); 1083 } 1084 #endif 1085 1086 static int skl_suspend_complete(struct drm_i915_private *dev_priv) 1087 { 1088 /* Enabling DC6 is not a hard requirement to enter runtime D3 */ 1089 1090 /* 1091 * This is to ensure that CSR isn't identified as loaded before 1092 * CSR-loading program is called during runtime-resume. 1093 */ 1094 intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED); 1095 1096 skl_uninit_cdclk(dev_priv); 1097 1098 return 0; 1099 } 1100 1101 static int hsw_suspend_complete(struct drm_i915_private *dev_priv) 1102 { 1103 hsw_enable_pc8(dev_priv); 1104 1105 return 0; 1106 } 1107 1108 static int bxt_suspend_complete(struct drm_i915_private *dev_priv) 1109 { 1110 struct drm_device *dev = dev_priv->dev; 1111 1112 /* TODO: when DC5 support is added disable DC5 here. */ 1113 1114 broxton_ddi_phy_uninit(dev); 1115 broxton_uninit_cdclk(dev); 1116 bxt_enable_dc9(dev_priv); 1117 1118 return 0; 1119 } 1120 1121 static int bxt_resume_prepare(struct drm_i915_private *dev_priv) 1122 { 1123 struct drm_device *dev = dev_priv->dev; 1124 1125 /* TODO: when CSR FW support is added make sure the FW is loaded */ 1126 1127 bxt_disable_dc9(dev_priv); 1128 1129 /* 1130 * TODO: when DC5 support is added enable DC5 here if the CSR FW 1131 * is available. 1132 */ 1133 broxton_init_cdclk(dev); 1134 broxton_ddi_phy_init(dev); 1135 intel_prepare_ddi(dev); 1136 1137 return 0; 1138 } 1139 1140 static int skl_resume_prepare(struct drm_i915_private *dev_priv) 1141 { 1142 struct drm_device *dev = dev_priv->dev; 1143 1144 skl_init_cdclk(dev_priv); 1145 intel_csr_load_program(dev); 1146 1147 return 0; 1148 } 1149 1150 /* 1151 * Save all Gunit registers that may be lost after a D3 and a subsequent 1152 * S0i[R123] transition. The list of registers needing a save/restore is 1153 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit 1154 * registers in the following way: 1155 * - Driver: saved/restored by the driver 1156 * - Punit : saved/restored by the Punit firmware 1157 * - No, w/o marking: no need to save/restore, since the register is R/O or 1158 * used internally by the HW in a way that doesn't depend 1159 * keeping the content across a suspend/resume. 1160 * - Debug : used for debugging 1161 * 1162 * We save/restore all registers marked with 'Driver', with the following 1163 * exceptions: 1164 * - Registers out of use, including also registers marked with 'Debug'. 1165 * These have no effect on the driver's operation, so we don't save/restore 1166 * them to reduce the overhead. 1167 * - Registers that are fully setup by an initialization function called from 1168 * the resume path. For example many clock gating and RPS/RC6 registers. 1169 * - Registers that provide the right functionality with their reset defaults. 1170 * 1171 * TODO: Except for registers that based on the above 3 criteria can be safely 1172 * ignored, we save/restore all others, practically treating the HW context as 1173 * a black-box for the driver. Further investigation is needed to reduce the 1174 * saved/restored registers even further, by following the same 3 criteria. 1175 */ 1176 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1177 { 1178 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1179 int i; 1180 1181 /* GAM 0x4000-0x4770 */ 1182 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); 1183 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); 1184 s->arb_mode = I915_READ(ARB_MODE); 1185 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); 1186 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); 1187 1188 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1189 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); 1190 1191 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); 1192 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); 1193 1194 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); 1195 s->ecochk = I915_READ(GAM_ECOCHK); 1196 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); 1197 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); 1198 1199 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); 1200 1201 /* MBC 0x9024-0x91D0, 0x8500 */ 1202 s->g3dctl = I915_READ(VLV_G3DCTL); 1203 s->gsckgctl = I915_READ(VLV_GSCKGCTL); 1204 s->mbctl = I915_READ(GEN6_MBCTL); 1205 1206 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1207 s->ucgctl1 = I915_READ(GEN6_UCGCTL1); 1208 s->ucgctl3 = I915_READ(GEN6_UCGCTL3); 1209 s->rcgctl1 = I915_READ(GEN6_RCGCTL1); 1210 s->rcgctl2 = I915_READ(GEN6_RCGCTL2); 1211 s->rstctl = I915_READ(GEN6_RSTCTL); 1212 s->misccpctl = I915_READ(GEN7_MISCCPCTL); 1213 1214 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1215 s->gfxpause = I915_READ(GEN6_GFXPAUSE); 1216 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); 1217 s->rpdeuc = I915_READ(GEN6_RPDEUC); 1218 s->ecobus = I915_READ(ECOBUS); 1219 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); 1220 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); 1221 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); 1222 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); 1223 s->rcedata = I915_READ(VLV_RCEDATA); 1224 s->spare2gh = I915_READ(VLV_SPAREG2H); 1225 1226 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1227 s->gt_imr = I915_READ(GTIMR); 1228 s->gt_ier = I915_READ(GTIER); 1229 s->pm_imr = I915_READ(GEN6_PMIMR); 1230 s->pm_ier = I915_READ(GEN6_PMIER); 1231 1232 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1233 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); 1234 1235 /* GT SA CZ domain, 0x100000-0x138124 */ 1236 s->tilectl = I915_READ(TILECTL); 1237 s->gt_fifoctl = I915_READ(GTFIFOCTL); 1238 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); 1239 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1240 s->pmwgicz = I915_READ(VLV_PMWGICZ); 1241 1242 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1243 s->gu_ctl0 = I915_READ(VLV_GU_CTL0); 1244 s->gu_ctl1 = I915_READ(VLV_GU_CTL1); 1245 s->pcbr = I915_READ(VLV_PCBR); 1246 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); 1247 1248 /* 1249 * Not saving any of: 1250 * DFT, 0x9800-0x9EC0 1251 * SARB, 0xB000-0xB1FC 1252 * GAC, 0x5208-0x524C, 0x14000-0x14C000 1253 * PCI CFG 1254 */ 1255 } 1256 1257 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1258 { 1259 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1260 u32 val; 1261 int i; 1262 1263 /* GAM 0x4000-0x4770 */ 1264 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); 1265 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); 1266 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); 1267 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); 1268 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); 1269 1270 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1271 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); 1272 1273 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); 1274 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); 1275 1276 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); 1277 I915_WRITE(GAM_ECOCHK, s->ecochk); 1278 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); 1279 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); 1280 1281 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); 1282 1283 /* MBC 0x9024-0x91D0, 0x8500 */ 1284 I915_WRITE(VLV_G3DCTL, s->g3dctl); 1285 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); 1286 I915_WRITE(GEN6_MBCTL, s->mbctl); 1287 1288 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1289 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); 1290 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); 1291 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); 1292 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); 1293 I915_WRITE(GEN6_RSTCTL, s->rstctl); 1294 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); 1295 1296 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1297 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); 1298 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); 1299 I915_WRITE(GEN6_RPDEUC, s->rpdeuc); 1300 I915_WRITE(ECOBUS, s->ecobus); 1301 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); 1302 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); 1303 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); 1304 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); 1305 I915_WRITE(VLV_RCEDATA, s->rcedata); 1306 I915_WRITE(VLV_SPAREG2H, s->spare2gh); 1307 1308 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1309 I915_WRITE(GTIMR, s->gt_imr); 1310 I915_WRITE(GTIER, s->gt_ier); 1311 I915_WRITE(GEN6_PMIMR, s->pm_imr); 1312 I915_WRITE(GEN6_PMIER, s->pm_ier); 1313 1314 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1315 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); 1316 1317 /* GT SA CZ domain, 0x100000-0x138124 */ 1318 I915_WRITE(TILECTL, s->tilectl); 1319 I915_WRITE(GTFIFOCTL, s->gt_fifoctl); 1320 /* 1321 * Preserve the GT allow wake and GFX force clock bit, they are not 1322 * be restored, as they are used to control the s0ix suspend/resume 1323 * sequence by the caller. 1324 */ 1325 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1326 val &= VLV_GTLC_ALLOWWAKEREQ; 1327 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; 1328 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1329 1330 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1331 val &= VLV_GFX_CLK_FORCE_ON_BIT; 1332 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; 1333 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1334 1335 I915_WRITE(VLV_PMWGICZ, s->pmwgicz); 1336 1337 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1338 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); 1339 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); 1340 I915_WRITE(VLV_PCBR, s->pcbr); 1341 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); 1342 } 1343 1344 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) 1345 { 1346 u32 val; 1347 int err; 1348 1349 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) 1350 1351 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1352 val &= ~VLV_GFX_CLK_FORCE_ON_BIT; 1353 if (force_on) 1354 val |= VLV_GFX_CLK_FORCE_ON_BIT; 1355 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1356 1357 if (!force_on) 1358 return 0; 1359 1360 err = wait_for(COND, 20); 1361 if (err) 1362 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", 1363 I915_READ(VLV_GTLC_SURVIVABILITY_REG)); 1364 1365 return err; 1366 #undef COND 1367 } 1368 1369 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) 1370 { 1371 u32 val; 1372 int err = 0; 1373 1374 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1375 val &= ~VLV_GTLC_ALLOWWAKEREQ; 1376 if (allow) 1377 val |= VLV_GTLC_ALLOWWAKEREQ; 1378 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1379 POSTING_READ(VLV_GTLC_WAKE_CTRL); 1380 1381 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ 1382 allow) 1383 err = wait_for(COND, 1); 1384 if (err) 1385 DRM_ERROR("timeout disabling GT waking\n"); 1386 return err; 1387 #undef COND 1388 } 1389 1390 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, 1391 bool wait_for_on) 1392 { 1393 u32 mask; 1394 u32 val; 1395 int err; 1396 1397 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; 1398 val = wait_for_on ? mask : 0; 1399 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) 1400 if (COND) 1401 return 0; 1402 1403 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", 1404 wait_for_on ? "on" : "off", 1405 I915_READ(VLV_GTLC_PW_STATUS)); 1406 1407 /* 1408 * RC6 transitioning can be delayed up to 2 msec (see 1409 * valleyview_enable_rps), use 3 msec for safety. 1410 */ 1411 err = wait_for(COND, 3); 1412 if (err) 1413 DRM_ERROR("timeout waiting for GT wells to go %s\n", 1414 wait_for_on ? "on" : "off"); 1415 1416 return err; 1417 #undef COND 1418 } 1419 1420 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) 1421 { 1422 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) 1423 return; 1424 1425 DRM_ERROR("GT register access while GT waking disabled\n"); 1426 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); 1427 } 1428 1429 static int vlv_suspend_complete(struct drm_i915_private *dev_priv) 1430 { 1431 u32 mask; 1432 int err; 1433 1434 /* 1435 * Bspec defines the following GT well on flags as debug only, so 1436 * don't treat them as hard failures. 1437 */ 1438 (void)vlv_wait_for_gt_wells(dev_priv, false); 1439 1440 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; 1441 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); 1442 1443 vlv_check_no_gt_access(dev_priv); 1444 1445 err = vlv_force_gfx_clock(dev_priv, true); 1446 if (err) 1447 goto err1; 1448 1449 err = vlv_allow_gt_wake(dev_priv, false); 1450 if (err) 1451 goto err2; 1452 1453 if (!IS_CHERRYVIEW(dev_priv->dev)) 1454 vlv_save_gunit_s0ix_state(dev_priv); 1455 1456 err = vlv_force_gfx_clock(dev_priv, false); 1457 if (err) 1458 goto err2; 1459 1460 return 0; 1461 1462 err2: 1463 /* For safety always re-enable waking and disable gfx clock forcing */ 1464 vlv_allow_gt_wake(dev_priv, true); 1465 err1: 1466 vlv_force_gfx_clock(dev_priv, false); 1467 1468 return err; 1469 } 1470 1471 static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 1472 bool rpm_resume) 1473 { 1474 struct drm_device *dev = dev_priv->dev; 1475 int err; 1476 int ret; 1477 1478 /* 1479 * If any of the steps fail just try to continue, that's the best we 1480 * can do at this point. Return the first error code (which will also 1481 * leave RPM permanently disabled). 1482 */ 1483 ret = vlv_force_gfx_clock(dev_priv, true); 1484 1485 if (!IS_CHERRYVIEW(dev_priv->dev)) 1486 vlv_restore_gunit_s0ix_state(dev_priv); 1487 1488 err = vlv_allow_gt_wake(dev_priv, true); 1489 if (!ret) 1490 ret = err; 1491 1492 err = vlv_force_gfx_clock(dev_priv, false); 1493 if (!ret) 1494 ret = err; 1495 1496 vlv_check_no_gt_access(dev_priv); 1497 1498 if (rpm_resume) { 1499 intel_init_clock_gating(dev); 1500 i915_gem_restore_fences(dev); 1501 } 1502 1503 return ret; 1504 } 1505 1506 #if 0 1507 static int intel_runtime_suspend(struct device *device) 1508 { 1509 struct pci_dev *pdev = to_pci_dev(device); 1510 struct drm_device *dev = pci_get_drvdata(pdev); 1511 struct drm_i915_private *dev_priv = dev->dev_private; 1512 int ret; 1513 1514 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) 1515 return -ENODEV; 1516 1517 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) 1518 return -ENODEV; 1519 1520 DRM_DEBUG_KMS("Suspending device\n"); 1521 1522 /* 1523 * We could deadlock here in case another thread holding struct_mutex 1524 * calls RPM suspend concurrently, since the RPM suspend will wait 1525 * first for this RPM suspend to finish. In this case the concurrent 1526 * RPM resume will be followed by its RPM suspend counterpart. Still 1527 * for consistency return -EAGAIN, which will reschedule this suspend. 1528 */ 1529 if (!mutex_trylock(&dev->struct_mutex)) { 1530 DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); 1531 /* 1532 * Bump the expiration timestamp, otherwise the suspend won't 1533 * be rescheduled. 1534 */ 1535 pm_runtime_mark_last_busy(device); 1536 1537 return -EAGAIN; 1538 } 1539 /* 1540 * We are safe here against re-faults, since the fault handler takes 1541 * an RPM reference. 1542 */ 1543 i915_gem_release_all_mmaps(dev_priv); 1544 mutex_unlock(&dev->struct_mutex); 1545 1546 intel_suspend_gt_powersave(dev); 1547 intel_runtime_pm_disable_interrupts(dev_priv); 1548 1549 ret = intel_suspend_complete(dev_priv); 1550 if (ret) { 1551 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); 1552 intel_runtime_pm_enable_interrupts(dev_priv); 1553 1554 return ret; 1555 } 1556 1557 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); 1558 intel_uncore_forcewake_reset(dev, false); 1559 dev_priv->pm.suspended = true; 1560 1561 /* 1562 * FIXME: We really should find a document that references the arguments 1563 * used below! 1564 */ 1565 if (IS_HASWELL(dev)) { 1566 /* 1567 * current versions of firmware which depend on this opregion 1568 * notification have repurposed the D1 definition to mean 1569 * "runtime suspended" vs. what you would normally expect (D3) 1570 * to distinguish it from notifications that might be sent via 1571 * the suspend path. 1572 */ 1573 intel_opregion_notify_adapter(dev, PCI_D1); 1574 } else { 1575 /* 1576 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1577 * being detected, and the call we do at intel_runtime_resume() 1578 * won't be able to restore them. Since PCI_D3hot matches the 1579 * actual specification and appears to be working, use it. Let's 1580 * assume the other non-Haswell platforms will stay the same as 1581 * Broadwell. 1582 */ 1583 intel_opregion_notify_adapter(dev, PCI_D3hot); 1584 } 1585 1586 assert_forcewakes_inactive(dev_priv); 1587 1588 DRM_DEBUG_KMS("Device suspended\n"); 1589 return 0; 1590 } 1591 1592 static int intel_runtime_resume(struct device *device) 1593 { 1594 struct pci_dev *pdev = to_pci_dev(device); 1595 struct drm_device *dev = pci_get_drvdata(pdev); 1596 struct drm_i915_private *dev_priv = dev->dev_private; 1597 int ret = 0; 1598 1599 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) 1600 return -ENODEV; 1601 1602 DRM_DEBUG_KMS("Resuming device\n"); 1603 1604 intel_opregion_notify_adapter(dev, PCI_D0); 1605 dev_priv->pm.suspended = false; 1606 1607 if (IS_GEN6(dev_priv)) 1608 intel_init_pch_refclk(dev); 1609 1610 if (IS_BROXTON(dev)) 1611 ret = bxt_resume_prepare(dev_priv); 1612 else if (IS_SKYLAKE(dev)) 1613 ret = skl_resume_prepare(dev_priv); 1614 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1615 hsw_disable_pc8(dev_priv); 1616 else if (IS_VALLEYVIEW(dev_priv)) 1617 ret = vlv_resume_prepare(dev_priv, true); 1618 1619 /* 1620 * No point of rolling back things in case of an error, as the best 1621 * we can do is to hope that things will still work (and disable RPM). 1622 */ 1623 i915_gem_init_swizzling(dev); 1624 gen6_update_ring_freq(dev); 1625 1626 intel_runtime_pm_enable_interrupts(dev_priv); 1627 intel_enable_gt_powersave(dev); 1628 1629 if (ret) 1630 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); 1631 else 1632 DRM_DEBUG_KMS("Device resumed\n"); 1633 1634 return ret; 1635 } 1636 #endif 1637 1638 /* 1639 * This function implements common functionality of runtime and system 1640 * suspend sequence. 1641 */ 1642 static int intel_suspend_complete(struct drm_i915_private *dev_priv) 1643 { 1644 int ret; 1645 1646 if (IS_BROXTON(dev_priv)) 1647 ret = bxt_suspend_complete(dev_priv); 1648 else if (IS_SKYLAKE(dev_priv)) 1649 ret = skl_suspend_complete(dev_priv); 1650 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1651 ret = hsw_suspend_complete(dev_priv); 1652 else if (IS_VALLEYVIEW(dev_priv)) 1653 ret = vlv_suspend_complete(dev_priv); 1654 else 1655 ret = 0; 1656 1657 return ret; 1658 } 1659 1660 #if 0 1661 static const struct dev_pm_ops i915_pm_ops = { 1662 /* 1663 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1664 * PMSG_RESUME] 1665 */ 1666 .suspend = i915_pm_suspend, 1667 .suspend_late = i915_pm_suspend_late, 1668 .resume_early = i915_pm_resume_early, 1669 .resume = i915_pm_resume, 1670 1671 /* 1672 * S4 event handlers 1673 * @freeze, @freeze_late : called (1) before creating the 1674 * hibernation image [PMSG_FREEZE] and 1675 * (2) after rebooting, before restoring 1676 * the image [PMSG_QUIESCE] 1677 * @thaw, @thaw_early : called (1) after creating the hibernation 1678 * image, before writing it [PMSG_THAW] 1679 * and (2) after failing to create or 1680 * restore the image [PMSG_RECOVER] 1681 * @poweroff, @poweroff_late: called after writing the hibernation 1682 * image, before rebooting [PMSG_HIBERNATE] 1683 * @restore, @restore_early : called after rebooting and restoring the 1684 * hibernation image [PMSG_RESTORE] 1685 */ 1686 .freeze = i915_pm_suspend, 1687 .freeze_late = i915_pm_suspend_late, 1688 .thaw_early = i915_pm_resume_early, 1689 .thaw = i915_pm_resume, 1690 .poweroff = i915_pm_suspend, 1691 .poweroff_late = i915_pm_poweroff_late, 1692 .restore_early = i915_pm_resume_early, 1693 .restore = i915_pm_resume, 1694 1695 /* S0ix (via runtime suspend) event handlers */ 1696 .runtime_suspend = intel_runtime_suspend, 1697 .runtime_resume = intel_runtime_resume, 1698 }; 1699 1700 static const struct vm_operations_struct i915_gem_vm_ops = { 1701 .fault = i915_gem_fault, 1702 .open = drm_gem_vm_open, 1703 .close = drm_gem_vm_close, 1704 }; 1705 1706 static const struct file_operations i915_driver_fops = { 1707 .owner = THIS_MODULE, 1708 .open = drm_open, 1709 .release = drm_release, 1710 .unlocked_ioctl = drm_ioctl, 1711 .mmap = drm_gem_mmap, 1712 .poll = drm_poll, 1713 .read = drm_read, 1714 #ifdef CONFIG_COMPAT 1715 .compat_ioctl = i915_compat_ioctl, 1716 #endif 1717 .llseek = noop_llseek, 1718 }; 1719 #endif 1720 1721 static struct cdev_pager_ops i915_gem_vm_ops = { 1722 .cdev_pg_fault = i915_gem_fault, 1723 .cdev_pg_ctor = i915_gem_pager_ctor, 1724 .cdev_pg_dtor = i915_gem_pager_dtor 1725 }; 1726 1727 static struct drm_driver driver = { 1728 /* Don't use MTRRs here; the Xserver or userspace app should 1729 * deal with them for Intel hardware. 1730 */ 1731 .driver_features = 1732 DRIVER_USE_AGP | 1733 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 1734 DRIVER_RENDER, 1735 .load = i915_driver_load, 1736 .unload = i915_driver_unload, 1737 .open = i915_driver_open, 1738 .lastclose = i915_driver_lastclose, 1739 .preclose = i915_driver_preclose, 1740 .postclose = i915_driver_postclose, 1741 1742 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ 1743 1744 .device_is_agp = i915_driver_device_is_agp, 1745 1746 #if defined(CONFIG_DEBUG_FS) 1747 .debugfs_init = i915_debugfs_init, 1748 .debugfs_cleanup = i915_debugfs_cleanup, 1749 #endif 1750 .gem_free_object = i915_gem_free_object, 1751 .gem_pager_ops = &i915_gem_vm_ops, 1752 1753 .dumb_create = i915_gem_dumb_create, 1754 .dumb_map_offset = i915_gem_mmap_gtt, 1755 .dumb_destroy = drm_gem_dumb_destroy, 1756 .ioctls = i915_ioctls, 1757 .name = DRIVER_NAME, 1758 .desc = DRIVER_DESC, 1759 .date = DRIVER_DATE, 1760 .major = DRIVER_MAJOR, 1761 .minor = DRIVER_MINOR, 1762 .patchlevel = DRIVER_PATCHLEVEL, 1763 }; 1764 1765 static int __init i915_init(void); 1766 1767 static int 1768 i915_attach(device_t kdev) 1769 { 1770 struct drm_device *dev = device_get_softc(kdev); 1771 int error; 1772 int dummy; 1773 1774 i915_init(); 1775 1776 dev->driver = &driver; 1777 error = drm_attach(kdev, i915_attach_list); 1778 1779 /* 1780 * XXX hack - give the kvm_console time to come up before X starts 1781 * messing with everything, avoiding at least one deadlock. 1782 */ 1783 tsleep(&dummy, 0, "i915_attach", hz*2); 1784 1785 return error; 1786 } 1787 1788 static device_method_t i915_methods[] = { 1789 /* Device interface */ 1790 DEVMETHOD(device_probe, i915_pci_probe), 1791 DEVMETHOD(device_attach, i915_attach), 1792 DEVMETHOD(device_suspend, i915_suspend_legacy), 1793 DEVMETHOD(device_resume, i915_resume_legacy), 1794 DEVMETHOD(device_detach, drm_release), 1795 DEVMETHOD_END 1796 }; 1797 1798 static driver_t i915_driver = { 1799 "drm", 1800 i915_methods, 1801 sizeof(struct drm_device) 1802 }; 1803 1804 static int __init i915_init(void) 1805 { 1806 driver.num_ioctls = i915_max_ioctl; 1807 1808 /* 1809 * If CONFIG_DRM_I915_KMS is set, default to KMS unless 1810 * explicitly disabled with the module pararmeter. 1811 * 1812 * Otherwise, just follow the parameter (defaulting to off). 1813 * 1814 * Allow optional vga_text_mode_force boot option to override 1815 * the default behavior. 1816 */ 1817 #if defined(CONFIG_DRM_I915_KMS) 1818 if (i915.modeset != 0) 1819 driver.driver_features |= DRIVER_MODESET; 1820 #endif 1821 if (i915.modeset == 1) 1822 driver.driver_features |= DRIVER_MODESET; 1823 1824 #ifdef CONFIG_VGA_CONSOLE 1825 if (vgacon_text_force() && i915.modeset == -1) 1826 driver.driver_features &= ~DRIVER_MODESET; 1827 #endif 1828 1829 if (!(driver.driver_features & DRIVER_MODESET)) { 1830 driver.get_vblank_timestamp = NULL; 1831 /* Silently fail loading to not upset userspace. */ 1832 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); 1833 return 0; 1834 } 1835 1836 /* 1837 * FIXME: Note that we're lying to the DRM core here so that we can get access 1838 * to the atomic ioctl and the atomic properties. Only plane operations on 1839 * a single CRTC will actually work. 1840 */ 1841 if (i915.nuclear_pageflip) 1842 driver.driver_features |= DRIVER_ATOMIC; 1843 1844 #if 0 1845 return drm_pci_init(&driver, &i915_pci_driver); 1846 #else 1847 return 1; 1848 #endif 1849 } 1850 1851 #if 0 1852 static void __exit i915_exit(void) 1853 { 1854 if (!(driver.driver_features & DRIVER_MODESET)) 1855 return; /* Never loaded a driver. */ 1856 1857 drm_pci_exit(&driver, &i915_pci_driver); 1858 } 1859 #endif 1860 1861 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY); 1862 MODULE_DEPEND(i915, drm, 1, 1, 1); 1863 MODULE_DEPEND(i915, iicbus, 1, 1, 1); 1864 MODULE_DEPEND(i915, iic, 1, 1, 1); 1865 MODULE_DEPEND(i915, iicbb, 1, 1, 1); 1866