1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 39 struct drm_i915_file_private; 40 41 typedef uint32_t gen6_pte_t; 42 typedef uint64_t gen8_pte_t; 43 typedef uint64_t gen8_pde_t; 44 typedef uint64_t gen8_ppgtt_pdpe_t; 45 typedef uint64_t gen8_ppgtt_pml4e_t; 46 47 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 48 49 #define I915_GTT_PAGE_SIZE_4K (1ULL << 12) 50 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE_4K 51 52 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 53 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 54 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 55 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 56 #define GEN6_PTE_CACHE_LLC (2 << 1) 57 #define GEN6_PTE_UNCACHED (1 << 1) 58 #define GEN6_PTE_VALID (1 << 0) 59 60 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 61 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 62 #define I915_PDES 512 63 #define I915_PDE_MASK (I915_PDES - 1) 64 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 65 66 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 67 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 68 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 69 #define GEN6_PDE_SHIFT 22 70 #define GEN6_PDE_VALID (1 << 0) 71 72 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 73 74 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 75 #define BYT_PTE_WRITEABLE (1 << 1) 76 77 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 78 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 79 */ 80 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 81 (((bits) & 0x8) << (11 - 3))) 82 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 83 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 84 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 85 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 86 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 87 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 88 #define HSW_PTE_UNCACHED (0) 89 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 90 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 91 92 /* GEN8 legacy style address is defined as a 3 level page table: 93 * 31:30 | 29:21 | 20:12 | 11:0 94 * PDPE | PDE | PTE | offset 95 * The difference as compared to normal x86 3 level page table is the PDPEs are 96 * programmed via register. 97 * 98 * GEN8 48b legacy style address is defined as a 4 level page table: 99 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 100 * PML4E | PDPE | PDE | PTE | offset 101 */ 102 #define GEN8_PML4ES_PER_PML4 512 103 #define GEN8_PML4E_SHIFT 39 104 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 105 #define GEN8_PDPE_SHIFT 30 106 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 107 * tables */ 108 #define GEN8_PDPE_MASK 0x1ff 109 #define GEN8_PDE_SHIFT 21 110 #define GEN8_PDE_MASK 0x1ff 111 #define GEN8_PTE_SHIFT 12 112 #define GEN8_PTE_MASK 0x1ff 113 #define GEN8_LEGACY_PDPES 4 114 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 115 116 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ 117 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 118 119 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 120 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 121 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 122 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 123 124 #define CHV_PPAT_SNOOP (1<<6) 125 #define GEN8_PPAT_AGE(x) (x<<4) 126 #define GEN8_PPAT_LLCeLLC (3<<2) 127 #define GEN8_PPAT_LLCELLC (2<<2) 128 #define GEN8_PPAT_LLC (1<<2) 129 #define GEN8_PPAT_WB (3<<0) 130 #define GEN8_PPAT_WT (2<<0) 131 #define GEN8_PPAT_WC (1<<0) 132 #define GEN8_PPAT_UC (0<<0) 133 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 134 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 135 136 enum i915_ggtt_view_type { 137 I915_GGTT_VIEW_NORMAL = 0, 138 I915_GGTT_VIEW_ROTATED, 139 I915_GGTT_VIEW_PARTIAL, 140 }; 141 142 struct intel_rotation_info { 143 unsigned int uv_offset; 144 uint32_t pixel_format; 145 unsigned int uv_start_page; 146 struct { 147 /* tiles */ 148 unsigned int width, height; 149 } plane[2]; 150 }; 151 152 struct i915_ggtt_view { 153 enum i915_ggtt_view_type type; 154 155 union { 156 struct { 157 u64 offset; 158 unsigned int size; 159 } partial; 160 struct intel_rotation_info rotated; 161 } params; 162 163 struct sg_table *pages; 164 }; 165 166 extern const struct i915_ggtt_view i915_ggtt_view_normal; 167 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 168 169 enum i915_cache_level; 170 171 /** 172 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 173 * VMA's presence cannot be guaranteed before binding, or after unbinding the 174 * object into/from the address space. 175 * 176 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 177 * will always be <= an objects lifetime. So object refcounting should cover us. 178 */ 179 struct i915_vma { 180 struct drm_mm_node node; 181 struct drm_i915_gem_object *obj; 182 struct i915_address_space *vm; 183 void __iomem *iomap; 184 185 /** Flags and address space this VMA is bound to */ 186 #define GLOBAL_BIND (1<<0) 187 #define LOCAL_BIND (1<<1) 188 unsigned int bound : 4; 189 bool is_ggtt : 1; 190 191 /** 192 * Support different GGTT views into the same object. 193 * This means there can be multiple VMA mappings per object and per VM. 194 * i915_ggtt_view_type is used to distinguish between those entries. 195 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 196 * assumed in GEM functions which take no ggtt view parameter. 197 */ 198 struct i915_ggtt_view ggtt_view; 199 200 /** This object's place on the active/inactive lists */ 201 struct list_head vm_link; 202 203 struct list_head obj_link; /* Link in the object's VMA list */ 204 205 /** This vma's place in the batchbuffer or on the eviction list */ 206 struct list_head exec_list; 207 208 /** 209 * Used for performing relocations during execbuffer insertion. 210 */ 211 struct hlist_node exec_node; 212 unsigned long exec_handle; 213 struct drm_i915_gem_exec_object2 *exec_entry; 214 215 /** 216 * How many users have pinned this object in GTT space. The following 217 * users can each hold at most one reference: pwrite/pread, execbuffer 218 * (objects are not allowed multiple times for the same batchbuffer), 219 * and the framebuffer code. When switching/pageflipping, the 220 * framebuffer code has at most two buffers pinned per crtc. 221 * 222 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 223 * bits with absolutely no headroom. So use 4 bits. */ 224 unsigned int pin_count:4; 225 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 226 }; 227 228 struct i915_page_dma { 229 struct page *page; 230 union { 231 dma_addr_t daddr; 232 233 /* For gen6/gen7 only. This is the offset in the GGTT 234 * where the page directory entries for PPGTT begin 235 */ 236 uint32_t ggtt_offset; 237 }; 238 }; 239 240 #define px_base(px) (&(px)->base) 241 #define px_page(px) (px_base(px)->page) 242 #define px_dma(px) (px_base(px)->daddr) 243 244 struct i915_page_scratch { 245 struct i915_page_dma base; 246 }; 247 248 struct i915_page_table { 249 struct i915_page_dma base; 250 251 unsigned long *used_ptes; 252 }; 253 254 struct i915_page_directory { 255 struct i915_page_dma base; 256 257 unsigned long *used_pdes; 258 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 259 }; 260 261 struct i915_page_directory_pointer { 262 struct i915_page_dma base; 263 264 unsigned long *used_pdpes; 265 struct i915_page_directory **page_directory; 266 }; 267 268 struct i915_pml4 { 269 struct i915_page_dma base; 270 271 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 272 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 273 }; 274 275 struct i915_address_space { 276 struct drm_mm mm; 277 struct drm_device *dev; 278 struct list_head global_link; 279 u64 start; /* Start offset always 0 for dri2 */ 280 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 281 282 bool is_ggtt; 283 284 struct i915_page_scratch *scratch_page; 285 struct i915_page_table *scratch_pt; 286 struct i915_page_directory *scratch_pd; 287 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 288 289 /** 290 * List of objects currently involved in rendering. 291 * 292 * Includes buffers having the contents of their GPU caches 293 * flushed, not necessarily primitives. last_read_req 294 * represents when the rendering involved will be completed. 295 * 296 * A reference is held on the buffer while on this list. 297 */ 298 struct list_head active_list; 299 300 /** 301 * LRU list of objects which are not in the ringbuffer and 302 * are ready to unbind, but are still in the GTT. 303 * 304 * last_read_req is NULL while an object is in this list. 305 * 306 * A reference is not held on the buffer while on this list, 307 * as merely being GTT-bound shouldn't prevent its being 308 * freed, and we'll pull it off the list in the free path. 309 */ 310 struct list_head inactive_list; 311 312 /* FIXME: Need a more generic return type */ 313 gen6_pte_t (*pte_encode)(dma_addr_t addr, 314 enum i915_cache_level level, 315 bool valid, u32 flags); /* Create a valid PTE */ 316 /* flags for pte_encode */ 317 #define PTE_READ_ONLY (1<<0) 318 int (*allocate_va_range)(struct i915_address_space *vm, 319 uint64_t start, 320 uint64_t length); 321 void (*clear_range)(struct i915_address_space *vm, 322 uint64_t start, 323 uint64_t length, 324 bool use_scratch); 325 void (*insert_page)(struct i915_address_space *vm, 326 dma_addr_t addr, 327 uint64_t offset, 328 enum i915_cache_level cache_level, 329 u32 flags); 330 void (*insert_entries)(struct i915_address_space *vm, 331 struct sg_table *st, 332 uint64_t start, 333 enum i915_cache_level cache_level, u32 flags); 334 void (*cleanup)(struct i915_address_space *vm); 335 /** Unmap an object from an address space. This usually consists of 336 * setting the valid PTE entries to a reserved scratch page. */ 337 void (*unbind_vma)(struct i915_vma *vma); 338 /* Map an object into an address space with the given cache flags. */ 339 int (*bind_vma)(struct i915_vma *vma, 340 enum i915_cache_level cache_level, 341 u32 flags); 342 }; 343 344 #define i915_is_ggtt(V) ((V)->is_ggtt) 345 346 /* The Graphics Translation Table is the way in which GEN hardware translates a 347 * Graphics Virtual Address into a Physical Address. In addition to the normal 348 * collateral associated with any va->pa translations GEN hardware also has a 349 * portion of the GTT which can be mapped by the CPU and remain both coherent 350 * and correct (in cases like swizzling). That region is referred to as GMADR in 351 * the spec. 352 */ 353 struct i915_ggtt { 354 struct i915_address_space base; 355 356 size_t stolen_size; /* Total size of stolen memory */ 357 size_t stolen_usable_size; /* Total size minus BIOS reserved */ 358 size_t stolen_reserved_base; 359 size_t stolen_reserved_size; 360 size_t size; /* Total size of Global GTT */ 361 u64 mappable_end; /* End offset that we can CPU map */ 362 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 363 phys_addr_t mappable_base; /* PA of our GMADR */ 364 365 /** "Graphics Stolen Memory" holds the global PTEs */ 366 void __iomem *gsm; 367 368 bool do_idle_maps; 369 370 int mtrr; 371 372 int (*probe)(struct i915_ggtt *ggtt); 373 }; 374 375 struct i915_hw_ppgtt { 376 struct i915_address_space base; 377 struct kref ref; 378 struct drm_mm_node node; 379 unsigned long pd_dirty_rings; 380 union { 381 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 382 struct i915_page_directory_pointer pdp; /* GEN8+ */ 383 struct i915_page_directory pd; /* GEN6-7 */ 384 }; 385 386 struct drm_i915_file_private *file_priv; 387 388 gen6_pte_t __iomem *pd_addr; 389 390 int (*enable)(struct i915_hw_ppgtt *ppgtt); 391 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 392 struct drm_i915_gem_request *req); 393 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 394 }; 395 396 /* 397 * gen6_for_each_pde() iterates over every pde from start until start+length. 398 * If start and start+length are not perfectly divisible, the macro will round 399 * down and up as needed. Start=0 and length=2G effectively iterates over 400 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 401 * so each of the other parameters should preferably be a simple variable, or 402 * at most an lvalue with no side-effects! 403 */ 404 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 405 for (iter = gen6_pde_index(start); \ 406 length > 0 && iter < I915_PDES && \ 407 (pt = (pd)->page_table[iter], true); \ 408 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 409 temp = min(temp - start, length); \ 410 start += temp, length -= temp; }), ++iter) 411 412 #define gen6_for_all_pdes(pt, pd, iter) \ 413 for (iter = 0; \ 414 iter < I915_PDES && \ 415 (pt = (pd)->page_table[iter], true); \ 416 ++iter) 417 418 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 419 { 420 const uint32_t mask = NUM_PTE(pde_shift) - 1; 421 422 return (address >> PAGE_SHIFT) & mask; 423 } 424 425 /* Helper to counts the number of PTEs within the given length. This count 426 * does not cross a page table boundary, so the max value would be 427 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 428 */ 429 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 430 uint32_t pde_shift) 431 { 432 const uint64_t mask = ~((1ULL << pde_shift) - 1); 433 uint64_t end; 434 435 WARN_ON(length == 0); 436 WARN_ON(offset_in_page(addr|length)); 437 438 end = addr + length; 439 440 if ((addr & mask) != (end & mask)) 441 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 442 443 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 444 } 445 446 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 447 { 448 return (addr >> shift) & I915_PDE_MASK; 449 } 450 451 static inline uint32_t gen6_pte_index(uint32_t addr) 452 { 453 return i915_pte_index(addr, GEN6_PDE_SHIFT); 454 } 455 456 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 457 { 458 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 459 } 460 461 static inline uint32_t gen6_pde_index(uint32_t addr) 462 { 463 return i915_pde_index(addr, GEN6_PDE_SHIFT); 464 } 465 466 /* Equivalent to the gen6 version, For each pde iterates over every pde 467 * between from start until start + length. On gen8+ it simply iterates 468 * over every page directory entry in a page directory. 469 */ 470 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 471 for (iter = gen8_pde_index(start); \ 472 length > 0 && iter < I915_PDES && \ 473 (pt = (pd)->page_table[iter], true); \ 474 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 475 temp = min(temp - start, length); \ 476 start += temp, length -= temp; }), ++iter) 477 478 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 479 for (iter = gen8_pdpe_index(start); \ 480 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ 481 (pd = (pdp)->page_directory[iter], true); \ 482 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 483 temp = min(temp - start, length); \ 484 start += temp, length -= temp; }), ++iter) 485 486 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 487 for (iter = gen8_pml4e_index(start); \ 488 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 489 (pdp = (pml4)->pdps[iter], true); \ 490 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 491 temp = min(temp - start, length); \ 492 start += temp, length -= temp; }), ++iter) 493 494 static inline uint32_t gen8_pte_index(uint64_t address) 495 { 496 return i915_pte_index(address, GEN8_PDE_SHIFT); 497 } 498 499 static inline uint32_t gen8_pde_index(uint64_t address) 500 { 501 return i915_pde_index(address, GEN8_PDE_SHIFT); 502 } 503 504 static inline uint32_t gen8_pdpe_index(uint64_t address) 505 { 506 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 507 } 508 509 static inline uint32_t gen8_pml4e_index(uint64_t address) 510 { 511 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 512 } 513 514 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 515 { 516 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 517 } 518 519 static inline dma_addr_t 520 i915_page_dir_dma_addr(struct i915_hw_ppgtt *ppgtt, const unsigned n) 521 { 522 return test_bit(n, ppgtt->pdp.used_pdpes) ? 523 px_dma(ppgtt->pdp.page_directory[n]) : 524 px_dma(ppgtt->base.scratch_pd); 525 } 526 527 int i915_ggtt_init_hw(struct drm_device *dev); 528 int i915_ggtt_enable_hw(struct drm_device *dev); 529 void i915_gem_init_ggtt(struct drm_device *dev); 530 void i915_ggtt_cleanup_hw(struct drm_device *dev); 531 532 int i915_ppgtt_init_hw(struct drm_device *dev); 533 void i915_ppgtt_release(struct kref *kref); 534 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, 535 struct drm_i915_file_private *fpriv); 536 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 537 { 538 if (ppgtt) 539 kref_get(&ppgtt->ref); 540 } 541 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 542 { 543 if (ppgtt) 544 kref_put(&ppgtt->ref, i915_ppgtt_release); 545 } 546 547 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 548 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 549 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 550 551 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 552 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 553 554 static inline bool 555 i915_ggtt_view_equal(const struct i915_ggtt_view *a, 556 const struct i915_ggtt_view *b) 557 { 558 if (WARN_ON(!a || !b)) 559 return false; 560 561 if (a->type != b->type) 562 return false; 563 if (a->type != I915_GGTT_VIEW_NORMAL) 564 return !memcmp(&a->params, &b->params, sizeof(a->params)); 565 return true; 566 } 567 568 size_t 569 i915_ggtt_view_size(struct drm_i915_gem_object *obj, 570 const struct i915_ggtt_view *view); 571 572 /** 573 * i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture 574 * @vma: VMA to iomap 575 * 576 * The passed in VMA has to be pinned in the global GTT mappable region. 577 * An extra pinning of the VMA is acquired for the return iomapping, 578 * the caller must call i915_vma_unpin_iomap to relinquish the pinning 579 * after the iomapping is no longer required. 580 * 581 * Callers must hold the struct_mutex. 582 * 583 * Returns a valid iomapped pointer or ERR_PTR. 584 */ 585 void __iomem *i915_vma_pin_iomap(struct i915_vma *vma); 586 #define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x)) 587 588 /** 589 * i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap 590 * @vma: VMA to unpin 591 * 592 * Unpins the previously iomapped VMA from i915_vma_pin_iomap(). 593 * 594 * Callers must hold the struct_mutex. This function is only valid to be 595 * called on a VMA previously iomapped by the caller with i915_vma_pin_iomap(). 596 */ 597 static inline void i915_vma_unpin_iomap(struct i915_vma *vma) 598 { 599 lockdep_assert_held(&vma->vm->dev->struct_mutex); 600 GEM_BUG_ON(vma->pin_count == 0); 601 GEM_BUG_ON(vma->iomap == NULL); 602 vma->pin_count--; 603 } 604 605 #endif 606