1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include "i915_drv.h" 26 27 static const char *i915_fence_get_driver_name(struct fence *fence) 28 { 29 return "i915"; 30 } 31 32 static const char *i915_fence_get_timeline_name(struct fence *fence) 33 { 34 /* Timelines are bound by eviction to a VM. However, since 35 * we only have a global seqno at the moment, we only have 36 * a single timeline. Note that each timeline will have 37 * multiple execution contexts (fence contexts) as we allow 38 * engines within a single timeline to execute in parallel. 39 */ 40 return "global"; 41 } 42 43 static bool i915_fence_signaled(struct fence *fence) 44 { 45 return i915_gem_request_completed(to_request(fence)); 46 } 47 48 static bool i915_fence_enable_signaling(struct fence *fence) 49 { 50 if (i915_fence_signaled(fence)) 51 return false; 52 53 intel_engine_enable_signaling(to_request(fence)); 54 return true; 55 } 56 57 static signed long i915_fence_wait(struct fence *fence, 58 bool interruptible, 59 signed long timeout_jiffies) 60 { 61 s64 timeout_ns, *timeout; 62 int ret; 63 64 if (timeout_jiffies != MAX_SCHEDULE_TIMEOUT) { 65 timeout_ns = jiffies_to_nsecs(timeout_jiffies); 66 timeout = &timeout_ns; 67 } else { 68 timeout = NULL; 69 } 70 71 ret = __i915_wait_request(to_request(fence), 72 interruptible, timeout, 73 NO_WAITBOOST); 74 if (ret == -ETIME) 75 return 0; 76 77 if (ret < 0) 78 return ret; 79 80 if (timeout_jiffies != MAX_SCHEDULE_TIMEOUT) 81 timeout_jiffies = nsecs_to_jiffies(timeout_ns); 82 83 return timeout_jiffies; 84 } 85 86 static void i915_fence_value_str(struct fence *fence, char *str, int size) 87 { 88 snprintf(str, size, "%u", fence->seqno); 89 } 90 91 static void i915_fence_timeline_value_str(struct fence *fence, char *str, 92 int size) 93 { 94 snprintf(str, size, "%u", 95 intel_engine_get_seqno(to_request(fence)->engine)); 96 } 97 98 static void i915_fence_release(struct fence *fence) 99 { 100 struct drm_i915_gem_request *req = to_request(fence); 101 102 kmem_cache_free(req->i915->requests, req); 103 } 104 105 const struct fence_ops i915_fence_ops = { 106 .get_driver_name = i915_fence_get_driver_name, 107 .get_timeline_name = i915_fence_get_timeline_name, 108 .enable_signaling = i915_fence_enable_signaling, 109 .signaled = i915_fence_signaled, 110 .wait = i915_fence_wait, 111 .release = i915_fence_release, 112 .fence_value_str = i915_fence_value_str, 113 .timeline_value_str = i915_fence_timeline_value_str, 114 }; 115 116 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, 117 struct drm_file *file) 118 { 119 struct drm_i915_private *dev_private; 120 struct drm_i915_file_private *file_priv; 121 122 WARN_ON(!req || !file || req->file_priv); 123 124 if (!req || !file) 125 return -EINVAL; 126 127 if (req->file_priv) 128 return -EINVAL; 129 130 dev_private = req->i915; 131 file_priv = file->driver_priv; 132 133 lockmgr(&file_priv->mm.lock, LK_EXCLUSIVE); 134 req->file_priv = file_priv; 135 list_add_tail(&req->client_list, &file_priv->mm.request_list); 136 lockmgr(&file_priv->mm.lock, LK_RELEASE); 137 138 req->pid = curproc->p_pid; 139 140 return 0; 141 } 142 143 static inline void 144 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) 145 { 146 struct drm_i915_file_private *file_priv = request->file_priv; 147 148 if (!file_priv) 149 return; 150 151 lockmgr(&file_priv->mm.lock, LK_EXCLUSIVE); 152 list_del(&request->client_list); 153 request->file_priv = NULL; 154 lockmgr(&file_priv->mm.lock, LK_RELEASE); 155 156 #if 0 157 put_pid(request->pid); 158 request->pid = NULL; 159 #else 160 request->pid = 0; 161 #endif 162 } 163 164 static void i915_gem_request_retire(struct drm_i915_gem_request *request) 165 { 166 trace_i915_gem_request_retire(request); 167 list_del_init(&request->list); 168 169 /* We know the GPU must have read the request to have 170 * sent us the seqno + interrupt, so use the position 171 * of tail of the request to update the last known position 172 * of the GPU head. 173 * 174 * Note this requires that we are always called in request 175 * completion order. 176 */ 177 request->ringbuf->last_retired_head = request->postfix; 178 179 i915_gem_request_remove_from_client(request); 180 181 if (request->previous_context) { 182 if (i915.enable_execlists) 183 intel_lr_context_unpin(request->previous_context, 184 request->engine); 185 } 186 187 i915_gem_context_put(request->ctx); 188 i915_gem_request_put(request); 189 } 190 191 void i915_gem_request_retire_upto(struct drm_i915_gem_request *req) 192 { 193 struct intel_engine_cs *engine = req->engine; 194 struct drm_i915_gem_request *tmp; 195 196 lockdep_assert_held(&req->i915->drm.struct_mutex); 197 198 if (list_empty(&req->list)) 199 return; 200 201 do { 202 tmp = list_first_entry(&engine->request_list, 203 typeof(*tmp), list); 204 205 i915_gem_request_retire(tmp); 206 } while (tmp != req); 207 208 WARN_ON(i915_verify_lists(engine->dev)); 209 } 210 211 static int i915_gem_check_wedge(unsigned int reset_counter, bool interruptible) 212 { 213 if (__i915_terminally_wedged(reset_counter)) 214 return -EIO; 215 216 if (__i915_reset_in_progress(reset_counter)) { 217 /* Non-interruptible callers can't handle -EAGAIN, hence return 218 * -EIO unconditionally for these. 219 */ 220 if (!interruptible) 221 return -EIO; 222 223 return -EAGAIN; 224 } 225 226 return 0; 227 } 228 229 static int i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno) 230 { 231 struct intel_engine_cs *engine; 232 int ret; 233 234 /* Carefully retire all requests without writing to the rings */ 235 for_each_engine(engine, dev_priv) { 236 ret = intel_engine_idle(engine); 237 if (ret) 238 return ret; 239 } 240 i915_gem_retire_requests(dev_priv); 241 242 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */ 243 if (!i915_seqno_passed(seqno, dev_priv->next_seqno)) { 244 while (intel_kick_waiters(dev_priv) || 245 intel_kick_signalers(dev_priv)) 246 yield(); 247 } 248 249 /* Finally reset hw state */ 250 for_each_engine(engine, dev_priv) 251 intel_ring_init_seqno(engine, seqno); 252 253 return 0; 254 } 255 256 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) 257 { 258 struct drm_i915_private *dev_priv = to_i915(dev); 259 int ret; 260 261 if (seqno == 0) 262 return -EINVAL; 263 264 /* HWS page needs to be set less than what we 265 * will inject to ring 266 */ 267 ret = i915_gem_init_seqno(dev_priv, seqno - 1); 268 if (ret) 269 return ret; 270 271 /* Carefully set the last_seqno value so that wrap 272 * detection still works 273 */ 274 dev_priv->next_seqno = seqno; 275 dev_priv->last_seqno = seqno - 1; 276 if (dev_priv->last_seqno == 0) 277 dev_priv->last_seqno--; 278 279 return 0; 280 } 281 282 static int i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno) 283 { 284 /* reserve 0 for non-seqno */ 285 if (unlikely(dev_priv->next_seqno == 0)) { 286 int ret; 287 288 ret = i915_gem_init_seqno(dev_priv, 0); 289 if (ret) 290 return ret; 291 292 dev_priv->next_seqno = 1; 293 } 294 295 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; 296 return 0; 297 } 298 299 static inline int 300 __i915_gem_request_alloc(struct intel_engine_cs *engine, 301 struct i915_gem_context *ctx, 302 struct drm_i915_gem_request **req_out) 303 { 304 struct drm_i915_private *dev_priv = engine->i915; 305 unsigned int reset_counter = i915_reset_counter(&dev_priv->gpu_error); 306 struct drm_i915_gem_request *req; 307 u32 seqno; 308 int ret; 309 310 if (!req_out) 311 return -EINVAL; 312 313 *req_out = NULL; 314 315 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report 316 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex 317 * and restart. 318 */ 319 ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible); 320 if (ret) 321 return ret; 322 323 /* Move the oldest request to the slab-cache (if not in use!) */ 324 if (!list_empty(&engine->request_list)) { 325 req = list_first_entry(&engine->request_list, 326 typeof(*req), list); 327 if (i915_gem_request_completed(req)) 328 i915_gem_request_retire(req); 329 } 330 331 req = kzalloc(sizeof(*req), GFP_KERNEL); 332 if (!req) 333 return -ENOMEM; 334 335 ret = i915_gem_get_seqno(dev_priv, &seqno); 336 if (ret) 337 goto err; 338 339 lockinit(&req->lock, "i915_rl", 0, LK_CANRECURSE); 340 fence_init(&req->fence, 341 &i915_fence_ops, 342 &req->lock, 343 engine->fence_context, 344 seqno); 345 346 req->i915 = dev_priv; 347 req->engine = engine; 348 req->ctx = i915_gem_context_get(ctx); 349 350 /* 351 * Reserve space in the ring buffer for all the commands required to 352 * eventually emit this request. This is to guarantee that the 353 * i915_add_request() call can't fail. Note that the reserve may need 354 * to be redone if the request is not actually submitted straight 355 * away, e.g. because a GPU scheduler has deferred it. 356 */ 357 req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; 358 359 if (i915.enable_execlists) 360 ret = intel_logical_ring_alloc_request_extras(req); 361 else 362 ret = intel_ring_alloc_request_extras(req); 363 if (ret) 364 goto err_ctx; 365 366 *req_out = req; 367 return 0; 368 369 err_ctx: 370 i915_gem_context_put(ctx); 371 err: 372 kmem_cache_free(dev_priv->requests, req); 373 return ret; 374 } 375 376 /** 377 * i915_gem_request_alloc - allocate a request structure 378 * 379 * @engine: engine that we wish to issue the request on. 380 * @ctx: context that the request will be associated with. 381 * This can be NULL if the request is not directly related to 382 * any specific user context, in which case this function will 383 * choose an appropriate context to use. 384 * 385 * Returns a pointer to the allocated request if successful, 386 * or an error code if not. 387 */ 388 struct drm_i915_gem_request * 389 i915_gem_request_alloc(struct intel_engine_cs *engine, 390 struct i915_gem_context *ctx) 391 { 392 struct drm_i915_gem_request *req; 393 int err; 394 395 if (!ctx) 396 ctx = engine->i915->kernel_context; 397 err = __i915_gem_request_alloc(engine, ctx, &req); 398 return err ? ERR_PTR(err) : req; 399 } 400 401 static void i915_gem_mark_busy(const struct intel_engine_cs *engine) 402 { 403 struct drm_i915_private *dev_priv = engine->i915; 404 405 dev_priv->gt.active_engines |= intel_engine_flag(engine); 406 if (dev_priv->gt.awake) 407 return; 408 409 intel_runtime_pm_get_noresume(dev_priv); 410 dev_priv->gt.awake = true; 411 412 intel_enable_gt_powersave(dev_priv); 413 i915_update_gfx_val(dev_priv); 414 if (INTEL_GEN(dev_priv) >= 6) 415 gen6_rps_busy(dev_priv); 416 417 queue_delayed_work(dev_priv->wq, 418 &dev_priv->gt.retire_work, 419 round_jiffies_up_relative(HZ)); 420 } 421 422 /* 423 * NB: This function is not allowed to fail. Doing so would mean the the 424 * request is not being tracked for completion but the work itself is 425 * going to happen on the hardware. This would be a Bad Thing(tm). 426 */ 427 void __i915_add_request(struct drm_i915_gem_request *request, 428 struct drm_i915_gem_object *obj, 429 bool flush_caches) 430 { 431 struct intel_engine_cs *engine; 432 struct intel_ringbuffer *ringbuf; 433 u32 request_start; 434 u32 reserved_tail; 435 int ret; 436 437 if (WARN_ON(!request)) 438 return; 439 440 engine = request->engine; 441 ringbuf = request->ringbuf; 442 443 /* 444 * To ensure that this call will not fail, space for its emissions 445 * should already have been reserved in the ring buffer. Let the ring 446 * know that it is time to use that space up. 447 */ 448 request_start = intel_ring_get_tail(ringbuf); 449 reserved_tail = request->reserved_space; 450 request->reserved_space = 0; 451 452 /* 453 * Emit any outstanding flushes - execbuf can fail to emit the flush 454 * after having emitted the batchbuffer command. Hence we need to fix 455 * things up similar to emitting the lazy request. The difference here 456 * is that the flush _must_ happen before the next request, no matter 457 * what. 458 */ 459 if (flush_caches) { 460 if (i915.enable_execlists) 461 ret = logical_ring_flush_all_caches(request); 462 else 463 ret = intel_ring_flush_all_caches(request); 464 /* Not allowed to fail! */ 465 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); 466 } 467 468 trace_i915_gem_request_add(request); 469 470 request->head = request_start; 471 472 /* Whilst this request exists, batch_obj will be on the 473 * active_list, and so will hold the active reference. Only when this 474 * request is retired will the the batch_obj be moved onto the 475 * inactive_list and lose its active reference. Hence we do not need 476 * to explicitly hold another reference here. 477 */ 478 request->batch_obj = obj; 479 480 /* Seal the request and mark it as pending execution. Note that 481 * we may inspect this state, without holding any locks, during 482 * hangcheck. Hence we apply the barrier to ensure that we do not 483 * see a more recent value in the hws than we are tracking. 484 */ 485 request->emitted_jiffies = jiffies; 486 request->previous_seqno = engine->last_submitted_seqno; 487 smp_store_mb(engine->last_submitted_seqno, request->fence.seqno); 488 list_add_tail(&request->list, &engine->request_list); 489 490 /* Record the position of the start of the request so that 491 * should we detect the updated seqno part-way through the 492 * GPU processing the request, we never over-estimate the 493 * position of the head. 494 */ 495 request->postfix = intel_ring_get_tail(ringbuf); 496 497 if (i915.enable_execlists) { 498 ret = engine->emit_request(request); 499 } else { 500 ret = engine->add_request(request); 501 502 request->tail = intel_ring_get_tail(ringbuf); 503 } 504 /* Not allowed to fail! */ 505 WARN(ret, "emit|add_request failed: %d!\n", ret); 506 /* Sanity check that the reserved size was large enough. */ 507 ret = intel_ring_get_tail(ringbuf) - request_start; 508 if (ret < 0) 509 ret += ringbuf->size; 510 WARN_ONCE(ret > reserved_tail, 511 "Not enough space reserved (%d bytes) " 512 "for adding the request (%d bytes)\n", 513 reserved_tail, ret); 514 515 i915_gem_mark_busy(engine); 516 } 517 518 static unsigned long local_clock_us(unsigned int *cpu) 519 { 520 unsigned long t; 521 522 /* Cheaply and approximately convert from nanoseconds to microseconds. 523 * The result and subsequent calculations are also defined in the same 524 * approximate microseconds units. The principal source of timing 525 * error here is from the simple truncation. 526 * 527 * Note that local_clock() is only defined wrt to the current CPU; 528 * the comparisons are no longer valid if we switch CPUs. Instead of 529 * blocking preemption for the entire busywait, we can detect the CPU 530 * switch and use that as indicator of system load and a reason to 531 * stop busywaiting, see busywait_stop(). 532 */ 533 *cpu = get_cpu(); 534 t = local_clock() >> 10; 535 put_cpu(); 536 537 return t; 538 } 539 540 static bool busywait_stop(unsigned long timeout, unsigned int cpu) 541 { 542 unsigned int this_cpu; 543 544 if (time_after(local_clock_us(&this_cpu), timeout)) 545 return true; 546 547 return this_cpu != cpu; 548 } 549 550 bool __i915_spin_request(const struct drm_i915_gem_request *req, 551 int state, unsigned long timeout_us) 552 { 553 unsigned int cpu; 554 555 /* When waiting for high frequency requests, e.g. during synchronous 556 * rendering split between the CPU and GPU, the finite amount of time 557 * required to set up the irq and wait upon it limits the response 558 * rate. By busywaiting on the request completion for a short while we 559 * can service the high frequency waits as quick as possible. However, 560 * if it is a slow request, we want to sleep as quickly as possible. 561 * The tradeoff between waiting and sleeping is roughly the time it 562 * takes to sleep on a request, on the order of a microsecond. 563 */ 564 565 timeout_us += local_clock_us(&cpu); 566 do { 567 if (i915_gem_request_completed(req)) 568 return true; 569 570 if (signal_pending_state(state, current)) 571 break; 572 573 if (busywait_stop(timeout_us, cpu)) 574 break; 575 576 cpu_relax(); 577 } while (!need_resched()); 578 579 return false; 580 } 581 582 /** 583 * __i915_wait_request - wait until execution of request has finished 584 * @req: duh! 585 * @interruptible: do an interruptible wait (normally yes) 586 * @timeout: in - how long to wait (NULL forever); out - how much time remaining 587 * @rps: client to charge for RPS boosting 588 * 589 * Note: It is of utmost importance that the passed in seqno and reset_counter 590 * values have been read by the caller in an smp safe manner. Where read-side 591 * locks are involved, it is sufficient to read the reset_counter before 592 * unlocking the lock that protects the seqno. For lockless tricks, the 593 * reset_counter _must_ be read before, and an appropriate smp_rmb must be 594 * inserted. 595 * 596 * Returns 0 if the request was found within the alloted time. Else returns the 597 * errno with remaining time filled in timeout argument. 598 */ 599 int __i915_wait_request(struct drm_i915_gem_request *req, 600 bool interruptible, 601 s64 *timeout, 602 struct intel_rps_client *rps) 603 { 604 int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; 605 DEFINE_WAIT(reset); 606 struct intel_wait wait; 607 unsigned long timeout_remain; 608 int ret = 0; 609 610 might_sleep(); 611 612 if (list_empty(&req->list)) 613 return 0; 614 615 if (i915_gem_request_completed(req)) 616 return 0; 617 618 timeout_remain = MAX_SCHEDULE_TIMEOUT; 619 if (timeout) { 620 if (WARN_ON(*timeout < 0)) 621 return -EINVAL; 622 623 if (*timeout == 0) 624 return -ETIME; 625 626 /* Record current time in case interrupted, or wedged */ 627 timeout_remain = nsecs_to_jiffies_timeout(*timeout); 628 *timeout += ktime_get_raw_ns(); 629 } 630 631 trace_i915_gem_request_wait_begin(req); 632 633 /* This client is about to stall waiting for the GPU. In many cases 634 * this is undesirable and limits the throughput of the system, as 635 * many clients cannot continue processing user input/output whilst 636 * blocked. RPS autotuning may take tens of milliseconds to respond 637 * to the GPU load and thus incurs additional latency for the client. 638 * We can circumvent that by promoting the GPU frequency to maximum 639 * before we wait. This makes the GPU throttle up much more quickly 640 * (good for benchmarks and user experience, e.g. window animations), 641 * but at a cost of spending more power processing the workload 642 * (bad for battery). Not all clients even want their results 643 * immediately and for them we should just let the GPU select its own 644 * frequency to maximise efficiency. To prevent a single client from 645 * forcing the clocks too high for the whole system, we only allow 646 * each client to waitboost once in a busy period. 647 */ 648 if (IS_RPS_CLIENT(rps) && INTEL_GEN(req->i915) >= 6) 649 gen6_rps_boost(req->i915, rps, req->emitted_jiffies); 650 651 /* Optimistic spin for the next ~jiffie before touching IRQs */ 652 if (i915_spin_request(req, state, 5)) 653 goto complete; 654 655 set_current_state(state); 656 add_wait_queue(&req->i915->gpu_error.wait_queue, &reset); 657 658 intel_wait_init(&wait, req->fence.seqno); 659 if (intel_engine_add_wait(req->engine, &wait)) 660 /* In order to check that we haven't missed the interrupt 661 * as we enabled it, we need to kick ourselves to do a 662 * coherent check on the seqno before we sleep. 663 */ 664 goto wakeup; 665 666 for (;;) { 667 if (signal_pending_state(state, current)) { 668 ret = -ERESTARTSYS; 669 break; 670 } 671 672 timeout_remain = io_schedule_timeout(timeout_remain); 673 if (timeout_remain == 0) { 674 ret = -ETIME; 675 break; 676 } 677 678 if (intel_wait_complete(&wait)) 679 break; 680 681 set_current_state(state); 682 683 wakeup: 684 /* Carefully check if the request is complete, giving time 685 * for the seqno to be visible following the interrupt. 686 * We also have to check in case we are kicked by the GPU 687 * reset in order to drop the struct_mutex. 688 */ 689 if (__i915_request_irq_complete(req)) 690 break; 691 692 /* Only spin if we know the GPU is processing this request */ 693 if (i915_spin_request(req, state, 2)) 694 break; 695 } 696 remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset); 697 698 intel_engine_remove_wait(req->engine, &wait); 699 __set_current_state(TASK_RUNNING); 700 complete: 701 trace_i915_gem_request_wait_end(req); 702 703 if (timeout) { 704 *timeout -= ktime_get_raw_ns(); 705 if (*timeout < 0) 706 *timeout = 0; 707 708 /* 709 * Apparently ktime isn't accurate enough and occasionally has a 710 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch 711 * things up to make the test happy. We allow up to 1 jiffy. 712 * 713 * This is a regrssion from the timespec->ktime conversion. 714 */ 715 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) 716 *timeout = 0; 717 } 718 719 if (IS_RPS_USER(rps) && 720 req->fence.seqno == req->engine->last_submitted_seqno) { 721 /* The GPU is now idle and this client has stalled. 722 * Since no other client has submitted a request in the 723 * meantime, assume that this client is the only one 724 * supplying work to the GPU but is unable to keep that 725 * work supplied because it is waiting. Since the GPU is 726 * then never kept fully busy, RPS autoclocking will 727 * keep the clocks relatively low, causing further delays. 728 * Compensate by giving the synchronous client credit for 729 * a waitboost next time. 730 */ 731 lockmgr(&req->i915->rps.client_lock, LK_EXCLUSIVE); 732 list_del_init(&rps->link); 733 lockmgr(&req->i915->rps.client_lock, LK_RELEASE); 734 } 735 736 return ret; 737 } 738 739 /** 740 * Waits for a request to be signaled, and cleans up the 741 * request and object lists appropriately for that event. 742 */ 743 int i915_wait_request(struct drm_i915_gem_request *req) 744 { 745 int ret; 746 747 GEM_BUG_ON(!req); 748 lockdep_assert_held(&req->i915->drm.struct_mutex); 749 750 ret = __i915_wait_request(req, req->i915->mm.interruptible, NULL, NULL); 751 if (ret) 752 return ret; 753 754 /* If the GPU hung, we want to keep the requests to find the guilty. */ 755 if (!i915_reset_in_progress(&req->i915->gpu_error)) 756 i915_gem_request_retire_upto(req); 757 758 return 0; 759 } 760