1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include "i915_drv.h" 30 #include "i915_selftest.h" 31 32 #define GEN_DEFAULT_PIPEOFFSETS \ 33 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 34 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 35 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 36 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 37 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 38 39 #define GEN_CHV_PIPEOFFSETS \ 40 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 41 CHV_PIPE_C_OFFSET }, \ 42 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 43 CHV_TRANSCODER_C_OFFSET, }, \ 44 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 45 CHV_PALETTE_C_OFFSET } 46 47 #define CURSOR_OFFSETS \ 48 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 49 50 #define IVB_CURSOR_OFFSETS \ 51 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 52 53 #define BDW_COLORS \ 54 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 55 #define CHV_COLORS \ 56 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } 57 58 /* Keep in gen based order, and chronological order within a gen */ 59 #define GEN2_FEATURES \ 60 .gen = 2, .num_pipes = 1, \ 61 .has_overlay = 1, .overlay_needs_physical = 1, \ 62 .has_gmch_display = 1, \ 63 .hws_needs_physical = 1, \ 64 .unfenced_needs_alignment = 1, \ 65 .ring_mask = RENDER_RING, \ 66 GEN_DEFAULT_PIPEOFFSETS, \ 67 CURSOR_OFFSETS 68 69 static const struct intel_device_info intel_i830_info = { 70 GEN2_FEATURES, 71 .platform = INTEL_I830, 72 .is_mobile = 1, .cursor_needs_physical = 1, 73 .num_pipes = 2, /* legal, last one wins */ 74 }; 75 76 static const struct intel_device_info intel_i845g_info = { 77 GEN2_FEATURES, 78 .platform = INTEL_I845G, 79 }; 80 81 static const struct intel_device_info intel_i85x_info = { 82 GEN2_FEATURES, 83 .platform = INTEL_I85X, .is_mobile = 1, 84 .num_pipes = 2, /* legal, last one wins */ 85 .cursor_needs_physical = 1, 86 .has_fbc = 1, 87 }; 88 89 static const struct intel_device_info intel_i865g_info = { 90 GEN2_FEATURES, 91 .platform = INTEL_I865G, 92 }; 93 94 #define GEN3_FEATURES \ 95 .gen = 3, .num_pipes = 2, \ 96 .has_gmch_display = 1, \ 97 .ring_mask = RENDER_RING, \ 98 GEN_DEFAULT_PIPEOFFSETS, \ 99 CURSOR_OFFSETS 100 101 static const struct intel_device_info intel_i915g_info = { 102 GEN3_FEATURES, 103 .platform = INTEL_I915G, .cursor_needs_physical = 1, 104 .has_overlay = 1, .overlay_needs_physical = 1, 105 .hws_needs_physical = 1, 106 .unfenced_needs_alignment = 1, 107 }; 108 109 static const struct intel_device_info intel_i915gm_info = { 110 GEN3_FEATURES, 111 .platform = INTEL_I915GM, 112 .is_mobile = 1, 113 .cursor_needs_physical = 1, 114 .has_overlay = 1, .overlay_needs_physical = 1, 115 .supports_tv = 1, 116 .has_fbc = 1, 117 .hws_needs_physical = 1, 118 .unfenced_needs_alignment = 1, 119 }; 120 121 static const struct intel_device_info intel_i945g_info = { 122 GEN3_FEATURES, 123 .platform = INTEL_I945G, 124 .has_hotplug = 1, .cursor_needs_physical = 1, 125 .has_overlay = 1, .overlay_needs_physical = 1, 126 .hws_needs_physical = 1, 127 .unfenced_needs_alignment = 1, 128 }; 129 130 static const struct intel_device_info intel_i945gm_info = { 131 GEN3_FEATURES, 132 .platform = INTEL_I945GM, .is_mobile = 1, 133 .has_hotplug = 1, .cursor_needs_physical = 1, 134 .has_overlay = 1, .overlay_needs_physical = 1, 135 .supports_tv = 1, 136 .has_fbc = 1, 137 .hws_needs_physical = 1, 138 .unfenced_needs_alignment = 1, 139 }; 140 141 static const struct intel_device_info intel_g33_info = { 142 GEN3_FEATURES, 143 .platform = INTEL_G33, 144 .has_hotplug = 1, 145 .has_overlay = 1, 146 }; 147 148 static const struct intel_device_info intel_pineview_info = { 149 GEN3_FEATURES, 150 .platform = INTEL_PINEVIEW, .is_mobile = 1, 151 .has_hotplug = 1, 152 .has_overlay = 1, 153 }; 154 155 #define GEN4_FEATURES \ 156 .gen = 4, .num_pipes = 2, \ 157 .has_hotplug = 1, \ 158 .has_gmch_display = 1, \ 159 .ring_mask = RENDER_RING, \ 160 GEN_DEFAULT_PIPEOFFSETS, \ 161 CURSOR_OFFSETS 162 163 static const struct intel_device_info intel_i965g_info = { 164 GEN4_FEATURES, 165 .platform = INTEL_I965G, 166 .has_overlay = 1, 167 .hws_needs_physical = 1, 168 }; 169 170 static const struct intel_device_info intel_i965gm_info = { 171 GEN4_FEATURES, 172 .platform = INTEL_I965GM, 173 .is_mobile = 1, .has_fbc = 1, 174 .has_overlay = 1, 175 .supports_tv = 1, 176 .hws_needs_physical = 1, 177 }; 178 179 static const struct intel_device_info intel_g45_info = { 180 GEN4_FEATURES, 181 .platform = INTEL_G45, 182 .has_pipe_cxsr = 1, 183 .ring_mask = RENDER_RING | BSD_RING, 184 }; 185 186 static const struct intel_device_info intel_gm45_info = { 187 GEN4_FEATURES, 188 .platform = INTEL_GM45, 189 .is_mobile = 1, .has_fbc = 1, 190 .has_pipe_cxsr = 1, 191 .supports_tv = 1, 192 .ring_mask = RENDER_RING | BSD_RING, 193 }; 194 195 #define GEN5_FEATURES \ 196 .gen = 5, .num_pipes = 2, \ 197 .has_hotplug = 1, \ 198 .has_gmbus_irq = 1, \ 199 .ring_mask = RENDER_RING | BSD_RING, \ 200 GEN_DEFAULT_PIPEOFFSETS, \ 201 CURSOR_OFFSETS 202 203 static const struct intel_device_info intel_ironlake_d_info = { 204 GEN5_FEATURES, 205 .platform = INTEL_IRONLAKE, 206 }; 207 208 static const struct intel_device_info intel_ironlake_m_info = { 209 GEN5_FEATURES, 210 .platform = INTEL_IRONLAKE, 211 .is_mobile = 1, .has_fbc = 1, 212 }; 213 214 #define GEN6_FEATURES \ 215 .gen = 6, .num_pipes = 2, \ 216 .has_hotplug = 1, \ 217 .has_fbc = 1, \ 218 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 219 .has_llc = 1, \ 220 .has_rc6 = 1, \ 221 .has_rc6p = 1, \ 222 .has_gmbus_irq = 1, \ 223 .has_hw_contexts = 1, \ 224 .has_aliasing_ppgtt = 1, \ 225 GEN_DEFAULT_PIPEOFFSETS, \ 226 CURSOR_OFFSETS 227 228 static const struct intel_device_info intel_sandybridge_d_info = { 229 GEN6_FEATURES, 230 .platform = INTEL_SANDYBRIDGE, 231 }; 232 233 static const struct intel_device_info intel_sandybridge_m_info = { 234 GEN6_FEATURES, 235 .platform = INTEL_SANDYBRIDGE, 236 .is_mobile = 1, 237 }; 238 239 #define GEN7_FEATURES \ 240 .gen = 7, .num_pipes = 3, \ 241 .has_hotplug = 1, \ 242 .has_fbc = 1, \ 243 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 244 .has_llc = 1, \ 245 .has_rc6 = 1, \ 246 .has_rc6p = 1, \ 247 .has_gmbus_irq = 1, \ 248 .has_hw_contexts = 1, \ 249 .has_aliasing_ppgtt = 1, \ 250 .has_full_ppgtt = 1, \ 251 GEN_DEFAULT_PIPEOFFSETS, \ 252 IVB_CURSOR_OFFSETS 253 254 static const struct intel_device_info intel_ivybridge_d_info = { 255 GEN7_FEATURES, 256 .platform = INTEL_IVYBRIDGE, 257 .has_l3_dpf = 1, 258 }; 259 260 static const struct intel_device_info intel_ivybridge_m_info = { 261 GEN7_FEATURES, 262 .platform = INTEL_IVYBRIDGE, 263 .is_mobile = 1, 264 .has_l3_dpf = 1, 265 }; 266 267 static const struct intel_device_info intel_ivybridge_q_info = { 268 GEN7_FEATURES, 269 .platform = INTEL_IVYBRIDGE, 270 .num_pipes = 0, /* legal, last one wins */ 271 .has_l3_dpf = 1, 272 }; 273 274 static const struct intel_device_info intel_valleyview_info = { 275 .platform = INTEL_VALLEYVIEW, 276 .gen = 7, 277 .is_lp = 1, 278 .num_pipes = 2, 279 .has_psr = 1, 280 .has_runtime_pm = 1, 281 .has_rc6 = 1, 282 .has_gmbus_irq = 1, 283 .has_hw_contexts = 1, 284 .has_gmch_display = 1, 285 .has_hotplug = 1, 286 .has_aliasing_ppgtt = 1, 287 .has_full_ppgtt = 1, 288 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 289 .display_mmio_offset = VLV_DISPLAY_BASE, 290 GEN_DEFAULT_PIPEOFFSETS, 291 CURSOR_OFFSETS 292 }; 293 294 #define HSW_FEATURES \ 295 GEN7_FEATURES, \ 296 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 297 .has_ddi = 1, \ 298 .has_fpga_dbg = 1, \ 299 .has_psr = 1, \ 300 .has_resource_streamer = 1, \ 301 .has_dp_mst = 1, \ 302 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 303 .has_runtime_pm = 1 304 305 static const struct intel_device_info intel_haswell_info = { 306 HSW_FEATURES, 307 .platform = INTEL_HASWELL, 308 .has_l3_dpf = 1, 309 }; 310 311 #define BDW_FEATURES \ 312 HSW_FEATURES, \ 313 BDW_COLORS, \ 314 .has_logical_ring_contexts = 1, \ 315 .has_full_48bit_ppgtt = 1, \ 316 .has_64bit_reloc = 1 317 318 static const struct intel_device_info intel_broadwell_info = { 319 BDW_FEATURES, 320 .gen = 8, 321 .platform = INTEL_BROADWELL, 322 }; 323 324 static const struct intel_device_info intel_broadwell_gt3_info = { 325 BDW_FEATURES, 326 .gen = 8, 327 .platform = INTEL_BROADWELL, 328 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 329 }; 330 331 static const struct intel_device_info intel_cherryview_info = { 332 .gen = 8, .num_pipes = 3, 333 .has_hotplug = 1, 334 .is_lp = 1, 335 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 336 .platform = INTEL_CHERRYVIEW, 337 .has_64bit_reloc = 1, 338 .has_psr = 1, 339 .has_runtime_pm = 1, 340 .has_resource_streamer = 1, 341 .has_rc6 = 1, 342 .has_gmbus_irq = 1, 343 .has_hw_contexts = 1, 344 .has_logical_ring_contexts = 1, 345 .has_gmch_display = 1, 346 .has_aliasing_ppgtt = 1, 347 .has_full_ppgtt = 1, 348 .display_mmio_offset = VLV_DISPLAY_BASE, 349 GEN_CHV_PIPEOFFSETS, 350 CURSOR_OFFSETS, 351 CHV_COLORS, 352 }; 353 354 #define GEN9_FEATURES \ 355 BDW_FEATURES, \ 356 .gen = 9, \ 357 .ddb_size = 896 358 359 static const struct intel_device_info intel_skylake_info = { 360 BDW_FEATURES, 361 .platform = INTEL_SKYLAKE, 362 .gen = 9, 363 .has_csr = 1, 364 .has_guc = 1, 365 .ddb_size = 896, 366 }; 367 368 static const struct intel_device_info intel_skylake_gt3_info = { 369 BDW_FEATURES, 370 .platform = INTEL_SKYLAKE, 371 .gen = 9, 372 .has_csr = 1, 373 .has_guc = 1, 374 .ddb_size = 896, 375 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 376 }; 377 378 #define GEN9_LP_FEATURES \ 379 .gen = 9, \ 380 .is_lp = 1, \ 381 .has_hotplug = 1, \ 382 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 383 .num_pipes = 3, \ 384 .has_64bit_reloc = 1, \ 385 .has_ddi = 1, \ 386 .has_fpga_dbg = 1, \ 387 .has_fbc = 1, \ 388 .has_runtime_pm = 1, \ 389 .has_pooled_eu = 0, \ 390 .has_csr = 1, \ 391 .has_resource_streamer = 1, \ 392 .has_rc6 = 1, \ 393 .has_dp_mst = 1, \ 394 .has_gmbus_irq = 1, \ 395 .has_hw_contexts = 1, \ 396 .has_logical_ring_contexts = 1, \ 397 .has_guc = 1, \ 398 .has_aliasing_ppgtt = 1, \ 399 .has_full_ppgtt = 1, \ 400 .has_full_48bit_ppgtt = 1, \ 401 GEN_DEFAULT_PIPEOFFSETS, \ 402 IVB_CURSOR_OFFSETS, \ 403 BDW_COLORS 404 405 static const struct intel_device_info intel_broxton_info = { 406 GEN9_LP_FEATURES, 407 .platform = INTEL_BROXTON, 408 .ddb_size = 512, 409 }; 410 411 static const struct intel_device_info intel_geminilake_info = { 412 GEN9_LP_FEATURES, 413 .platform = INTEL_GEMINILAKE, 414 .is_alpha_support = 1, 415 .ddb_size = 1024, 416 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 } 417 }; 418 419 static const struct intel_device_info intel_kabylake_gt1_info = { 420 BDW_FEATURES, 421 .platform = INTEL_KABYLAKE, 422 .gen = 9, 423 .has_csr = 1, 424 .has_guc = 1, 425 .ddb_size = 896, 426 }; 427 428 static const struct intel_device_info intel_kabylake_gt2_info = { 429 BDW_FEATURES, 430 .platform = INTEL_KABYLAKE, 431 .gen = 9, 432 .has_csr = 1, 433 .has_guc = 1, 434 .ddb_size = 896, 435 }; 436 437 static const struct intel_device_info intel_kabylake_gt3_info = { 438 BDW_FEATURES, 439 .platform = INTEL_KABYLAKE, 440 .gen = 9, 441 .has_csr = 1, 442 .has_guc = 1, 443 .ddb_size = 896, 444 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 445 }; 446 447 #define CFL_PLATFORM \ 448 GEN9_FEATURES, \ 449 .platform = INTEL_KABYLAKE 450 451 static const struct intel_device_info intel_coffeelake_gt1_info = { 452 CFL_PLATFORM, 453 }; 454 455 static const struct intel_device_info intel_coffeelake_gt2_info = { 456 CFL_PLATFORM, 457 }; 458 459 static const struct intel_device_info intel_coffeelake_gt3_info = { 460 CFL_PLATFORM, 461 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 462 }; 463 464 /* 465 * Make sure any device matches here are from most specific to most 466 * general. For example, since the Quanta match is based on the subsystem 467 * and subvendor IDs, we need it to come before the more general IVB 468 * PCI ID matches, otherwise we'll use the wrong info struct above. 469 */ 470 static const struct pci_device_id pciidlist[] = { 471 INTEL_I830_IDS(&intel_i830_info), 472 INTEL_I845G_IDS(&intel_i845g_info), 473 INTEL_I85X_IDS(&intel_i85x_info), 474 INTEL_I865G_IDS(&intel_i865g_info), 475 INTEL_I915G_IDS(&intel_i915g_info), 476 INTEL_I915GM_IDS(&intel_i915gm_info), 477 INTEL_I945G_IDS(&intel_i945g_info), 478 INTEL_I945GM_IDS(&intel_i945gm_info), 479 INTEL_I965G_IDS(&intel_i965g_info), 480 INTEL_G33_IDS(&intel_g33_info), 481 INTEL_I965GM_IDS(&intel_i965gm_info), 482 INTEL_GM45_IDS(&intel_gm45_info), 483 INTEL_G45_IDS(&intel_g45_info), 484 INTEL_PINEVIEW_IDS(&intel_pineview_info), 485 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 486 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 487 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), 488 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), 489 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 490 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 491 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 492 INTEL_HSW_IDS(&intel_haswell_info), 493 INTEL_VLV_IDS(&intel_valleyview_info), 494 INTEL_BDW_GT12_IDS(&intel_broadwell_info), 495 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 496 INTEL_BDW_RSVD_IDS(&intel_broadwell_info), 497 INTEL_CHV_IDS(&intel_cherryview_info), 498 INTEL_SKL_GT1_IDS(&intel_skylake_info), 499 INTEL_SKL_GT2_IDS(&intel_skylake_info), 500 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 501 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), 502 INTEL_BXT_IDS(&intel_broxton_info), 503 INTEL_GLK_IDS(&intel_geminilake_info), 504 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), 505 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), 506 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 507 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 508 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info), 509 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 510 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 511 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info), 512 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 513 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 514 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 515 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info), 516 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info), 517 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info), 518 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info), 519 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info), 520 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info), 521 {0, 0, 0} 522 }; 523 MODULE_DEVICE_TABLE(pci, pciidlist); 524 525 static void i915_pci_remove(struct pci_dev *pdev) 526 { 527 struct drm_device *dev = pci_get_drvdata(pdev); 528 529 i915_driver_unload(dev); 530 drm_dev_unref(dev); 531 } 532 533 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 534 { 535 struct intel_device_info *intel_info = 536 (struct intel_device_info *) ent->driver_data; 537 int err; 538 539 if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) { 540 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n" 541 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n" 542 "to enable support in this kernel version, or check for kernel updates.\n"); 543 return -ENODEV; 544 } 545 546 /* Only bind to function 0 of the device. Early generations 547 * used function 1 as a placeholder for multi-head. This causes 548 * us confusion instead, especially on the systems where both 549 * functions have the same PCI-ID! 550 */ 551 if (PCI_FUNC(pdev->devfn)) 552 return -ENODEV; 553 554 /* 555 * apple-gmux is needed on dual GPU MacBook Pro 556 * to probe the panel if we're the inactive GPU. 557 */ 558 if (vga_switcheroo_client_probe_defer(pdev)) 559 return -EPROBE_DEFER; 560 561 err = i915_driver_load(pdev, ent); 562 if (err) 563 return err; 564 565 err = i915_live_selftests(pdev); 566 if (err) { 567 i915_pci_remove(pdev); 568 return err > 0 ? -ENOTTY : err; 569 } 570 571 return 0; 572 } 573 574 static struct pci_driver i915_pci_driver = { 575 .name = DRIVER_NAME, 576 .id_table = pciidlist, 577 .probe = i915_pci_probe, 578 .remove = i915_pci_remove, 579 #if 0 580 .driver.pm = &i915_pm_ops, 581 #endif 582 }; 583 584 static int __init i915_init(void) 585 { 586 bool use_kms = true; 587 int err; 588 589 err = i915_mock_selftests(); 590 if (err) 591 return err > 0 ? 0 : err; 592 593 /* 594 * Enable KMS by default, unless explicitly overriden by 595 * either the i915.modeset prarameter or by the 596 * vga_text_mode_force boot option. 597 */ 598 599 if (i915.modeset == 0) 600 use_kms = false; 601 602 if (vgacon_text_force() && i915.modeset == -1) 603 use_kms = false; 604 605 if (!use_kms) { 606 /* Silently fail loading to not upset userspace. */ 607 DRM_DEBUG_DRIVER("KMS disabled.\n"); 608 return 0; 609 } 610 611 return pci_register_driver(&i915_pci_driver); 612 } 613 614 static void __exit i915_exit(void) 615 { 616 #if 0 617 if (!i915_pci_driver.driver.owner) 618 return; 619 #endif 620 621 pci_unregister_driver(&i915_pci_driver); 622 } 623 624 module_init(i915_init); 625 module_exit(i915_exit); 626 627 MODULE_AUTHOR("Tungsten Graphics, Inc."); 628 MODULE_AUTHOR("Intel Corporation"); 629 630 static int 631 i915_pci_probe_dfly(device_t kdev) 632 { 633 int device, i = 0; 634 const struct pci_device_id *ent; 635 static struct pci_dev *pdev = NULL; 636 static device_t bsddev; 637 638 if (pci_get_class(kdev) != PCIC_DISPLAY) 639 return ENXIO; 640 641 if (pci_get_vendor(kdev) != PCI_VENDOR_ID_INTEL) 642 return ENXIO; 643 644 device = pci_get_device(kdev); 645 646 for (i = 0; pciidlist[i].device != 0; i++) { 647 if (pciidlist[i].device == device) { 648 ent = &pciidlist[i]; 649 goto found; 650 } 651 } 652 653 return ENXIO; 654 found: 655 if (!strcmp(device_get_name(kdev), "drmsub")) 656 bsddev = device_get_parent(kdev); 657 else 658 bsddev = kdev; 659 660 drm_init_pdev(bsddev, &pdev); 661 662 /* Print the contents of pdev struct. */ 663 drm_print_pdev(pdev); 664 665 return i915_pci_probe(pdev, ent); 666 } 667 668 static int i915_driver_attach(device_t kdev) 669 { 670 return 0; 671 } 672 673 static device_method_t i915_methods[] = { 674 /* Device interface */ 675 DEVMETHOD(device_probe, i915_pci_probe_dfly), 676 DEVMETHOD(device_attach, i915_driver_attach), 677 #if 0 678 DEVMETHOD(device_suspend, i915_suspend_switcheroo), 679 DEVMETHOD(device_resume, i915_resume_switcheroo), 680 #endif 681 DEVMETHOD(device_detach, drm_release), 682 DEVMETHOD_END 683 }; 684 685 static driver_t i915_driver = { 686 "drm", 687 i915_methods, 688 sizeof(struct drm_softc) 689 }; 690 691 extern devclass_t drm_devclass; 692 693 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY); 694 MODULE_DEPEND(i915, drm, 1, 1, 1); 695 #ifdef CONFIG_ACPI 696 MODULE_DEPEND(i915, acpi, 1, 1, 1); 697 #endif 698