1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 29 #define _PLANE(plane, a, b) _PIPE(plane, a, b) 30 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) 31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ 33 (pipe) == PIPE_B ? (b) : (c)) 34 #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ 35 (port) == PORT_B ? (b) : (c)) 36 37 #define _MASKED_FIELD(mask, value) ({ \ 38 if (__builtin_constant_p(mask)) \ 39 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 40 if (__builtin_constant_p(value)) \ 41 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 42 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 43 BUILD_BUG_ON_MSG((value) & ~(mask), \ 44 "Incorrect value for mask"); \ 45 (mask) << 16 | (value); }) 46 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 47 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 48 49 50 51 /* PCI config space */ 52 53 #define HPLLCC 0xc0 /* 855 only */ 54 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 55 #define GC_CLOCK_133_200 (0 << 0) 56 #define GC_CLOCK_100_200 (1 << 0) 57 #define GC_CLOCK_100_133 (2 << 0) 58 #define GC_CLOCK_166_250 (3 << 0) 59 #define GCFGC2 0xda 60 #define GCFGC 0xf0 /* 915+ only */ 61 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 62 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 63 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 64 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 65 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 66 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 67 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 68 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 69 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 70 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 71 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 72 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 73 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 74 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 75 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 76 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 77 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 78 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 79 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 80 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 81 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 82 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 83 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 84 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 85 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 86 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 87 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 88 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 89 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 90 #define GCDGMBUS 0xcc 91 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 92 93 94 /* Graphics reset regs */ 95 #define I915_GDRST 0xc0 /* PCI config register */ 96 #define GRDOM_FULL (0<<2) 97 #define GRDOM_RENDER (1<<2) 98 #define GRDOM_MEDIA (3<<2) 99 #define GRDOM_MASK (3<<2) 100 #define GRDOM_RESET_STATUS (1<<1) 101 #define GRDOM_RESET_ENABLE (1<<0) 102 103 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 104 #define ILK_GRDOM_FULL (0<<1) 105 #define ILK_GRDOM_RENDER (1<<1) 106 #define ILK_GRDOM_MEDIA (3<<1) 107 #define ILK_GRDOM_MASK (3<<1) 108 #define ILK_GRDOM_RESET_ENABLE (1<<0) 109 110 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 111 #define GEN6_MBC_SNPCR_SHIFT 21 112 #define GEN6_MBC_SNPCR_MASK (3<<21) 113 #define GEN6_MBC_SNPCR_MAX (0<<21) 114 #define GEN6_MBC_SNPCR_MED (1<<21) 115 #define GEN6_MBC_SNPCR_LOW (2<<21) 116 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 117 118 #define VLV_G3DCTL 0x9024 119 #define VLV_GSCKGCTL 0x9028 120 121 #define GEN6_MBCTL 0x0907c 122 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 123 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 124 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 125 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 126 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 127 128 #define GEN6_GDRST 0x941c 129 #define GEN6_GRDOM_FULL (1 << 0) 130 #define GEN6_GRDOM_RENDER (1 << 1) 131 #define GEN6_GRDOM_MEDIA (1 << 2) 132 #define GEN6_GRDOM_BLT (1 << 3) 133 134 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 135 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 136 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 137 #define PP_DIR_DCLV_2G 0xffffffff 138 139 #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) 140 #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) 141 142 #define GEN8_R_PWR_CLK_STATE 0x20C8 143 #define GEN8_RPCS_ENABLE (1 << 31) 144 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 145 #define GEN8_RPCS_S_CNT_SHIFT 15 146 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 147 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 148 #define GEN8_RPCS_SS_CNT_SHIFT 8 149 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 150 #define GEN8_RPCS_EU_MAX_SHIFT 4 151 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 152 #define GEN8_RPCS_EU_MIN_SHIFT 0 153 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 154 155 #define GAM_ECOCHK 0x4090 156 #define BDW_DISABLE_HDC_INVALIDATION (1<<25) 157 #define ECOCHK_SNB_BIT (1<<10) 158 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) 159 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 160 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 161 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) 162 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) 163 #define ECOCHK_PPGTT_UC_HSW (0x1<<3) 164 #define ECOCHK_PPGTT_WT_HSW (0x2<<3) 165 #define ECOCHK_PPGTT_WB_HSW (0x3<<3) 166 167 #define GAC_ECO_BITS 0x14090 168 #define ECOBITS_SNB_BIT (1<<13) 169 #define ECOBITS_PPGTT_CACHE64B (3<<8) 170 #define ECOBITS_PPGTT_CACHE4B (0<<8) 171 172 #define GAB_CTL 0x24000 173 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 174 175 #define GEN7_BIOS_RESERVED 0x1082C0 176 #define GEN7_BIOS_RESERVED_1M (0 << 5) 177 #define GEN7_BIOS_RESERVED_256K (1 << 5) 178 #define GEN8_BIOS_RESERVED_SHIFT 7 179 #define GEN7_BIOS_RESERVED_MASK 0x1 180 #define GEN8_BIOS_RESERVED_MASK 0x3 181 182 183 /* VGA stuff */ 184 185 #define VGA_ST01_MDA 0x3ba 186 #define VGA_ST01_CGA 0x3da 187 188 #define VGA_MSR_WRITE 0x3c2 189 #define VGA_MSR_READ 0x3cc 190 #define VGA_MSR_MEM_EN (1<<1) 191 #define VGA_MSR_CGA_MODE (1<<0) 192 193 #define VGA_SR_INDEX 0x3c4 194 #define SR01 1 195 #define VGA_SR_DATA 0x3c5 196 197 #define VGA_AR_INDEX 0x3c0 198 #define VGA_AR_VID_EN (1<<5) 199 #define VGA_AR_DATA_WRITE 0x3c0 200 #define VGA_AR_DATA_READ 0x3c1 201 202 #define VGA_GR_INDEX 0x3ce 203 #define VGA_GR_DATA 0x3cf 204 /* GR05 */ 205 #define VGA_GR_MEM_READ_MODE_SHIFT 3 206 #define VGA_GR_MEM_READ_MODE_PLANE 1 207 /* GR06 */ 208 #define VGA_GR_MEM_MODE_MASK 0xc 209 #define VGA_GR_MEM_MODE_SHIFT 2 210 #define VGA_GR_MEM_A0000_AFFFF 0 211 #define VGA_GR_MEM_A0000_BFFFF 1 212 #define VGA_GR_MEM_B0000_B7FFF 2 213 #define VGA_GR_MEM_B0000_BFFFF 3 214 215 #define VGA_DACMASK 0x3c6 216 #define VGA_DACRX 0x3c7 217 #define VGA_DACWX 0x3c8 218 #define VGA_DACDATA 0x3c9 219 220 #define VGA_CR_INDEX_MDA 0x3b4 221 #define VGA_CR_DATA_MDA 0x3b5 222 #define VGA_CR_INDEX_CGA 0x3d4 223 #define VGA_CR_DATA_CGA 0x3d5 224 225 /* 226 * Instruction field definitions used by the command parser 227 */ 228 #define INSTR_CLIENT_SHIFT 29 229 #define INSTR_CLIENT_MASK 0xE0000000 230 #define INSTR_MI_CLIENT 0x0 231 #define INSTR_BC_CLIENT 0x2 232 #define INSTR_RC_CLIENT 0x3 233 #define INSTR_SUBCLIENT_SHIFT 27 234 #define INSTR_SUBCLIENT_MASK 0x18000000 235 #define INSTR_MEDIA_SUBCLIENT 0x2 236 #define INSTR_26_TO_24_MASK 0x7000000 237 #define INSTR_26_TO_24_SHIFT 24 238 239 /* 240 * Memory interface instructions used by the kernel 241 */ 242 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 243 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ 244 #define MI_GLOBAL_GTT (1<<22) 245 246 #define MI_NOOP MI_INSTR(0, 0) 247 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 248 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 249 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 250 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 251 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 252 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 253 #define MI_FLUSH MI_INSTR(0x04, 0) 254 #define MI_READ_FLUSH (1 << 0) 255 #define MI_EXE_FLUSH (1 << 1) 256 #define MI_NO_WRITE_FLUSH (1 << 2) 257 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 258 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 259 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 260 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 261 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 262 #define MI_ARB_ENABLE (1<<0) 263 #define MI_ARB_DISABLE (0<<0) 264 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 265 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 266 #define MI_SUSPEND_FLUSH_EN (1<<0) 267 #define MI_SET_APPID MI_INSTR(0x0e, 0) 268 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 269 #define MI_OVERLAY_CONTINUE (0x0<<21) 270 #define MI_OVERLAY_ON (0x1<<21) 271 #define MI_OVERLAY_OFF (0x2<<21) 272 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 273 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 274 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 275 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 276 /* IVB has funny definitions for which plane to flip. */ 277 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 278 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 279 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 280 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 281 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 282 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 283 /* SKL ones */ 284 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) 285 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) 286 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) 287 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) 288 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) 289 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) 290 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) 291 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) 292 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) 293 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ 294 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 295 #define MI_SEMAPHORE_UPDATE (1<<21) 296 #define MI_SEMAPHORE_COMPARE (1<<20) 297 #define MI_SEMAPHORE_REGISTER (1<<18) 298 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 299 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 300 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 301 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 302 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 303 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 304 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 305 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 306 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 307 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 308 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 309 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 310 #define MI_SEMAPHORE_SYNC_INVALID (3<<16) 311 #define MI_SEMAPHORE_SYNC_MASK (3<<16) 312 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 313 #define MI_MM_SPACE_GTT (1<<8) 314 #define MI_MM_SPACE_PHYSICAL (0<<8) 315 #define MI_SAVE_EXT_STATE_EN (1<<3) 316 #define MI_RESTORE_EXT_STATE_EN (1<<2) 317 #define MI_FORCE_RESTORE (1<<1) 318 #define MI_RESTORE_INHIBIT (1<<0) 319 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ 320 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) 321 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ 322 #define MI_SEMAPHORE_POLL (1<<15) 323 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) 324 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 325 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) 326 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ 327 #define MI_USE_GGTT (1 << 22) /* g4x+ */ 328 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 329 #define MI_STORE_DWORD_INDEX_SHIFT 2 330 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 331 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 332 * simply ignores the register load under certain conditions. 333 * - One can actually load arbitrary many arbitrary registers: Simply issue x 334 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 335 */ 336 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) 337 #define MI_LRI_FORCE_POSTED (1<<12) 338 #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) 339 #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) 340 #define MI_SRM_LRM_GLOBAL_GTT (1<<22) 341 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 342 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 343 #define MI_INVALIDATE_TLB (1<<18) 344 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 345 #define MI_FLUSH_DW_OP_MASK (3<<14) 346 #define MI_FLUSH_DW_NOTIFY (1<<8) 347 #define MI_INVALIDATE_BSD (1<<7) 348 #define MI_FLUSH_DW_USE_GTT (1<<2) 349 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 350 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 351 #define MI_BATCH_NON_SECURE (1) 352 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 353 #define MI_BATCH_NON_SECURE_I965 (1<<8) 354 #define MI_BATCH_PPGTT_HSW (1<<8) 355 #define MI_BATCH_NON_SECURE_HSW (1<<13) 356 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 357 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 358 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) 359 360 #define MI_PREDICATE_SRC0 (0x2400) 361 #define MI_PREDICATE_SRC1 (0x2408) 362 363 #define MI_PREDICATE_RESULT_2 (0x2214) 364 #define LOWER_SLICE_ENABLED (1<<0) 365 #define LOWER_SLICE_DISABLED (0<<0) 366 367 /* 368 * 3D instructions used by the kernel 369 */ 370 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 371 372 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 373 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 374 #define SC_UPDATE_SCISSOR (0x1<<1) 375 #define SC_ENABLE_MASK (0x1<<0) 376 #define SC_ENABLE (0x1<<0) 377 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 378 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 379 #define SCI_YMIN_MASK (0xffff<<16) 380 #define SCI_XMIN_MASK (0xffff<<0) 381 #define SCI_YMAX_MASK (0xffff<<16) 382 #define SCI_XMAX_MASK (0xffff<<0) 383 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 384 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 385 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 386 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 387 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 388 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 389 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 390 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 391 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 392 393 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) 394 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 395 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 396 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 397 #define BLT_WRITE_A (2<<20) 398 #define BLT_WRITE_RGB (1<<20) 399 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) 400 #define BLT_DEPTH_8 (0<<24) 401 #define BLT_DEPTH_16_565 (1<<24) 402 #define BLT_DEPTH_16_1555 (2<<24) 403 #define BLT_DEPTH_32 (3<<24) 404 #define BLT_ROP_SRC_COPY (0xcc<<16) 405 #define BLT_ROP_COLOR_COPY (0xf0<<16) 406 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 407 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 408 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 409 #define ASYNC_FLIP (1<<22) 410 #define DISPLAY_PLANE_A (0<<20) 411 #define DISPLAY_PLANE_B (1<<20) 412 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 413 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 414 #define PIPE_CONTROL_MMIO_WRITE (1<<23) 415 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 416 #define PIPE_CONTROL_CS_STALL (1<<20) 417 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 418 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) 419 #define PIPE_CONTROL_QW_WRITE (1<<14) 420 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) 421 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 422 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 423 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 424 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 425 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 426 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 427 #define PIPE_CONTROL_NOTIFY (1<<8) 428 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ 429 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 430 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 431 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 432 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 433 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 434 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 435 436 /* 437 * Commands used only by the command parser 438 */ 439 #define MI_SET_PREDICATE MI_INSTR(0x01, 0) 440 #define MI_ARB_CHECK MI_INSTR(0x05, 0) 441 #define MI_RS_CONTROL MI_INSTR(0x06, 0) 442 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) 443 #define MI_PREDICATE MI_INSTR(0x0C, 0) 444 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) 445 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) 446 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) 447 #define MI_URB_CLEAR MI_INSTR(0x19, 0) 448 #define MI_UPDATE_GTT MI_INSTR(0x23, 0) 449 #define MI_CLFLUSH MI_INSTR(0x27, 0) 450 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) 451 #define MI_REPORT_PERF_COUNT_GGTT (1<<0) 452 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) 453 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) 454 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) 455 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) 456 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) 457 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) 458 459 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) 460 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) 461 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) 462 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) 463 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) 464 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) 465 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ 466 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) 467 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ 468 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) 469 #define GFX_OP_3DSTATE_SO_DECL_LIST \ 470 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) 471 472 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ 473 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) 474 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ 475 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) 476 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ 477 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) 478 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ 479 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) 480 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ 481 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) 482 483 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) 484 485 #define COLOR_BLT ((0x2<<29)|(0x40<<22)) 486 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) 487 488 /* 489 * Registers used only by the command parser 490 */ 491 #define BCS_SWCTRL 0x22200 492 493 #define GPGPU_THREADS_DISPATCHED 0x2290 494 #define HS_INVOCATION_COUNT 0x2300 495 #define DS_INVOCATION_COUNT 0x2308 496 #define IA_VERTICES_COUNT 0x2310 497 #define IA_PRIMITIVES_COUNT 0x2318 498 #define VS_INVOCATION_COUNT 0x2320 499 #define GS_INVOCATION_COUNT 0x2328 500 #define GS_PRIMITIVES_COUNT 0x2330 501 #define CL_INVOCATION_COUNT 0x2338 502 #define CL_PRIMITIVES_COUNT 0x2340 503 #define PS_INVOCATION_COUNT 0x2348 504 #define PS_DEPTH_COUNT 0x2350 505 506 /* There are the 4 64-bit counter registers, one for each stream output */ 507 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) 508 509 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) 510 511 #define GEN7_3DPRIM_END_OFFSET 0x2420 512 #define GEN7_3DPRIM_START_VERTEX 0x2430 513 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 514 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 515 #define GEN7_3DPRIM_START_INSTANCE 0x243C 516 #define GEN7_3DPRIM_BASE_VERTEX 0x2440 517 518 #define OACONTROL 0x2360 519 520 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 521 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 522 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ 523 _GEN7_PIPEA_DE_LOAD_SL, \ 524 _GEN7_PIPEB_DE_LOAD_SL) 525 526 /* 527 * Reset registers 528 */ 529 #define DEBUG_RESET_I830 0x6070 530 #define DEBUG_RESET_FULL (1<<7) 531 #define DEBUG_RESET_RENDER (1<<8) 532 #define DEBUG_RESET_DISPLAY (1<<9) 533 534 /* 535 * IOSF sideband 536 */ 537 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) 538 #define IOSF_DEVFN_SHIFT 24 539 #define IOSF_OPCODE_SHIFT 16 540 #define IOSF_PORT_SHIFT 8 541 #define IOSF_BYTE_ENABLES_SHIFT 4 542 #define IOSF_BAR_SHIFT 1 543 #define IOSF_SB_BUSY (1<<0) 544 #define IOSF_PORT_BUNIT 0x3 545 #define IOSF_PORT_PUNIT 0x4 546 #define IOSF_PORT_NC 0x11 547 #define IOSF_PORT_DPIO 0x12 548 #define IOSF_PORT_DPIO_2 0x1a 549 #define IOSF_PORT_GPIO_NC 0x13 550 #define IOSF_PORT_CCK 0x14 551 #define IOSF_PORT_CCU 0xA9 552 #define IOSF_PORT_GPS_CORE 0x48 553 #define IOSF_PORT_FLISDSI 0x1B 554 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) 555 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) 556 557 /* See configdb bunit SB addr map */ 558 #define BUNIT_REG_BISOC 0x11 559 560 #define PUNIT_REG_DSPFREQ 0x36 561 #define DSPFREQSTAT_SHIFT_CHV 24 562 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 563 #define DSPFREQGUAR_SHIFT_CHV 8 564 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 565 #define DSPFREQSTAT_SHIFT 30 566 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 567 #define DSPFREQGUAR_SHIFT 14 568 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 569 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 570 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 571 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 572 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 573 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 574 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 575 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 576 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 577 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 578 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 579 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 580 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 581 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 582 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 583 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 584 585 /* See the PUNIT HAS v0.8 for the below bits */ 586 enum punit_power_well { 587 PUNIT_POWER_WELL_RENDER = 0, 588 PUNIT_POWER_WELL_MEDIA = 1, 589 PUNIT_POWER_WELL_DISP2D = 3, 590 PUNIT_POWER_WELL_DPIO_CMN_BC = 5, 591 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, 592 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, 593 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, 594 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, 595 PUNIT_POWER_WELL_DPIO_RX0 = 10, 596 PUNIT_POWER_WELL_DPIO_RX1 = 11, 597 PUNIT_POWER_WELL_DPIO_CMN_D = 12, 598 599 PUNIT_POWER_WELL_NUM, 600 }; 601 602 enum skl_disp_power_wells { 603 SKL_DISP_PW_MISC_IO, 604 SKL_DISP_PW_DDI_A_E, 605 SKL_DISP_PW_DDI_B, 606 SKL_DISP_PW_DDI_C, 607 SKL_DISP_PW_DDI_D, 608 SKL_DISP_PW_1 = 14, 609 SKL_DISP_PW_2, 610 }; 611 612 #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) 613 #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) 614 615 #define PUNIT_REG_PWRGT_CTRL 0x60 616 #define PUNIT_REG_PWRGT_STATUS 0x61 617 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) 618 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) 619 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) 620 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) 621 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) 622 623 #define PUNIT_REG_GPU_LFM 0xd3 624 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 625 #define PUNIT_REG_GPU_FREQ_STS 0xd8 626 #define GPLLENABLE (1<<4) 627 #define GENFREQSTATUS (1<<0) 628 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 629 #define PUNIT_REG_CZ_TIMESTAMP 0xce 630 631 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 632 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 633 634 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 635 #define FB_GFX_FREQ_FUSE_MASK 0xff 636 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 637 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 638 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 639 640 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 641 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 642 643 #define PUNIT_REG_DDR_SETUP2 0x139 644 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 645 #define FORCE_DDR_LOW_FREQ (1 << 1) 646 #define FORCE_DDR_HIGH_FREQ (1 << 0) 647 648 #define PUNIT_GPU_STATUS_REG 0xdb 649 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 650 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 651 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 652 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 653 654 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 655 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 656 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 657 658 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 659 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 660 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 661 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 662 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 663 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 664 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 665 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 666 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 667 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 668 669 #define VLV_TURBO_SOC_OVERRIDE 0x04 670 #define VLV_OVERRIDE_EN 1 671 #define VLV_SOC_TDP_EN (1 << 1) 672 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 673 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 674 675 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 676 677 /* vlv2 north clock has */ 678 #define CCK_FUSE_REG 0x8 679 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 680 #define CCK_REG_DSI_PLL_FUSE 0x44 681 #define CCK_REG_DSI_PLL_CONTROL 0x48 682 #define DSI_PLL_VCO_EN (1 << 31) 683 #define DSI_PLL_LDO_GATE (1 << 30) 684 #define DSI_PLL_P1_POST_DIV_SHIFT 17 685 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 686 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 687 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 688 #define DSI_PLL_MUX_MASK (3 << 9) 689 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 690 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 691 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 692 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 693 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 694 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 695 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 696 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 697 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 698 #define DSI_PLL_LOCK (1 << 0) 699 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 700 #define DSI_PLL_LFSR (1 << 31) 701 #define DSI_PLL_FRACTION_EN (1 << 30) 702 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 703 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 704 #define DSI_PLL_USYNC_CNT_SHIFT 18 705 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 706 #define DSI_PLL_N1_DIV_SHIFT 16 707 #define DSI_PLL_N1_DIV_MASK (3 << 16) 708 #define DSI_PLL_M1_DIV_SHIFT 0 709 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 710 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 711 #define DISPLAY_TRUNK_FORCE_ON (1 << 17) 712 #define DISPLAY_TRUNK_FORCE_OFF (1 << 16) 713 #define DISPLAY_FREQUENCY_STATUS (0x1f << 8) 714 #define DISPLAY_FREQUENCY_STATUS_SHIFT 8 715 #define DISPLAY_FREQUENCY_VALUES (0x1f << 0) 716 717 /** 718 * DOC: DPIO 719 * 720 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI 721 * ports. DPIO is the name given to such a display PHY. These PHYs 722 * don't follow the standard programming model using direct MMIO 723 * registers, and instead their registers must be accessed trough IOSF 724 * sideband. VLV has one such PHY for driving ports B and C, and CHV 725 * adds another PHY for driving port D. Each PHY responds to specific 726 * IOSF-SB port. 727 * 728 * Each display PHY is made up of one or two channels. Each channel 729 * houses a common lane part which contains the PLL and other common 730 * logic. CH0 common lane also contains the IOSF-SB logic for the 731 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 732 * must be running when any DPIO registers are accessed. 733 * 734 * In addition to having their own registers, the PHYs are also 735 * controlled through some dedicated signals from the display 736 * controller. These include PLL reference clock enable, PLL enable, 737 * and CRI clock selection, for example. 738 * 739 * Eeach channel also has two splines (also called data lanes), and 740 * each spline is made up of one Physical Access Coding Sub-Layer 741 * (PCS) block and two TX lanes. So each channel has two PCS blocks 742 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 743 * data/clock pairs depending on the output type. 744 * 745 * Additionally the PHY also contains an AUX lane with AUX blocks 746 * for each channel. This is used for DP AUX communication, but 747 * this fact isn't really relevant for the driver since AUX is 748 * controlled from the display controller side. No DPIO registers 749 * need to be accessed during AUX communication, 750 * 751 * Generally on VLV/CHV the common lane corresponds to the pipe and 752 * the spline (PCS/TX) corresponds to the port. 753 * 754 * For dual channel PHY (VLV/CHV): 755 * 756 * pipe A == CMN/PLL/REF CH0 757 * 758 * pipe B == CMN/PLL/REF CH1 759 * 760 * port B == PCS/TX CH0 761 * 762 * port C == PCS/TX CH1 763 * 764 * This is especially important when we cross the streams 765 * ie. drive port B with pipe B, or port C with pipe A. 766 * 767 * For single channel PHY (CHV): 768 * 769 * pipe C == CMN/PLL/REF CH0 770 * 771 * port D == PCS/TX CH0 772 * 773 * On BXT the entire PHY channel corresponds to the port. That means 774 * the PLL is also now associated with the port rather than the pipe, 775 * and so the clock needs to be routed to the appropriate transcoder. 776 * Port A PLL is directly connected to transcoder EDP and port B/C 777 * PLLs can be routed to any transcoder A/B/C. 778 * 779 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 780 * digital port D (CHV) or port A (BXT). 781 */ 782 /* 783 * Dual channel PHY (VLV/CHV/BXT) 784 * --------------------------------- 785 * | CH0 | CH1 | 786 * | CMN/PLL/REF | CMN/PLL/REF | 787 * |---------------|---------------| Display PHY 788 * | PCS01 | PCS23 | PCS01 | PCS23 | 789 * |-------|-------|-------|-------| 790 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 791 * --------------------------------- 792 * | DDI0 | DDI1 | DP/HDMI ports 793 * --------------------------------- 794 * 795 * Single channel PHY (CHV/BXT) 796 * ----------------- 797 * | CH0 | 798 * | CMN/PLL/REF | 799 * |---------------| Display PHY 800 * | PCS01 | PCS23 | 801 * |-------|-------| 802 * |TX0|TX1|TX2|TX3| 803 * ----------------- 804 * | DDI2 | DP/HDMI port 805 * ----------------- 806 */ 807 #define DPIO_DEVFN 0 808 809 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) 810 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 811 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 812 #define DPIO_SFR_BYPASS (1<<1) 813 #define DPIO_CMNRST (1<<0) 814 815 #define DPIO_PHY(pipe) ((pipe) >> 1) 816 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 817 818 /* 819 * Per pipe/PLL DPIO regs 820 */ 821 #define _VLV_PLL_DW3_CH0 0x800c 822 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 823 #define DPIO_POST_DIV_DAC 0 824 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 825 #define DPIO_POST_DIV_LVDS1 2 826 #define DPIO_POST_DIV_LVDS2 3 827 #define DPIO_K_SHIFT (24) /* 4 bits */ 828 #define DPIO_P1_SHIFT (21) /* 3 bits */ 829 #define DPIO_P2_SHIFT (16) /* 5 bits */ 830 #define DPIO_N_SHIFT (12) /* 4 bits */ 831 #define DPIO_ENABLE_CALIBRATION (1<<11) 832 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 833 #define DPIO_M2DIV_MASK 0xff 834 #define _VLV_PLL_DW3_CH1 0x802c 835 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 836 837 #define _VLV_PLL_DW5_CH0 0x8014 838 #define DPIO_REFSEL_OVERRIDE 27 839 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 840 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 841 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 842 #define DPIO_PLL_REFCLK_SEL_MASK 3 843 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 844 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 845 #define _VLV_PLL_DW5_CH1 0x8034 846 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 847 848 #define _VLV_PLL_DW7_CH0 0x801c 849 #define _VLV_PLL_DW7_CH1 0x803c 850 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 851 852 #define _VLV_PLL_DW8_CH0 0x8040 853 #define _VLV_PLL_DW8_CH1 0x8060 854 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 855 856 #define VLV_PLL_DW9_BCAST 0xc044 857 #define _VLV_PLL_DW9_CH0 0x8044 858 #define _VLV_PLL_DW9_CH1 0x8064 859 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 860 861 #define _VLV_PLL_DW10_CH0 0x8048 862 #define _VLV_PLL_DW10_CH1 0x8068 863 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 864 865 #define _VLV_PLL_DW11_CH0 0x804c 866 #define _VLV_PLL_DW11_CH1 0x806c 867 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 868 869 /* Spec for ref block start counts at DW10 */ 870 #define VLV_REF_DW13 0x80ac 871 872 #define VLV_CMN_DW0 0x8100 873 874 /* 875 * Per DDI channel DPIO regs 876 */ 877 878 #define _VLV_PCS_DW0_CH0 0x8200 879 #define _VLV_PCS_DW0_CH1 0x8400 880 #define DPIO_PCS_TX_LANE2_RESET (1<<16) 881 #define DPIO_PCS_TX_LANE1_RESET (1<<7) 882 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) 883 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) 884 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 885 886 #define _VLV_PCS01_DW0_CH0 0x200 887 #define _VLV_PCS23_DW0_CH0 0x400 888 #define _VLV_PCS01_DW0_CH1 0x2600 889 #define _VLV_PCS23_DW0_CH1 0x2800 890 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 891 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 892 893 #define _VLV_PCS_DW1_CH0 0x8204 894 #define _VLV_PCS_DW1_CH1 0x8404 895 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) 896 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 897 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 898 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 899 #define DPIO_PCS_CLK_SOFT_RESET (1<<5) 900 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 901 902 #define _VLV_PCS01_DW1_CH0 0x204 903 #define _VLV_PCS23_DW1_CH0 0x404 904 #define _VLV_PCS01_DW1_CH1 0x2604 905 #define _VLV_PCS23_DW1_CH1 0x2804 906 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 907 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 908 909 #define _VLV_PCS_DW8_CH0 0x8220 910 #define _VLV_PCS_DW8_CH1 0x8420 911 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 912 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 913 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 914 915 #define _VLV_PCS01_DW8_CH0 0x0220 916 #define _VLV_PCS23_DW8_CH0 0x0420 917 #define _VLV_PCS01_DW8_CH1 0x2620 918 #define _VLV_PCS23_DW8_CH1 0x2820 919 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 920 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 921 922 #define _VLV_PCS_DW9_CH0 0x8224 923 #define _VLV_PCS_DW9_CH1 0x8424 924 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) 925 #define DPIO_PCS_TX2MARGIN_000 (0<<13) 926 #define DPIO_PCS_TX2MARGIN_101 (1<<13) 927 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) 928 #define DPIO_PCS_TX1MARGIN_000 (0<<10) 929 #define DPIO_PCS_TX1MARGIN_101 (1<<10) 930 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 931 932 #define _VLV_PCS01_DW9_CH0 0x224 933 #define _VLV_PCS23_DW9_CH0 0x424 934 #define _VLV_PCS01_DW9_CH1 0x2624 935 #define _VLV_PCS23_DW9_CH1 0x2824 936 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 937 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 938 939 #define _CHV_PCS_DW10_CH0 0x8228 940 #define _CHV_PCS_DW10_CH1 0x8428 941 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) 942 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) 943 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) 944 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) 945 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) 946 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) 947 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) 948 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) 949 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 950 951 #define _VLV_PCS01_DW10_CH0 0x0228 952 #define _VLV_PCS23_DW10_CH0 0x0428 953 #define _VLV_PCS01_DW10_CH1 0x2628 954 #define _VLV_PCS23_DW10_CH1 0x2828 955 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 956 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 957 958 #define _VLV_PCS_DW11_CH0 0x822c 959 #define _VLV_PCS_DW11_CH1 0x842c 960 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24) 961 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) 962 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) 963 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) 964 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 965 966 #define _VLV_PCS01_DW11_CH0 0x022c 967 #define _VLV_PCS23_DW11_CH0 0x042c 968 #define _VLV_PCS01_DW11_CH1 0x262c 969 #define _VLV_PCS23_DW11_CH1 0x282c 970 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 971 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 972 973 #define _VLV_PCS01_DW12_CH0 0x0230 974 #define _VLV_PCS23_DW12_CH0 0x0430 975 #define _VLV_PCS01_DW12_CH1 0x2630 976 #define _VLV_PCS23_DW12_CH1 0x2830 977 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 978 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 979 980 #define _VLV_PCS_DW12_CH0 0x8230 981 #define _VLV_PCS_DW12_CH1 0x8430 982 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20) 983 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16) 984 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8) 985 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6) 986 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0) 987 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 988 989 #define _VLV_PCS_DW14_CH0 0x8238 990 #define _VLV_PCS_DW14_CH1 0x8438 991 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 992 993 #define _VLV_PCS_DW23_CH0 0x825c 994 #define _VLV_PCS_DW23_CH1 0x845c 995 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 996 997 #define _VLV_TX_DW2_CH0 0x8288 998 #define _VLV_TX_DW2_CH1 0x8488 999 #define DPIO_SWING_MARGIN000_SHIFT 16 1000 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 1001 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 1002 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 1003 1004 #define _VLV_TX_DW3_CH0 0x828c 1005 #define _VLV_TX_DW3_CH1 0x848c 1006 /* The following bit for CHV phy */ 1007 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) 1008 #define DPIO_SWING_MARGIN101_SHIFT 16 1009 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 1010 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 1011 1012 #define _VLV_TX_DW4_CH0 0x8290 1013 #define _VLV_TX_DW4_CH1 0x8490 1014 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 1015 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 1016 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 1017 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 1018 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 1019 1020 #define _VLV_TX3_DW4_CH0 0x690 1021 #define _VLV_TX3_DW4_CH1 0x2a90 1022 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 1023 1024 #define _VLV_TX_DW5_CH0 0x8294 1025 #define _VLV_TX_DW5_CH1 0x8494 1026 #define DPIO_TX_OCALINIT_EN (1<<31) 1027 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 1028 1029 #define _VLV_TX_DW11_CH0 0x82ac 1030 #define _VLV_TX_DW11_CH1 0x84ac 1031 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 1032 1033 #define _VLV_TX_DW14_CH0 0x82b8 1034 #define _VLV_TX_DW14_CH1 0x84b8 1035 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 1036 1037 /* CHV dpPhy registers */ 1038 #define _CHV_PLL_DW0_CH0 0x8000 1039 #define _CHV_PLL_DW0_CH1 0x8180 1040 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 1041 1042 #define _CHV_PLL_DW1_CH0 0x8004 1043 #define _CHV_PLL_DW1_CH1 0x8184 1044 #define DPIO_CHV_N_DIV_SHIFT 8 1045 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 1046 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 1047 1048 #define _CHV_PLL_DW2_CH0 0x8008 1049 #define _CHV_PLL_DW2_CH1 0x8188 1050 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 1051 1052 #define _CHV_PLL_DW3_CH0 0x800c 1053 #define _CHV_PLL_DW3_CH1 0x818c 1054 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 1055 #define DPIO_CHV_FIRST_MOD (0 << 8) 1056 #define DPIO_CHV_SECOND_MOD (1 << 8) 1057 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 1058 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 1059 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 1060 1061 #define _CHV_PLL_DW6_CH0 0x8018 1062 #define _CHV_PLL_DW6_CH1 0x8198 1063 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 1064 #define DPIO_CHV_INT_COEFF_SHIFT 8 1065 #define DPIO_CHV_PROP_COEFF_SHIFT 0 1066 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 1067 1068 #define _CHV_PLL_DW8_CH0 0x8020 1069 #define _CHV_PLL_DW8_CH1 0x81A0 1070 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 1071 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 1072 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 1073 1074 #define _CHV_PLL_DW9_CH0 0x8024 1075 #define _CHV_PLL_DW9_CH1 0x81A4 1076 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 1077 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 1078 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 1079 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 1080 1081 #define _CHV_CMN_DW5_CH0 0x8114 1082 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1083 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1084 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1085 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 1086 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1087 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1088 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 1089 #define CHV_BUFLEFTENA1_MASK (3 << 22) 1090 1091 #define _CHV_CMN_DW13_CH0 0x8134 1092 #define _CHV_CMN_DW0_CH1 0x8080 1093 #define DPIO_CHV_S1_DIV_SHIFT 21 1094 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1095 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1096 #define DPIO_CHV_K_DIV_SHIFT 4 1097 #define DPIO_PLL_FREQLOCK (1 << 1) 1098 #define DPIO_PLL_LOCK (1 << 0) 1099 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1100 1101 #define _CHV_CMN_DW14_CH0 0x8138 1102 #define _CHV_CMN_DW1_CH1 0x8084 1103 #define DPIO_AFC_RECAL (1 << 14) 1104 #define DPIO_DCLKP_EN (1 << 13) 1105 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1106 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1107 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1108 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1109 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1110 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1111 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1112 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1113 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1114 1115 #define _CHV_CMN_DW19_CH0 0x814c 1116 #define _CHV_CMN_DW6_CH1 0x8098 1117 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1118 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1119 1120 #define CHV_CMN_DW30 0x8178 1121 #define DPIO_LRC_BYPASS (1 << 3) 1122 1123 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1124 (lane) * 0x200 + (offset)) 1125 1126 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1127 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1128 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1129 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1130 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1131 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1132 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1133 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1134 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1135 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1136 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1137 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1138 #define DPIO_FRC_LATENCY_SHFIT 8 1139 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1140 #define DPIO_UPAR_SHIFT 30 1141 1142 /* BXT PHY registers */ 1143 #define _BXT_PHY(phy, a, b) _PIPE((phy), (a), (b)) 1144 1145 #define BXT_P_CR_GT_DISP_PWRON 0x138090 1146 #define GT_DISPLAY_POWER_ON(phy) (1 << (phy)) 1147 1148 #define _PHY_CTL_FAMILY_EDP 0x64C80 1149 #define _PHY_CTL_FAMILY_DDI 0x64C90 1150 #define COMMON_RESET_DIS (1 << 31) 1151 #define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \ 1152 _PHY_CTL_FAMILY_EDP) 1153 1154 /* BXT PHY PLL registers */ 1155 #define _PORT_PLL_A 0x46074 1156 #define _PORT_PLL_B 0x46078 1157 #define _PORT_PLL_C 0x4607c 1158 #define PORT_PLL_ENABLE (1 << 31) 1159 #define PORT_PLL_LOCK (1 << 30) 1160 #define PORT_PLL_REF_SEL (1 << 27) 1161 #define BXT_PORT_PLL_ENABLE(port) _PORT(port, _PORT_PLL_A, _PORT_PLL_B) 1162 1163 #define _PORT_PLL_EBB_0_A 0x162034 1164 #define _PORT_PLL_EBB_0_B 0x6C034 1165 #define _PORT_PLL_EBB_0_C 0x6C340 1166 #define PORT_PLL_P1_MASK (0x07 << 13) 1167 #define PORT_PLL_P1(x) ((x) << 13) 1168 #define PORT_PLL_P2_MASK (0x1f << 8) 1169 #define PORT_PLL_P2(x) ((x) << 8) 1170 #define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \ 1171 _PORT_PLL_EBB_0_B, \ 1172 _PORT_PLL_EBB_0_C) 1173 1174 #define _PORT_PLL_EBB_4_A 0x162038 1175 #define _PORT_PLL_EBB_4_B 0x6C038 1176 #define _PORT_PLL_EBB_4_C 0x6C344 1177 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 1178 #define PORT_PLL_RECALIBRATE (1 << 14) 1179 #define BXT_PORT_PLL_EBB_4(port) _PORT3(port, _PORT_PLL_EBB_4_A, \ 1180 _PORT_PLL_EBB_4_B, \ 1181 _PORT_PLL_EBB_4_C) 1182 1183 #define _PORT_PLL_0_A 0x162100 1184 #define _PORT_PLL_0_B 0x6C100 1185 #define _PORT_PLL_0_C 0x6C380 1186 /* PORT_PLL_0_A */ 1187 #define PORT_PLL_M2_MASK 0xFF 1188 /* PORT_PLL_1_A */ 1189 #define PORT_PLL_N_MASK (0x0F << 8) 1190 #define PORT_PLL_N(x) ((x) << 8) 1191 /* PORT_PLL_2_A */ 1192 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 1193 /* PORT_PLL_3_A */ 1194 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 1195 /* PORT_PLL_6_A */ 1196 #define PORT_PLL_PROP_COEFF_MASK 0xF 1197 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 1198 #define PORT_PLL_INT_COEFF(x) ((x) << 8) 1199 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 1200 #define PORT_PLL_GAIN_CTL(x) ((x) << 16) 1201 /* PORT_PLL_8_A */ 1202 #define PORT_PLL_TARGET_CNT_MASK 0x3FF 1203 /* PORT_PLL_9_A */ 1204 #define PORT_PLL_LOCK_THRESHOLD_MASK 0xe 1205 /* PORT_PLL_10_A */ 1206 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) 1207 #define PORT_PLL_DCO_AMP_MASK 0x3c00 1208 #define PORT_PLL_DCO_AMP(x) (x<<10) 1209 #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ 1210 _PORT_PLL_0_B, \ 1211 _PORT_PLL_0_C) 1212 #define BXT_PORT_PLL(port, idx) (_PORT_PLL_BASE(port) + (idx) * 4) 1213 1214 /* BXT PHY common lane registers */ 1215 #define _PORT_CL1CM_DW0_A 0x162000 1216 #define _PORT_CL1CM_DW0_BC 0x6C000 1217 #define PHY_POWER_GOOD (1 << 16) 1218 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ 1219 _PORT_CL1CM_DW0_A) 1220 1221 #define _PORT_CL1CM_DW9_A 0x162024 1222 #define _PORT_CL1CM_DW9_BC 0x6C024 1223 #define IREF0RC_OFFSET_SHIFT 8 1224 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 1225 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \ 1226 _PORT_CL1CM_DW9_A) 1227 1228 #define _PORT_CL1CM_DW10_A 0x162028 1229 #define _PORT_CL1CM_DW10_BC 0x6C028 1230 #define IREF1RC_OFFSET_SHIFT 8 1231 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1232 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \ 1233 _PORT_CL1CM_DW10_A) 1234 1235 #define _PORT_CL1CM_DW28_A 0x162070 1236 #define _PORT_CL1CM_DW28_BC 0x6C070 1237 #define OCL1_POWER_DOWN_EN (1 << 23) 1238 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 1239 #define SUS_CLK_CONFIG 0x3 1240 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \ 1241 _PORT_CL1CM_DW28_A) 1242 1243 #define _PORT_CL1CM_DW30_A 0x162078 1244 #define _PORT_CL1CM_DW30_BC 0x6C078 1245 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1246 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \ 1247 _PORT_CL1CM_DW30_A) 1248 1249 /* Defined for PHY0 only */ 1250 #define BXT_PORT_CL2CM_DW6_BC 0x6C358 1251 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 1252 1253 /* BXT PHY Ref registers */ 1254 #define _PORT_REF_DW3_A 0x16218C 1255 #define _PORT_REF_DW3_BC 0x6C18C 1256 #define GRC_DONE (1 << 22) 1257 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \ 1258 _PORT_REF_DW3_A) 1259 1260 #define _PORT_REF_DW6_A 0x162198 1261 #define _PORT_REF_DW6_BC 0x6C198 1262 /* 1263 * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them 1264 * after testing. 1265 */ 1266 #define GRC_CODE_SHIFT 23 1267 #define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT) 1268 #define GRC_CODE_FAST_SHIFT 16 1269 #define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT) 1270 #define GRC_CODE_SLOW_SHIFT 8 1271 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 1272 #define GRC_CODE_NOM_MASK 0xFF 1273 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \ 1274 _PORT_REF_DW6_A) 1275 1276 #define _PORT_REF_DW8_A 0x1621A0 1277 #define _PORT_REF_DW8_BC 0x6C1A0 1278 #define GRC_DIS (1 << 15) 1279 #define GRC_RDY_OVRD (1 << 1) 1280 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \ 1281 _PORT_REF_DW8_A) 1282 1283 /* BXT PHY PCS registers */ 1284 #define _PORT_PCS_DW10_LN01_A 0x162428 1285 #define _PORT_PCS_DW10_LN01_B 0x6C428 1286 #define _PORT_PCS_DW10_LN01_C 0x6C828 1287 #define _PORT_PCS_DW10_GRP_A 0x162C28 1288 #define _PORT_PCS_DW10_GRP_B 0x6CC28 1289 #define _PORT_PCS_DW10_GRP_C 0x6CE28 1290 #define BXT_PORT_PCS_DW10_LN01(port) _PORT3(port, _PORT_PCS_DW10_LN01_A, \ 1291 _PORT_PCS_DW10_LN01_B, \ 1292 _PORT_PCS_DW10_LN01_C) 1293 #define BXT_PORT_PCS_DW10_GRP(port) _PORT3(port, _PORT_PCS_DW10_GRP_A, \ 1294 _PORT_PCS_DW10_GRP_B, \ 1295 _PORT_PCS_DW10_GRP_C) 1296 #define TX2_SWING_CALC_INIT (1 << 31) 1297 #define TX1_SWING_CALC_INIT (1 << 30) 1298 1299 #define _PORT_PCS_DW12_LN01_A 0x162430 1300 #define _PORT_PCS_DW12_LN01_B 0x6C430 1301 #define _PORT_PCS_DW12_LN01_C 0x6C830 1302 #define _PORT_PCS_DW12_LN23_A 0x162630 1303 #define _PORT_PCS_DW12_LN23_B 0x6C630 1304 #define _PORT_PCS_DW12_LN23_C 0x6CA30 1305 #define _PORT_PCS_DW12_GRP_A 0x162c30 1306 #define _PORT_PCS_DW12_GRP_B 0x6CC30 1307 #define _PORT_PCS_DW12_GRP_C 0x6CE30 1308 #define LANESTAGGER_STRAP_OVRD (1 << 6) 1309 #define LANE_STAGGER_MASK 0x1F 1310 #define BXT_PORT_PCS_DW12_LN01(port) _PORT3(port, _PORT_PCS_DW12_LN01_A, \ 1311 _PORT_PCS_DW12_LN01_B, \ 1312 _PORT_PCS_DW12_LN01_C) 1313 #define BXT_PORT_PCS_DW12_LN23(port) _PORT3(port, _PORT_PCS_DW12_LN23_A, \ 1314 _PORT_PCS_DW12_LN23_B, \ 1315 _PORT_PCS_DW12_LN23_C) 1316 #define BXT_PORT_PCS_DW12_GRP(port) _PORT3(port, _PORT_PCS_DW12_GRP_A, \ 1317 _PORT_PCS_DW12_GRP_B, \ 1318 _PORT_PCS_DW12_GRP_C) 1319 1320 /* BXT PHY TX registers */ 1321 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 1322 ((lane) & 1) * 0x80) 1323 1324 #define _PORT_TX_DW2_LN0_A 0x162508 1325 #define _PORT_TX_DW2_LN0_B 0x6C508 1326 #define _PORT_TX_DW2_LN0_C 0x6C908 1327 #define _PORT_TX_DW2_GRP_A 0x162D08 1328 #define _PORT_TX_DW2_GRP_B 0x6CD08 1329 #define _PORT_TX_DW2_GRP_C 0x6CF08 1330 #define BXT_PORT_TX_DW2_GRP(port) _PORT3(port, _PORT_TX_DW2_GRP_A, \ 1331 _PORT_TX_DW2_GRP_B, \ 1332 _PORT_TX_DW2_GRP_C) 1333 #define BXT_PORT_TX_DW2_LN0(port) _PORT3(port, _PORT_TX_DW2_LN0_A, \ 1334 _PORT_TX_DW2_LN0_B, \ 1335 _PORT_TX_DW2_LN0_C) 1336 #define MARGIN_000_SHIFT 16 1337 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 1338 #define UNIQ_TRANS_SCALE_SHIFT 8 1339 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 1340 1341 #define _PORT_TX_DW3_LN0_A 0x16250C 1342 #define _PORT_TX_DW3_LN0_B 0x6C50C 1343 #define _PORT_TX_DW3_LN0_C 0x6C90C 1344 #define _PORT_TX_DW3_GRP_A 0x162D0C 1345 #define _PORT_TX_DW3_GRP_B 0x6CD0C 1346 #define _PORT_TX_DW3_GRP_C 0x6CF0C 1347 #define BXT_PORT_TX_DW3_GRP(port) _PORT3(port, _PORT_TX_DW3_GRP_A, \ 1348 _PORT_TX_DW3_GRP_B, \ 1349 _PORT_TX_DW3_GRP_C) 1350 #define BXT_PORT_TX_DW3_LN0(port) _PORT3(port, _PORT_TX_DW3_LN0_A, \ 1351 _PORT_TX_DW3_LN0_B, \ 1352 _PORT_TX_DW3_LN0_C) 1353 #define UNIQE_TRANGE_EN_METHOD (1 << 27) 1354 1355 #define _PORT_TX_DW4_LN0_A 0x162510 1356 #define _PORT_TX_DW4_LN0_B 0x6C510 1357 #define _PORT_TX_DW4_LN0_C 0x6C910 1358 #define _PORT_TX_DW4_GRP_A 0x162D10 1359 #define _PORT_TX_DW4_GRP_B 0x6CD10 1360 #define _PORT_TX_DW4_GRP_C 0x6CF10 1361 #define BXT_PORT_TX_DW4_LN0(port) _PORT3(port, _PORT_TX_DW4_LN0_A, \ 1362 _PORT_TX_DW4_LN0_B, \ 1363 _PORT_TX_DW4_LN0_C) 1364 #define BXT_PORT_TX_DW4_GRP(port) _PORT3(port, _PORT_TX_DW4_GRP_A, \ 1365 _PORT_TX_DW4_GRP_B, \ 1366 _PORT_TX_DW4_GRP_C) 1367 #define DEEMPH_SHIFT 24 1368 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 1369 1370 #define _PORT_TX_DW14_LN0_A 0x162538 1371 #define _PORT_TX_DW14_LN0_B 0x6C538 1372 #define _PORT_TX_DW14_LN0_C 0x6C938 1373 #define LATENCY_OPTIM_SHIFT 30 1374 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 1375 #define BXT_PORT_TX_DW14_LN(port, lane) (_PORT3((port), _PORT_TX_DW14_LN0_A, \ 1376 _PORT_TX_DW14_LN0_B, \ 1377 _PORT_TX_DW14_LN0_C) + \ 1378 _BXT_LANE_OFFSET(lane)) 1379 1380 /* 1381 * Fence registers 1382 */ 1383 #define FENCE_REG_830_0 0x2000 1384 #define FENCE_REG_945_8 0x3000 1385 #define I830_FENCE_START_MASK 0x07f80000 1386 #define I830_FENCE_TILING_Y_SHIFT 12 1387 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 1388 #define I830_FENCE_PITCH_SHIFT 4 1389 #define I830_FENCE_REG_VALID (1<<0) 1390 #define I915_FENCE_MAX_PITCH_VAL 4 1391 #define I830_FENCE_MAX_PITCH_VAL 6 1392 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 1393 1394 #define I915_FENCE_START_MASK 0x0ff00000 1395 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 1396 1397 #define FENCE_REG_965_0 0x03000 1398 #define I965_FENCE_PITCH_SHIFT 2 1399 #define I965_FENCE_TILING_Y_SHIFT 1 1400 #define I965_FENCE_REG_VALID (1<<0) 1401 #define I965_FENCE_MAX_PITCH_VAL 0x0400 1402 1403 #define FENCE_REG_SANDYBRIDGE_0 0x100000 1404 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 1405 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 1406 1407 1408 /* control register for cpu gtt access */ 1409 #define TILECTL 0x101000 1410 #define TILECTL_SWZCTL (1 << 0) 1411 #define TILECTL_TLBPF (1 << 1) 1412 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 1413 #define TILECTL_BACKSNOOP_DIS (1 << 3) 1414 1415 /* 1416 * Instruction and interrupt control regs 1417 */ 1418 #define PGTBL_CTL 0x02020 1419 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 1420 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 1421 #define PGTBL_ER 0x02024 1422 #define PRB0_BASE (0x2030-0x30) 1423 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ 1424 #define PRB2_BASE (0x2050-0x30) /* gen3 */ 1425 #define SRB0_BASE (0x2100-0x30) /* gen2 */ 1426 #define SRB1_BASE (0x2110-0x30) /* gen2 */ 1427 #define SRB2_BASE (0x2120-0x30) /* 830 */ 1428 #define SRB3_BASE (0x2130-0x30) /* 830 */ 1429 #define RENDER_RING_BASE 0x02000 1430 #define BSD_RING_BASE 0x04000 1431 #define GEN6_BSD_RING_BASE 0x12000 1432 #define GEN8_BSD2_RING_BASE 0x1c000 1433 #define VEBOX_RING_BASE 0x1a000 1434 #define BLT_RING_BASE 0x22000 1435 #define RING_TAIL(base) ((base)+0x30) 1436 #define RING_HEAD(base) ((base)+0x34) 1437 #define RING_START(base) ((base)+0x38) 1438 #define RING_CTL(base) ((base)+0x3c) 1439 #define RING_SYNC_0(base) ((base)+0x40) 1440 #define RING_SYNC_1(base) ((base)+0x44) 1441 #define RING_SYNC_2(base) ((base)+0x48) 1442 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 1443 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 1444 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 1445 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 1446 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 1447 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 1448 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 1449 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 1450 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 1451 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 1452 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 1453 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 1454 #define GEN6_NOSYNC 0 1455 #define RING_PSMI_CTL(base) ((base)+0x50) 1456 #define RING_MAX_IDLE(base) ((base)+0x54) 1457 #define RING_HWS_PGA(base) ((base)+0x80) 1458 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 1459 1460 #define HSW_GTT_CACHE_EN 0x4024 1461 #define GTT_CACHE_EN_ALL 0xF0007FFF 1462 #define GEN7_WR_WATERMARK 0x4028 1463 #define GEN7_GFX_PRIO_CTRL 0x402C 1464 #define ARB_MODE 0x4030 1465 #define ARB_MODE_SWIZZLE_SNB (1<<4) 1466 #define ARB_MODE_SWIZZLE_IVB (1<<5) 1467 #define GEN7_GFX_PEND_TLB0 0x4034 1468 #define GEN7_GFX_PEND_TLB1 0x4038 1469 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 1470 #define GEN7_LRA_LIMITS_BASE 0x403C 1471 #define GEN7_LRA_LIMITS_REG_NUM 13 1472 #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 1473 #define GEN7_GFX_MAX_REQ_COUNT 0x4074 1474 1475 #define GAMTARBMODE 0x04a08 1476 #define ARB_MODE_BWGTLB_DISABLE (1<<9) 1477 #define ARB_MODE_SWIZZLE_BDW (1<<1) 1478 #define RENDER_HWS_PGA_GEN7 (0x04080) 1479 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 1480 #define RING_FAULT_GTTSEL_MASK (1<<11) 1481 #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) 1482 #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) 1483 #define RING_FAULT_VALID (1<<0) 1484 #define DONE_REG 0x40b0 1485 #define GEN8_PRIVATE_PAT 0x40e0 1486 #define BSD_HWS_PGA_GEN7 (0x04180) 1487 #define BLT_HWS_PGA_GEN7 (0x04280) 1488 #define VEBOX_HWS_PGA_GEN7 (0x04380) 1489 #define RING_ACTHD(base) ((base)+0x74) 1490 #define RING_ACTHD_UDW(base) ((base)+0x5c) 1491 #define RING_NOPID(base) ((base)+0x94) 1492 #define RING_IMR(base) ((base)+0xa8) 1493 #define RING_HWSTAM(base) ((base)+0x98) 1494 #define RING_TIMESTAMP(base) ((base)+0x358) 1495 #define TAIL_ADDR 0x001FFFF8 1496 #define HEAD_WRAP_COUNT 0xFFE00000 1497 #define HEAD_WRAP_ONE 0x00200000 1498 #define HEAD_ADDR 0x001FFFFC 1499 #define RING_NR_PAGES 0x001FF000 1500 #define RING_REPORT_MASK 0x00000006 1501 #define RING_REPORT_64K 0x00000002 1502 #define RING_REPORT_128K 0x00000004 1503 #define RING_NO_REPORT 0x00000000 1504 #define RING_VALID_MASK 0x00000001 1505 #define RING_VALID 0x00000001 1506 #define RING_INVALID 0x00000000 1507 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 1508 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 1509 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 1510 1511 #define GEN7_TLB_RD_ADDR 0x4700 1512 1513 #if 0 1514 #define PRB0_TAIL 0x02030 1515 #define PRB0_HEAD 0x02034 1516 #define PRB0_START 0x02038 1517 #define PRB0_CTL 0x0203c 1518 #define PRB1_TAIL 0x02040 /* 915+ only */ 1519 #define PRB1_HEAD 0x02044 /* 915+ only */ 1520 #define PRB1_START 0x02048 /* 915+ only */ 1521 #define PRB1_CTL 0x0204c /* 915+ only */ 1522 #endif 1523 #define IPEIR_I965 0x02064 1524 #define IPEHR_I965 0x02068 1525 #define INSTDONE_I965 0x0206c 1526 #define GEN7_INSTDONE_1 0x0206c 1527 #define GEN7_SC_INSTDONE 0x07100 1528 #define GEN7_SAMPLER_INSTDONE 0x0e160 1529 #define GEN7_ROW_INSTDONE 0x0e164 1530 #define I915_NUM_INSTDONE_REG 4 1531 #define RING_IPEIR(base) ((base)+0x64) 1532 #define RING_IPEHR(base) ((base)+0x68) 1533 #define RING_INSTDONE(base) ((base)+0x6c) 1534 #define RING_INSTPS(base) ((base)+0x70) 1535 #define RING_DMA_FADD(base) ((base)+0x78) 1536 #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ 1537 #define RING_INSTPM(base) ((base)+0xc0) 1538 #define RING_MI_MODE(base) ((base)+0x9c) 1539 #define INSTPS 0x02070 /* 965+ only */ 1540 #define INSTDONE1 0x0207c /* 965+ only */ 1541 #define ACTHD_I965 0x02074 1542 #define HWS_PGA 0x02080 1543 #define HWS_ADDRESS_MASK 0xfffff000 1544 #define HWS_START_ADDRESS_SHIFT 4 1545 #define PWRCTXA 0x2088 /* 965GM+ only */ 1546 #define PWRCTX_EN (1<<0) 1547 #define IPEIR 0x02088 1548 #define IPEHR 0x0208c 1549 #define INSTDONE 0x02090 1550 #define NOPID 0x02094 1551 #define HWSTAM 0x02098 1552 #define DMA_FADD_I8XX 0x020d0 1553 #define RING_BBSTATE(base) ((base)+0x110) 1554 #define RING_BBADDR(base) ((base)+0x140) 1555 #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ 1556 1557 #define ERROR_GEN6 0x040a0 1558 #define GEN7_ERR_INT 0x44040 1559 #define ERR_INT_POISON (1<<31) 1560 #define ERR_INT_MMIO_UNCLAIMED (1<<13) 1561 #define ERR_INT_PIPE_CRC_DONE_C (1<<8) 1562 #define ERR_INT_FIFO_UNDERRUN_C (1<<6) 1563 #define ERR_INT_PIPE_CRC_DONE_B (1<<5) 1564 #define ERR_INT_FIFO_UNDERRUN_B (1<<3) 1565 #define ERR_INT_PIPE_CRC_DONE_A (1<<2) 1566 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) 1567 #define ERR_INT_FIFO_UNDERRUN_A (1<<0) 1568 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 1569 1570 #define GEN8_FAULT_TLB_DATA0 0x04b10 1571 #define GEN8_FAULT_TLB_DATA1 0x04b14 1572 1573 #define FPGA_DBG 0x42300 1574 #define FPGA_DBG_RM_NOCLAIM (1<<31) 1575 1576 #define DERRMR 0x44050 1577 /* Note that HBLANK events are reserved on bdw+ */ 1578 #define DERRMR_PIPEA_SCANLINE (1<<0) 1579 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) 1580 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) 1581 #define DERRMR_PIPEA_VBLANK (1<<3) 1582 #define DERRMR_PIPEA_HBLANK (1<<5) 1583 #define DERRMR_PIPEB_SCANLINE (1<<8) 1584 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) 1585 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) 1586 #define DERRMR_PIPEB_VBLANK (1<<11) 1587 #define DERRMR_PIPEB_HBLANK (1<<13) 1588 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1589 #define DERRMR_PIPEC_SCANLINE (1<<14) 1590 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) 1591 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) 1592 #define DERRMR_PIPEC_VBLANK (1<<21) 1593 #define DERRMR_PIPEC_HBLANK (1<<22) 1594 1595 1596 /* GM45+ chicken bits -- debug workaround bits that may be required 1597 * for various sorts of correct behavior. The top 16 bits of each are 1598 * the enables for writing to the corresponding low bit. 1599 */ 1600 #define _3D_CHICKEN 0x02084 1601 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 1602 #define _3D_CHICKEN2 0x0208c 1603 /* Disables pipelining of read flushes past the SF-WIZ interface. 1604 * Required on all Ironlake steppings according to the B-Spec, but the 1605 * particular danger of not doing so is not specified. 1606 */ 1607 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 1608 #define _3D_CHICKEN3 0x02090 1609 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 1610 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 1611 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ 1612 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 1613 1614 #define MI_MODE 0x0209c 1615 # define VS_TIMER_DISPATCH (1 << 6) 1616 # define MI_FLUSH_ENABLE (1 << 12) 1617 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 1618 # define MODE_IDLE (1 << 9) 1619 # define STOP_RING (1 << 8) 1620 1621 #define GEN6_GT_MODE 0x20d0 1622 #define GEN7_GT_MODE 0x7008 1623 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 1624 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 1625 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 1626 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 1627 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 1628 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 1629 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << (slice * 2)) 1630 #define GEN9_IZ_HASHING(slice, val) ((val) << (slice * 2)) 1631 1632 #define GFX_MODE 0x02520 1633 #define GFX_MODE_GEN7 0x0229c 1634 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 1635 #define GFX_RUN_LIST_ENABLE (1<<15) 1636 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) 1637 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 1638 #define GFX_REPLAY_MODE (1<<11) 1639 #define GFX_PSMI_GRANULARITY (1<<10) 1640 #define GFX_PPGTT_ENABLE (1<<9) 1641 1642 #define VLV_DISPLAY_BASE 0x180000 1643 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 1644 1645 #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) 1646 #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) 1647 #define SCPD0 0x0209c /* 915+ only */ 1648 #define IER 0x020a0 1649 #define IIR 0x020a4 1650 #define IMR 0x020a8 1651 #define ISR 0x020ac 1652 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) 1653 #define GINT_DIS (1<<22) 1654 #define GCFG_DIS (1<<8) 1655 #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064) 1656 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) 1657 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) 1658 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) 1659 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) 1660 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) 1661 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) 1662 #define VLV_PCBR_ADDR_SHIFT 12 1663 1664 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ 1665 #define EIR 0x020b0 1666 #define EMR 0x020b4 1667 #define ESR 0x020b8 1668 #define GM45_ERROR_PAGE_TABLE (1<<5) 1669 #define GM45_ERROR_MEM_PRIV (1<<4) 1670 #define I915_ERROR_PAGE_TABLE (1<<4) 1671 #define GM45_ERROR_CP_PRIV (1<<3) 1672 #define I915_ERROR_MEMORY_REFRESH (1<<1) 1673 #define I915_ERROR_INSTRUCTION (1<<0) 1674 #define INSTPM 0x020c0 1675 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 1676 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts 1677 will not assert AGPBUSY# and will only 1678 be delivered when out of C3. */ 1679 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 1680 #define INSTPM_TLB_INVALIDATE (1<<9) 1681 #define INSTPM_SYNC_FLUSH (1<<5) 1682 #define ACTHD 0x020c8 1683 #define MEM_MODE 0x020cc 1684 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ 1685 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ 1686 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ 1687 #define FW_BLC 0x020d8 1688 #define FW_BLC2 0x020dc 1689 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 1690 #define FW_BLC_SELF_EN_MASK (1<<31) 1691 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 1692 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 1693 #define MM_BURST_LENGTH 0x00700000 1694 #define MM_FIFO_WATERMARK 0x0001F000 1695 #define LM_BURST_LENGTH 0x00000700 1696 #define LM_FIFO_WATERMARK 0x0000001F 1697 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 1698 1699 /* Make render/texture TLB fetches lower priorty than associated data 1700 * fetches. This is not turned on by default 1701 */ 1702 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1703 1704 /* Isoch request wait on GTT enable (Display A/B/C streams). 1705 * Make isoch requests stall on the TLB update. May cause 1706 * display underruns (test mode only) 1707 */ 1708 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1709 1710 /* Block grant count for isoch requests when block count is 1711 * set to a finite value. 1712 */ 1713 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1714 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1715 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1716 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1717 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1718 1719 /* Enable render writes to complete in C2/C3/C4 power states. 1720 * If this isn't enabled, render writes are prevented in low 1721 * power states. That seems bad to me. 1722 */ 1723 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1724 1725 /* This acknowledges an async flip immediately instead 1726 * of waiting for 2TLB fetches. 1727 */ 1728 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1729 1730 /* Enables non-sequential data reads through arbiter 1731 */ 1732 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1733 1734 /* Disable FSB snooping of cacheable write cycles from binner/render 1735 * command stream 1736 */ 1737 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1738 1739 /* Arbiter time slice for non-isoch streams */ 1740 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1741 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1742 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1743 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1744 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1745 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1746 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1747 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1748 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1749 1750 /* Low priority grace period page size */ 1751 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1752 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1753 1754 /* Disable display A/B trickle feed */ 1755 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1756 1757 /* Set display plane priority */ 1758 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1759 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1760 1761 #define MI_STATE 0x020e4 /* gen2 only */ 1762 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1763 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1764 1765 #define CACHE_MODE_0 0x02120 /* 915+ only */ 1766 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 1767 #define CM0_IZ_OPT_DISABLE (1<<6) 1768 #define CM0_ZR_OPT_DISABLE (1<<5) 1769 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 1770 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 1771 #define CM0_COLOR_EVICT_DISABLE (1<<3) 1772 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 1773 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 1774 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 1775 #define GFX_FLSH_CNTL_GEN6 0x101008 1776 #define GFX_FLSH_CNTL_EN (1<<0) 1777 #define ECOSKPD 0x021d0 1778 #define ECO_GATING_CX_ONLY (1<<3) 1779 #define ECO_FLIP_DONE (1<<0) 1780 1781 #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ 1782 #define RC_OP_FLUSH_ENABLE (1<<0) 1783 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) 1784 #define CACHE_MODE_1 0x7004 /* IVB+ */ 1785 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 1786 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) 1787 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1) 1788 1789 #define GEN6_BLITTER_ECOSKPD 0x221d0 1790 #define GEN6_BLITTER_LOCK_SHIFT 16 1791 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 1792 1793 #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 1794 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 1795 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 1796 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) 1797 1798 /* Fuse readout registers for GT */ 1799 #define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) 1800 #define CHV_FGT_DISABLE_SS0 (1 << 10) 1801 #define CHV_FGT_DISABLE_SS1 (1 << 11) 1802 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 1803 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 1804 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 1805 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 1806 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 1807 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 1808 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 1809 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 1810 1811 #define GEN8_FUSE2 0x9120 1812 #define GEN8_F2_S_ENA_SHIFT 25 1813 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 1814 1815 #define GEN9_F2_SS_DIS_SHIFT 20 1816 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 1817 1818 #define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4) 1819 1820 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 1821 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 1822 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 1823 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 1824 #define GEN6_BSD_GO_INDICATOR (1 << 4) 1825 1826 /* On modern GEN architectures interrupt control consists of two sets 1827 * of registers. The first set pertains to the ring generating the 1828 * interrupt. The second control is for the functional block generating the 1829 * interrupt. These are PM, GT, DE, etc. 1830 * 1831 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1832 * GT interrupt bits, so we don't need to duplicate the defines. 1833 * 1834 * These defines should cover us well from SNB->HSW with minor exceptions 1835 * it can also work on ILK. 1836 */ 1837 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1838 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1839 #define GT_BLT_USER_INTERRUPT (1 << 22) 1840 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1841 #define GT_BSD_USER_INTERRUPT (1 << 12) 1842 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1843 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1844 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1845 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1846 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 1847 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1848 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1849 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1850 1851 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1852 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1853 1854 #define GT_PARITY_ERROR(dev) \ 1855 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1856 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1857 1858 /* These are all the "old" interrupts */ 1859 #define ILK_BSD_USER_INTERRUPT (1<<5) 1860 1861 #define I915_PM_INTERRUPT (1<<31) 1862 #define I915_ISP_INTERRUPT (1<<22) 1863 #define I915_LPE_PIPE_B_INTERRUPT (1<<21) 1864 #define I915_LPE_PIPE_A_INTERRUPT (1<<20) 1865 #define I915_MIPIC_INTERRUPT (1<<19) 1866 #define I915_MIPIA_INTERRUPT (1<<18) 1867 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 1868 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 1869 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) 1870 #define I915_MASTER_ERROR_INTERRUPT (1<<15) 1871 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 1872 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) 1873 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 1874 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) 1875 #define I915_HWB_OOM_INTERRUPT (1<<13) 1876 #define I915_LPE_PIPE_C_INTERRUPT (1<<12) 1877 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 1878 #define I915_MISC_INTERRUPT (1<<11) 1879 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 1880 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) 1881 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 1882 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) 1883 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 1884 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) 1885 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 1886 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 1887 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 1888 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 1889 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 1890 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) 1891 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) 1892 #define I915_DEBUG_INTERRUPT (1<<2) 1893 #define I915_WINVALID_INTERRUPT (1<<1) 1894 #define I915_USER_INTERRUPT (1<<1) 1895 #define I915_ASLE_INTERRUPT (1<<0) 1896 #define I915_BSD_USER_INTERRUPT (1<<25) 1897 1898 #define GEN6_BSD_RNCID 0x12198 1899 1900 #define GEN7_FF_THREAD_MODE 0x20a0 1901 #define GEN7_FF_SCHED_MASK 0x0077070 1902 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1903 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 1904 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 1905 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 1906 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 1907 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1908 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 1909 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 1910 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 1911 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 1912 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 1913 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 1914 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 1915 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 1916 1917 /* 1918 * Framebuffer compression (915+ only) 1919 */ 1920 1921 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 1922 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 1923 #define FBC_CONTROL 0x03208 1924 #define FBC_CTL_EN (1<<31) 1925 #define FBC_CTL_PERIODIC (1<<30) 1926 #define FBC_CTL_INTERVAL_SHIFT (16) 1927 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 1928 #define FBC_CTL_C3_IDLE (1<<13) 1929 #define FBC_CTL_STRIDE_SHIFT (5) 1930 #define FBC_CTL_FENCENO_SHIFT (0) 1931 #define FBC_COMMAND 0x0320c 1932 #define FBC_CMD_COMPRESS (1<<0) 1933 #define FBC_STATUS 0x03210 1934 #define FBC_STAT_COMPRESSING (1<<31) 1935 #define FBC_STAT_COMPRESSED (1<<30) 1936 #define FBC_STAT_MODIFIED (1<<29) 1937 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 1938 #define FBC_CONTROL2 0x03214 1939 #define FBC_CTL_FENCE_DBL (0<<4) 1940 #define FBC_CTL_IDLE_IMM (0<<2) 1941 #define FBC_CTL_IDLE_FULL (1<<2) 1942 #define FBC_CTL_IDLE_LINE (2<<2) 1943 #define FBC_CTL_IDLE_DEBUG (3<<2) 1944 #define FBC_CTL_CPU_FENCE (1<<1) 1945 #define FBC_CTL_PLANE(plane) ((plane)<<0) 1946 #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ 1947 #define FBC_TAG 0x03300 1948 1949 #define FBC_LL_SIZE (1536) 1950 1951 /* Framebuffer compression for GM45+ */ 1952 #define DPFC_CB_BASE 0x3200 1953 #define DPFC_CONTROL 0x3208 1954 #define DPFC_CTL_EN (1<<31) 1955 #define DPFC_CTL_PLANE(plane) ((plane)<<30) 1956 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) 1957 #define DPFC_CTL_FENCE_EN (1<<29) 1958 #define IVB_DPFC_CTL_FENCE_EN (1<<28) 1959 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 1960 #define DPFC_SR_EN (1<<10) 1961 #define DPFC_CTL_LIMIT_1X (0<<6) 1962 #define DPFC_CTL_LIMIT_2X (1<<6) 1963 #define DPFC_CTL_LIMIT_4X (2<<6) 1964 #define DPFC_RECOMP_CTL 0x320c 1965 #define DPFC_RECOMP_STALL_EN (1<<27) 1966 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 1967 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 1968 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 1969 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 1970 #define DPFC_STATUS 0x3210 1971 #define DPFC_INVAL_SEG_SHIFT (16) 1972 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 1973 #define DPFC_COMP_SEG_SHIFT (0) 1974 #define DPFC_COMP_SEG_MASK (0x000003ff) 1975 #define DPFC_STATUS2 0x3214 1976 #define DPFC_FENCE_YOFF 0x3218 1977 #define DPFC_CHICKEN 0x3224 1978 #define DPFC_HT_MODIFY (1<<31) 1979 1980 /* Framebuffer compression for Ironlake */ 1981 #define ILK_DPFC_CB_BASE 0x43200 1982 #define ILK_DPFC_CONTROL 0x43208 1983 #define FBC_CTL_FALSE_COLOR (1<<10) 1984 /* The bit 28-8 is reserved */ 1985 #define DPFC_RESERVED (0x1FFFFF00) 1986 #define ILK_DPFC_RECOMP_CTL 0x4320c 1987 #define ILK_DPFC_STATUS 0x43210 1988 #define ILK_DPFC_FENCE_YOFF 0x43218 1989 #define ILK_DPFC_CHICKEN 0x43224 1990 #define ILK_FBC_RT_BASE 0x2128 1991 #define ILK_FBC_RT_VALID (1<<0) 1992 #define SNB_FBC_FRONT_BUFFER (1<<1) 1993 1994 #define ILK_DISPLAY_CHICKEN1 0x42000 1995 #define ILK_FBCQ_DIS (1<<22) 1996 #define ILK_PABSTRETCH_DIS (1<<21) 1997 1998 1999 /* 2000 * Framebuffer compression for Sandybridge 2001 * 2002 * The following two registers are of type GTTMMADR 2003 */ 2004 #define SNB_DPFC_CTL_SA 0x100100 2005 #define SNB_CPU_FENCE_ENABLE (1<<29) 2006 #define DPFC_CPU_FENCE_OFFSET 0x100104 2007 2008 /* Framebuffer compression for Ivybridge */ 2009 #define IVB_FBC_RT_BASE 0x7020 2010 2011 #define IPS_CTL 0x43408 2012 #define IPS_ENABLE (1 << 31) 2013 2014 #define MSG_FBC_REND_STATE 0x50380 2015 #define FBC_REND_NUKE (1<<2) 2016 #define FBC_REND_CACHE_CLEAN (1<<1) 2017 2018 /* 2019 * GPIO regs 2020 */ 2021 #define GPIOA 0x5010 2022 #define GPIOB 0x5014 2023 #define GPIOC 0x5018 2024 #define GPIOD 0x501c 2025 #define GPIOE 0x5020 2026 #define GPIOF 0x5024 2027 #define GPIOG 0x5028 2028 #define GPIOH 0x502c 2029 # define GPIO_CLOCK_DIR_MASK (1 << 0) 2030 # define GPIO_CLOCK_DIR_IN (0 << 1) 2031 # define GPIO_CLOCK_DIR_OUT (1 << 1) 2032 # define GPIO_CLOCK_VAL_MASK (1 << 2) 2033 # define GPIO_CLOCK_VAL_OUT (1 << 3) 2034 # define GPIO_CLOCK_VAL_IN (1 << 4) 2035 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 2036 # define GPIO_DATA_DIR_MASK (1 << 8) 2037 # define GPIO_DATA_DIR_IN (0 << 9) 2038 # define GPIO_DATA_DIR_OUT (1 << 9) 2039 # define GPIO_DATA_VAL_MASK (1 << 10) 2040 # define GPIO_DATA_VAL_OUT (1 << 11) 2041 # define GPIO_DATA_VAL_IN (1 << 12) 2042 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 2043 2044 #define GMBUS0 0x5100 /* clock/port select */ 2045 #define GMBUS_RATE_100KHZ (0<<8) 2046 #define GMBUS_RATE_50KHZ (1<<8) 2047 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 2048 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 2049 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 2050 #define GMBUS_PIN_DISABLED 0 2051 #define GMBUS_PIN_SSC 1 2052 #define GMBUS_PIN_VGADDC 2 2053 #define GMBUS_PIN_PANEL 3 2054 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ 2055 #define GMBUS_PIN_DPC 4 /* HDMIC */ 2056 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ 2057 #define GMBUS_PIN_DPD 6 /* HDMID */ 2058 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ 2059 #define GMBUS_PIN_1_BXT 1 2060 #define GMBUS_PIN_2_BXT 2 2061 #define GMBUS_PIN_3_BXT 3 2062 #define GMBUS_NUM_PINS 7 /* including 0 */ 2063 #define GMBUS1 0x5104 /* command/status */ 2064 #define GMBUS_SW_CLR_INT (1<<31) 2065 #define GMBUS_SW_RDY (1<<30) 2066 #define GMBUS_ENT (1<<29) /* enable timeout */ 2067 #define GMBUS_CYCLE_NONE (0<<25) 2068 #define GMBUS_CYCLE_WAIT (1<<25) 2069 #define GMBUS_CYCLE_INDEX (2<<25) 2070 #define GMBUS_CYCLE_STOP (4<<25) 2071 #define GMBUS_BYTE_COUNT_SHIFT 16 2072 #define GMBUS_BYTE_COUNT_MAX 256U 2073 #define GMBUS_SLAVE_INDEX_SHIFT 8 2074 #define GMBUS_SLAVE_ADDR_SHIFT 1 2075 #define GMBUS_SLAVE_READ (1<<0) 2076 #define GMBUS_SLAVE_WRITE (0<<0) 2077 #define GMBUS2 0x5108 /* status */ 2078 #define GMBUS_INUSE (1<<15) 2079 #define GMBUS_HW_WAIT_PHASE (1<<14) 2080 #define GMBUS_STALL_TIMEOUT (1<<13) 2081 #define GMBUS_INT (1<<12) 2082 #define GMBUS_HW_RDY (1<<11) 2083 #define GMBUS_SATOER (1<<10) 2084 #define GMBUS_ACTIVE (1<<9) 2085 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 2086 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 2087 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 2088 #define GMBUS_NAK_EN (1<<3) 2089 #define GMBUS_IDLE_EN (1<<2) 2090 #define GMBUS_HW_WAIT_EN (1<<1) 2091 #define GMBUS_HW_RDY_EN (1<<0) 2092 #define GMBUS5 0x5120 /* byte index */ 2093 #define GMBUS_2BYTE_INDEX_EN (1<<31) 2094 2095 /* 2096 * Clock control & power management 2097 */ 2098 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) 2099 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) 2100 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) 2101 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 2102 2103 #define VGA0 0x6000 2104 #define VGA1 0x6004 2105 #define VGA_PD 0x6010 2106 #define VGA0_PD_P2_DIV_4 (1 << 7) 2107 #define VGA0_PD_P1_DIV_2 (1 << 5) 2108 #define VGA0_PD_P1_SHIFT 0 2109 #define VGA0_PD_P1_MASK (0x1f << 0) 2110 #define VGA1_PD_P2_DIV_4 (1 << 15) 2111 #define VGA1_PD_P1_DIV_2 (1 << 13) 2112 #define VGA1_PD_P1_SHIFT 8 2113 #define VGA1_PD_P1_MASK (0x1f << 8) 2114 #define DPLL_VCO_ENABLE (1 << 31) 2115 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 2116 #define DPLL_DVO_2X_MODE (1 << 30) 2117 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 2118 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 2119 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) 2120 #define DPLL_VGA_MODE_DIS (1 << 28) 2121 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 2122 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 2123 #define DPLL_MODE_MASK (3 << 26) 2124 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 2125 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 2126 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 2127 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 2128 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 2129 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 2130 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 2131 #define DPLL_LOCK_VLV (1<<15) 2132 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) 2133 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) 2134 #define DPLL_SSC_REF_CLOCK_CHV (1<<13) 2135 #define DPLL_PORTC_READY_MASK (0xf << 4) 2136 #define DPLL_PORTB_READY_MASK (0xf) 2137 2138 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 2139 2140 /* Additional CHV pll/phy registers */ 2141 #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) 2142 #define DPLL_PORTD_READY_MASK (0xf) 2143 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) 2144 #define PHY_LDO_DELAY_0NS 0x0 2145 #define PHY_LDO_DELAY_200NS 0x1 2146 #define PHY_LDO_DELAY_600NS 0x2 2147 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23)) 2148 #define PHY_CH_SU_PSR 0x1 2149 #define PHY_CH_DEEP_PSR 0x7 2150 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) 2151 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 2152 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) 2153 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) 2154 2155 /* 2156 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 2157 * this field (only one bit may be set). 2158 */ 2159 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 2160 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 2161 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 2162 /* i830, required in DVO non-gang */ 2163 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 2164 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 2165 #define PLL_REF_INPUT_DREFCLK (0 << 13) 2166 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 2167 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 2168 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 2169 #define PLL_REF_INPUT_MASK (3 << 13) 2170 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 2171 /* Ironlake */ 2172 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 2173 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 2174 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 2175 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 2176 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 2177 2178 /* 2179 * Parallel to Serial Load Pulse phase selection. 2180 * Selects the phase for the 10X DPLL clock for the PCIe 2181 * digital display port. The range is 4 to 13; 10 or more 2182 * is just a flip delay. The default is 6 2183 */ 2184 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 2185 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 2186 /* 2187 * SDVO multiplier for 945G/GM. Not used on 965. 2188 */ 2189 #define SDVO_MULTIPLIER_MASK 0x000000ff 2190 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 2191 #define SDVO_MULTIPLIER_SHIFT_VGA 0 2192 2193 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) 2194 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) 2195 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) 2196 #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 2197 2198 /* 2199 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 2200 * 2201 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 2202 */ 2203 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 2204 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 2205 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 2206 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 2207 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 2208 /* 2209 * SDVO/UDI pixel multiplier. 2210 * 2211 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 2212 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 2213 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 2214 * dummy bytes in the datastream at an increased clock rate, with both sides of 2215 * the link knowing how many bytes are fill. 2216 * 2217 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 2218 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 2219 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 2220 * through an SDVO command. 2221 * 2222 * This register field has values of multiplication factor minus 1, with 2223 * a maximum multiplier of 5 for SDVO. 2224 */ 2225 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 2226 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 2227 /* 2228 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 2229 * This best be set to the default value (3) or the CRT won't work. No, 2230 * I don't entirely understand what this does... 2231 */ 2232 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 2233 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 2234 2235 #define _FPA0 0x06040 2236 #define _FPA1 0x06044 2237 #define _FPB0 0x06048 2238 #define _FPB1 0x0604c 2239 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 2240 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 2241 #define FP_N_DIV_MASK 0x003f0000 2242 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 2243 #define FP_N_DIV_SHIFT 16 2244 #define FP_M1_DIV_MASK 0x00003f00 2245 #define FP_M1_DIV_SHIFT 8 2246 #define FP_M2_DIV_MASK 0x0000003f 2247 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 2248 #define FP_M2_DIV_SHIFT 0 2249 #define DPLL_TEST 0x606c 2250 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 2251 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 2252 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 2253 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 2254 #define DPLLB_TEST_N_BYPASS (1 << 19) 2255 #define DPLLB_TEST_M_BYPASS (1 << 18) 2256 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 2257 #define DPLLA_TEST_N_BYPASS (1 << 3) 2258 #define DPLLA_TEST_M_BYPASS (1 << 2) 2259 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 2260 #define D_STATE 0x6104 2261 #define DSTATE_GFX_RESET_I830 (1<<6) 2262 #define DSTATE_PLL_D3_OFF (1<<3) 2263 #define DSTATE_GFX_CLOCK_GATING (1<<1) 2264 #define DSTATE_DOT_CLOCK_GATING (1<<0) 2265 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) 2266 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 2267 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 2268 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 2269 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 2270 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 2271 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 2272 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 2273 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 2274 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 2275 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 2276 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 2277 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 2278 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 2279 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 2280 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 2281 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 2282 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 2283 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 2284 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 2285 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 2286 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 2287 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 2288 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 2289 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 2290 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 2291 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 2292 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 2293 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 2294 /* 2295 * This bit must be set on the 830 to prevent hangs when turning off the 2296 * overlay scaler. 2297 */ 2298 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 2299 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 2300 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 2301 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 2302 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 2303 2304 #define RENCLK_GATE_D1 0x6204 2305 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 2306 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 2307 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 2308 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 2309 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 2310 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 2311 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 2312 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 2313 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 2314 /* This bit must be unset on 855,865 */ 2315 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 2316 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 2317 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 2318 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 2319 /* This bit must be set on 855,865. */ 2320 # define SV_CLOCK_GATE_DISABLE (1 << 0) 2321 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 2322 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 2323 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 2324 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 2325 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 2326 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 2327 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 2328 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 2329 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 2330 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 2331 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 2332 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 2333 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 2334 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 2335 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 2336 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 2337 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 2338 2339 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 2340 /* This bit must always be set on 965G/965GM */ 2341 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 2342 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 2343 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 2344 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 2345 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 2346 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 2347 /* This bit must always be set on 965G */ 2348 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 2349 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 2350 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 2351 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 2352 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 2353 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 2354 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 2355 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 2356 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 2357 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 2358 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 2359 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 2360 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 2361 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 2362 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 2363 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 2364 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 2365 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 2366 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 2367 2368 #define RENCLK_GATE_D2 0x6208 2369 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 2370 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 2371 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 2372 2373 #define VDECCLK_GATE_D 0x620C /* g4x only */ 2374 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 2375 2376 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 2377 #define DEUC 0x6214 /* CRL only */ 2378 2379 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) 2380 #define FW_CSPWRDWNEN (1<<15) 2381 2382 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) 2383 2384 #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) 2385 #define CDCLK_FREQ_SHIFT 4 2386 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 2387 #define CZCLK_FREQ_MASK 0xf 2388 2389 #define GCI_CONTROL (VLV_DISPLAY_BASE + 0x650C) 2390 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 2391 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 2392 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 2393 #define PFI_CREDIT_RESEND (1 << 27) 2394 #define VGA_FAST_MODE_DISABLE (1 << 14) 2395 2396 #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) 2397 2398 /* 2399 * Palette regs 2400 */ 2401 #define PALETTE_A_OFFSET 0xa000 2402 #define PALETTE_B_OFFSET 0xa800 2403 #define CHV_PALETTE_C_OFFSET 0xc000 2404 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ 2405 dev_priv->info.display_mmio_offset) 2406 2407 /* MCH MMIO space */ 2408 2409 /* 2410 * MCHBAR mirror. 2411 * 2412 * This mirrors the MCHBAR MMIO space whose location is determined by 2413 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 2414 * every way. It is not accessible from the CP register read instructions. 2415 * 2416 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 2417 * just read. 2418 */ 2419 #define MCHBAR_MIRROR_BASE 0x10000 2420 2421 #define MCHBAR_MIRROR_BASE_SNB 0x140000 2422 2423 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 2424 #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) 2425 2426 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 2427 #define DCC 0x10200 2428 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 2429 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 2430 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 2431 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 2432 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 2433 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 2434 #define DCC2 0x10204 2435 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 2436 2437 /* Pineview MCH register contains DDR3 setting */ 2438 #define CSHRDDR3CTL 0x101a8 2439 #define CSHRDDR3CTL_DDR3 (1 << 2) 2440 2441 /* 965 MCH register controlling DRAM channel configuration */ 2442 #define C0DRB3 0x10206 2443 #define C1DRB3 0x10606 2444 2445 /* snb MCH registers for reading the DRAM channel configuration */ 2446 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) 2447 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) 2448 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) 2449 #define MAD_DIMM_ECC_MASK (0x3 << 24) 2450 #define MAD_DIMM_ECC_OFF (0x0 << 24) 2451 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 2452 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 2453 #define MAD_DIMM_ECC_ON (0x3 << 24) 2454 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 2455 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 2456 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 2457 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 2458 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 2459 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 2460 #define MAD_DIMM_A_SELECT (0x1 << 16) 2461 /* DIMM sizes are in multiples of 256mb. */ 2462 #define MAD_DIMM_B_SIZE_SHIFT 8 2463 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 2464 #define MAD_DIMM_A_SIZE_SHIFT 0 2465 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 2466 2467 /* snb MCH registers for priority tuning */ 2468 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) 2469 #define MCH_SSKPD_WM0_MASK 0x3f 2470 #define MCH_SSKPD_WM0_VAL 0xc 2471 2472 #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c) 2473 2474 /* Clocking configuration register */ 2475 #define CLKCFG 0x10c00 2476 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 2477 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 2478 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 2479 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 2480 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 2481 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 2482 /* Note, below two are guess */ 2483 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 2484 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 2485 #define CLKCFG_FSB_MASK (7 << 0) 2486 #define CLKCFG_MEM_533 (1 << 4) 2487 #define CLKCFG_MEM_667 (2 << 4) 2488 #define CLKCFG_MEM_800 (3 << 4) 2489 #define CLKCFG_MEM_MASK (7 << 4) 2490 2491 #define TSC1 0x11001 2492 #define TSE (1<<0) 2493 #define TR1 0x11006 2494 #define TSFS 0x11020 2495 #define TSFS_SLOPE_MASK 0x0000ff00 2496 #define TSFS_SLOPE_SHIFT 8 2497 #define TSFS_INTR_MASK 0x000000ff 2498 2499 #define CRSTANDVID 0x11100 2500 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 2501 #define PXVFREQ_PX_MASK 0x7f000000 2502 #define PXVFREQ_PX_SHIFT 24 2503 #define VIDFREQ_BASE 0x11110 2504 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 2505 #define VIDFREQ2 0x11114 2506 #define VIDFREQ3 0x11118 2507 #define VIDFREQ4 0x1111c 2508 #define VIDFREQ_P0_MASK 0x1f000000 2509 #define VIDFREQ_P0_SHIFT 24 2510 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 2511 #define VIDFREQ_P0_CSCLK_SHIFT 20 2512 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 2513 #define VIDFREQ_P0_CRCLK_SHIFT 16 2514 #define VIDFREQ_P1_MASK 0x00001f00 2515 #define VIDFREQ_P1_SHIFT 8 2516 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 2517 #define VIDFREQ_P1_CSCLK_SHIFT 4 2518 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 2519 #define INTTOEXT_BASE_ILK 0x11300 2520 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 2521 #define INTTOEXT_MAP3_SHIFT 24 2522 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 2523 #define INTTOEXT_MAP2_SHIFT 16 2524 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 2525 #define INTTOEXT_MAP1_SHIFT 8 2526 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 2527 #define INTTOEXT_MAP0_SHIFT 0 2528 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 2529 #define MEMSWCTL 0x11170 /* Ironlake only */ 2530 #define MEMCTL_CMD_MASK 0xe000 2531 #define MEMCTL_CMD_SHIFT 13 2532 #define MEMCTL_CMD_RCLK_OFF 0 2533 #define MEMCTL_CMD_RCLK_ON 1 2534 #define MEMCTL_CMD_CHFREQ 2 2535 #define MEMCTL_CMD_CHVID 3 2536 #define MEMCTL_CMD_VMMOFF 4 2537 #define MEMCTL_CMD_VMMON 5 2538 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 2539 when command complete */ 2540 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 2541 #define MEMCTL_FREQ_SHIFT 8 2542 #define MEMCTL_SFCAVM (1<<7) 2543 #define MEMCTL_TGT_VID_MASK 0x007f 2544 #define MEMIHYST 0x1117c 2545 #define MEMINTREN 0x11180 /* 16 bits */ 2546 #define MEMINT_RSEXIT_EN (1<<8) 2547 #define MEMINT_CX_SUPR_EN (1<<7) 2548 #define MEMINT_CONT_BUSY_EN (1<<6) 2549 #define MEMINT_AVG_BUSY_EN (1<<5) 2550 #define MEMINT_EVAL_CHG_EN (1<<4) 2551 #define MEMINT_MON_IDLE_EN (1<<3) 2552 #define MEMINT_UP_EVAL_EN (1<<2) 2553 #define MEMINT_DOWN_EVAL_EN (1<<1) 2554 #define MEMINT_SW_CMD_EN (1<<0) 2555 #define MEMINTRSTR 0x11182 /* 16 bits */ 2556 #define MEM_RSEXIT_MASK 0xc000 2557 #define MEM_RSEXIT_SHIFT 14 2558 #define MEM_CONT_BUSY_MASK 0x3000 2559 #define MEM_CONT_BUSY_SHIFT 12 2560 #define MEM_AVG_BUSY_MASK 0x0c00 2561 #define MEM_AVG_BUSY_SHIFT 10 2562 #define MEM_EVAL_CHG_MASK 0x0300 2563 #define MEM_EVAL_BUSY_SHIFT 8 2564 #define MEM_MON_IDLE_MASK 0x00c0 2565 #define MEM_MON_IDLE_SHIFT 6 2566 #define MEM_UP_EVAL_MASK 0x0030 2567 #define MEM_UP_EVAL_SHIFT 4 2568 #define MEM_DOWN_EVAL_MASK 0x000c 2569 #define MEM_DOWN_EVAL_SHIFT 2 2570 #define MEM_SW_CMD_MASK 0x0003 2571 #define MEM_INT_STEER_GFX 0 2572 #define MEM_INT_STEER_CMR 1 2573 #define MEM_INT_STEER_SMI 2 2574 #define MEM_INT_STEER_SCI 3 2575 #define MEMINTRSTS 0x11184 2576 #define MEMINT_RSEXIT (1<<7) 2577 #define MEMINT_CONT_BUSY (1<<6) 2578 #define MEMINT_AVG_BUSY (1<<5) 2579 #define MEMINT_EVAL_CHG (1<<4) 2580 #define MEMINT_MON_IDLE (1<<3) 2581 #define MEMINT_UP_EVAL (1<<2) 2582 #define MEMINT_DOWN_EVAL (1<<1) 2583 #define MEMINT_SW_CMD (1<<0) 2584 #define MEMMODECTL 0x11190 2585 #define MEMMODE_BOOST_EN (1<<31) 2586 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 2587 #define MEMMODE_BOOST_FREQ_SHIFT 24 2588 #define MEMMODE_IDLE_MODE_MASK 0x00030000 2589 #define MEMMODE_IDLE_MODE_SHIFT 16 2590 #define MEMMODE_IDLE_MODE_EVAL 0 2591 #define MEMMODE_IDLE_MODE_CONT 1 2592 #define MEMMODE_HWIDLE_EN (1<<15) 2593 #define MEMMODE_SWMODE_EN (1<<14) 2594 #define MEMMODE_RCLK_GATE (1<<13) 2595 #define MEMMODE_HW_UPDATE (1<<12) 2596 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 2597 #define MEMMODE_FSTART_SHIFT 8 2598 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 2599 #define MEMMODE_FMAX_SHIFT 4 2600 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 2601 #define RCBMAXAVG 0x1119c 2602 #define MEMSWCTL2 0x1119e /* Cantiga only */ 2603 #define SWMEMCMD_RENDER_OFF (0 << 13) 2604 #define SWMEMCMD_RENDER_ON (1 << 13) 2605 #define SWMEMCMD_SWFREQ (2 << 13) 2606 #define SWMEMCMD_TARVID (3 << 13) 2607 #define SWMEMCMD_VRM_OFF (4 << 13) 2608 #define SWMEMCMD_VRM_ON (5 << 13) 2609 #define CMDSTS (1<<12) 2610 #define SFCAVM (1<<11) 2611 #define SWFREQ_MASK 0x0380 /* P0-7 */ 2612 #define SWFREQ_SHIFT 7 2613 #define TARVID_MASK 0x001f 2614 #define MEMSTAT_CTG 0x111a0 2615 #define RCBMINAVG 0x111a0 2616 #define RCUPEI 0x111b0 2617 #define RCDNEI 0x111b4 2618 #define RSTDBYCTL 0x111b8 2619 #define RS1EN (1<<31) 2620 #define RS2EN (1<<30) 2621 #define RS3EN (1<<29) 2622 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 2623 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 2624 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 2625 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 2626 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 2627 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 2628 #define RSX_STATUS_MASK (7<<20) 2629 #define RSX_STATUS_ON (0<<20) 2630 #define RSX_STATUS_RC1 (1<<20) 2631 #define RSX_STATUS_RC1E (2<<20) 2632 #define RSX_STATUS_RS1 (3<<20) 2633 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 2634 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 2635 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 2636 #define RSX_STATUS_RSVD2 (7<<20) 2637 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 2638 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 2639 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 2640 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 2641 #define RS1CONTSAV_MASK (3<<14) 2642 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 2643 #define RS1CONTSAV_RSVD (1<<14) 2644 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 2645 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 2646 #define NORMSLEXLAT_MASK (3<<12) 2647 #define SLOW_RS123 (0<<12) 2648 #define SLOW_RS23 (1<<12) 2649 #define SLOW_RS3 (2<<12) 2650 #define NORMAL_RS123 (3<<12) 2651 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 2652 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 2653 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 2654 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 2655 #define RS_CSTATE_MASK (3<<4) 2656 #define RS_CSTATE_C367_RS1 (0<<4) 2657 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 2658 #define RS_CSTATE_RSVD (2<<4) 2659 #define RS_CSTATE_C367_RS2 (3<<4) 2660 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 2661 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 2662 #define VIDCTL 0x111c0 2663 #define VIDSTS 0x111c8 2664 #define VIDSTART 0x111cc /* 8 bits */ 2665 #define MEMSTAT_ILK 0x111f8 2666 #define MEMSTAT_VID_MASK 0x7f00 2667 #define MEMSTAT_VID_SHIFT 8 2668 #define MEMSTAT_PSTATE_MASK 0x00f8 2669 #define MEMSTAT_PSTATE_SHIFT 3 2670 #define MEMSTAT_MON_ACTV (1<<2) 2671 #define MEMSTAT_SRC_CTL_MASK 0x0003 2672 #define MEMSTAT_SRC_CTL_CORE 0 2673 #define MEMSTAT_SRC_CTL_TRB 1 2674 #define MEMSTAT_SRC_CTL_THM 2 2675 #define MEMSTAT_SRC_CTL_STDBY 3 2676 #define RCPREVBSYTUPAVG 0x113b8 2677 #define RCPREVBSYTDNAVG 0x113bc 2678 #define PMMISC 0x11214 2679 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 2680 #define SDEW 0x1124c 2681 #define CSIEW0 0x11250 2682 #define CSIEW1 0x11254 2683 #define CSIEW2 0x11258 2684 #define PEW 0x1125c 2685 #define DEW 0x11270 2686 #define MCHAFE 0x112c0 2687 #define CSIEC 0x112e0 2688 #define DMIEC 0x112e4 2689 #define DDREC 0x112e8 2690 #define PEG0EC 0x112ec 2691 #define PEG1EC 0x112f0 2692 #define GFXEC 0x112f4 2693 #define RPPREVBSYTUPAVG 0x113b8 2694 #define RPPREVBSYTDNAVG 0x113bc 2695 #define ECR 0x11600 2696 #define ECR_GPFE (1<<31) 2697 #define ECR_IMONE (1<<30) 2698 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 2699 #define OGW0 0x11608 2700 #define OGW1 0x1160c 2701 #define EG0 0x11610 2702 #define EG1 0x11614 2703 #define EG2 0x11618 2704 #define EG3 0x1161c 2705 #define EG4 0x11620 2706 #define EG5 0x11624 2707 #define EG6 0x11628 2708 #define EG7 0x1162c 2709 #define PXW 0x11664 2710 #define PXWL 0x11680 2711 #define LCFUSE02 0x116c0 2712 #define LCFUSE_HIV_MASK 0x000000ff 2713 #define CSIPLL0 0x12c10 2714 #define DDRMPLL1 0X12c20 2715 #define PEG_BAND_GAP_DATA 0x14d68 2716 2717 #define GEN6_GT_THREAD_STATUS_REG 0x13805c 2718 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 2719 2720 #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) 2721 #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) 2722 #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) 2723 2724 #define INTERVAL_1_28_US(us) (((us) * 100) >> 7) 2725 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) 2726 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ 2727 INTERVAL_1_33_US(us) : \ 2728 INTERVAL_1_28_US(us)) 2729 2730 /* 2731 * Logical Context regs 2732 */ 2733 #define CCID 0x2180 2734 #define CCID_EN (1<<0) 2735 /* 2736 * Notes on SNB/IVB/VLV context size: 2737 * - Power context is saved elsewhere (LLC or stolen) 2738 * - Ring/execlist context is saved on SNB, not on IVB 2739 * - Extended context size already includes render context size 2740 * - We always need to follow the extended context size. 2741 * SNB BSpec has comments indicating that we should use the 2742 * render context size instead if execlists are disabled, but 2743 * based on empirical testing that's just nonsense. 2744 * - Pipelined/VF state is saved on SNB/IVB respectively 2745 * - GT1 size just indicates how much of render context 2746 * doesn't need saving on GT1 2747 */ 2748 #define CXT_SIZE 0x21a0 2749 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) 2750 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) 2751 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) 2752 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) 2753 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) 2754 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 2755 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 2756 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 2757 #define GEN7_CXT_SIZE 0x21a8 2758 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) 2759 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) 2760 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) 2761 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) 2762 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) 2763 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) 2764 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 2765 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 2766 /* Haswell does have the CXT_SIZE register however it does not appear to be 2767 * valid. Now, docs explain in dwords what is in the context object. The full 2768 * size is 70720 bytes, however, the power context and execlist context will 2769 * never be saved (power context is stored elsewhere, and execlists don't work 2770 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. 2771 */ 2772 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 2773 /* Same as Haswell, but 72064 bytes now. */ 2774 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) 2775 2776 #define CHV_CLK_CTL1 0x101100 2777 #define VLV_CLK_CTL2 0x101104 2778 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 2779 2780 /* 2781 * Overlay regs 2782 */ 2783 2784 #define OVADD 0x30000 2785 #define DOVSTA 0x30008 2786 #define OC_BUF (0x3<<20) 2787 #define OGAMC5 0x30010 2788 #define OGAMC4 0x30014 2789 #define OGAMC3 0x30018 2790 #define OGAMC2 0x3001c 2791 #define OGAMC1 0x30020 2792 #define OGAMC0 0x30024 2793 2794 /* 2795 * Display engine regs 2796 */ 2797 2798 /* Pipe A CRC regs */ 2799 #define _PIPE_CRC_CTL_A 0x60050 2800 #define PIPE_CRC_ENABLE (1 << 31) 2801 /* ivb+ source selection */ 2802 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 2803 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 2804 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 2805 /* ilk+ source selection */ 2806 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 2807 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 2808 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 2809 /* embedded DP port on the north display block, reserved on ivb */ 2810 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 2811 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 2812 /* vlv source selection */ 2813 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 2814 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 2815 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 2816 /* with DP port the pipe source is invalid */ 2817 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 2818 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 2819 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 2820 /* gen3+ source selection */ 2821 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 2822 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 2823 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 2824 /* with DP/TV port the pipe source is invalid */ 2825 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 2826 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 2827 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 2828 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 2829 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 2830 /* gen2 doesn't have source selection bits */ 2831 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 2832 2833 #define _PIPE_CRC_RES_1_A_IVB 0x60064 2834 #define _PIPE_CRC_RES_2_A_IVB 0x60068 2835 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 2836 #define _PIPE_CRC_RES_4_A_IVB 0x60070 2837 #define _PIPE_CRC_RES_5_A_IVB 0x60074 2838 2839 #define _PIPE_CRC_RES_RED_A 0x60060 2840 #define _PIPE_CRC_RES_GREEN_A 0x60064 2841 #define _PIPE_CRC_RES_BLUE_A 0x60068 2842 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 2843 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 2844 2845 /* Pipe B CRC regs */ 2846 #define _PIPE_CRC_RES_1_B_IVB 0x61064 2847 #define _PIPE_CRC_RES_2_B_IVB 0x61068 2848 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 2849 #define _PIPE_CRC_RES_4_B_IVB 0x61070 2850 #define _PIPE_CRC_RES_5_B_IVB 0x61074 2851 2852 #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A) 2853 #define PIPE_CRC_RES_1_IVB(pipe) \ 2854 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB) 2855 #define PIPE_CRC_RES_2_IVB(pipe) \ 2856 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB) 2857 #define PIPE_CRC_RES_3_IVB(pipe) \ 2858 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB) 2859 #define PIPE_CRC_RES_4_IVB(pipe) \ 2860 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB) 2861 #define PIPE_CRC_RES_5_IVB(pipe) \ 2862 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB) 2863 2864 #define PIPE_CRC_RES_RED(pipe) \ 2865 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A) 2866 #define PIPE_CRC_RES_GREEN(pipe) \ 2867 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A) 2868 #define PIPE_CRC_RES_BLUE(pipe) \ 2869 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A) 2870 #define PIPE_CRC_RES_RES1_I915(pipe) \ 2871 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915) 2872 #define PIPE_CRC_RES_RES2_G4X(pipe) \ 2873 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 2874 2875 /* Pipe A timing regs */ 2876 #define _HTOTAL_A 0x60000 2877 #define _HBLANK_A 0x60004 2878 #define _HSYNC_A 0x60008 2879 #define _VTOTAL_A 0x6000c 2880 #define _VBLANK_A 0x60010 2881 #define _VSYNC_A 0x60014 2882 #define _PIPEASRC 0x6001c 2883 #define _BCLRPAT_A 0x60020 2884 #define _VSYNCSHIFT_A 0x60028 2885 #define _PIPE_MULT_A 0x6002c 2886 2887 /* Pipe B timing regs */ 2888 #define _HTOTAL_B 0x61000 2889 #define _HBLANK_B 0x61004 2890 #define _HSYNC_B 0x61008 2891 #define _VTOTAL_B 0x6100c 2892 #define _VBLANK_B 0x61010 2893 #define _VSYNC_B 0x61014 2894 #define _PIPEBSRC 0x6101c 2895 #define _BCLRPAT_B 0x61020 2896 #define _VSYNCSHIFT_B 0x61028 2897 #define _PIPE_MULT_B 0x6102c 2898 2899 #define TRANSCODER_A_OFFSET 0x60000 2900 #define TRANSCODER_B_OFFSET 0x61000 2901 #define TRANSCODER_C_OFFSET 0x62000 2902 #define CHV_TRANSCODER_C_OFFSET 0x63000 2903 #define TRANSCODER_EDP_OFFSET 0x6f000 2904 2905 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ 2906 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ 2907 dev_priv->info.display_mmio_offset) 2908 2909 #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) 2910 #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) 2911 #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) 2912 #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) 2913 #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) 2914 #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) 2915 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) 2916 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) 2917 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) 2918 #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) 2919 2920 /* VLV eDP PSR registers */ 2921 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) 2922 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) 2923 #define VLV_EDP_PSR_ENABLE (1<<0) 2924 #define VLV_EDP_PSR_RESET (1<<1) 2925 #define VLV_EDP_PSR_MODE_MASK (7<<2) 2926 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) 2927 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) 2928 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) 2929 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) 2930 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) 2931 #define VLV_EDP_PSR_DBL_FRAME (1<<10) 2932 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) 2933 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 2934 #define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB) 2935 2936 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) 2937 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) 2938 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) 2939 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) 2940 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) 2941 #define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB) 2942 2943 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) 2944 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) 2945 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) 2946 #define VLV_EDP_PSR_CURR_STATE_MASK 7 2947 #define VLV_EDP_PSR_DISABLED (0<<0) 2948 #define VLV_EDP_PSR_INACTIVE (1<<0) 2949 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) 2950 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) 2951 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) 2952 #define VLV_EDP_PSR_EXIT (5<<0) 2953 #define VLV_EDP_PSR_IN_TRANS (1<<7) 2954 #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB) 2955 2956 /* HSW+ eDP PSR registers */ 2957 #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) 2958 #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) 2959 #define EDP_PSR_ENABLE (1<<31) 2960 #define BDW_PSR_SINGLE_FRAME (1<<30) 2961 #define EDP_PSR_LINK_STANDBY (1<<27) 2962 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) 2963 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) 2964 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) 2965 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) 2966 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) 2967 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2968 #define EDP_PSR_SKIP_AUX_EXIT (1<<12) 2969 #define EDP_PSR_TP1_TP2_SEL (0<<11) 2970 #define EDP_PSR_TP1_TP3_SEL (1<<11) 2971 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) 2972 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) 2973 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) 2974 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) 2975 #define EDP_PSR_TP1_TIME_500us (0<<4) 2976 #define EDP_PSR_TP1_TIME_100us (1<<4) 2977 #define EDP_PSR_TP1_TIME_2500us (2<<4) 2978 #define EDP_PSR_TP1_TIME_0us (3<<4) 2979 #define EDP_PSR_IDLE_FRAME_SHIFT 0 2980 2981 #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) 2982 #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) 2983 #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) 2984 #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) 2985 #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) 2986 #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) 2987 2988 #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40) 2989 #define EDP_PSR_STATUS_STATE_MASK (7<<29) 2990 #define EDP_PSR_STATUS_STATE_IDLE (0<<29) 2991 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) 2992 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) 2993 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) 2994 #define EDP_PSR_STATUS_STATE_BUFON (4<<29) 2995 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) 2996 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) 2997 #define EDP_PSR_STATUS_LINK_MASK (3<<26) 2998 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) 2999 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) 3000 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) 3001 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 3002 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 3003 #define EDP_PSR_STATUS_COUNT_SHIFT 16 3004 #define EDP_PSR_STATUS_COUNT_MASK 0xf 3005 #define EDP_PSR_STATUS_AUX_ERROR (1<<15) 3006 #define EDP_PSR_STATUS_AUX_SENDING (1<<12) 3007 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) 3008 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) 3009 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) 3010 #define EDP_PSR_STATUS_IDLE_MASK 0xf 3011 3012 #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44) 3013 #define EDP_PSR_PERF_CNT_MASK 0xffffff 3014 3015 #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) 3016 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) 3017 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) 3018 #define EDP_PSR_DEBUG_MASK_HPD (1<<25) 3019 3020 #define EDP_PSR2_CTL 0x6f900 3021 #define EDP_PSR2_ENABLE (1<<31) 3022 #define EDP_SU_TRACK_ENABLE (1<<30) 3023 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) 3024 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) 3025 #define EDP_PSR2_TP2_TIME_500 (0<<8) 3026 #define EDP_PSR2_TP2_TIME_100 (1<<8) 3027 #define EDP_PSR2_TP2_TIME_2500 (2<<8) 3028 #define EDP_PSR2_TP2_TIME_50 (3<<8) 3029 #define EDP_PSR2_TP2_TIME_MASK (3<<8) 3030 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 3031 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) 3032 #define EDP_PSR2_IDLE_MASK 0xf 3033 3034 /* VGA port control */ 3035 #define ADPA 0x61100 3036 #define PCH_ADPA 0xe1100 3037 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) 3038 3039 #define ADPA_DAC_ENABLE (1<<31) 3040 #define ADPA_DAC_DISABLE 0 3041 #define ADPA_PIPE_SELECT_MASK (1<<30) 3042 #define ADPA_PIPE_A_SELECT 0 3043 #define ADPA_PIPE_B_SELECT (1<<30) 3044 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 3045 /* CPT uses bits 29:30 for pch transcoder select */ 3046 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3047 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3048 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3049 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3050 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3051 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3052 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3053 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3054 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3055 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3056 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3057 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3058 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3059 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3060 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3061 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3062 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3063 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3064 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3065 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 3066 #define ADPA_SETS_HVPOLARITY 0 3067 #define ADPA_VSYNC_CNTL_DISABLE (1<<10) 3068 #define ADPA_VSYNC_CNTL_ENABLE 0 3069 #define ADPA_HSYNC_CNTL_DISABLE (1<<11) 3070 #define ADPA_HSYNC_CNTL_ENABLE 0 3071 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 3072 #define ADPA_VSYNC_ACTIVE_LOW 0 3073 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 3074 #define ADPA_HSYNC_ACTIVE_LOW 0 3075 #define ADPA_DPMS_MASK (~(3<<10)) 3076 #define ADPA_DPMS_ON (0<<10) 3077 #define ADPA_DPMS_SUSPEND (1<<10) 3078 #define ADPA_DPMS_STANDBY (2<<10) 3079 #define ADPA_DPMS_OFF (3<<10) 3080 3081 3082 /* Hotplug control (945+ only) */ 3083 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110) 3084 #define PORTB_HOTPLUG_INT_EN (1 << 29) 3085 #define PORTC_HOTPLUG_INT_EN (1 << 28) 3086 #define PORTD_HOTPLUG_INT_EN (1 << 27) 3087 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 3088 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 3089 #define TV_HOTPLUG_INT_EN (1 << 18) 3090 #define CRT_HOTPLUG_INT_EN (1 << 9) 3091 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 3092 PORTC_HOTPLUG_INT_EN | \ 3093 PORTD_HOTPLUG_INT_EN | \ 3094 SDVOC_HOTPLUG_INT_EN | \ 3095 SDVOB_HOTPLUG_INT_EN | \ 3096 CRT_HOTPLUG_INT_EN) 3097 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 3098 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 3099 /* must use period 64 on GM45 according to docs */ 3100 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 3101 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 3102 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 3103 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 3104 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 3105 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 3106 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 3107 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 3108 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 3109 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 3110 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 3111 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 3112 3113 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) 3114 /* 3115 * HDMI/DP bits are gen4+ 3116 * 3117 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 3118 * Please check the detailed lore in the commit message for for experimental 3119 * evidence. 3120 */ 3121 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 3122 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 3123 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 3124 /* VLV DP/HDMI bits again match Bspec */ 3125 #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) 3126 #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) 3127 #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) 3128 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 3129 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 3130 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 3131 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 3132 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 3133 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 3134 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 3135 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 3136 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 3137 /* CRT/TV common between gen3+ */ 3138 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 3139 #define TV_HOTPLUG_INT_STATUS (1 << 10) 3140 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 3141 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 3142 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 3143 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 3144 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 3145 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 3146 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 3147 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 3148 3149 /* SDVO is different across gen3/4 */ 3150 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 3151 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 3152 /* 3153 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 3154 * since reality corrobates that they're the same as on gen3. But keep these 3155 * bits here (and the comment!) to help any other lost wanderers back onto the 3156 * right tracks. 3157 */ 3158 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 3159 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 3160 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 3161 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 3162 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 3163 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 3164 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 3165 PORTB_HOTPLUG_INT_STATUS | \ 3166 PORTC_HOTPLUG_INT_STATUS | \ 3167 PORTD_HOTPLUG_INT_STATUS) 3168 3169 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 3170 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 3171 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 3172 PORTB_HOTPLUG_INT_STATUS | \ 3173 PORTC_HOTPLUG_INT_STATUS | \ 3174 PORTD_HOTPLUG_INT_STATUS) 3175 3176 /* SDVO and HDMI port control. 3177 * The same register may be used for SDVO or HDMI */ 3178 #define GEN3_SDVOB 0x61140 3179 #define GEN3_SDVOC 0x61160 3180 #define GEN4_HDMIB GEN3_SDVOB 3181 #define GEN4_HDMIC GEN3_SDVOC 3182 #define CHV_HDMID 0x6116C 3183 #define PCH_SDVOB 0xe1140 3184 #define PCH_HDMIB PCH_SDVOB 3185 #define PCH_HDMIC 0xe1150 3186 #define PCH_HDMID 0xe1160 3187 3188 #define PORT_DFT_I9XX 0x61150 3189 #define DC_BALANCE_RESET (1 << 25) 3190 #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) 3191 #define DC_BALANCE_RESET_VLV (1 << 31) 3192 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 3193 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ 3194 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 3195 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 3196 3197 /* Gen 3 SDVO bits: */ 3198 #define SDVO_ENABLE (1 << 31) 3199 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 3200 #define SDVO_PIPE_SEL_MASK (1 << 30) 3201 #define SDVO_PIPE_B_SELECT (1 << 30) 3202 #define SDVO_STALL_SELECT (1 << 29) 3203 #define SDVO_INTERRUPT_ENABLE (1 << 26) 3204 /* 3205 * 915G/GM SDVO pixel multiplier. 3206 * Programmed value is multiplier - 1, up to 5x. 3207 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 3208 */ 3209 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 3210 #define SDVO_PORT_MULTIPLY_SHIFT 23 3211 #define SDVO_PHASE_SELECT_MASK (15 << 19) 3212 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 3213 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 3214 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 3215 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 3216 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 3217 #define SDVO_DETECTED (1 << 2) 3218 /* Bits to be preserved when writing */ 3219 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 3220 SDVO_INTERRUPT_ENABLE) 3221 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 3222 3223 /* Gen 4 SDVO/HDMI bits: */ 3224 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 3225 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 3226 #define SDVO_ENCODING_SDVO (0 << 10) 3227 #define SDVO_ENCODING_HDMI (2 << 10) 3228 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 3229 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 3230 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 3231 #define SDVO_AUDIO_ENABLE (1 << 6) 3232 /* VSYNC/HSYNC bits new with 965, default is to be set */ 3233 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 3234 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 3235 3236 /* Gen 5 (IBX) SDVO/HDMI bits: */ 3237 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 3238 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 3239 3240 /* Gen 6 (CPT) SDVO/HDMI bits: */ 3241 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 3242 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 3243 3244 /* CHV SDVO/HDMI bits: */ 3245 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 3246 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 3247 3248 3249 /* DVO port control */ 3250 #define DVOA 0x61120 3251 #define DVOB 0x61140 3252 #define DVOC 0x61160 3253 #define DVO_ENABLE (1 << 31) 3254 #define DVO_PIPE_B_SELECT (1 << 30) 3255 #define DVO_PIPE_STALL_UNUSED (0 << 28) 3256 #define DVO_PIPE_STALL (1 << 28) 3257 #define DVO_PIPE_STALL_TV (2 << 28) 3258 #define DVO_PIPE_STALL_MASK (3 << 28) 3259 #define DVO_USE_VGA_SYNC (1 << 15) 3260 #define DVO_DATA_ORDER_I740 (0 << 14) 3261 #define DVO_DATA_ORDER_FP (1 << 14) 3262 #define DVO_VSYNC_DISABLE (1 << 11) 3263 #define DVO_HSYNC_DISABLE (1 << 10) 3264 #define DVO_VSYNC_TRISTATE (1 << 9) 3265 #define DVO_HSYNC_TRISTATE (1 << 8) 3266 #define DVO_BORDER_ENABLE (1 << 7) 3267 #define DVO_DATA_ORDER_GBRG (1 << 6) 3268 #define DVO_DATA_ORDER_RGGB (0 << 6) 3269 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 3270 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 3271 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 3272 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 3273 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 3274 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 3275 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 3276 #define DVO_PRESERVE_MASK (0x7<<24) 3277 #define DVOA_SRCDIM 0x61124 3278 #define DVOB_SRCDIM 0x61144 3279 #define DVOC_SRCDIM 0x61164 3280 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 3281 #define DVO_SRCDIM_VERTICAL_SHIFT 0 3282 3283 /* LVDS port control */ 3284 #define LVDS 0x61180 3285 /* 3286 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 3287 * the DPLL semantics change when the LVDS is assigned to that pipe. 3288 */ 3289 #define LVDS_PORT_EN (1 << 31) 3290 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 3291 #define LVDS_PIPEB_SELECT (1 << 30) 3292 #define LVDS_PIPE_MASK (1 << 30) 3293 #define LVDS_PIPE(pipe) ((pipe) << 30) 3294 /* LVDS dithering flag on 965/g4x platform */ 3295 #define LVDS_ENABLE_DITHER (1 << 25) 3296 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 3297 #define LVDS_VSYNC_POLARITY (1 << 21) 3298 #define LVDS_HSYNC_POLARITY (1 << 20) 3299 3300 /* Enable border for unscaled (or aspect-scaled) display */ 3301 #define LVDS_BORDER_ENABLE (1 << 15) 3302 /* 3303 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 3304 * pixel. 3305 */ 3306 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 3307 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 3308 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 3309 /* 3310 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 3311 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 3312 * on. 3313 */ 3314 #define LVDS_A3_POWER_MASK (3 << 6) 3315 #define LVDS_A3_POWER_DOWN (0 << 6) 3316 #define LVDS_A3_POWER_UP (3 << 6) 3317 /* 3318 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 3319 * is set. 3320 */ 3321 #define LVDS_CLKB_POWER_MASK (3 << 4) 3322 #define LVDS_CLKB_POWER_DOWN (0 << 4) 3323 #define LVDS_CLKB_POWER_UP (3 << 4) 3324 /* 3325 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 3326 * setting for whether we are in dual-channel mode. The B3 pair will 3327 * additionally only be powered up when LVDS_A3_POWER_UP is set. 3328 */ 3329 #define LVDS_B0B3_POWER_MASK (3 << 2) 3330 #define LVDS_B0B3_POWER_DOWN (0 << 2) 3331 #define LVDS_B0B3_POWER_UP (3 << 2) 3332 3333 /* Video Data Island Packet control */ 3334 #define VIDEO_DIP_DATA 0x61178 3335 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 3336 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 3337 * of the infoframe structure specified by CEA-861. */ 3338 #define VIDEO_DIP_DATA_SIZE 32 3339 #define VIDEO_DIP_VSC_DATA_SIZE 36 3340 #define VIDEO_DIP_CTL 0x61170 3341 /* Pre HSW: */ 3342 #define VIDEO_DIP_ENABLE (1 << 31) 3343 #define VIDEO_DIP_PORT(port) ((port) << 29) 3344 #define VIDEO_DIP_PORT_MASK (3 << 29) 3345 #define VIDEO_DIP_ENABLE_GCP (1 << 25) 3346 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 3347 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 3348 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 3349 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 3350 #define VIDEO_DIP_SELECT_AVI (0 << 19) 3351 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 3352 #define VIDEO_DIP_SELECT_SPD (3 << 19) 3353 #define VIDEO_DIP_SELECT_MASK (3 << 19) 3354 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 3355 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 3356 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 3357 #define VIDEO_DIP_FREQ_MASK (3 << 16) 3358 /* HSW and later: */ 3359 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 3360 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 3361 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 3362 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 3363 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 3364 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 3365 3366 /* Panel power sequencing */ 3367 #define PP_STATUS 0x61200 3368 #define PP_ON (1 << 31) 3369 /* 3370 * Indicates that all dependencies of the panel are on: 3371 * 3372 * - PLL enabled 3373 * - pipe enabled 3374 * - LVDS/DVOB/DVOC on 3375 */ 3376 #define PP_READY (1 << 30) 3377 #define PP_SEQUENCE_NONE (0 << 28) 3378 #define PP_SEQUENCE_POWER_UP (1 << 28) 3379 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 3380 #define PP_SEQUENCE_MASK (3 << 28) 3381 #define PP_SEQUENCE_SHIFT 28 3382 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 3383 #define PP_SEQUENCE_STATE_MASK 0x0000000f 3384 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 3385 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 3386 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 3387 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 3388 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 3389 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 3390 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 3391 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 3392 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 3393 #define PP_CONTROL 0x61204 3394 #define POWER_TARGET_ON (1 << 0) 3395 #define PP_ON_DELAYS 0x61208 3396 #define PP_OFF_DELAYS 0x6120c 3397 #define PP_DIVISOR 0x61210 3398 3399 /* Panel fitting */ 3400 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) 3401 #define PFIT_ENABLE (1 << 31) 3402 #define PFIT_PIPE_MASK (3 << 29) 3403 #define PFIT_PIPE_SHIFT 29 3404 #define VERT_INTERP_DISABLE (0 << 10) 3405 #define VERT_INTERP_BILINEAR (1 << 10) 3406 #define VERT_INTERP_MASK (3 << 10) 3407 #define VERT_AUTO_SCALE (1 << 9) 3408 #define HORIZ_INTERP_DISABLE (0 << 6) 3409 #define HORIZ_INTERP_BILINEAR (1 << 6) 3410 #define HORIZ_INTERP_MASK (3 << 6) 3411 #define HORIZ_AUTO_SCALE (1 << 5) 3412 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 3413 #define PFIT_FILTER_FUZZY (0 << 24) 3414 #define PFIT_SCALING_AUTO (0 << 26) 3415 #define PFIT_SCALING_PROGRAMMED (1 << 26) 3416 #define PFIT_SCALING_PILLAR (2 << 26) 3417 #define PFIT_SCALING_LETTER (3 << 26) 3418 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234) 3419 /* Pre-965 */ 3420 #define PFIT_VERT_SCALE_SHIFT 20 3421 #define PFIT_VERT_SCALE_MASK 0xfff00000 3422 #define PFIT_HORIZ_SCALE_SHIFT 4 3423 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 3424 /* 965+ */ 3425 #define PFIT_VERT_SCALE_SHIFT_965 16 3426 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 3427 #define PFIT_HORIZ_SCALE_SHIFT_965 0 3428 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 3429 3430 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238) 3431 3432 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) 3433 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) 3434 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 3435 _VLV_BLC_PWM_CTL2_B) 3436 3437 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) 3438 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) 3439 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 3440 _VLV_BLC_PWM_CTL_B) 3441 3442 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) 3443 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) 3444 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 3445 _VLV_BLC_HIST_CTL_B) 3446 3447 /* Backlight control */ 3448 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ 3449 #define BLM_PWM_ENABLE (1 << 31) 3450 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 3451 #define BLM_PIPE_SELECT (1 << 29) 3452 #define BLM_PIPE_SELECT_IVB (3 << 29) 3453 #define BLM_PIPE_A (0 << 29) 3454 #define BLM_PIPE_B (1 << 29) 3455 #define BLM_PIPE_C (2 << 29) /* ivb + */ 3456 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 3457 #define BLM_TRANSCODER_B BLM_PIPE_B 3458 #define BLM_TRANSCODER_C BLM_PIPE_C 3459 #define BLM_TRANSCODER_EDP (3 << 29) 3460 #define BLM_PIPE(pipe) ((pipe) << 29) 3461 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 3462 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 3463 #define BLM_PHASE_IN_ENABLE (1 << 25) 3464 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 3465 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 3466 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 3467 #define BLM_PHASE_IN_COUNT_SHIFT (8) 3468 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 3469 #define BLM_PHASE_IN_INCR_SHIFT (0) 3470 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 3471 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254) 3472 /* 3473 * This is the most significant 15 bits of the number of backlight cycles in a 3474 * complete cycle of the modulated backlight control. 3475 * 3476 * The actual value is this field multiplied by two. 3477 */ 3478 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 3479 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 3480 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 3481 /* 3482 * This is the number of cycles out of the backlight modulation cycle for which 3483 * the backlight is on. 3484 * 3485 * This field must be no greater than the number of cycles in the complete 3486 * backlight modulation cycle. 3487 */ 3488 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 3489 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 3490 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 3491 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 3492 3493 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) 3494 #define BLM_HISTOGRAM_ENABLE (1 << 31) 3495 3496 /* New registers for PCH-split platforms. Safe where new bits show up, the 3497 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 3498 #define BLC_PWM_CPU_CTL2 0x48250 3499 #define BLC_PWM_CPU_CTL 0x48254 3500 3501 #define HSW_BLC_PWM2_CTL 0x48350 3502 3503 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 3504 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 3505 #define BLC_PWM_PCH_CTL1 0xc8250 3506 #define BLM_PCH_PWM_ENABLE (1 << 31) 3507 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 3508 #define BLM_PCH_POLARITY (1 << 29) 3509 #define BLC_PWM_PCH_CTL2 0xc8254 3510 3511 #define UTIL_PIN_CTL 0x48400 3512 #define UTIL_PIN_ENABLE (1 << 31) 3513 3514 /* BXT backlight register definition. */ 3515 #define BXT_BLC_PWM_CTL1 0xC8250 3516 #define BXT_BLC_PWM_ENABLE (1 << 31) 3517 #define BXT_BLC_PWM_POLARITY (1 << 29) 3518 #define BXT_BLC_PWM_FREQ1 0xC8254 3519 #define BXT_BLC_PWM_DUTY1 0xC8258 3520 3521 #define BXT_BLC_PWM_CTL2 0xC8350 3522 #define BXT_BLC_PWM_FREQ2 0xC8354 3523 #define BXT_BLC_PWM_DUTY2 0xC8358 3524 3525 3526 #define PCH_GTC_CTL 0xe7000 3527 #define PCH_GTC_ENABLE (1 << 31) 3528 3529 /* TV port control */ 3530 #define TV_CTL 0x68000 3531 /* Enables the TV encoder */ 3532 # define TV_ENC_ENABLE (1 << 31) 3533 /* Sources the TV encoder input from pipe B instead of A. */ 3534 # define TV_ENC_PIPEB_SELECT (1 << 30) 3535 /* Outputs composite video (DAC A only) */ 3536 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 3537 /* Outputs SVideo video (DAC B/C) */ 3538 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 3539 /* Outputs Component video (DAC A/B/C) */ 3540 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 3541 /* Outputs Composite and SVideo (DAC A/B/C) */ 3542 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 3543 # define TV_TRILEVEL_SYNC (1 << 21) 3544 /* Enables slow sync generation (945GM only) */ 3545 # define TV_SLOW_SYNC (1 << 20) 3546 /* Selects 4x oversampling for 480i and 576p */ 3547 # define TV_OVERSAMPLE_4X (0 << 18) 3548 /* Selects 2x oversampling for 720p and 1080i */ 3549 # define TV_OVERSAMPLE_2X (1 << 18) 3550 /* Selects no oversampling for 1080p */ 3551 # define TV_OVERSAMPLE_NONE (2 << 18) 3552 /* Selects 8x oversampling */ 3553 # define TV_OVERSAMPLE_8X (3 << 18) 3554 /* Selects progressive mode rather than interlaced */ 3555 # define TV_PROGRESSIVE (1 << 17) 3556 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 3557 # define TV_PAL_BURST (1 << 16) 3558 /* Field for setting delay of Y compared to C */ 3559 # define TV_YC_SKEW_MASK (7 << 12) 3560 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 3561 # define TV_ENC_SDP_FIX (1 << 11) 3562 /* 3563 * Enables a fix for the 915GM only. 3564 * 3565 * Not sure what it does. 3566 */ 3567 # define TV_ENC_C0_FIX (1 << 10) 3568 /* Bits that must be preserved by software */ 3569 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 3570 # define TV_FUSE_STATE_MASK (3 << 4) 3571 /* Read-only state that reports all features enabled */ 3572 # define TV_FUSE_STATE_ENABLED (0 << 4) 3573 /* Read-only state that reports that Macrovision is disabled in hardware*/ 3574 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 3575 /* Read-only state that reports that TV-out is disabled in hardware. */ 3576 # define TV_FUSE_STATE_DISABLED (2 << 4) 3577 /* Normal operation */ 3578 # define TV_TEST_MODE_NORMAL (0 << 0) 3579 /* Encoder test pattern 1 - combo pattern */ 3580 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 3581 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 3582 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 3583 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 3584 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 3585 /* Encoder test pattern 4 - random noise */ 3586 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 3587 /* Encoder test pattern 5 - linear color ramps */ 3588 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 3589 /* 3590 * This test mode forces the DACs to 50% of full output. 3591 * 3592 * This is used for load detection in combination with TVDAC_SENSE_MASK 3593 */ 3594 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 3595 # define TV_TEST_MODE_MASK (7 << 0) 3596 3597 #define TV_DAC 0x68004 3598 # define TV_DAC_SAVE 0x00ffff00 3599 /* 3600 * Reports that DAC state change logic has reported change (RO). 3601 * 3602 * This gets cleared when TV_DAC_STATE_EN is cleared 3603 */ 3604 # define TVDAC_STATE_CHG (1 << 31) 3605 # define TVDAC_SENSE_MASK (7 << 28) 3606 /* Reports that DAC A voltage is above the detect threshold */ 3607 # define TVDAC_A_SENSE (1 << 30) 3608 /* Reports that DAC B voltage is above the detect threshold */ 3609 # define TVDAC_B_SENSE (1 << 29) 3610 /* Reports that DAC C voltage is above the detect threshold */ 3611 # define TVDAC_C_SENSE (1 << 28) 3612 /* 3613 * Enables DAC state detection logic, for load-based TV detection. 3614 * 3615 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 3616 * to off, for load detection to work. 3617 */ 3618 # define TVDAC_STATE_CHG_EN (1 << 27) 3619 /* Sets the DAC A sense value to high */ 3620 # define TVDAC_A_SENSE_CTL (1 << 26) 3621 /* Sets the DAC B sense value to high */ 3622 # define TVDAC_B_SENSE_CTL (1 << 25) 3623 /* Sets the DAC C sense value to high */ 3624 # define TVDAC_C_SENSE_CTL (1 << 24) 3625 /* Overrides the ENC_ENABLE and DAC voltage levels */ 3626 # define DAC_CTL_OVERRIDE (1 << 7) 3627 /* Sets the slew rate. Must be preserved in software */ 3628 # define ENC_TVDAC_SLEW_FAST (1 << 6) 3629 # define DAC_A_1_3_V (0 << 4) 3630 # define DAC_A_1_1_V (1 << 4) 3631 # define DAC_A_0_7_V (2 << 4) 3632 # define DAC_A_MASK (3 << 4) 3633 # define DAC_B_1_3_V (0 << 2) 3634 # define DAC_B_1_1_V (1 << 2) 3635 # define DAC_B_0_7_V (2 << 2) 3636 # define DAC_B_MASK (3 << 2) 3637 # define DAC_C_1_3_V (0 << 0) 3638 # define DAC_C_1_1_V (1 << 0) 3639 # define DAC_C_0_7_V (2 << 0) 3640 # define DAC_C_MASK (3 << 0) 3641 3642 /* 3643 * CSC coefficients are stored in a floating point format with 9 bits of 3644 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3645 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3646 * -1 (0x3) being the only legal negative value. 3647 */ 3648 #define TV_CSC_Y 0x68010 3649 # define TV_RY_MASK 0x07ff0000 3650 # define TV_RY_SHIFT 16 3651 # define TV_GY_MASK 0x00000fff 3652 # define TV_GY_SHIFT 0 3653 3654 #define TV_CSC_Y2 0x68014 3655 # define TV_BY_MASK 0x07ff0000 3656 # define TV_BY_SHIFT 16 3657 /* 3658 * Y attenuation for component video. 3659 * 3660 * Stored in 1.9 fixed point. 3661 */ 3662 # define TV_AY_MASK 0x000003ff 3663 # define TV_AY_SHIFT 0 3664 3665 #define TV_CSC_U 0x68018 3666 # define TV_RU_MASK 0x07ff0000 3667 # define TV_RU_SHIFT 16 3668 # define TV_GU_MASK 0x000007ff 3669 # define TV_GU_SHIFT 0 3670 3671 #define TV_CSC_U2 0x6801c 3672 # define TV_BU_MASK 0x07ff0000 3673 # define TV_BU_SHIFT 16 3674 /* 3675 * U attenuation for component video. 3676 * 3677 * Stored in 1.9 fixed point. 3678 */ 3679 # define TV_AU_MASK 0x000003ff 3680 # define TV_AU_SHIFT 0 3681 3682 #define TV_CSC_V 0x68020 3683 # define TV_RV_MASK 0x0fff0000 3684 # define TV_RV_SHIFT 16 3685 # define TV_GV_MASK 0x000007ff 3686 # define TV_GV_SHIFT 0 3687 3688 #define TV_CSC_V2 0x68024 3689 # define TV_BV_MASK 0x07ff0000 3690 # define TV_BV_SHIFT 16 3691 /* 3692 * V attenuation for component video. 3693 * 3694 * Stored in 1.9 fixed point. 3695 */ 3696 # define TV_AV_MASK 0x000007ff 3697 # define TV_AV_SHIFT 0 3698 3699 #define TV_CLR_KNOBS 0x68028 3700 /* 2s-complement brightness adjustment */ 3701 # define TV_BRIGHTNESS_MASK 0xff000000 3702 # define TV_BRIGHTNESS_SHIFT 24 3703 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 3704 # define TV_CONTRAST_MASK 0x00ff0000 3705 # define TV_CONTRAST_SHIFT 16 3706 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 3707 # define TV_SATURATION_MASK 0x0000ff00 3708 # define TV_SATURATION_SHIFT 8 3709 /* Hue adjustment, as an integer phase angle in degrees */ 3710 # define TV_HUE_MASK 0x000000ff 3711 # define TV_HUE_SHIFT 0 3712 3713 #define TV_CLR_LEVEL 0x6802c 3714 /* Controls the DAC level for black */ 3715 # define TV_BLACK_LEVEL_MASK 0x01ff0000 3716 # define TV_BLACK_LEVEL_SHIFT 16 3717 /* Controls the DAC level for blanking */ 3718 # define TV_BLANK_LEVEL_MASK 0x000001ff 3719 # define TV_BLANK_LEVEL_SHIFT 0 3720 3721 #define TV_H_CTL_1 0x68030 3722 /* Number of pixels in the hsync. */ 3723 # define TV_HSYNC_END_MASK 0x1fff0000 3724 # define TV_HSYNC_END_SHIFT 16 3725 /* Total number of pixels minus one in the line (display and blanking). */ 3726 # define TV_HTOTAL_MASK 0x00001fff 3727 # define TV_HTOTAL_SHIFT 0 3728 3729 #define TV_H_CTL_2 0x68034 3730 /* Enables the colorburst (needed for non-component color) */ 3731 # define TV_BURST_ENA (1 << 31) 3732 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3733 # define TV_HBURST_START_SHIFT 16 3734 # define TV_HBURST_START_MASK 0x1fff0000 3735 /* Length of the colorburst */ 3736 # define TV_HBURST_LEN_SHIFT 0 3737 # define TV_HBURST_LEN_MASK 0x0001fff 3738 3739 #define TV_H_CTL_3 0x68038 3740 /* End of hblank, measured in pixels minus one from start of hsync */ 3741 # define TV_HBLANK_END_SHIFT 16 3742 # define TV_HBLANK_END_MASK 0x1fff0000 3743 /* Start of hblank, measured in pixels minus one from start of hsync */ 3744 # define TV_HBLANK_START_SHIFT 0 3745 # define TV_HBLANK_START_MASK 0x0001fff 3746 3747 #define TV_V_CTL_1 0x6803c 3748 /* XXX */ 3749 # define TV_NBR_END_SHIFT 16 3750 # define TV_NBR_END_MASK 0x07ff0000 3751 /* XXX */ 3752 # define TV_VI_END_F1_SHIFT 8 3753 # define TV_VI_END_F1_MASK 0x00003f00 3754 /* XXX */ 3755 # define TV_VI_END_F2_SHIFT 0 3756 # define TV_VI_END_F2_MASK 0x0000003f 3757 3758 #define TV_V_CTL_2 0x68040 3759 /* Length of vsync, in half lines */ 3760 # define TV_VSYNC_LEN_MASK 0x07ff0000 3761 # define TV_VSYNC_LEN_SHIFT 16 3762 /* Offset of the start of vsync in field 1, measured in one less than the 3763 * number of half lines. 3764 */ 3765 # define TV_VSYNC_START_F1_MASK 0x00007f00 3766 # define TV_VSYNC_START_F1_SHIFT 8 3767 /* 3768 * Offset of the start of vsync in field 2, measured in one less than the 3769 * number of half lines. 3770 */ 3771 # define TV_VSYNC_START_F2_MASK 0x0000007f 3772 # define TV_VSYNC_START_F2_SHIFT 0 3773 3774 #define TV_V_CTL_3 0x68044 3775 /* Enables generation of the equalization signal */ 3776 # define TV_EQUAL_ENA (1 << 31) 3777 /* Length of vsync, in half lines */ 3778 # define TV_VEQ_LEN_MASK 0x007f0000 3779 # define TV_VEQ_LEN_SHIFT 16 3780 /* Offset of the start of equalization in field 1, measured in one less than 3781 * the number of half lines. 3782 */ 3783 # define TV_VEQ_START_F1_MASK 0x0007f00 3784 # define TV_VEQ_START_F1_SHIFT 8 3785 /* 3786 * Offset of the start of equalization in field 2, measured in one less than 3787 * the number of half lines. 3788 */ 3789 # define TV_VEQ_START_F2_MASK 0x000007f 3790 # define TV_VEQ_START_F2_SHIFT 0 3791 3792 #define TV_V_CTL_4 0x68048 3793 /* 3794 * Offset to start of vertical colorburst, measured in one less than the 3795 * number of lines from vertical start. 3796 */ 3797 # define TV_VBURST_START_F1_MASK 0x003f0000 3798 # define TV_VBURST_START_F1_SHIFT 16 3799 /* 3800 * Offset to the end of vertical colorburst, measured in one less than the 3801 * number of lines from the start of NBR. 3802 */ 3803 # define TV_VBURST_END_F1_MASK 0x000000ff 3804 # define TV_VBURST_END_F1_SHIFT 0 3805 3806 #define TV_V_CTL_5 0x6804c 3807 /* 3808 * Offset to start of vertical colorburst, measured in one less than the 3809 * number of lines from vertical start. 3810 */ 3811 # define TV_VBURST_START_F2_MASK 0x003f0000 3812 # define TV_VBURST_START_F2_SHIFT 16 3813 /* 3814 * Offset to the end of vertical colorburst, measured in one less than the 3815 * number of lines from the start of NBR. 3816 */ 3817 # define TV_VBURST_END_F2_MASK 0x000000ff 3818 # define TV_VBURST_END_F2_SHIFT 0 3819 3820 #define TV_V_CTL_6 0x68050 3821 /* 3822 * Offset to start of vertical colorburst, measured in one less than the 3823 * number of lines from vertical start. 3824 */ 3825 # define TV_VBURST_START_F3_MASK 0x003f0000 3826 # define TV_VBURST_START_F3_SHIFT 16 3827 /* 3828 * Offset to the end of vertical colorburst, measured in one less than the 3829 * number of lines from the start of NBR. 3830 */ 3831 # define TV_VBURST_END_F3_MASK 0x000000ff 3832 # define TV_VBURST_END_F3_SHIFT 0 3833 3834 #define TV_V_CTL_7 0x68054 3835 /* 3836 * Offset to start of vertical colorburst, measured in one less than the 3837 * number of lines from vertical start. 3838 */ 3839 # define TV_VBURST_START_F4_MASK 0x003f0000 3840 # define TV_VBURST_START_F4_SHIFT 16 3841 /* 3842 * Offset to the end of vertical colorburst, measured in one less than the 3843 * number of lines from the start of NBR. 3844 */ 3845 # define TV_VBURST_END_F4_MASK 0x000000ff 3846 # define TV_VBURST_END_F4_SHIFT 0 3847 3848 #define TV_SC_CTL_1 0x68060 3849 /* Turns on the first subcarrier phase generation DDA */ 3850 # define TV_SC_DDA1_EN (1 << 31) 3851 /* Turns on the first subcarrier phase generation DDA */ 3852 # define TV_SC_DDA2_EN (1 << 30) 3853 /* Turns on the first subcarrier phase generation DDA */ 3854 # define TV_SC_DDA3_EN (1 << 29) 3855 /* Sets the subcarrier DDA to reset frequency every other field */ 3856 # define TV_SC_RESET_EVERY_2 (0 << 24) 3857 /* Sets the subcarrier DDA to reset frequency every fourth field */ 3858 # define TV_SC_RESET_EVERY_4 (1 << 24) 3859 /* Sets the subcarrier DDA to reset frequency every eighth field */ 3860 # define TV_SC_RESET_EVERY_8 (2 << 24) 3861 /* Sets the subcarrier DDA to never reset the frequency */ 3862 # define TV_SC_RESET_NEVER (3 << 24) 3863 /* Sets the peak amplitude of the colorburst.*/ 3864 # define TV_BURST_LEVEL_MASK 0x00ff0000 3865 # define TV_BURST_LEVEL_SHIFT 16 3866 /* Sets the increment of the first subcarrier phase generation DDA */ 3867 # define TV_SCDDA1_INC_MASK 0x00000fff 3868 # define TV_SCDDA1_INC_SHIFT 0 3869 3870 #define TV_SC_CTL_2 0x68064 3871 /* Sets the rollover for the second subcarrier phase generation DDA */ 3872 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 3873 # define TV_SCDDA2_SIZE_SHIFT 16 3874 /* Sets the increent of the second subcarrier phase generation DDA */ 3875 # define TV_SCDDA2_INC_MASK 0x00007fff 3876 # define TV_SCDDA2_INC_SHIFT 0 3877 3878 #define TV_SC_CTL_3 0x68068 3879 /* Sets the rollover for the third subcarrier phase generation DDA */ 3880 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 3881 # define TV_SCDDA3_SIZE_SHIFT 16 3882 /* Sets the increent of the third subcarrier phase generation DDA */ 3883 # define TV_SCDDA3_INC_MASK 0x00007fff 3884 # define TV_SCDDA3_INC_SHIFT 0 3885 3886 #define TV_WIN_POS 0x68070 3887 /* X coordinate of the display from the start of horizontal active */ 3888 # define TV_XPOS_MASK 0x1fff0000 3889 # define TV_XPOS_SHIFT 16 3890 /* Y coordinate of the display from the start of vertical active (NBR) */ 3891 # define TV_YPOS_MASK 0x00000fff 3892 # define TV_YPOS_SHIFT 0 3893 3894 #define TV_WIN_SIZE 0x68074 3895 /* Horizontal size of the display window, measured in pixels*/ 3896 # define TV_XSIZE_MASK 0x1fff0000 3897 # define TV_XSIZE_SHIFT 16 3898 /* 3899 * Vertical size of the display window, measured in pixels. 3900 * 3901 * Must be even for interlaced modes. 3902 */ 3903 # define TV_YSIZE_MASK 0x00000fff 3904 # define TV_YSIZE_SHIFT 0 3905 3906 #define TV_FILTER_CTL_1 0x68080 3907 /* 3908 * Enables automatic scaling calculation. 3909 * 3910 * If set, the rest of the registers are ignored, and the calculated values can 3911 * be read back from the register. 3912 */ 3913 # define TV_AUTO_SCALE (1 << 31) 3914 /* 3915 * Disables the vertical filter. 3916 * 3917 * This is required on modes more than 1024 pixels wide */ 3918 # define TV_V_FILTER_BYPASS (1 << 29) 3919 /* Enables adaptive vertical filtering */ 3920 # define TV_VADAPT (1 << 28) 3921 # define TV_VADAPT_MODE_MASK (3 << 26) 3922 /* Selects the least adaptive vertical filtering mode */ 3923 # define TV_VADAPT_MODE_LEAST (0 << 26) 3924 /* Selects the moderately adaptive vertical filtering mode */ 3925 # define TV_VADAPT_MODE_MODERATE (1 << 26) 3926 /* Selects the most adaptive vertical filtering mode */ 3927 # define TV_VADAPT_MODE_MOST (3 << 26) 3928 /* 3929 * Sets the horizontal scaling factor. 3930 * 3931 * This should be the fractional part of the horizontal scaling factor divided 3932 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3933 * 3934 * (src width - 1) / ((oversample * dest width) - 1) 3935 */ 3936 # define TV_HSCALE_FRAC_MASK 0x00003fff 3937 # define TV_HSCALE_FRAC_SHIFT 0 3938 3939 #define TV_FILTER_CTL_2 0x68084 3940 /* 3941 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3942 * 3943 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3944 */ 3945 # define TV_VSCALE_INT_MASK 0x00038000 3946 # define TV_VSCALE_INT_SHIFT 15 3947 /* 3948 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3949 * 3950 * \sa TV_VSCALE_INT_MASK 3951 */ 3952 # define TV_VSCALE_FRAC_MASK 0x00007fff 3953 # define TV_VSCALE_FRAC_SHIFT 0 3954 3955 #define TV_FILTER_CTL_3 0x68088 3956 /* 3957 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3958 * 3959 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3960 * 3961 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3962 */ 3963 # define TV_VSCALE_IP_INT_MASK 0x00038000 3964 # define TV_VSCALE_IP_INT_SHIFT 15 3965 /* 3966 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3967 * 3968 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3969 * 3970 * \sa TV_VSCALE_IP_INT_MASK 3971 */ 3972 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3973 # define TV_VSCALE_IP_FRAC_SHIFT 0 3974 3975 #define TV_CC_CONTROL 0x68090 3976 # define TV_CC_ENABLE (1 << 31) 3977 /* 3978 * Specifies which field to send the CC data in. 3979 * 3980 * CC data is usually sent in field 0. 3981 */ 3982 # define TV_CC_FID_MASK (1 << 27) 3983 # define TV_CC_FID_SHIFT 27 3984 /* Sets the horizontal position of the CC data. Usually 135. */ 3985 # define TV_CC_HOFF_MASK 0x03ff0000 3986 # define TV_CC_HOFF_SHIFT 16 3987 /* Sets the vertical position of the CC data. Usually 21 */ 3988 # define TV_CC_LINE_MASK 0x0000003f 3989 # define TV_CC_LINE_SHIFT 0 3990 3991 #define TV_CC_DATA 0x68094 3992 # define TV_CC_RDY (1 << 31) 3993 /* Second word of CC data to be transmitted. */ 3994 # define TV_CC_DATA_2_MASK 0x007f0000 3995 # define TV_CC_DATA_2_SHIFT 16 3996 /* First word of CC data to be transmitted. */ 3997 # define TV_CC_DATA_1_MASK 0x0000007f 3998 # define TV_CC_DATA_1_SHIFT 0 3999 4000 #define TV_H_LUMA_0 0x68100 4001 #define TV_H_LUMA_59 0x681ec 4002 #define TV_H_CHROMA_0 0x68200 4003 #define TV_H_CHROMA_59 0x682ec 4004 #define TV_V_LUMA_0 0x68300 4005 #define TV_V_LUMA_42 0x683a8 4006 #define TV_V_CHROMA_0 0x68400 4007 #define TV_V_CHROMA_42 0x684a8 4008 4009 /* Display Port */ 4010 #define DP_A 0x64000 /* eDP */ 4011 #define DP_B 0x64100 4012 #define DP_C 0x64200 4013 #define DP_D 0x64300 4014 4015 #define DP_PORT_EN (1 << 31) 4016 #define DP_PIPEB_SELECT (1 << 30) 4017 #define DP_PIPE_MASK (1 << 30) 4018 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) 4019 #define DP_PIPE_MASK_CHV (3 << 16) 4020 4021 /* Link training mode - select a suitable mode for each stage */ 4022 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 4023 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 4024 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 4025 #define DP_LINK_TRAIN_OFF (3 << 28) 4026 #define DP_LINK_TRAIN_MASK (3 << 28) 4027 #define DP_LINK_TRAIN_SHIFT 28 4028 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) 4029 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) 4030 4031 /* CPT Link training mode */ 4032 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 4033 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 4034 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 4035 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 4036 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 4037 #define DP_LINK_TRAIN_SHIFT_CPT 8 4038 4039 /* Signal voltages. These are mostly controlled by the other end */ 4040 #define DP_VOLTAGE_0_4 (0 << 25) 4041 #define DP_VOLTAGE_0_6 (1 << 25) 4042 #define DP_VOLTAGE_0_8 (2 << 25) 4043 #define DP_VOLTAGE_1_2 (3 << 25) 4044 #define DP_VOLTAGE_MASK (7 << 25) 4045 #define DP_VOLTAGE_SHIFT 25 4046 4047 /* Signal pre-emphasis levels, like voltages, the other end tells us what 4048 * they want 4049 */ 4050 #define DP_PRE_EMPHASIS_0 (0 << 22) 4051 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 4052 #define DP_PRE_EMPHASIS_6 (2 << 22) 4053 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 4054 #define DP_PRE_EMPHASIS_MASK (7 << 22) 4055 #define DP_PRE_EMPHASIS_SHIFT 22 4056 4057 /* How many wires to use. I guess 3 was too hard */ 4058 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 4059 #define DP_PORT_WIDTH_MASK (7 << 19) 4060 4061 /* Mystic DPCD version 1.1 special mode */ 4062 #define DP_ENHANCED_FRAMING (1 << 18) 4063 4064 /* eDP */ 4065 #define DP_PLL_FREQ_270MHZ (0 << 16) 4066 #define DP_PLL_FREQ_160MHZ (1 << 16) 4067 #define DP_PLL_FREQ_MASK (3 << 16) 4068 4069 /* locked once port is enabled */ 4070 #define DP_PORT_REVERSAL (1 << 15) 4071 4072 /* eDP */ 4073 #define DP_PLL_ENABLE (1 << 14) 4074 4075 /* sends the clock on lane 15 of the PEG for debug */ 4076 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 4077 4078 #define DP_SCRAMBLING_DISABLE (1 << 12) 4079 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 4080 4081 /* limit RGB values to avoid confusing TVs */ 4082 #define DP_COLOR_RANGE_16_235 (1 << 8) 4083 4084 /* Turn on the audio link */ 4085 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 4086 4087 /* vs and hs sync polarity */ 4088 #define DP_SYNC_VS_HIGH (1 << 4) 4089 #define DP_SYNC_HS_HIGH (1 << 3) 4090 4091 /* A fantasy */ 4092 #define DP_DETECTED (1 << 2) 4093 4094 /* The aux channel provides a way to talk to the 4095 * signal sink for DDC etc. Max packet size supported 4096 * is 20 bytes in each direction, hence the 5 fixed 4097 * data registers 4098 */ 4099 #define DPA_AUX_CH_CTL 0x64010 4100 #define DPA_AUX_CH_DATA1 0x64014 4101 #define DPA_AUX_CH_DATA2 0x64018 4102 #define DPA_AUX_CH_DATA3 0x6401c 4103 #define DPA_AUX_CH_DATA4 0x64020 4104 #define DPA_AUX_CH_DATA5 0x64024 4105 4106 #define DPB_AUX_CH_CTL 0x64110 4107 #define DPB_AUX_CH_DATA1 0x64114 4108 #define DPB_AUX_CH_DATA2 0x64118 4109 #define DPB_AUX_CH_DATA3 0x6411c 4110 #define DPB_AUX_CH_DATA4 0x64120 4111 #define DPB_AUX_CH_DATA5 0x64124 4112 4113 #define DPC_AUX_CH_CTL 0x64210 4114 #define DPC_AUX_CH_DATA1 0x64214 4115 #define DPC_AUX_CH_DATA2 0x64218 4116 #define DPC_AUX_CH_DATA3 0x6421c 4117 #define DPC_AUX_CH_DATA4 0x64220 4118 #define DPC_AUX_CH_DATA5 0x64224 4119 4120 #define DPD_AUX_CH_CTL 0x64310 4121 #define DPD_AUX_CH_DATA1 0x64314 4122 #define DPD_AUX_CH_DATA2 0x64318 4123 #define DPD_AUX_CH_DATA3 0x6431c 4124 #define DPD_AUX_CH_DATA4 0x64320 4125 #define DPD_AUX_CH_DATA5 0x64324 4126 4127 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 4128 #define DP_AUX_CH_CTL_DONE (1 << 30) 4129 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 4130 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 4131 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 4132 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 4133 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 4134 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 4135 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 4136 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 4137 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 4138 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 4139 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 4140 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 4141 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 4142 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 4143 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 4144 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 4145 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 4146 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 4147 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 4148 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 4149 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 4150 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 4151 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5) 4152 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 4153 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 4154 4155 /* 4156 * Computing GMCH M and N values for the Display Port link 4157 * 4158 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 4159 * 4160 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 4161 * 4162 * The GMCH value is used internally 4163 * 4164 * bytes_per_pixel is the number of bytes coming out of the plane, 4165 * which is after the LUTs, so we want the bytes for our color format. 4166 * For our current usage, this is always 3, one byte for R, G and B. 4167 */ 4168 #define _PIPEA_DATA_M_G4X 0x70050 4169 #define _PIPEB_DATA_M_G4X 0x71050 4170 4171 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 4172 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 4173 #define TU_SIZE_SHIFT 25 4174 #define TU_SIZE_MASK (0x3f << 25) 4175 4176 #define DATA_LINK_M_N_MASK (0xffffff) 4177 #define DATA_LINK_N_MAX (0x800000) 4178 4179 #define _PIPEA_DATA_N_G4X 0x70054 4180 #define _PIPEB_DATA_N_G4X 0x71054 4181 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 4182 4183 /* 4184 * Computing Link M and N values for the Display Port link 4185 * 4186 * Link M / N = pixel_clock / ls_clk 4187 * 4188 * (the DP spec calls pixel_clock the 'strm_clk') 4189 * 4190 * The Link value is transmitted in the Main Stream 4191 * Attributes and VB-ID. 4192 */ 4193 4194 #define _PIPEA_LINK_M_G4X 0x70060 4195 #define _PIPEB_LINK_M_G4X 0x71060 4196 #define PIPEA_DP_LINK_M_MASK (0xffffff) 4197 4198 #define _PIPEA_LINK_N_G4X 0x70064 4199 #define _PIPEB_LINK_N_G4X 0x71064 4200 #define PIPEA_DP_LINK_N_MASK (0xffffff) 4201 4202 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 4203 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 4204 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 4205 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 4206 4207 /* Display & cursor control */ 4208 4209 /* Pipe A */ 4210 #define _PIPEADSL 0x70000 4211 #define DSL_LINEMASK_GEN2 0x00000fff 4212 #define DSL_LINEMASK_GEN3 0x00001fff 4213 #define _PIPEACONF 0x70008 4214 #define PIPECONF_ENABLE (1<<31) 4215 #define PIPECONF_DISABLE 0 4216 #define PIPECONF_DOUBLE_WIDE (1<<30) 4217 #define I965_PIPECONF_ACTIVE (1<<30) 4218 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ 4219 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 4220 #define PIPECONF_SINGLE_WIDE 0 4221 #define PIPECONF_PIPE_UNLOCKED 0 4222 #define PIPECONF_PIPE_LOCKED (1<<25) 4223 #define PIPECONF_PALETTE 0 4224 #define PIPECONF_GAMMA (1<<24) 4225 #define PIPECONF_FORCE_BORDER (1<<25) 4226 #define PIPECONF_INTERLACE_MASK (7 << 21) 4227 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 4228 /* Note that pre-gen3 does not support interlaced display directly. Panel 4229 * fitting must be disabled on pre-ilk for interlaced. */ 4230 #define PIPECONF_PROGRESSIVE (0 << 21) 4231 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 4232 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 4233 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 4234 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 4235 /* Ironlake and later have a complete new set of values for interlaced. PFIT 4236 * means panel fitter required, PF means progressive fetch, DBL means power 4237 * saving pixel doubling. */ 4238 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 4239 #define PIPECONF_INTERLACED_ILK (3 << 21) 4240 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 4241 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 4242 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 4243 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 4244 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 4245 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) 4246 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 4247 #define PIPECONF_BPC_MASK (0x7 << 5) 4248 #define PIPECONF_8BPC (0<<5) 4249 #define PIPECONF_10BPC (1<<5) 4250 #define PIPECONF_6BPC (2<<5) 4251 #define PIPECONF_12BPC (3<<5) 4252 #define PIPECONF_DITHER_EN (1<<4) 4253 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 4254 #define PIPECONF_DITHER_TYPE_SP (0<<2) 4255 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 4256 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 4257 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 4258 #define _PIPEASTAT 0x70024 4259 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 4260 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) 4261 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 4262 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 4263 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) 4264 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 4265 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 4266 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 4267 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 4268 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 4269 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 4270 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) 4271 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 4272 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 4273 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 4274 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) 4275 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) 4276 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 4277 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 4278 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) 4279 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 4280 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 4281 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 4282 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) 4283 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) 4284 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 4285 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 4286 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) 4287 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 4288 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) 4289 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 4290 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 4291 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 4292 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 4293 #define PIPE_A_PSR_STATUS_VLV (1UL<<6) 4294 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 4295 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 4296 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 4297 #define PIPE_B_PSR_STATUS_VLV (1UL<<3) 4298 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) 4299 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 4300 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 4301 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) 4302 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 4303 #define PIPE_HBLANK_INT_STATUS (1UL<<0) 4304 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 4305 4306 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 4307 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 4308 4309 #define PIPE_A_OFFSET 0x70000 4310 #define PIPE_B_OFFSET 0x71000 4311 #define PIPE_C_OFFSET 0x72000 4312 #define CHV_PIPE_C_OFFSET 0x74000 4313 /* 4314 * There's actually no pipe EDP. Some pipe registers have 4315 * simply shifted from the pipe to the transcoder, while 4316 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 4317 * to access such registers in transcoder EDP. 4318 */ 4319 #define PIPE_EDP_OFFSET 0x7f000 4320 4321 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \ 4322 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ 4323 dev_priv->info.display_mmio_offset) 4324 4325 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) 4326 #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) 4327 #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) 4328 #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) 4329 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) 4330 4331 #define _PIPE_MISC_A 0x70030 4332 #define _PIPE_MISC_B 0x71030 4333 #define PIPEMISC_DITHER_BPC_MASK (7<<5) 4334 #define PIPEMISC_DITHER_8_BPC (0<<5) 4335 #define PIPEMISC_DITHER_10_BPC (1<<5) 4336 #define PIPEMISC_DITHER_6_BPC (2<<5) 4337 #define PIPEMISC_DITHER_12_BPC (3<<5) 4338 #define PIPEMISC_DITHER_ENABLE (1<<4) 4339 #define PIPEMISC_DITHER_TYPE_MASK (3<<2) 4340 #define PIPEMISC_DITHER_TYPE_SP (0<<2) 4341 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) 4342 4343 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) 4344 #define PIPEB_LINE_COMPARE_INT_EN (1<<29) 4345 #define PIPEB_HLINE_INT_EN (1<<28) 4346 #define PIPEB_VBLANK_INT_EN (1<<27) 4347 #define SPRITED_FLIP_DONE_INT_EN (1<<26) 4348 #define SPRITEC_FLIP_DONE_INT_EN (1<<25) 4349 #define PLANEB_FLIP_DONE_INT_EN (1<<24) 4350 #define PIPE_PSR_INT_EN (1<<22) 4351 #define PIPEA_LINE_COMPARE_INT_EN (1<<21) 4352 #define PIPEA_HLINE_INT_EN (1<<20) 4353 #define PIPEA_VBLANK_INT_EN (1<<19) 4354 #define SPRITEB_FLIP_DONE_INT_EN (1<<18) 4355 #define SPRITEA_FLIP_DONE_INT_EN (1<<17) 4356 #define PLANEA_FLIPDONE_INT_EN (1<<16) 4357 #define PIPEC_LINE_COMPARE_INT_EN (1<<13) 4358 #define PIPEC_HLINE_INT_EN (1<<12) 4359 #define PIPEC_VBLANK_INT_EN (1<<11) 4360 #define SPRITEF_FLIPDONE_INT_EN (1<<10) 4361 #define SPRITEE_FLIPDONE_INT_EN (1<<9) 4362 #define PLANEC_FLIPDONE_INT_EN (1<<8) 4363 4364 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 4365 #define SPRITEF_INVALID_GTT_INT_EN (1<<27) 4366 #define SPRITEE_INVALID_GTT_INT_EN (1<<26) 4367 #define PLANEC_INVALID_GTT_INT_EN (1<<25) 4368 #define CURSORC_INVALID_GTT_INT_EN (1<<24) 4369 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 4370 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 4371 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 4372 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 4373 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 4374 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 4375 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 4376 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 4377 #define DPINVGTT_EN_MASK 0xff0000 4378 #define DPINVGTT_EN_MASK_CHV 0xfff0000 4379 #define SPRITEF_INVALID_GTT_STATUS (1<<11) 4380 #define SPRITEE_INVALID_GTT_STATUS (1<<10) 4381 #define PLANEC_INVALID_GTT_STATUS (1<<9) 4382 #define CURSORC_INVALID_GTT_STATUS (1<<8) 4383 #define CURSORB_INVALID_GTT_STATUS (1<<7) 4384 #define CURSORA_INVALID_GTT_STATUS (1<<6) 4385 #define SPRITED_INVALID_GTT_STATUS (1<<5) 4386 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 4387 #define PLANEB_INVALID_GTT_STATUS (1<<3) 4388 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 4389 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 4390 #define PLANEA_INVALID_GTT_STATUS (1<<0) 4391 #define DPINVGTT_STATUS_MASK 0xff 4392 #define DPINVGTT_STATUS_MASK_CHV 0xfff 4393 4394 #define DSPARB (dev_priv->info.display_mmio_offset + 0x70030) 4395 #define DSPARB_CSTART_MASK (0x7f << 7) 4396 #define DSPARB_CSTART_SHIFT 7 4397 #define DSPARB_BSTART_MASK (0x7f) 4398 #define DSPARB_BSTART_SHIFT 0 4399 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 4400 #define DSPARB_AEND_SHIFT 0 4401 4402 #define DSPARB2 (VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 4403 #define DSPARB3 (VLV_DISPLAY_BASE + 0x7006c) /* chv */ 4404 4405 /* pnv/gen4/g4x/vlv/chv */ 4406 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) 4407 #define DSPFW_SR_SHIFT 23 4408 #define DSPFW_SR_MASK (0x1ff<<23) 4409 #define DSPFW_CURSORB_SHIFT 16 4410 #define DSPFW_CURSORB_MASK (0x3f<<16) 4411 #define DSPFW_PLANEB_SHIFT 8 4412 #define DSPFW_PLANEB_MASK (0x7f<<8) 4413 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ 4414 #define DSPFW_PLANEA_SHIFT 0 4415 #define DSPFW_PLANEA_MASK (0x7f<<0) 4416 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ 4417 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) 4418 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ 4419 #define DSPFW_FBC_SR_SHIFT 28 4420 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ 4421 #define DSPFW_FBC_HPLL_SR_SHIFT 24 4422 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ 4423 #define DSPFW_SPRITEB_SHIFT (16) 4424 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ 4425 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ 4426 #define DSPFW_CURSORA_SHIFT 8 4427 #define DSPFW_CURSORA_MASK (0x3f<<8) 4428 #define DSPFW_PLANEC_OLD_SHIFT 0 4429 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */ 4430 #define DSPFW_SPRITEA_SHIFT 0 4431 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ 4432 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ 4433 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) 4434 #define DSPFW_HPLL_SR_EN (1<<31) 4435 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 4436 #define DSPFW_CURSOR_SR_SHIFT 24 4437 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 4438 #define DSPFW_HPLL_CURSOR_SHIFT 16 4439 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 4440 #define DSPFW_HPLL_SR_SHIFT 0 4441 #define DSPFW_HPLL_SR_MASK (0x1ff<<0) 4442 4443 /* vlv/chv */ 4444 #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070) 4445 #define DSPFW_SPRITEB_WM1_SHIFT 16 4446 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) 4447 #define DSPFW_CURSORA_WM1_SHIFT 8 4448 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) 4449 #define DSPFW_SPRITEA_WM1_SHIFT 0 4450 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) 4451 #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074) 4452 #define DSPFW_PLANEB_WM1_SHIFT 24 4453 #define DSPFW_PLANEB_WM1_MASK (0xff<<24) 4454 #define DSPFW_PLANEA_WM1_SHIFT 16 4455 #define DSPFW_PLANEA_WM1_MASK (0xff<<16) 4456 #define DSPFW_CURSORB_WM1_SHIFT 8 4457 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) 4458 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 4459 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) 4460 #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078) 4461 #define DSPFW_SR_WM1_SHIFT 0 4462 #define DSPFW_SR_WM1_MASK (0x1ff<<0) 4463 #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c) 4464 #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 4465 #define DSPFW_SPRITED_WM1_SHIFT 24 4466 #define DSPFW_SPRITED_WM1_MASK (0xff<<24) 4467 #define DSPFW_SPRITED_SHIFT 16 4468 #define DSPFW_SPRITED_MASK_VLV (0xff<<16) 4469 #define DSPFW_SPRITEC_WM1_SHIFT 8 4470 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) 4471 #define DSPFW_SPRITEC_SHIFT 0 4472 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0) 4473 #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8) 4474 #define DSPFW_SPRITEF_WM1_SHIFT 24 4475 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) 4476 #define DSPFW_SPRITEF_SHIFT 16 4477 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16) 4478 #define DSPFW_SPRITEE_WM1_SHIFT 8 4479 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) 4480 #define DSPFW_SPRITEE_SHIFT 0 4481 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0) 4482 #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 4483 #define DSPFW_PLANEC_WM1_SHIFT 24 4484 #define DSPFW_PLANEC_WM1_MASK (0xff<<24) 4485 #define DSPFW_PLANEC_SHIFT 16 4486 #define DSPFW_PLANEC_MASK_VLV (0xff<<16) 4487 #define DSPFW_CURSORC_WM1_SHIFT 8 4488 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) 4489 #define DSPFW_CURSORC_SHIFT 0 4490 #define DSPFW_CURSORC_MASK (0x3f<<0) 4491 4492 /* vlv/chv high order bits */ 4493 #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064) 4494 #define DSPFW_SR_HI_SHIFT 24 4495 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 4496 #define DSPFW_SPRITEF_HI_SHIFT 23 4497 #define DSPFW_SPRITEF_HI_MASK (1<<23) 4498 #define DSPFW_SPRITEE_HI_SHIFT 22 4499 #define DSPFW_SPRITEE_HI_MASK (1<<22) 4500 #define DSPFW_PLANEC_HI_SHIFT 21 4501 #define DSPFW_PLANEC_HI_MASK (1<<21) 4502 #define DSPFW_SPRITED_HI_SHIFT 20 4503 #define DSPFW_SPRITED_HI_MASK (1<<20) 4504 #define DSPFW_SPRITEC_HI_SHIFT 16 4505 #define DSPFW_SPRITEC_HI_MASK (1<<16) 4506 #define DSPFW_PLANEB_HI_SHIFT 12 4507 #define DSPFW_PLANEB_HI_MASK (1<<12) 4508 #define DSPFW_SPRITEB_HI_SHIFT 8 4509 #define DSPFW_SPRITEB_HI_MASK (1<<8) 4510 #define DSPFW_SPRITEA_HI_SHIFT 4 4511 #define DSPFW_SPRITEA_HI_MASK (1<<4) 4512 #define DSPFW_PLANEA_HI_SHIFT 0 4513 #define DSPFW_PLANEA_HI_MASK (1<<0) 4514 #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068) 4515 #define DSPFW_SR_WM1_HI_SHIFT 24 4516 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 4517 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 4518 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) 4519 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 4520 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) 4521 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 4522 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) 4523 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 4524 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) 4525 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 4526 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) 4527 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 4528 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) 4529 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 4530 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) 4531 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 4532 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) 4533 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 4534 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) 4535 4536 /* drain latency register values*/ 4537 #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 4538 #define DDL_CURSOR_SHIFT 24 4539 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) 4540 #define DDL_PLANE_SHIFT 0 4541 #define DDL_PRECISION_HIGH (1<<7) 4542 #define DDL_PRECISION_LOW (0<<7) 4543 #define DRAIN_LATENCY_MASK 0x7f 4544 4545 #define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400) 4546 #define CBR_PND_DEADLINE_DISABLE (1<<31) 4547 4548 /* FIFO watermark sizes etc */ 4549 #define G4X_FIFO_LINE_SIZE 64 4550 #define I915_FIFO_LINE_SIZE 64 4551 #define I830_FIFO_LINE_SIZE 32 4552 4553 #define VALLEYVIEW_FIFO_SIZE 255 4554 #define G4X_FIFO_SIZE 127 4555 #define I965_FIFO_SIZE 512 4556 #define I945_FIFO_SIZE 127 4557 #define I915_FIFO_SIZE 95 4558 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 4559 #define I830_FIFO_SIZE 95 4560 4561 #define VALLEYVIEW_MAX_WM 0xff 4562 #define G4X_MAX_WM 0x3f 4563 #define I915_MAX_WM 0x3f 4564 4565 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4566 #define PINEVIEW_FIFO_LINE_SIZE 64 4567 #define PINEVIEW_MAX_WM 0x1ff 4568 #define PINEVIEW_DFT_WM 0x3f 4569 #define PINEVIEW_DFT_HPLLOFF_WM 0 4570 #define PINEVIEW_GUARD_WM 10 4571 #define PINEVIEW_CURSOR_FIFO 64 4572 #define PINEVIEW_CURSOR_MAX_WM 0x3f 4573 #define PINEVIEW_CURSOR_DFT_WM 0 4574 #define PINEVIEW_CURSOR_GUARD_WM 5 4575 4576 #define VALLEYVIEW_CURSOR_MAX_WM 64 4577 #define I965_CURSOR_FIFO 64 4578 #define I965_CURSOR_MAX_WM 32 4579 #define I965_CURSOR_DFT_WM 8 4580 4581 /* Watermark register definitions for SKL */ 4582 #define CUR_WM_A_0 0x70140 4583 #define CUR_WM_B_0 0x71140 4584 #define PLANE_WM_1_A_0 0x70240 4585 #define PLANE_WM_1_B_0 0x71240 4586 #define PLANE_WM_2_A_0 0x70340 4587 #define PLANE_WM_2_B_0 0x71340 4588 #define PLANE_WM_TRANS_1_A_0 0x70268 4589 #define PLANE_WM_TRANS_1_B_0 0x71268 4590 #define PLANE_WM_TRANS_2_A_0 0x70368 4591 #define PLANE_WM_TRANS_2_B_0 0x71368 4592 #define CUR_WM_TRANS_A_0 0x70168 4593 #define CUR_WM_TRANS_B_0 0x71168 4594 #define PLANE_WM_EN (1 << 31) 4595 #define PLANE_WM_LINES_SHIFT 14 4596 #define PLANE_WM_LINES_MASK 0x1f 4597 #define PLANE_WM_BLOCKS_MASK 0x3ff 4598 4599 #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0) 4600 #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level))) 4601 #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0) 4602 4603 #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0) 4604 #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0) 4605 #define _PLANE_WM_BASE(pipe, plane) \ 4606 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 4607 #define PLANE_WM(pipe, plane, level) \ 4608 (_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 4609 #define _PLANE_WM_TRANS_1(pipe) \ 4610 _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0) 4611 #define _PLANE_WM_TRANS_2(pipe) \ 4612 _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0) 4613 #define PLANE_WM_TRANS(pipe, plane) \ 4614 _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)) 4615 4616 /* define the Watermark register on Ironlake */ 4617 #define WM0_PIPEA_ILK 0x45100 4618 #define WM0_PIPE_PLANE_MASK (0xffff<<16) 4619 #define WM0_PIPE_PLANE_SHIFT 16 4620 #define WM0_PIPE_SPRITE_MASK (0xff<<8) 4621 #define WM0_PIPE_SPRITE_SHIFT 8 4622 #define WM0_PIPE_CURSOR_MASK (0xff) 4623 4624 #define WM0_PIPEB_ILK 0x45104 4625 #define WM0_PIPEC_IVB 0x45200 4626 #define WM1_LP_ILK 0x45108 4627 #define WM1_LP_SR_EN (1<<31) 4628 #define WM1_LP_LATENCY_SHIFT 24 4629 #define WM1_LP_LATENCY_MASK (0x7f<<24) 4630 #define WM1_LP_FBC_MASK (0xf<<20) 4631 #define WM1_LP_FBC_SHIFT 20 4632 #define WM1_LP_FBC_SHIFT_BDW 19 4633 #define WM1_LP_SR_MASK (0x7ff<<8) 4634 #define WM1_LP_SR_SHIFT 8 4635 #define WM1_LP_CURSOR_MASK (0xff) 4636 #define WM2_LP_ILK 0x4510c 4637 #define WM2_LP_EN (1<<31) 4638 #define WM3_LP_ILK 0x45110 4639 #define WM3_LP_EN (1<<31) 4640 #define WM1S_LP_ILK 0x45120 4641 #define WM2S_LP_IVB 0x45124 4642 #define WM3S_LP_IVB 0x45128 4643 #define WM1S_LP_EN (1<<31) 4644 4645 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 4646 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 4647 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 4648 4649 /* Memory latency timer register */ 4650 #define MLTR_ILK 0x11222 4651 #define MLTR_WM1_SHIFT 0 4652 #define MLTR_WM2_SHIFT 8 4653 /* the unit of memory self-refresh latency time is 0.5us */ 4654 #define ILK_SRLT_MASK 0x3f 4655 4656 4657 /* the address where we get all kinds of latency value */ 4658 #define SSKPD 0x5d10 4659 #define SSKPD_WM_MASK 0x3f 4660 #define SSKPD_WM0_SHIFT 0 4661 #define SSKPD_WM1_SHIFT 8 4662 #define SSKPD_WM2_SHIFT 16 4663 #define SSKPD_WM3_SHIFT 24 4664 4665 /* 4666 * The two pipe frame counter registers are not synchronized, so 4667 * reading a stable value is somewhat tricky. The following code 4668 * should work: 4669 * 4670 * do { 4671 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4672 * PIPE_FRAME_HIGH_SHIFT; 4673 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4674 * PIPE_FRAME_LOW_SHIFT); 4675 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4676 * PIPE_FRAME_HIGH_SHIFT); 4677 * } while (high1 != high2); 4678 * frame = (high1 << 8) | low1; 4679 */ 4680 #define _PIPEAFRAMEHIGH 0x70040 4681 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 4682 #define PIPE_FRAME_HIGH_SHIFT 0 4683 #define _PIPEAFRAMEPIXEL 0x70044 4684 #define PIPE_FRAME_LOW_MASK 0xff000000 4685 #define PIPE_FRAME_LOW_SHIFT 24 4686 #define PIPE_PIXEL_MASK 0x00ffffff 4687 #define PIPE_PIXEL_SHIFT 0 4688 /* GM45+ just has to be different */ 4689 #define _PIPEA_FRMCOUNT_GM45 0x70040 4690 #define _PIPEA_FLIPCOUNT_GM45 0x70044 4691 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) 4692 #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) 4693 4694 /* Cursor A & B regs */ 4695 #define _CURACNTR 0x70080 4696 /* Old style CUR*CNTR flags (desktop 8xx) */ 4697 #define CURSOR_ENABLE 0x80000000 4698 #define CURSOR_GAMMA_ENABLE 0x40000000 4699 #define CURSOR_STRIDE_SHIFT 28 4700 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 4701 #define CURSOR_PIPE_CSC_ENABLE (1<<24) 4702 #define CURSOR_FORMAT_SHIFT 24 4703 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 4704 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 4705 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 4706 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 4707 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 4708 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 4709 /* New style CUR*CNTR flags */ 4710 #define CURSOR_MODE 0x27 4711 #define CURSOR_MODE_DISABLE 0x00 4712 #define CURSOR_MODE_128_32B_AX 0x02 4713 #define CURSOR_MODE_256_32B_AX 0x03 4714 #define CURSOR_MODE_64_32B_AX 0x07 4715 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) 4716 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) 4717 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 4718 #define MCURSOR_PIPE_SELECT (1 << 28) 4719 #define MCURSOR_PIPE_A 0x00 4720 #define MCURSOR_PIPE_B (1 << 28) 4721 #define MCURSOR_GAMMA_ENABLE (1 << 26) 4722 #define CURSOR_ROTATE_180 (1<<15) 4723 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 4724 #define _CURABASE 0x70084 4725 #define _CURAPOS 0x70088 4726 #define CURSOR_POS_MASK 0x007FF 4727 #define CURSOR_POS_SIGN 0x8000 4728 #define CURSOR_X_SHIFT 0 4729 #define CURSOR_Y_SHIFT 16 4730 #define CURSIZE 0x700a0 4731 #define _CURBCNTR 0x700c0 4732 #define _CURBBASE 0x700c4 4733 #define _CURBPOS 0x700c8 4734 4735 #define _CURBCNTR_IVB 0x71080 4736 #define _CURBBASE_IVB 0x71084 4737 #define _CURBPOS_IVB 0x71088 4738 4739 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \ 4740 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ 4741 dev_priv->info.display_mmio_offset) 4742 4743 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 4744 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 4745 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 4746 4747 #define CURSOR_A_OFFSET 0x70080 4748 #define CURSOR_B_OFFSET 0x700c0 4749 #define CHV_CURSOR_C_OFFSET 0x700e0 4750 #define IVB_CURSOR_B_OFFSET 0x71080 4751 #define IVB_CURSOR_C_OFFSET 0x72080 4752 4753 /* Display A control */ 4754 #define _DSPACNTR 0x70180 4755 #define DISPLAY_PLANE_ENABLE (1<<31) 4756 #define DISPLAY_PLANE_DISABLE 0 4757 #define DISPPLANE_GAMMA_ENABLE (1<<30) 4758 #define DISPPLANE_GAMMA_DISABLE 0 4759 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 4760 #define DISPPLANE_YUV422 (0x0<<26) 4761 #define DISPPLANE_8BPP (0x2<<26) 4762 #define DISPPLANE_BGRA555 (0x3<<26) 4763 #define DISPPLANE_BGRX555 (0x4<<26) 4764 #define DISPPLANE_BGRX565 (0x5<<26) 4765 #define DISPPLANE_BGRX888 (0x6<<26) 4766 #define DISPPLANE_BGRA888 (0x7<<26) 4767 #define DISPPLANE_RGBX101010 (0x8<<26) 4768 #define DISPPLANE_RGBA101010 (0x9<<26) 4769 #define DISPPLANE_BGRX101010 (0xa<<26) 4770 #define DISPPLANE_RGBX161616 (0xc<<26) 4771 #define DISPPLANE_RGBX888 (0xe<<26) 4772 #define DISPPLANE_RGBA888 (0xf<<26) 4773 #define DISPPLANE_STEREO_ENABLE (1<<25) 4774 #define DISPPLANE_STEREO_DISABLE 0 4775 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) 4776 #define DISPPLANE_SEL_PIPE_SHIFT 24 4777 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 4778 #define DISPPLANE_SEL_PIPE_A 0 4779 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 4780 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 4781 #define DISPPLANE_SRC_KEY_DISABLE 0 4782 #define DISPPLANE_LINE_DOUBLE (1<<20) 4783 #define DISPPLANE_NO_LINE_DOUBLE 0 4784 #define DISPPLANE_STEREO_POLARITY_FIRST 0 4785 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 4786 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ 4787 #define DISPPLANE_ROTATE_180 (1<<15) 4788 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 4789 #define DISPPLANE_TILED (1<<10) 4790 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ 4791 #define _DSPAADDR 0x70184 4792 #define _DSPASTRIDE 0x70188 4793 #define _DSPAPOS 0x7018C /* reserved */ 4794 #define _DSPASIZE 0x70190 4795 #define _DSPASURF 0x7019C /* 965+ only */ 4796 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 4797 #define _DSPAOFFSET 0x701A4 /* HSW */ 4798 #define _DSPASURFLIVE 0x701AC 4799 4800 #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) 4801 #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) 4802 #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) 4803 #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) 4804 #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) 4805 #define DSPSURF(plane) _PIPE2(plane, _DSPASURF) 4806 #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) 4807 #define DSPLINOFF(plane) DSPADDR(plane) 4808 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) 4809 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) 4810 4811 /* CHV pipe B blender and primary plane */ 4812 #define _CHV_BLEND_A 0x60a00 4813 #define CHV_BLEND_LEGACY (0<<30) 4814 #define CHV_BLEND_ANDROID (1<<30) 4815 #define CHV_BLEND_MPO (2<<30) 4816 #define CHV_BLEND_MASK (3<<30) 4817 #define _CHV_CANVAS_A 0x60a04 4818 #define _PRIMPOS_A 0x60a08 4819 #define _PRIMSIZE_A 0x60a0c 4820 #define _PRIMCNSTALPHA_A 0x60a10 4821 #define PRIM_CONST_ALPHA_ENABLE (1<<31) 4822 4823 #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A) 4824 #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A) 4825 #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A) 4826 #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A) 4827 #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A) 4828 4829 /* Display/Sprite base address macros */ 4830 #define DISP_BASEADDR_MASK (0xfffff000) 4831 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 4832 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 4833 4834 /* VBIOS flags */ 4835 #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) 4836 #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) 4837 #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) 4838 #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) 4839 #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) 4840 #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) 4841 #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) 4842 #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) 4843 #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) 4844 #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) 4845 #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) 4846 #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) 4847 #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) 4848 4849 /* Pipe B */ 4850 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) 4851 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) 4852 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) 4853 #define _PIPEBFRAMEHIGH 0x71040 4854 #define _PIPEBFRAMEPIXEL 0x71044 4855 #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) 4856 #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) 4857 4858 4859 /* Display B control */ 4860 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) 4861 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 4862 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 4863 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 4864 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 4865 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) 4866 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) 4867 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) 4868 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) 4869 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) 4870 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) 4871 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) 4872 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) 4873 4874 /* Sprite A control */ 4875 #define _DVSACNTR 0x72180 4876 #define DVS_ENABLE (1<<31) 4877 #define DVS_GAMMA_ENABLE (1<<30) 4878 #define DVS_PIXFORMAT_MASK (3<<25) 4879 #define DVS_FORMAT_YUV422 (0<<25) 4880 #define DVS_FORMAT_RGBX101010 (1<<25) 4881 #define DVS_FORMAT_RGBX888 (2<<25) 4882 #define DVS_FORMAT_RGBX161616 (3<<25) 4883 #define DVS_PIPE_CSC_ENABLE (1<<24) 4884 #define DVS_SOURCE_KEY (1<<22) 4885 #define DVS_RGB_ORDER_XBGR (1<<20) 4886 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 4887 #define DVS_YUV_ORDER_YUYV (0<<16) 4888 #define DVS_YUV_ORDER_UYVY (1<<16) 4889 #define DVS_YUV_ORDER_YVYU (2<<16) 4890 #define DVS_YUV_ORDER_VYUY (3<<16) 4891 #define DVS_ROTATE_180 (1<<15) 4892 #define DVS_DEST_KEY (1<<2) 4893 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 4894 #define DVS_TILED (1<<10) 4895 #define _DVSALINOFF 0x72184 4896 #define _DVSASTRIDE 0x72188 4897 #define _DVSAPOS 0x7218c 4898 #define _DVSASIZE 0x72190 4899 #define _DVSAKEYVAL 0x72194 4900 #define _DVSAKEYMSK 0x72198 4901 #define _DVSASURF 0x7219c 4902 #define _DVSAKEYMAXVAL 0x721a0 4903 #define _DVSATILEOFF 0x721a4 4904 #define _DVSASURFLIVE 0x721ac 4905 #define _DVSASCALE 0x72204 4906 #define DVS_SCALE_ENABLE (1<<31) 4907 #define DVS_FILTER_MASK (3<<29) 4908 #define DVS_FILTER_MEDIUM (0<<29) 4909 #define DVS_FILTER_ENHANCING (1<<29) 4910 #define DVS_FILTER_SOFTENING (2<<29) 4911 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 4912 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 4913 #define _DVSAGAMC 0x72300 4914 4915 #define _DVSBCNTR 0x73180 4916 #define _DVSBLINOFF 0x73184 4917 #define _DVSBSTRIDE 0x73188 4918 #define _DVSBPOS 0x7318c 4919 #define _DVSBSIZE 0x73190 4920 #define _DVSBKEYVAL 0x73194 4921 #define _DVSBKEYMSK 0x73198 4922 #define _DVSBSURF 0x7319c 4923 #define _DVSBKEYMAXVAL 0x731a0 4924 #define _DVSBTILEOFF 0x731a4 4925 #define _DVSBSURFLIVE 0x731ac 4926 #define _DVSBSCALE 0x73204 4927 #define _DVSBGAMC 0x73300 4928 4929 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4930 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4931 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4932 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 4933 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 4934 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4935 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4936 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4937 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4938 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4939 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4940 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4941 4942 #define _SPRA_CTL 0x70280 4943 #define SPRITE_ENABLE (1<<31) 4944 #define SPRITE_GAMMA_ENABLE (1<<30) 4945 #define SPRITE_PIXFORMAT_MASK (7<<25) 4946 #define SPRITE_FORMAT_YUV422 (0<<25) 4947 #define SPRITE_FORMAT_RGBX101010 (1<<25) 4948 #define SPRITE_FORMAT_RGBX888 (2<<25) 4949 #define SPRITE_FORMAT_RGBX161616 (3<<25) 4950 #define SPRITE_FORMAT_YUV444 (4<<25) 4951 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 4952 #define SPRITE_PIPE_CSC_ENABLE (1<<24) 4953 #define SPRITE_SOURCE_KEY (1<<22) 4954 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 4955 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 4956 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 4957 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 4958 #define SPRITE_YUV_ORDER_YUYV (0<<16) 4959 #define SPRITE_YUV_ORDER_UYVY (1<<16) 4960 #define SPRITE_YUV_ORDER_YVYU (2<<16) 4961 #define SPRITE_YUV_ORDER_VYUY (3<<16) 4962 #define SPRITE_ROTATE_180 (1<<15) 4963 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 4964 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 4965 #define SPRITE_TILED (1<<10) 4966 #define SPRITE_DEST_KEY (1<<2) 4967 #define _SPRA_LINOFF 0x70284 4968 #define _SPRA_STRIDE 0x70288 4969 #define _SPRA_POS 0x7028c 4970 #define _SPRA_SIZE 0x70290 4971 #define _SPRA_KEYVAL 0x70294 4972 #define _SPRA_KEYMSK 0x70298 4973 #define _SPRA_SURF 0x7029c 4974 #define _SPRA_KEYMAX 0x702a0 4975 #define _SPRA_TILEOFF 0x702a4 4976 #define _SPRA_OFFSET 0x702a4 4977 #define _SPRA_SURFLIVE 0x702ac 4978 #define _SPRA_SCALE 0x70304 4979 #define SPRITE_SCALE_ENABLE (1<<31) 4980 #define SPRITE_FILTER_MASK (3<<29) 4981 #define SPRITE_FILTER_MEDIUM (0<<29) 4982 #define SPRITE_FILTER_ENHANCING (1<<29) 4983 #define SPRITE_FILTER_SOFTENING (2<<29) 4984 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 4985 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 4986 #define _SPRA_GAMC 0x70400 4987 4988 #define _SPRB_CTL 0x71280 4989 #define _SPRB_LINOFF 0x71284 4990 #define _SPRB_STRIDE 0x71288 4991 #define _SPRB_POS 0x7128c 4992 #define _SPRB_SIZE 0x71290 4993 #define _SPRB_KEYVAL 0x71294 4994 #define _SPRB_KEYMSK 0x71298 4995 #define _SPRB_SURF 0x7129c 4996 #define _SPRB_KEYMAX 0x712a0 4997 #define _SPRB_TILEOFF 0x712a4 4998 #define _SPRB_OFFSET 0x712a4 4999 #define _SPRB_SURFLIVE 0x712ac 5000 #define _SPRB_SCALE 0x71304 5001 #define _SPRB_GAMC 0x71400 5002 5003 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 5004 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 5005 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 5006 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 5007 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 5008 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 5009 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 5010 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 5011 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 5012 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 5013 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 5014 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 5015 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 5016 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 5017 5018 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 5019 #define SP_ENABLE (1<<31) 5020 #define SP_GAMMA_ENABLE (1<<30) 5021 #define SP_PIXFORMAT_MASK (0xf<<26) 5022 #define SP_FORMAT_YUV422 (0<<26) 5023 #define SP_FORMAT_BGR565 (5<<26) 5024 #define SP_FORMAT_BGRX8888 (6<<26) 5025 #define SP_FORMAT_BGRA8888 (7<<26) 5026 #define SP_FORMAT_RGBX1010102 (8<<26) 5027 #define SP_FORMAT_RGBA1010102 (9<<26) 5028 #define SP_FORMAT_RGBX8888 (0xe<<26) 5029 #define SP_FORMAT_RGBA8888 (0xf<<26) 5030 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ 5031 #define SP_SOURCE_KEY (1<<22) 5032 #define SP_YUV_BYTE_ORDER_MASK (3<<16) 5033 #define SP_YUV_ORDER_YUYV (0<<16) 5034 #define SP_YUV_ORDER_UYVY (1<<16) 5035 #define SP_YUV_ORDER_YVYU (2<<16) 5036 #define SP_YUV_ORDER_VYUY (3<<16) 5037 #define SP_ROTATE_180 (1<<15) 5038 #define SP_TILED (1<<10) 5039 #define SP_MIRROR (1<<8) /* CHV pipe B */ 5040 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 5041 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 5042 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 5043 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 5044 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 5045 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 5046 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 5047 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 5048 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 5049 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 5050 #define SP_CONST_ALPHA_ENABLE (1<<31) 5051 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 5052 5053 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 5054 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 5055 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 5056 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 5057 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 5058 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 5059 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 5060 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 5061 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 5062 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 5063 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 5064 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 5065 5066 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) 5067 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) 5068 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) 5069 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) 5070 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) 5071 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) 5072 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) 5073 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) 5074 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) 5075 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) 5076 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) 5077 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) 5078 5079 /* 5080 * CHV pipe B sprite CSC 5081 * 5082 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 5083 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 5084 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 5085 */ 5086 #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000) 5087 #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000) 5088 #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000) 5089 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 5090 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 5091 5092 #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000) 5093 #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000) 5094 #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000) 5095 #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000) 5096 #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000) 5097 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 5098 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 5099 5100 #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000) 5101 #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000) 5102 #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000) 5103 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 5104 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 5105 5106 #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000) 5107 #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000) 5108 #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000) 5109 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 5110 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 5111 5112 /* Skylake plane registers */ 5113 5114 #define _PLANE_CTL_1_A 0x70180 5115 #define _PLANE_CTL_2_A 0x70280 5116 #define _PLANE_CTL_3_A 0x70380 5117 #define PLANE_CTL_ENABLE (1 << 31) 5118 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) 5119 #define PLANE_CTL_FORMAT_MASK (0xf << 24) 5120 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) 5121 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) 5122 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) 5123 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) 5124 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) 5125 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) 5126 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) 5127 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) 5128 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) 5129 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 5130 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) 5131 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) 5132 #define PLANE_CTL_ORDER_BGRX (0 << 20) 5133 #define PLANE_CTL_ORDER_RGBX (1 << 20) 5134 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 5135 #define PLANE_CTL_YUV422_YUYV ( 0 << 16) 5136 #define PLANE_CTL_YUV422_UYVY ( 1 << 16) 5137 #define PLANE_CTL_YUV422_YVYU ( 2 << 16) 5138 #define PLANE_CTL_YUV422_VYUY ( 3 << 16) 5139 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) 5140 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 5141 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) 5142 #define PLANE_CTL_TILED_MASK (0x7 << 10) 5143 #define PLANE_CTL_TILED_LINEAR ( 0 << 10) 5144 #define PLANE_CTL_TILED_X ( 1 << 10) 5145 #define PLANE_CTL_TILED_Y ( 4 << 10) 5146 #define PLANE_CTL_TILED_YF ( 5 << 10) 5147 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) 5148 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) 5149 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) 5150 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) 5151 #define PLANE_CTL_ROTATE_MASK 0x3 5152 #define PLANE_CTL_ROTATE_0 0x0 5153 #define PLANE_CTL_ROTATE_90 0x1 5154 #define PLANE_CTL_ROTATE_180 0x2 5155 #define PLANE_CTL_ROTATE_270 0x3 5156 #define _PLANE_STRIDE_1_A 0x70188 5157 #define _PLANE_STRIDE_2_A 0x70288 5158 #define _PLANE_STRIDE_3_A 0x70388 5159 #define _PLANE_POS_1_A 0x7018c 5160 #define _PLANE_POS_2_A 0x7028c 5161 #define _PLANE_POS_3_A 0x7038c 5162 #define _PLANE_SIZE_1_A 0x70190 5163 #define _PLANE_SIZE_2_A 0x70290 5164 #define _PLANE_SIZE_3_A 0x70390 5165 #define _PLANE_SURF_1_A 0x7019c 5166 #define _PLANE_SURF_2_A 0x7029c 5167 #define _PLANE_SURF_3_A 0x7039c 5168 #define _PLANE_OFFSET_1_A 0x701a4 5169 #define _PLANE_OFFSET_2_A 0x702a4 5170 #define _PLANE_OFFSET_3_A 0x703a4 5171 #define _PLANE_KEYVAL_1_A 0x70194 5172 #define _PLANE_KEYVAL_2_A 0x70294 5173 #define _PLANE_KEYMSK_1_A 0x70198 5174 #define _PLANE_KEYMSK_2_A 0x70298 5175 #define _PLANE_KEYMAX_1_A 0x701a0 5176 #define _PLANE_KEYMAX_2_A 0x702a0 5177 #define _PLANE_BUF_CFG_1_A 0x7027c 5178 #define _PLANE_BUF_CFG_2_A 0x7037c 5179 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 5180 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 5181 5182 #define _PLANE_CTL_1_B 0x71180 5183 #define _PLANE_CTL_2_B 0x71280 5184 #define _PLANE_CTL_3_B 0x71380 5185 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 5186 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 5187 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 5188 #define PLANE_CTL(pipe, plane) \ 5189 _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 5190 5191 #define _PLANE_STRIDE_1_B 0x71188 5192 #define _PLANE_STRIDE_2_B 0x71288 5193 #define _PLANE_STRIDE_3_B 0x71388 5194 #define _PLANE_STRIDE_1(pipe) \ 5195 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 5196 #define _PLANE_STRIDE_2(pipe) \ 5197 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 5198 #define _PLANE_STRIDE_3(pipe) \ 5199 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 5200 #define PLANE_STRIDE(pipe, plane) \ 5201 _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 5202 5203 #define _PLANE_POS_1_B 0x7118c 5204 #define _PLANE_POS_2_B 0x7128c 5205 #define _PLANE_POS_3_B 0x7138c 5206 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 5207 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 5208 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 5209 #define PLANE_POS(pipe, plane) \ 5210 _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 5211 5212 #define _PLANE_SIZE_1_B 0x71190 5213 #define _PLANE_SIZE_2_B 0x71290 5214 #define _PLANE_SIZE_3_B 0x71390 5215 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 5216 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 5217 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 5218 #define PLANE_SIZE(pipe, plane) \ 5219 _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 5220 5221 #define _PLANE_SURF_1_B 0x7119c 5222 #define _PLANE_SURF_2_B 0x7129c 5223 #define _PLANE_SURF_3_B 0x7139c 5224 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 5225 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 5226 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 5227 #define PLANE_SURF(pipe, plane) \ 5228 _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 5229 5230 #define _PLANE_OFFSET_1_B 0x711a4 5231 #define _PLANE_OFFSET_2_B 0x712a4 5232 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 5233 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 5234 #define PLANE_OFFSET(pipe, plane) \ 5235 _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 5236 5237 #define _PLANE_KEYVAL_1_B 0x71194 5238 #define _PLANE_KEYVAL_2_B 0x71294 5239 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 5240 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 5241 #define PLANE_KEYVAL(pipe, plane) \ 5242 _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 5243 5244 #define _PLANE_KEYMSK_1_B 0x71198 5245 #define _PLANE_KEYMSK_2_B 0x71298 5246 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 5247 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 5248 #define PLANE_KEYMSK(pipe, plane) \ 5249 _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 5250 5251 #define _PLANE_KEYMAX_1_B 0x711a0 5252 #define _PLANE_KEYMAX_2_B 0x712a0 5253 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 5254 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 5255 #define PLANE_KEYMAX(pipe, plane) \ 5256 _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 5257 5258 #define _PLANE_BUF_CFG_1_B 0x7127c 5259 #define _PLANE_BUF_CFG_2_B 0x7137c 5260 #define _PLANE_BUF_CFG_1(pipe) \ 5261 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 5262 #define _PLANE_BUF_CFG_2(pipe) \ 5263 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 5264 #define PLANE_BUF_CFG(pipe, plane) \ 5265 _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 5266 5267 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 5268 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 5269 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 5270 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 5271 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 5272 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 5273 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 5274 _PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 5275 5276 /* SKL new cursor registers */ 5277 #define _CUR_BUF_CFG_A 0x7017c 5278 #define _CUR_BUF_CFG_B 0x7117c 5279 #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 5280 5281 /* VBIOS regs */ 5282 #define VGACNTRL 0x71400 5283 # define VGA_DISP_DISABLE (1 << 31) 5284 # define VGA_2X_MODE (1 << 30) 5285 # define VGA_PIPE_B_SELECT (1 << 29) 5286 5287 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400) 5288 5289 /* Ironlake */ 5290 5291 #define CPU_VGACNTRL 0x41000 5292 5293 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 5294 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 5295 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 5296 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 5297 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 5298 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 5299 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 5300 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 5301 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 5302 5303 /* refresh rate hardware control */ 5304 #define RR_HW_CTL 0x45300 5305 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 5306 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 5307 5308 #define FDI_PLL_BIOS_0 0x46000 5309 #define FDI_PLL_FB_CLOCK_MASK 0xff 5310 #define FDI_PLL_BIOS_1 0x46004 5311 #define FDI_PLL_BIOS_2 0x46008 5312 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 5313 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 5314 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 5315 5316 #define PCH_3DCGDIS0 0x46020 5317 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 5318 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 5319 5320 #define PCH_3DCGDIS1 0x46024 5321 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 5322 5323 #define FDI_PLL_FREQ_CTL 0x46030 5324 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 5325 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 5326 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 5327 5328 5329 #define _PIPEA_DATA_M1 0x60030 5330 #define PIPE_DATA_M1_OFFSET 0 5331 #define _PIPEA_DATA_N1 0x60034 5332 #define PIPE_DATA_N1_OFFSET 0 5333 5334 #define _PIPEA_DATA_M2 0x60038 5335 #define PIPE_DATA_M2_OFFSET 0 5336 #define _PIPEA_DATA_N2 0x6003c 5337 #define PIPE_DATA_N2_OFFSET 0 5338 5339 #define _PIPEA_LINK_M1 0x60040 5340 #define PIPE_LINK_M1_OFFSET 0 5341 #define _PIPEA_LINK_N1 0x60044 5342 #define PIPE_LINK_N1_OFFSET 0 5343 5344 #define _PIPEA_LINK_M2 0x60048 5345 #define PIPE_LINK_M2_OFFSET 0 5346 #define _PIPEA_LINK_N2 0x6004c 5347 #define PIPE_LINK_N2_OFFSET 0 5348 5349 /* PIPEB timing regs are same start from 0x61000 */ 5350 5351 #define _PIPEB_DATA_M1 0x61030 5352 #define _PIPEB_DATA_N1 0x61034 5353 #define _PIPEB_DATA_M2 0x61038 5354 #define _PIPEB_DATA_N2 0x6103c 5355 #define _PIPEB_LINK_M1 0x61040 5356 #define _PIPEB_LINK_N1 0x61044 5357 #define _PIPEB_LINK_M2 0x61048 5358 #define _PIPEB_LINK_N2 0x6104c 5359 5360 #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) 5361 #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) 5362 #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) 5363 #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) 5364 #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) 5365 #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) 5366 #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) 5367 #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) 5368 5369 /* CPU panel fitter */ 5370 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 5371 #define _PFA_CTL_1 0x68080 5372 #define _PFB_CTL_1 0x68880 5373 #define PF_ENABLE (1<<31) 5374 #define PF_PIPE_SEL_MASK_IVB (3<<29) 5375 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 5376 #define PF_FILTER_MASK (3<<23) 5377 #define PF_FILTER_PROGRAMMED (0<<23) 5378 #define PF_FILTER_MED_3x3 (1<<23) 5379 #define PF_FILTER_EDGE_ENHANCE (2<<23) 5380 #define PF_FILTER_EDGE_SOFTEN (3<<23) 5381 #define _PFA_WIN_SZ 0x68074 5382 #define _PFB_WIN_SZ 0x68874 5383 #define _PFA_WIN_POS 0x68070 5384 #define _PFB_WIN_POS 0x68870 5385 #define _PFA_VSCALE 0x68084 5386 #define _PFB_VSCALE 0x68884 5387 #define _PFA_HSCALE 0x68090 5388 #define _PFB_HSCALE 0x68890 5389 5390 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 5391 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 5392 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 5393 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 5394 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 5395 5396 #define _PSA_CTL 0x68180 5397 #define _PSB_CTL 0x68980 5398 #define PS_ENABLE (1<<31) 5399 #define _PSA_WIN_SZ 0x68174 5400 #define _PSB_WIN_SZ 0x68974 5401 #define _PSA_WIN_POS 0x68170 5402 #define _PSB_WIN_POS 0x68970 5403 5404 #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL) 5405 #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 5406 #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 5407 5408 /* 5409 * Skylake scalers 5410 */ 5411 #define _PS_1A_CTRL 0x68180 5412 #define _PS_2A_CTRL 0x68280 5413 #define _PS_1B_CTRL 0x68980 5414 #define _PS_2B_CTRL 0x68A80 5415 #define _PS_1C_CTRL 0x69180 5416 #define PS_SCALER_EN (1 << 31) 5417 #define PS_SCALER_MODE_MASK (3 << 28) 5418 #define PS_SCALER_MODE_DYN (0 << 28) 5419 #define PS_SCALER_MODE_HQ (1 << 28) 5420 #define PS_PLANE_SEL_MASK (7 << 25) 5421 #define PS_PLANE_SEL(plane) ((plane + 1) << 25) 5422 #define PS_FILTER_MASK (3 << 23) 5423 #define PS_FILTER_MEDIUM (0 << 23) 5424 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 5425 #define PS_FILTER_BILINEAR (3 << 23) 5426 #define PS_VERT3TAP (1 << 21) 5427 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 5428 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 5429 #define PS_PWRUP_PROGRESS (1 << 17) 5430 #define PS_V_FILTER_BYPASS (1 << 8) 5431 #define PS_VADAPT_EN (1 << 7) 5432 #define PS_VADAPT_MODE_MASK (3 << 5) 5433 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 5434 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 5435 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 5436 5437 #define _PS_PWR_GATE_1A 0x68160 5438 #define _PS_PWR_GATE_2A 0x68260 5439 #define _PS_PWR_GATE_1B 0x68960 5440 #define _PS_PWR_GATE_2B 0x68A60 5441 #define _PS_PWR_GATE_1C 0x69160 5442 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 5443 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 5444 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 5445 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 5446 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 5447 #define PS_PWR_GATE_SLPEN_8 0 5448 #define PS_PWR_GATE_SLPEN_16 1 5449 #define PS_PWR_GATE_SLPEN_24 2 5450 #define PS_PWR_GATE_SLPEN_32 3 5451 5452 #define _PS_WIN_POS_1A 0x68170 5453 #define _PS_WIN_POS_2A 0x68270 5454 #define _PS_WIN_POS_1B 0x68970 5455 #define _PS_WIN_POS_2B 0x68A70 5456 #define _PS_WIN_POS_1C 0x69170 5457 5458 #define _PS_WIN_SZ_1A 0x68174 5459 #define _PS_WIN_SZ_2A 0x68274 5460 #define _PS_WIN_SZ_1B 0x68974 5461 #define _PS_WIN_SZ_2B 0x68A74 5462 #define _PS_WIN_SZ_1C 0x69174 5463 5464 #define _PS_VSCALE_1A 0x68184 5465 #define _PS_VSCALE_2A 0x68284 5466 #define _PS_VSCALE_1B 0x68984 5467 #define _PS_VSCALE_2B 0x68A84 5468 #define _PS_VSCALE_1C 0x69184 5469 5470 #define _PS_HSCALE_1A 0x68190 5471 #define _PS_HSCALE_2A 0x68290 5472 #define _PS_HSCALE_1B 0x68990 5473 #define _PS_HSCALE_2B 0x68A90 5474 #define _PS_HSCALE_1C 0x69190 5475 5476 #define _PS_VPHASE_1A 0x68188 5477 #define _PS_VPHASE_2A 0x68288 5478 #define _PS_VPHASE_1B 0x68988 5479 #define _PS_VPHASE_2B 0x68A88 5480 #define _PS_VPHASE_1C 0x69188 5481 5482 #define _PS_HPHASE_1A 0x68194 5483 #define _PS_HPHASE_2A 0x68294 5484 #define _PS_HPHASE_1B 0x68994 5485 #define _PS_HPHASE_2B 0x68A94 5486 #define _PS_HPHASE_1C 0x69194 5487 5488 #define _PS_ECC_STAT_1A 0x681D0 5489 #define _PS_ECC_STAT_2A 0x682D0 5490 #define _PS_ECC_STAT_1B 0x689D0 5491 #define _PS_ECC_STAT_2B 0x68AD0 5492 #define _PS_ECC_STAT_1C 0x691D0 5493 5494 #define _ID(id, a, b) ((a) + (id)*((b)-(a))) 5495 #define SKL_PS_CTRL(pipe, id) _PIPE(pipe, \ 5496 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 5497 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 5498 #define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe, \ 5499 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 5500 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 5501 #define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe, \ 5502 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 5503 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 5504 #define SKL_PS_WIN_SZ(pipe, id) _PIPE(pipe, \ 5505 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 5506 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 5507 #define SKL_PS_VSCALE(pipe, id) _PIPE(pipe, \ 5508 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 5509 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 5510 #define SKL_PS_HSCALE(pipe, id) _PIPE(pipe, \ 5511 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 5512 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 5513 #define SKL_PS_VPHASE(pipe, id) _PIPE(pipe, \ 5514 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 5515 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 5516 #define SKL_PS_HPHASE(pipe, id) _PIPE(pipe, \ 5517 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 5518 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 5519 #define SKL_PS_ECC_STAT(pipe, id) _PIPE(pipe, \ 5520 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 5521 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B) 5522 5523 /* legacy palette */ 5524 #define _LGC_PALETTE_A 0x4a000 5525 #define _LGC_PALETTE_B 0x4a800 5526 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 5527 5528 #define _GAMMA_MODE_A 0x4a480 5529 #define _GAMMA_MODE_B 0x4ac80 5530 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 5531 #define GAMMA_MODE_MODE_MASK (3 << 0) 5532 #define GAMMA_MODE_MODE_8BIT (0 << 0) 5533 #define GAMMA_MODE_MODE_10BIT (1 << 0) 5534 #define GAMMA_MODE_MODE_12BIT (2 << 0) 5535 #define GAMMA_MODE_MODE_SPLIT (3 << 0) 5536 5537 /* interrupts */ 5538 #define DE_MASTER_IRQ_CONTROL (1 << 31) 5539 #define DE_SPRITEB_FLIP_DONE (1 << 29) 5540 #define DE_SPRITEA_FLIP_DONE (1 << 28) 5541 #define DE_PLANEB_FLIP_DONE (1 << 27) 5542 #define DE_PLANEA_FLIP_DONE (1 << 26) 5543 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 5544 #define DE_PCU_EVENT (1 << 25) 5545 #define DE_GTT_FAULT (1 << 24) 5546 #define DE_POISON (1 << 23) 5547 #define DE_PERFORM_COUNTER (1 << 22) 5548 #define DE_PCH_EVENT (1 << 21) 5549 #define DE_AUX_CHANNEL_A (1 << 20) 5550 #define DE_DP_A_HOTPLUG (1 << 19) 5551 #define DE_GSE (1 << 18) 5552 #define DE_PIPEB_VBLANK (1 << 15) 5553 #define DE_PIPEB_EVEN_FIELD (1 << 14) 5554 #define DE_PIPEB_ODD_FIELD (1 << 13) 5555 #define DE_PIPEB_LINE_COMPARE (1 << 12) 5556 #define DE_PIPEB_VSYNC (1 << 11) 5557 #define DE_PIPEB_CRC_DONE (1 << 10) 5558 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 5559 #define DE_PIPEA_VBLANK (1 << 7) 5560 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) 5561 #define DE_PIPEA_EVEN_FIELD (1 << 6) 5562 #define DE_PIPEA_ODD_FIELD (1 << 5) 5563 #define DE_PIPEA_LINE_COMPARE (1 << 4) 5564 #define DE_PIPEA_VSYNC (1 << 3) 5565 #define DE_PIPEA_CRC_DONE (1 << 2) 5566 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) 5567 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 5568 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) 5569 5570 /* More Ivybridge lolz */ 5571 #define DE_ERR_INT_IVB (1<<30) 5572 #define DE_GSE_IVB (1<<29) 5573 #define DE_PCH_EVENT_IVB (1<<28) 5574 #define DE_DP_A_HOTPLUG_IVB (1<<27) 5575 #define DE_AUX_CHANNEL_A_IVB (1<<26) 5576 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 5577 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 5578 #define DE_PIPEC_VBLANK_IVB (1<<10) 5579 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 5580 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 5581 #define DE_PIPEB_VBLANK_IVB (1<<5) 5582 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 5583 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 5584 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) 5585 #define DE_PIPEA_VBLANK_IVB (1<<0) 5586 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) 5587 5588 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ 5589 #define MASTER_INTERRUPT_ENABLE (1<<31) 5590 5591 #define DEISR 0x44000 5592 #define DEIMR 0x44004 5593 #define DEIIR 0x44008 5594 #define DEIER 0x4400c 5595 5596 #define GTISR 0x44010 5597 #define GTIMR 0x44014 5598 #define GTIIR 0x44018 5599 #define GTIER 0x4401c 5600 5601 #define GEN8_MASTER_IRQ 0x44200 5602 #define GEN8_MASTER_IRQ_CONTROL (1<<31) 5603 #define GEN8_PCU_IRQ (1<<30) 5604 #define GEN8_DE_PCH_IRQ (1<<23) 5605 #define GEN8_DE_MISC_IRQ (1<<22) 5606 #define GEN8_DE_PORT_IRQ (1<<20) 5607 #define GEN8_DE_PIPE_C_IRQ (1<<18) 5608 #define GEN8_DE_PIPE_B_IRQ (1<<17) 5609 #define GEN8_DE_PIPE_A_IRQ (1<<16) 5610 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) 5611 #define GEN8_GT_VECS_IRQ (1<<6) 5612 #define GEN8_GT_PM_IRQ (1<<4) 5613 #define GEN8_GT_VCS2_IRQ (1<<3) 5614 #define GEN8_GT_VCS1_IRQ (1<<2) 5615 #define GEN8_GT_BCS_IRQ (1<<1) 5616 #define GEN8_GT_RCS_IRQ (1<<0) 5617 5618 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) 5619 #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) 5620 #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) 5621 #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) 5622 5623 #define GEN8_BCS_IRQ_SHIFT 16 5624 #define GEN8_RCS_IRQ_SHIFT 0 5625 #define GEN8_VCS2_IRQ_SHIFT 16 5626 #define GEN8_VCS1_IRQ_SHIFT 0 5627 #define GEN8_VECS_IRQ_SHIFT 0 5628 5629 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) 5630 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) 5631 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) 5632 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) 5633 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5634 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5635 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5636 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 5637 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 5638 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 5639 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 5640 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 5641 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 5642 #define GEN8_PIPE_VSYNC (1 << 1) 5643 #define GEN8_PIPE_VBLANK (1 << 0) 5644 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 5645 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 5646 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 5647 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 5648 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 5649 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 5650 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 5651 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 5652 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 5653 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p)) 5654 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 5655 (GEN8_PIPE_CURSOR_FAULT | \ 5656 GEN8_PIPE_SPRITE_FAULT | \ 5657 GEN8_PIPE_PRIMARY_FAULT) 5658 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 5659 (GEN9_PIPE_CURSOR_FAULT | \ 5660 GEN9_PIPE_PLANE4_FAULT | \ 5661 GEN9_PIPE_PLANE3_FAULT | \ 5662 GEN9_PIPE_PLANE2_FAULT | \ 5663 GEN9_PIPE_PLANE1_FAULT) 5664 5665 #define GEN8_DE_PORT_ISR 0x44440 5666 #define GEN8_DE_PORT_IMR 0x44444 5667 #define GEN8_DE_PORT_IIR 0x44448 5668 #define GEN8_DE_PORT_IER 0x4444c 5669 #define GEN9_AUX_CHANNEL_D (1 << 27) 5670 #define GEN9_AUX_CHANNEL_C (1 << 26) 5671 #define GEN9_AUX_CHANNEL_B (1 << 25) 5672 #define BXT_DE_PORT_HP_DDIC (1 << 5) 5673 #define BXT_DE_PORT_HP_DDIB (1 << 4) 5674 #define BXT_DE_PORT_HP_DDIA (1 << 3) 5675 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ 5676 BXT_DE_PORT_HP_DDIB | \ 5677 BXT_DE_PORT_HP_DDIC) 5678 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 5679 #define BXT_DE_PORT_GMBUS (1 << 1) 5680 #define GEN8_AUX_CHANNEL_A (1 << 0) 5681 5682 #define GEN8_DE_MISC_ISR 0x44460 5683 #define GEN8_DE_MISC_IMR 0x44464 5684 #define GEN8_DE_MISC_IIR 0x44468 5685 #define GEN8_DE_MISC_IER 0x4446c 5686 #define GEN8_DE_MISC_GSE (1 << 27) 5687 5688 #define GEN8_PCU_ISR 0x444e0 5689 #define GEN8_PCU_IMR 0x444e4 5690 #define GEN8_PCU_IIR 0x444e8 5691 #define GEN8_PCU_IER 0x444ec 5692 5693 /* BXT hotplug control */ 5694 #define BXT_HOTPLUG_CTL 0xC4030 5695 #define BXT_DDIA_HPD_ENABLE (1 << 28) 5696 #define BXT_DDIA_HPD_STATUS (3 << 24) 5697 #define BXT_DDIC_HPD_ENABLE (1 << 12) 5698 #define BXT_DDIC_HPD_STATUS (3 << 8) 5699 #define BXT_DDIB_HPD_ENABLE (1 << 4) 5700 #define BXT_DDIB_HPD_STATUS (3 << 0) 5701 #define BXT_HOTPLUG_CTL_MASK (BXT_DDIA_HPD_ENABLE | \ 5702 BXT_DDIB_HPD_ENABLE | \ 5703 BXT_DDIC_HPD_ENABLE) 5704 #define BXT_HPD_STATUS_MASK (BXT_DDIA_HPD_STATUS | \ 5705 BXT_DDIB_HPD_STATUS | \ 5706 BXT_DDIC_HPD_STATUS) 5707 5708 #define ILK_DISPLAY_CHICKEN2 0x42004 5709 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 5710 #define ILK_ELPIN_409_SELECT (1 << 25) 5711 #define ILK_DPARB_GATE (1<<22) 5712 #define ILK_VSDPFD_FULL (1<<21) 5713 #define FUSE_STRAP 0x42014 5714 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 5715 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 5716 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 5717 #define ILK_HDCP_DISABLE (1 << 25) 5718 #define ILK_eDP_A_DISABLE (1 << 24) 5719 #define HSW_CDCLK_LIMIT (1 << 24) 5720 #define ILK_DESKTOP (1 << 23) 5721 5722 #define ILK_DSPCLK_GATE_D 0x42020 5723 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 5724 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 5725 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 5726 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 5727 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 5728 5729 #define IVB_CHICKEN3 0x4200c 5730 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 5731 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 5732 5733 #define CHICKEN_PAR1_1 0x42080 5734 #define DPA_MASK_VBLANK_SRD (1 << 15) 5735 #define FORCE_ARB_IDLE_PLANES (1 << 14) 5736 5737 #define _CHICKEN_PIPESL_1_A 0x420b0 5738 #define _CHICKEN_PIPESL_1_B 0x420b4 5739 #define HSW_FBCQ_DIS (1 << 22) 5740 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 5741 #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 5742 5743 #define DISP_ARB_CTL 0x45000 5744 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 5745 #define DISP_FBC_WM_DIS (1<<15) 5746 #define DISP_ARB_CTL2 0x45004 5747 #define DISP_DATA_PARTITION_5_6 (1<<6) 5748 #define DBUF_CTL 0x45008 5749 #define DBUF_POWER_REQUEST (1<<31) 5750 #define DBUF_POWER_STATE (1<<30) 5751 #define GEN7_MSG_CTL 0x45010 5752 #define WAIT_FOR_PCH_RESET_ACK (1<<1) 5753 #define WAIT_FOR_PCH_FLR_ACK (1<<0) 5754 #define HSW_NDE_RSTWRN_OPT 0x46408 5755 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) 5756 5757 #define FF_SLICE_CS_CHICKEN2 0x20e4 5758 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) 5759 5760 /* GEN7 chicken */ 5761 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 5762 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 5763 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) 5764 #define COMMON_SLICE_CHICKEN2 0x7014 5765 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) 5766 5767 #define HIZ_CHICKEN 0x7018 5768 # define CHV_HZ_8X8_MODE_IN_1X (1<<15) 5769 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3) 5770 5771 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 0x7308 5772 #define DISABLE_PIXEL_MASK_CAMMING (1<<14) 5773 5774 #define GEN7_L3SQCREG1 0xB010 5775 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 5776 5777 #define GEN8_L3SQCREG1 0xB100 5778 #define BDW_WA_L3SQCREG1_DEFAULT 0x784000 5779 5780 #define GEN7_L3CNTLREG1 0xB01C 5781 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 5782 #define GEN7_L3AGDIS (1<<19) 5783 #define GEN7_L3CNTLREG2 0xB020 5784 #define GEN7_L3CNTLREG3 0xB024 5785 5786 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 5787 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 5788 5789 #define GEN7_L3SQCREG4 0xb034 5790 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 5791 5792 #define GEN8_L3SQCREG4 0xb118 5793 #define GEN8_LQSC_RO_PERF_DIS (1<<27) 5794 5795 /* GEN8 chicken */ 5796 #define HDC_CHICKEN0 0x7300 5797 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) 5798 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) 5799 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) 5800 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) 5801 #define HDC_FORCE_NON_COHERENT (1<<4) 5802 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) 5803 5804 /* GEN9 chicken */ 5805 #define SLICE_ECO_CHICKEN0 0x7308 5806 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) 5807 5808 /* WaCatErrorRejectionIssue */ 5809 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 5810 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 5811 5812 #define HSW_SCRATCH1 0xb038 5813 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 5814 5815 #define BDW_SCRATCH1 0xb11c 5816 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2) 5817 5818 /* PCH */ 5819 5820 /* south display engine interrupt: IBX */ 5821 #define SDE_AUDIO_POWER_D (1 << 27) 5822 #define SDE_AUDIO_POWER_C (1 << 26) 5823 #define SDE_AUDIO_POWER_B (1 << 25) 5824 #define SDE_AUDIO_POWER_SHIFT (25) 5825 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 5826 #define SDE_GMBUS (1 << 24) 5827 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 5828 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 5829 #define SDE_AUDIO_HDCP_MASK (3 << 22) 5830 #define SDE_AUDIO_TRANSB (1 << 21) 5831 #define SDE_AUDIO_TRANSA (1 << 20) 5832 #define SDE_AUDIO_TRANS_MASK (3 << 20) 5833 #define SDE_POISON (1 << 19) 5834 /* 18 reserved */ 5835 #define SDE_FDI_RXB (1 << 17) 5836 #define SDE_FDI_RXA (1 << 16) 5837 #define SDE_FDI_MASK (3 << 16) 5838 #define SDE_AUXD (1 << 15) 5839 #define SDE_AUXC (1 << 14) 5840 #define SDE_AUXB (1 << 13) 5841 #define SDE_AUX_MASK (7 << 13) 5842 /* 12 reserved */ 5843 #define SDE_CRT_HOTPLUG (1 << 11) 5844 #define SDE_PORTD_HOTPLUG (1 << 10) 5845 #define SDE_PORTC_HOTPLUG (1 << 9) 5846 #define SDE_PORTB_HOTPLUG (1 << 8) 5847 #define SDE_SDVOB_HOTPLUG (1 << 6) 5848 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 5849 SDE_SDVOB_HOTPLUG | \ 5850 SDE_PORTB_HOTPLUG | \ 5851 SDE_PORTC_HOTPLUG | \ 5852 SDE_PORTD_HOTPLUG) 5853 #define SDE_TRANSB_CRC_DONE (1 << 5) 5854 #define SDE_TRANSB_CRC_ERR (1 << 4) 5855 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 5856 #define SDE_TRANSA_CRC_DONE (1 << 2) 5857 #define SDE_TRANSA_CRC_ERR (1 << 1) 5858 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 5859 #define SDE_TRANS_MASK (0x3f) 5860 5861 /* south display engine interrupt: CPT/PPT */ 5862 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 5863 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 5864 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 5865 #define SDE_AUDIO_POWER_SHIFT_CPT 29 5866 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 5867 #define SDE_AUXD_CPT (1 << 27) 5868 #define SDE_AUXC_CPT (1 << 26) 5869 #define SDE_AUXB_CPT (1 << 25) 5870 #define SDE_AUX_MASK_CPT (7 << 25) 5871 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 5872 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 5873 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 5874 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 5875 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 5876 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 5877 SDE_SDVOB_HOTPLUG_CPT | \ 5878 SDE_PORTD_HOTPLUG_CPT | \ 5879 SDE_PORTC_HOTPLUG_CPT | \ 5880 SDE_PORTB_HOTPLUG_CPT) 5881 #define SDE_GMBUS_CPT (1 << 17) 5882 #define SDE_ERROR_CPT (1 << 16) 5883 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 5884 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 5885 #define SDE_FDI_RXC_CPT (1 << 8) 5886 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 5887 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 5888 #define SDE_FDI_RXB_CPT (1 << 4) 5889 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 5890 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 5891 #define SDE_FDI_RXA_CPT (1 << 0) 5892 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 5893 SDE_AUDIO_CP_REQ_B_CPT | \ 5894 SDE_AUDIO_CP_REQ_A_CPT) 5895 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 5896 SDE_AUDIO_CP_CHG_B_CPT | \ 5897 SDE_AUDIO_CP_CHG_A_CPT) 5898 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 5899 SDE_FDI_RXB_CPT | \ 5900 SDE_FDI_RXA_CPT) 5901 5902 #define SDEISR 0xc4000 5903 #define SDEIMR 0xc4004 5904 #define SDEIIR 0xc4008 5905 #define SDEIER 0xc400c 5906 5907 #define SERR_INT 0xc4040 5908 #define SERR_INT_POISON (1<<31) 5909 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) 5910 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) 5911 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) 5912 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 5913 5914 /* digital port hotplug */ 5915 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 5916 #define PORTD_HOTPLUG_ENABLE (1 << 20) 5917 #define PORTD_PULSE_DURATION_2ms (0) 5918 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 5919 #define PORTD_PULSE_DURATION_6ms (2 << 18) 5920 #define PORTD_PULSE_DURATION_100ms (3 << 18) 5921 #define PORTD_PULSE_DURATION_MASK (3 << 18) 5922 #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) 5923 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 5924 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 5925 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 5926 #define PORTC_HOTPLUG_ENABLE (1 << 12) 5927 #define PORTC_PULSE_DURATION_2ms (0) 5928 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 5929 #define PORTC_PULSE_DURATION_6ms (2 << 10) 5930 #define PORTC_PULSE_DURATION_100ms (3 << 10) 5931 #define PORTC_PULSE_DURATION_MASK (3 << 10) 5932 #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) 5933 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 5934 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 5935 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 5936 #define PORTB_HOTPLUG_ENABLE (1 << 4) 5937 #define PORTB_PULSE_DURATION_2ms (0) 5938 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 5939 #define PORTB_PULSE_DURATION_6ms (2 << 2) 5940 #define PORTB_PULSE_DURATION_100ms (3 << 2) 5941 #define PORTB_PULSE_DURATION_MASK (3 << 2) 5942 #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) 5943 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 5944 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 5945 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 5946 5947 #define PCH_GPIOA 0xc5010 5948 #define PCH_GPIOB 0xc5014 5949 #define PCH_GPIOC 0xc5018 5950 #define PCH_GPIOD 0xc501c 5951 #define PCH_GPIOE 0xc5020 5952 #define PCH_GPIOF 0xc5024 5953 5954 #define PCH_GMBUS0 0xc5100 5955 #define PCH_GMBUS1 0xc5104 5956 #define PCH_GMBUS2 0xc5108 5957 #define PCH_GMBUS3 0xc510c 5958 #define PCH_GMBUS4 0xc5110 5959 #define PCH_GMBUS5 0xc5120 5960 5961 #define _PCH_DPLL_A 0xc6014 5962 #define _PCH_DPLL_B 0xc6018 5963 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 5964 5965 #define _PCH_FPA0 0xc6040 5966 #define FP_CB_TUNE (0x3<<22) 5967 #define _PCH_FPA1 0xc6044 5968 #define _PCH_FPB0 0xc6048 5969 #define _PCH_FPB1 0xc604c 5970 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 5971 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 5972 5973 #define PCH_DPLL_TEST 0xc606c 5974 5975 #define PCH_DREF_CONTROL 0xC6200 5976 #define DREF_CONTROL_MASK 0x7fc3 5977 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 5978 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 5979 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 5980 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 5981 #define DREF_SSC_SOURCE_DISABLE (0<<11) 5982 #define DREF_SSC_SOURCE_ENABLE (2<<11) 5983 #define DREF_SSC_SOURCE_MASK (3<<11) 5984 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 5985 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 5986 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 5987 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 5988 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 5989 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 5990 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 5991 #define DREF_SSC4_DOWNSPREAD (0<<6) 5992 #define DREF_SSC4_CENTERSPREAD (1<<6) 5993 #define DREF_SSC1_DISABLE (0<<1) 5994 #define DREF_SSC1_ENABLE (1<<1) 5995 #define DREF_SSC4_DISABLE (0) 5996 #define DREF_SSC4_ENABLE (1) 5997 5998 #define PCH_RAWCLK_FREQ 0xc6204 5999 #define FDL_TP1_TIMER_SHIFT 12 6000 #define FDL_TP1_TIMER_MASK (3<<12) 6001 #define FDL_TP2_TIMER_SHIFT 10 6002 #define FDL_TP2_TIMER_MASK (3<<10) 6003 #define RAWCLK_FREQ_MASK 0x3ff 6004 6005 #define PCH_DPLL_TMR_CFG 0xc6208 6006 6007 #define PCH_SSC4_PARMS 0xc6210 6008 #define PCH_SSC4_AUX_PARMS 0xc6214 6009 6010 #define PCH_DPLL_SEL 0xc7000 6011 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) 6012 #define TRANS_DPLLA_SEL(pipe) 0 6013 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) 6014 6015 /* transcoder */ 6016 6017 #define _PCH_TRANS_HTOTAL_A 0xe0000 6018 #define TRANS_HTOTAL_SHIFT 16 6019 #define TRANS_HACTIVE_SHIFT 0 6020 #define _PCH_TRANS_HBLANK_A 0xe0004 6021 #define TRANS_HBLANK_END_SHIFT 16 6022 #define TRANS_HBLANK_START_SHIFT 0 6023 #define _PCH_TRANS_HSYNC_A 0xe0008 6024 #define TRANS_HSYNC_END_SHIFT 16 6025 #define TRANS_HSYNC_START_SHIFT 0 6026 #define _PCH_TRANS_VTOTAL_A 0xe000c 6027 #define TRANS_VTOTAL_SHIFT 16 6028 #define TRANS_VACTIVE_SHIFT 0 6029 #define _PCH_TRANS_VBLANK_A 0xe0010 6030 #define TRANS_VBLANK_END_SHIFT 16 6031 #define TRANS_VBLANK_START_SHIFT 0 6032 #define _PCH_TRANS_VSYNC_A 0xe0014 6033 #define TRANS_VSYNC_END_SHIFT 16 6034 #define TRANS_VSYNC_START_SHIFT 0 6035 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 6036 6037 #define _PCH_TRANSA_DATA_M1 0xe0030 6038 #define _PCH_TRANSA_DATA_N1 0xe0034 6039 #define _PCH_TRANSA_DATA_M2 0xe0038 6040 #define _PCH_TRANSA_DATA_N2 0xe003c 6041 #define _PCH_TRANSA_LINK_M1 0xe0040 6042 #define _PCH_TRANSA_LINK_N1 0xe0044 6043 #define _PCH_TRANSA_LINK_M2 0xe0048 6044 #define _PCH_TRANSA_LINK_N2 0xe004c 6045 6046 /* Per-transcoder DIP controls (PCH) */ 6047 #define _VIDEO_DIP_CTL_A 0xe0200 6048 #define _VIDEO_DIP_DATA_A 0xe0208 6049 #define _VIDEO_DIP_GCP_A 0xe0210 6050 6051 #define _VIDEO_DIP_CTL_B 0xe1200 6052 #define _VIDEO_DIP_DATA_B 0xe1208 6053 #define _VIDEO_DIP_GCP_B 0xe1210 6054 6055 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 6056 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 6057 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 6058 6059 /* Per-transcoder DIP controls (VLV) */ 6060 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 6061 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 6062 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 6063 6064 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 6065 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 6066 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 6067 6068 #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 6069 #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 6070 #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 6071 6072 #define VLV_TVIDEO_DIP_CTL(pipe) \ 6073 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \ 6074 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C) 6075 #define VLV_TVIDEO_DIP_DATA(pipe) \ 6076 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \ 6077 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C) 6078 #define VLV_TVIDEO_DIP_GCP(pipe) \ 6079 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 6080 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 6081 6082 /* Haswell DIP controls */ 6083 #define HSW_VIDEO_DIP_CTL_A 0x60200 6084 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 6085 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 6086 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 6087 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 6088 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 6089 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 6090 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 6091 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 6092 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 6093 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 6094 #define HSW_VIDEO_DIP_GCP_A 0x60210 6095 6096 #define HSW_VIDEO_DIP_CTL_B 0x61200 6097 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 6098 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 6099 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 6100 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 6101 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 6102 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 6103 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 6104 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 6105 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 6106 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 6107 #define HSW_VIDEO_DIP_GCP_B 0x61210 6108 6109 #define HSW_TVIDEO_DIP_CTL(trans) \ 6110 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) 6111 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \ 6112 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) 6113 #define HSW_TVIDEO_DIP_VS_DATA(trans) \ 6114 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) 6115 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \ 6116 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) 6117 #define HSW_TVIDEO_DIP_GCP(trans) \ 6118 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) 6119 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \ 6120 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) 6121 6122 #define HSW_STEREO_3D_CTL_A 0x70020 6123 #define S3D_ENABLE (1<<31) 6124 #define HSW_STEREO_3D_CTL_B 0x71020 6125 6126 #define HSW_STEREO_3D_CTL(trans) \ 6127 _PIPE2(trans, HSW_STEREO_3D_CTL_A) 6128 6129 #define _PCH_TRANS_HTOTAL_B 0xe1000 6130 #define _PCH_TRANS_HBLANK_B 0xe1004 6131 #define _PCH_TRANS_HSYNC_B 0xe1008 6132 #define _PCH_TRANS_VTOTAL_B 0xe100c 6133 #define _PCH_TRANS_VBLANK_B 0xe1010 6134 #define _PCH_TRANS_VSYNC_B 0xe1014 6135 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 6136 6137 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 6138 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 6139 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 6140 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 6141 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 6142 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 6143 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \ 6144 _PCH_TRANS_VSYNCSHIFT_B) 6145 6146 #define _PCH_TRANSB_DATA_M1 0xe1030 6147 #define _PCH_TRANSB_DATA_N1 0xe1034 6148 #define _PCH_TRANSB_DATA_M2 0xe1038 6149 #define _PCH_TRANSB_DATA_N2 0xe103c 6150 #define _PCH_TRANSB_LINK_M1 0xe1040 6151 #define _PCH_TRANSB_LINK_N1 0xe1044 6152 #define _PCH_TRANSB_LINK_M2 0xe1048 6153 #define _PCH_TRANSB_LINK_N2 0xe104c 6154 6155 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 6156 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 6157 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 6158 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 6159 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 6160 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 6161 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 6162 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 6163 6164 #define _PCH_TRANSACONF 0xf0008 6165 #define _PCH_TRANSBCONF 0xf1008 6166 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 6167 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ 6168 #define TRANS_DISABLE (0<<31) 6169 #define TRANS_ENABLE (1<<31) 6170 #define TRANS_STATE_MASK (1<<30) 6171 #define TRANS_STATE_DISABLE (0<<30) 6172 #define TRANS_STATE_ENABLE (1<<30) 6173 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 6174 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 6175 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 6176 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 6177 #define TRANS_INTERLACE_MASK (7<<21) 6178 #define TRANS_PROGRESSIVE (0<<21) 6179 #define TRANS_INTERLACED (3<<21) 6180 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 6181 #define TRANS_8BPC (0<<5) 6182 #define TRANS_10BPC (1<<5) 6183 #define TRANS_6BPC (2<<5) 6184 #define TRANS_12BPC (3<<5) 6185 6186 #define _TRANSA_CHICKEN1 0xf0060 6187 #define _TRANSB_CHICKEN1 0xf1060 6188 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 6189 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 6190 #define _TRANSA_CHICKEN2 0xf0064 6191 #define _TRANSB_CHICKEN2 0xf1064 6192 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 6193 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 6194 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) 6195 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) 6196 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) 6197 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) 6198 6199 #define SOUTH_CHICKEN1 0xc2000 6200 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 6201 #define FDIA_PHASE_SYNC_SHIFT_EN 18 6202 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 6203 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 6204 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 6205 #define SOUTH_CHICKEN2 0xc2004 6206 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 6207 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 6208 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 6209 6210 #define _FDI_RXA_CHICKEN 0xc200c 6211 #define _FDI_RXB_CHICKEN 0xc2010 6212 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 6213 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 6214 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 6215 6216 #define SOUTH_DSPCLK_GATE_D 0xc2020 6217 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 6218 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 6219 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 6220 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 6221 6222 /* CPU: FDI_TX */ 6223 #define _FDI_TXA_CTL 0x60100 6224 #define _FDI_TXB_CTL 0x61100 6225 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 6226 #define FDI_TX_DISABLE (0<<31) 6227 #define FDI_TX_ENABLE (1<<31) 6228 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 6229 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 6230 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 6231 #define FDI_LINK_TRAIN_NONE (3<<28) 6232 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 6233 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 6234 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 6235 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 6236 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 6237 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 6238 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 6239 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 6240 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 6241 SNB has different settings. */ 6242 /* SNB A-stepping */ 6243 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 6244 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 6245 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 6246 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 6247 /* SNB B-stepping */ 6248 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 6249 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 6250 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 6251 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 6252 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 6253 #define FDI_DP_PORT_WIDTH_SHIFT 19 6254 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 6255 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 6256 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 6257 /* Ironlake: hardwired to 1 */ 6258 #define FDI_TX_PLL_ENABLE (1<<14) 6259 6260 /* Ivybridge has different bits for lolz */ 6261 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 6262 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 6263 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 6264 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 6265 6266 /* both Tx and Rx */ 6267 #define FDI_COMPOSITE_SYNC (1<<11) 6268 #define FDI_LINK_TRAIN_AUTO (1<<10) 6269 #define FDI_SCRAMBLING_ENABLE (0<<7) 6270 #define FDI_SCRAMBLING_DISABLE (1<<7) 6271 6272 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 6273 #define _FDI_RXA_CTL 0xf000c 6274 #define _FDI_RXB_CTL 0xf100c 6275 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 6276 #define FDI_RX_ENABLE (1<<31) 6277 /* train, dp width same as FDI_TX */ 6278 #define FDI_FS_ERRC_ENABLE (1<<27) 6279 #define FDI_FE_ERRC_ENABLE (1<<26) 6280 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 6281 #define FDI_8BPC (0<<16) 6282 #define FDI_10BPC (1<<16) 6283 #define FDI_6BPC (2<<16) 6284 #define FDI_12BPC (3<<16) 6285 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) 6286 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 6287 #define FDI_RX_PLL_ENABLE (1<<13) 6288 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 6289 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 6290 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 6291 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 6292 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 6293 #define FDI_PCDCLK (1<<4) 6294 /* CPT */ 6295 #define FDI_AUTO_TRAINING (1<<10) 6296 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 6297 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 6298 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 6299 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 6300 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 6301 6302 #define _FDI_RXA_MISC 0xf0010 6303 #define _FDI_RXB_MISC 0xf1010 6304 #define FDI_RX_PWRDN_LANE1_MASK (3<<26) 6305 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 6306 #define FDI_RX_PWRDN_LANE0_MASK (3<<24) 6307 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 6308 #define FDI_RX_TP1_TO_TP2_48 (2<<20) 6309 #define FDI_RX_TP1_TO_TP2_64 (3<<20) 6310 #define FDI_RX_FDI_DELAY_90 (0x90<<0) 6311 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 6312 6313 #define _FDI_RXA_TUSIZE1 0xf0030 6314 #define _FDI_RXA_TUSIZE2 0xf0038 6315 #define _FDI_RXB_TUSIZE1 0xf1030 6316 #define _FDI_RXB_TUSIZE2 0xf1038 6317 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 6318 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 6319 6320 /* FDI_RX interrupt register format */ 6321 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 6322 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 6323 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 6324 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 6325 #define FDI_RX_FS_CODE_ERR (1<<6) 6326 #define FDI_RX_FE_CODE_ERR (1<<5) 6327 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 6328 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 6329 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 6330 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 6331 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 6332 6333 #define _FDI_RXA_IIR 0xf0014 6334 #define _FDI_RXA_IMR 0xf0018 6335 #define _FDI_RXB_IIR 0xf1014 6336 #define _FDI_RXB_IMR 0xf1018 6337 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 6338 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 6339 6340 #define FDI_PLL_CTL_1 0xfe000 6341 #define FDI_PLL_CTL_2 0xfe004 6342 6343 #define PCH_LVDS 0xe1180 6344 #define LVDS_DETECTED (1 << 1) 6345 6346 /* vlv has 2 sets of panel control regs. */ 6347 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) 6348 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) 6349 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) 6350 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) 6351 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) 6352 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) 6353 6354 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) 6355 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) 6356 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) 6357 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) 6358 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) 6359 6360 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS) 6361 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL) 6362 #define VLV_PIPE_PP_ON_DELAYS(pipe) \ 6363 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS) 6364 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \ 6365 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS) 6366 #define VLV_PIPE_PP_DIVISOR(pipe) \ 6367 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR) 6368 6369 #define PCH_PP_STATUS 0xc7200 6370 #define PCH_PP_CONTROL 0xc7204 6371 #define PANEL_UNLOCK_REGS (0xabcd << 16) 6372 #define PANEL_UNLOCK_MASK (0xffff << 16) 6373 #define EDP_FORCE_VDD (1 << 3) 6374 #define EDP_BLC_ENABLE (1 << 2) 6375 #define PANEL_POWER_RESET (1 << 1) 6376 #define PANEL_POWER_OFF (0 << 0) 6377 #define PANEL_POWER_ON (1 << 0) 6378 #define PCH_PP_ON_DELAYS 0xc7208 6379 #define PANEL_PORT_SELECT_MASK (3 << 30) 6380 #define PANEL_PORT_SELECT_LVDS (0 << 30) 6381 #define PANEL_PORT_SELECT_DPA (1 << 30) 6382 #define PANEL_PORT_SELECT_DPC (2 << 30) 6383 #define PANEL_PORT_SELECT_DPD (3 << 30) 6384 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 6385 #define PANEL_POWER_UP_DELAY_SHIFT 16 6386 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 6387 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 6388 6389 #define PCH_PP_OFF_DELAYS 0xc720c 6390 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 6391 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 6392 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 6393 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 6394 6395 #define PCH_PP_DIVISOR 0xc7210 6396 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 6397 #define PP_REFERENCE_DIVIDER_SHIFT 8 6398 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 6399 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 6400 6401 #define PCH_DP_B 0xe4100 6402 #define PCH_DPB_AUX_CH_CTL 0xe4110 6403 #define PCH_DPB_AUX_CH_DATA1 0xe4114 6404 #define PCH_DPB_AUX_CH_DATA2 0xe4118 6405 #define PCH_DPB_AUX_CH_DATA3 0xe411c 6406 #define PCH_DPB_AUX_CH_DATA4 0xe4120 6407 #define PCH_DPB_AUX_CH_DATA5 0xe4124 6408 6409 #define PCH_DP_C 0xe4200 6410 #define PCH_DPC_AUX_CH_CTL 0xe4210 6411 #define PCH_DPC_AUX_CH_DATA1 0xe4214 6412 #define PCH_DPC_AUX_CH_DATA2 0xe4218 6413 #define PCH_DPC_AUX_CH_DATA3 0xe421c 6414 #define PCH_DPC_AUX_CH_DATA4 0xe4220 6415 #define PCH_DPC_AUX_CH_DATA5 0xe4224 6416 6417 #define PCH_DP_D 0xe4300 6418 #define PCH_DPD_AUX_CH_CTL 0xe4310 6419 #define PCH_DPD_AUX_CH_DATA1 0xe4314 6420 #define PCH_DPD_AUX_CH_DATA2 0xe4318 6421 #define PCH_DPD_AUX_CH_DATA3 0xe431c 6422 #define PCH_DPD_AUX_CH_DATA4 0xe4320 6423 #define PCH_DPD_AUX_CH_DATA5 0xe4324 6424 6425 /* CPT */ 6426 #define PORT_TRANS_A_SEL_CPT 0 6427 #define PORT_TRANS_B_SEL_CPT (1<<29) 6428 #define PORT_TRANS_C_SEL_CPT (2<<29) 6429 #define PORT_TRANS_SEL_MASK (3<<29) 6430 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 6431 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 6432 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 6433 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) 6434 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) 6435 6436 #define TRANS_DP_CTL_A 0xe0300 6437 #define TRANS_DP_CTL_B 0xe1300 6438 #define TRANS_DP_CTL_C 0xe2300 6439 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) 6440 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 6441 #define TRANS_DP_PORT_SEL_B (0<<29) 6442 #define TRANS_DP_PORT_SEL_C (1<<29) 6443 #define TRANS_DP_PORT_SEL_D (2<<29) 6444 #define TRANS_DP_PORT_SEL_NONE (3<<29) 6445 #define TRANS_DP_PORT_SEL_MASK (3<<29) 6446 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B) 6447 #define TRANS_DP_AUDIO_ONLY (1<<26) 6448 #define TRANS_DP_ENH_FRAMING (1<<18) 6449 #define TRANS_DP_8BPC (0<<9) 6450 #define TRANS_DP_10BPC (1<<9) 6451 #define TRANS_DP_6BPC (2<<9) 6452 #define TRANS_DP_12BPC (3<<9) 6453 #define TRANS_DP_BPC_MASK (3<<9) 6454 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 6455 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 6456 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 6457 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 6458 #define TRANS_DP_SYNC_MASK (3<<3) 6459 6460 /* SNB eDP training params */ 6461 /* SNB A-stepping */ 6462 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 6463 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 6464 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 6465 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 6466 /* SNB B-stepping */ 6467 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 6468 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 6469 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 6470 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 6471 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 6472 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 6473 6474 /* IVB */ 6475 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 6476 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 6477 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 6478 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 6479 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 6480 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 6481 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) 6482 6483 /* legacy values */ 6484 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 6485 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 6486 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 6487 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 6488 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 6489 6490 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 6491 6492 #define VLV_PMWGICZ 0x1300a4 6493 6494 #define FORCEWAKE 0xA18C 6495 #define FORCEWAKE_VLV 0x1300b0 6496 #define FORCEWAKE_ACK_VLV 0x1300b4 6497 #define FORCEWAKE_MEDIA_VLV 0x1300b8 6498 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc 6499 #define FORCEWAKE_ACK_HSW 0x130044 6500 #define FORCEWAKE_ACK 0x130090 6501 #define VLV_GTLC_WAKE_CTRL 0x130090 6502 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 6503 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 6504 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 6505 6506 #define VLV_GTLC_PW_STATUS 0x130094 6507 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 6508 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 6509 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 6510 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 6511 #define FORCEWAKE_MT 0xa188 /* multi-threaded */ 6512 #define FORCEWAKE_MEDIA_GEN9 0xa270 6513 #define FORCEWAKE_RENDER_GEN9 0xa278 6514 #define FORCEWAKE_BLITTER_GEN9 0xa188 6515 #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88 6516 #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84 6517 #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044 6518 #define FORCEWAKE_KERNEL 0x1 6519 #define FORCEWAKE_USER 0x2 6520 #define FORCEWAKE_MT_ACK 0x130040 6521 #define ECOBUS 0xa180 6522 #define FORCEWAKE_MT_ENABLE (1<<5) 6523 #define VLV_SPAREG2H 0xA194 6524 6525 #define GTFIFODBG 0x120000 6526 #define GT_FIFO_SBDROPERR (1<<6) 6527 #define GT_FIFO_BLOBDROPERR (1<<5) 6528 #define GT_FIFO_SB_READ_ABORTERR (1<<4) 6529 #define GT_FIFO_DROPERR (1<<3) 6530 #define GT_FIFO_OVFERR (1<<2) 6531 #define GT_FIFO_IAWRERR (1<<1) 6532 #define GT_FIFO_IARDERR (1<<0) 6533 6534 #define GTFIFOCTL 0x120008 6535 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 6536 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 6537 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 6538 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 6539 6540 #define HSW_IDICR 0x9008 6541 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 6542 #define HSW_EDRAM_PRESENT 0x120010 6543 #define EDRAM_ENABLED 0x1 6544 6545 #define GEN6_UCGCTL1 0x9400 6546 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 6547 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 6548 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 6549 6550 #define GEN6_UCGCTL2 0x9404 6551 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 6552 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 6553 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 6554 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 6555 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 6556 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 6557 6558 #define GEN6_UCGCTL3 0x9408 6559 6560 #define GEN7_UCGCTL4 0x940c 6561 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 6562 6563 #define GEN6_RCGCTL1 0x9410 6564 #define GEN6_RCGCTL2 0x9414 6565 #define GEN6_RSTCTL 0x9420 6566 6567 #define GEN8_UCGCTL6 0x9430 6568 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) 6569 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) 6570 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28) 6571 6572 #define GEN6_GFXPAUSE 0xA000 6573 #define GEN6_RPNSWREQ 0xA008 6574 #define GEN6_TURBO_DISABLE (1<<31) 6575 #define GEN6_FREQUENCY(x) ((x)<<25) 6576 #define HSW_FREQUENCY(x) ((x)<<24) 6577 #define GEN9_FREQUENCY(x) ((x)<<23) 6578 #define GEN6_OFFSET(x) ((x)<<19) 6579 #define GEN6_AGGRESSIVE_TURBO (0<<15) 6580 #define GEN6_RC_VIDEO_FREQ 0xA00C 6581 #define GEN6_RC_CONTROL 0xA090 6582 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 6583 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 6584 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 6585 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 6586 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 6587 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) 6588 #define GEN7_RC_CTL_TO_MODE (1<<28) 6589 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 6590 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 6591 #define GEN6_RP_DOWN_TIMEOUT 0xA010 6592 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 6593 #define GEN6_RPSTAT1 0xA01C 6594 #define GEN6_CAGF_SHIFT 8 6595 #define HSW_CAGF_SHIFT 7 6596 #define GEN9_CAGF_SHIFT 23 6597 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 6598 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 6599 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) 6600 #define GEN6_RP_CONTROL 0xA024 6601 #define GEN6_RP_MEDIA_TURBO (1<<11) 6602 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 6603 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 6604 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 6605 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 6606 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 6607 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 6608 #define GEN6_RP_ENABLE (1<<7) 6609 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 6610 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 6611 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 6612 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) 6613 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 6614 #define GEN6_RP_UP_THRESHOLD 0xA02C 6615 #define GEN6_RP_DOWN_THRESHOLD 0xA030 6616 #define GEN6_RP_CUR_UP_EI 0xA050 6617 #define GEN6_CURICONT_MASK 0xffffff 6618 #define GEN6_RP_CUR_UP 0xA054 6619 #define GEN6_CURBSYTAVG_MASK 0xffffff 6620 #define GEN6_RP_PREV_UP 0xA058 6621 #define GEN6_RP_CUR_DOWN_EI 0xA05C 6622 #define GEN6_CURIAVG_MASK 0xffffff 6623 #define GEN6_RP_CUR_DOWN 0xA060 6624 #define GEN6_RP_PREV_DOWN 0xA064 6625 #define GEN6_RP_UP_EI 0xA068 6626 #define GEN6_RP_DOWN_EI 0xA06C 6627 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 6628 #define GEN6_RPDEUHWTC 0xA080 6629 #define GEN6_RPDEUC 0xA084 6630 #define GEN6_RPDEUCSW 0xA088 6631 #define GEN6_RC_STATE 0xA094 6632 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 6633 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 6634 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 6635 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 6636 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 6637 #define GEN6_RC_SLEEP 0xA0B0 6638 #define GEN6_RCUBMABDTMR 0xA0B0 6639 #define GEN6_RC1e_THRESHOLD 0xA0B4 6640 #define GEN6_RC6_THRESHOLD 0xA0B8 6641 #define GEN6_RC6p_THRESHOLD 0xA0BC 6642 #define VLV_RCEDATA 0xA0BC 6643 #define GEN6_RC6pp_THRESHOLD 0xA0C0 6644 #define GEN6_PMINTRMSK 0xA168 6645 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) 6646 #define VLV_PWRDWNUPCTL 0xA294 6647 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4 6648 #define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8 6649 #define GEN9_PG_ENABLE 0xA210 6650 #define GEN9_RENDER_PG_ENABLE (1<<0) 6651 #define GEN9_MEDIA_PG_ENABLE (1<<1) 6652 6653 #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C) 6654 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 6655 #define PIXEL_OVERLAP_CNT_SHIFT 30 6656 6657 #define GEN6_PMISR 0x44020 6658 #define GEN6_PMIMR 0x44024 /* rps_lock */ 6659 #define GEN6_PMIIR 0x44028 6660 #define GEN6_PMIER 0x4402C 6661 #define GEN6_PM_MBOX_EVENT (1<<25) 6662 #define GEN6_PM_THERMAL_EVENT (1<<24) 6663 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 6664 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 6665 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 6666 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 6667 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 6668 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 6669 GEN6_PM_RP_DOWN_THRESHOLD | \ 6670 GEN6_PM_RP_DOWN_TIMEOUT) 6671 6672 #define GEN7_GT_SCRATCH_BASE 0x4F100 6673 #define GEN7_GT_SCRATCH_REG_NUM 8 6674 6675 #define VLV_GTLC_SURVIVABILITY_REG 0x130098 6676 #define VLV_GFX_CLK_STATUS_BIT (1<<3) 6677 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) 6678 6679 #define GEN6_GT_GFX_RC6_LOCKED 0x138104 6680 #define VLV_COUNTER_CONTROL 0x138104 6681 #define VLV_COUNT_RANGE_HIGH (1<<15) 6682 #define VLV_MEDIA_RC0_COUNT_EN (1<<5) 6683 #define VLV_RENDER_RC0_COUNT_EN (1<<4) 6684 #define VLV_MEDIA_RC6_COUNT_EN (1<<1) 6685 #define VLV_RENDER_RC6_COUNT_EN (1<<0) 6686 #define GEN6_GT_GFX_RC6 0x138108 6687 #define VLV_GT_RENDER_RC6 0x138108 6688 #define VLV_GT_MEDIA_RC6 0x13810C 6689 6690 #define GEN6_GT_GFX_RC6p 0x13810C 6691 #define GEN6_GT_GFX_RC6pp 0x138110 6692 #define VLV_RENDER_C0_COUNT 0x138118 6693 #define VLV_MEDIA_C0_COUNT 0x13811C 6694 6695 #define GEN6_PCODE_MAILBOX 0x138124 6696 #define GEN6_PCODE_READY (1<<31) 6697 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 6698 #define GEN6_PCODE_READ_RC6VIDS 0x5 6699 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 6700 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 6701 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 6702 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 6703 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 6704 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 6705 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 6706 #define SKL_PCODE_CDCLK_CONTROL 0x7 6707 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 6708 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 6709 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 6710 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 6711 #define GEN6_READ_OC_PARAMS 0xc 6712 #define GEN6_PCODE_READ_D_COMP 0x10 6713 #define GEN6_PCODE_WRITE_D_COMP 0x11 6714 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 6715 #define DISPLAY_IPS_CONTROL 0x19 6716 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 6717 #define GEN6_PCODE_DATA 0x138128 6718 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 6719 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 6720 #define GEN6_PCODE_DATA1 0x13812C 6721 6722 #define GEN6_GT_CORE_STATUS 0x138060 6723 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 6724 #define GEN6_RCn_MASK 7 6725 #define GEN6_RC0 0 6726 #define GEN6_RC3 2 6727 #define GEN6_RC6 3 6728 #define GEN6_RC7 4 6729 6730 #define CHV_POWER_SS0_SIG1 0xa720 6731 #define CHV_POWER_SS1_SIG1 0xa728 6732 #define CHV_SS_PG_ENABLE (1<<1) 6733 #define CHV_EU08_PG_ENABLE (1<<9) 6734 #define CHV_EU19_PG_ENABLE (1<<17) 6735 #define CHV_EU210_PG_ENABLE (1<<25) 6736 6737 #define CHV_POWER_SS0_SIG2 0xa724 6738 #define CHV_POWER_SS1_SIG2 0xa72c 6739 #define CHV_EU311_PG_ENABLE (1<<1) 6740 6741 #define GEN9_SLICE_PGCTL_ACK(slice) (0x804c + (slice)*0x4) 6742 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 6743 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2)) 6744 6745 #define GEN9_SS01_EU_PGCTL_ACK(slice) (0x805c + (slice)*0x8) 6746 #define GEN9_SS23_EU_PGCTL_ACK(slice) (0x8060 + (slice)*0x8) 6747 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 6748 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 6749 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 6750 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 6751 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 6752 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 6753 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 6754 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 6755 6756 #define GEN7_MISCCPCTL (0x9424) 6757 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 6758 6759 /* IVYBRIDGE DPF */ 6760 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ 6761 #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */ 6762 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 6763 #define GEN7_PARITY_ERROR_VALID (1<<13) 6764 #define GEN7_L3CDERRST1_BANK_MASK (3<<11) 6765 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 6766 #define GEN7_PARITY_ERROR_ROW(reg) \ 6767 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 6768 #define GEN7_PARITY_ERROR_BANK(reg) \ 6769 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 6770 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 6771 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 6772 #define GEN7_L3CDERRST1_ENABLE (1<<7) 6773 6774 #define GEN7_L3LOG_BASE 0xB070 6775 #define HSW_L3LOG_BASE_SLICE1 0xB270 6776 #define GEN7_L3LOG_SIZE 0x80 6777 6778 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ 6779 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 6780 #define GEN7_MAX_PS_THREAD_DEP (8<<12) 6781 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) 6782 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) 6783 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 6784 6785 #define GEN9_HALF_SLICE_CHICKEN5 0xe188 6786 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) 6787 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3) 6788 6789 #define GEN8_ROW_CHICKEN 0xe4f0 6790 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) 6791 #define STALL_DOP_GATING_DISABLE (1<<5) 6792 6793 #define GEN7_ROW_CHICKEN2 0xe4f4 6794 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 6795 #define DOP_CLOCK_GATING_DISABLE (1<<0) 6796 6797 #define HSW_ROW_CHICKEN3 0xe49c 6798 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 6799 6800 #define HALF_SLICE_CHICKEN3 0xe184 6801 #define HSW_SAMPLE_C_PERFORMANCE (1<<9) 6802 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 6803 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) 6804 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 6805 6806 #define GEN9_HALF_SLICE_CHICKEN7 0xe194 6807 #define GEN9_ENABLE_YV12_BUGFIX (1<<4) 6808 6809 /* Audio */ 6810 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) 6811 #define INTEL_AUDIO_DEVCL 0x808629FB 6812 #define INTEL_AUDIO_DEVBLC 0x80862801 6813 #define INTEL_AUDIO_DEVCTG 0x80862802 6814 6815 #define G4X_AUD_CNTL_ST 0x620B4 6816 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 6817 #define G4X_ELDV_DEVCTG (1 << 14) 6818 #define G4X_ELD_ADDR_MASK (0xf << 5) 6819 #define G4X_ELD_ACK (1 << 4) 6820 #define G4X_HDMIW_HDMIEDID 0x6210C 6821 6822 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 6823 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 6824 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 6825 _IBX_HDMIW_HDMIEDID_A, \ 6826 _IBX_HDMIW_HDMIEDID_B) 6827 #define _IBX_AUD_CNTL_ST_A 0xE20B4 6828 #define _IBX_AUD_CNTL_ST_B 0xE21B4 6829 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 6830 _IBX_AUD_CNTL_ST_A, \ 6831 _IBX_AUD_CNTL_ST_B) 6832 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 6833 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 6834 #define IBX_ELD_ACK (1 << 4) 6835 #define IBX_AUD_CNTL_ST2 0xE20C0 6836 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 6837 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 6838 6839 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 6840 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 6841 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 6842 _CPT_HDMIW_HDMIEDID_A, \ 6843 _CPT_HDMIW_HDMIEDID_B) 6844 #define _CPT_AUD_CNTL_ST_A 0xE50B4 6845 #define _CPT_AUD_CNTL_ST_B 0xE51B4 6846 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 6847 _CPT_AUD_CNTL_ST_A, \ 6848 _CPT_AUD_CNTL_ST_B) 6849 #define CPT_AUD_CNTRL_ST2 0xE50C0 6850 6851 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 6852 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 6853 #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 6854 _VLV_HDMIW_HDMIEDID_A, \ 6855 _VLV_HDMIW_HDMIEDID_B) 6856 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 6857 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 6858 #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 6859 _VLV_AUD_CNTL_ST_A, \ 6860 _VLV_AUD_CNTL_ST_B) 6861 #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) 6862 6863 /* These are the 4 32-bit write offset registers for each stream 6864 * output buffer. It determines the offset from the 6865 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 6866 */ 6867 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 6868 6869 #define _IBX_AUD_CONFIG_A 0xe2000 6870 #define _IBX_AUD_CONFIG_B 0xe2100 6871 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ 6872 _IBX_AUD_CONFIG_A, \ 6873 _IBX_AUD_CONFIG_B) 6874 #define _CPT_AUD_CONFIG_A 0xe5000 6875 #define _CPT_AUD_CONFIG_B 0xe5100 6876 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ 6877 _CPT_AUD_CONFIG_A, \ 6878 _CPT_AUD_CONFIG_B) 6879 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 6880 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 6881 #define VLV_AUD_CFG(pipe) _PIPE(pipe, \ 6882 _VLV_AUD_CONFIG_A, \ 6883 _VLV_AUD_CONFIG_B) 6884 6885 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 6886 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 6887 #define AUD_CONFIG_UPPER_N_SHIFT 20 6888 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 6889 #define AUD_CONFIG_LOWER_N_SHIFT 4 6890 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 6891 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 6892 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 6893 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 6894 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 6895 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 6896 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 6897 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 6898 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 6899 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 6900 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 6901 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 6902 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 6903 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 6904 6905 /* HSW Audio */ 6906 #define _HSW_AUD_CONFIG_A 0x65000 6907 #define _HSW_AUD_CONFIG_B 0x65100 6908 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ 6909 _HSW_AUD_CONFIG_A, \ 6910 _HSW_AUD_CONFIG_B) 6911 6912 #define _HSW_AUD_MISC_CTRL_A 0x65010 6913 #define _HSW_AUD_MISC_CTRL_B 0x65110 6914 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ 6915 _HSW_AUD_MISC_CTRL_A, \ 6916 _HSW_AUD_MISC_CTRL_B) 6917 6918 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 6919 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 6920 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ 6921 _HSW_AUD_DIP_ELD_CTRL_ST_A, \ 6922 _HSW_AUD_DIP_ELD_CTRL_ST_B) 6923 6924 /* Audio Digital Converter */ 6925 #define _HSW_AUD_DIG_CNVT_1 0x65080 6926 #define _HSW_AUD_DIG_CNVT_2 0x65180 6927 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ 6928 _HSW_AUD_DIG_CNVT_1, \ 6929 _HSW_AUD_DIG_CNVT_2) 6930 #define DIP_PORT_SEL_MASK 0x3 6931 6932 #define _HSW_AUD_EDID_DATA_A 0x65050 6933 #define _HSW_AUD_EDID_DATA_B 0x65150 6934 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ 6935 _HSW_AUD_EDID_DATA_A, \ 6936 _HSW_AUD_EDID_DATA_B) 6937 6938 #define HSW_AUD_PIPE_CONV_CFG 0x6507c 6939 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 6940 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 6941 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 6942 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 6943 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 6944 6945 #define HSW_AUD_CHICKENBIT 0x65f10 6946 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 6947 6948 /* HSW Power Wells */ 6949 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ 6950 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ 6951 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ 6952 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ 6953 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) 6954 #define HSW_PWR_WELL_STATE_ENABLED (1<<30) 6955 #define HSW_PWR_WELL_CTL5 0x45410 6956 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 6957 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 6958 #define HSW_PWR_WELL_FORCE_ON (1<<19) 6959 #define HSW_PWR_WELL_CTL6 0x45414 6960 6961 /* SKL Fuse Status */ 6962 #define SKL_FUSE_STATUS 0x42000 6963 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31) 6964 #define SKL_FUSE_PG0_DIST_STATUS (1<<27) 6965 #define SKL_FUSE_PG1_DIST_STATUS (1<<26) 6966 #define SKL_FUSE_PG2_DIST_STATUS (1<<25) 6967 6968 /* Per-pipe DDI Function Control */ 6969 #define TRANS_DDI_FUNC_CTL_A 0x60400 6970 #define TRANS_DDI_FUNC_CTL_B 0x61400 6971 #define TRANS_DDI_FUNC_CTL_C 0x62400 6972 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 6973 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A) 6974 6975 #define TRANS_DDI_FUNC_ENABLE (1<<31) 6976 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 6977 #define TRANS_DDI_PORT_MASK (7<<28) 6978 #define TRANS_DDI_PORT_SHIFT 28 6979 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) 6980 #define TRANS_DDI_PORT_NONE (0<<28) 6981 #define TRANS_DDI_MODE_SELECT_MASK (7<<24) 6982 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 6983 #define TRANS_DDI_MODE_SELECT_DVI (1<<24) 6984 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 6985 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 6986 #define TRANS_DDI_MODE_SELECT_FDI (4<<24) 6987 #define TRANS_DDI_BPC_MASK (7<<20) 6988 #define TRANS_DDI_BPC_8 (0<<20) 6989 #define TRANS_DDI_BPC_10 (1<<20) 6990 #define TRANS_DDI_BPC_6 (2<<20) 6991 #define TRANS_DDI_BPC_12 (3<<20) 6992 #define TRANS_DDI_PVSYNC (1<<17) 6993 #define TRANS_DDI_PHSYNC (1<<16) 6994 #define TRANS_DDI_EDP_INPUT_MASK (7<<12) 6995 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 6996 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 6997 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 6998 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 6999 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) 7000 #define TRANS_DDI_BFI_ENABLE (1<<4) 7001 7002 /* DisplayPort Transport Control */ 7003 #define DP_TP_CTL_A 0x64040 7004 #define DP_TP_CTL_B 0x64140 7005 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) 7006 #define DP_TP_CTL_ENABLE (1<<31) 7007 #define DP_TP_CTL_MODE_SST (0<<27) 7008 #define DP_TP_CTL_MODE_MST (1<<27) 7009 #define DP_TP_CTL_FORCE_ACT (1<<25) 7010 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 7011 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 7012 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 7013 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 7014 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 7015 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 7016 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 7017 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 7018 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 7019 7020 /* DisplayPort Transport Status */ 7021 #define DP_TP_STATUS_A 0x64044 7022 #define DP_TP_STATUS_B 0x64144 7023 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) 7024 #define DP_TP_STATUS_IDLE_DONE (1<<25) 7025 #define DP_TP_STATUS_ACT_SENT (1<<24) 7026 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) 7027 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 7028 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 7029 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 7030 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 7031 7032 /* DDI Buffer Control */ 7033 #define DDI_BUF_CTL_A 0x64000 7034 #define DDI_BUF_CTL_B 0x64100 7035 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) 7036 #define DDI_BUF_CTL_ENABLE (1<<31) 7037 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 7038 #define DDI_BUF_EMP_MASK (0xf<<24) 7039 #define DDI_BUF_PORT_REVERSAL (1<<16) 7040 #define DDI_BUF_IS_IDLE (1<<7) 7041 #define DDI_A_4_LANES (1<<4) 7042 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 7043 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 7044 7045 /* DDI Buffer Translations */ 7046 #define DDI_BUF_TRANS_A 0x64E00 7047 #define DDI_BUF_TRANS_B 0x64E60 7048 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) 7049 7050 /* Sideband Interface (SBI) is programmed indirectly, via 7051 * SBI_ADDR, which contains the register offset; and SBI_DATA, 7052 * which contains the payload */ 7053 #define SBI_ADDR 0xC6000 7054 #define SBI_DATA 0xC6004 7055 #define SBI_CTL_STAT 0xC6008 7056 #define SBI_CTL_DEST_ICLK (0x0<<16) 7057 #define SBI_CTL_DEST_MPHY (0x1<<16) 7058 #define SBI_CTL_OP_IORD (0x2<<8) 7059 #define SBI_CTL_OP_IOWR (0x3<<8) 7060 #define SBI_CTL_OP_CRRD (0x6<<8) 7061 #define SBI_CTL_OP_CRWR (0x7<<8) 7062 #define SBI_RESPONSE_FAIL (0x1<<1) 7063 #define SBI_RESPONSE_SUCCESS (0x0<<1) 7064 #define SBI_BUSY (0x1<<0) 7065 #define SBI_READY (0x0<<0) 7066 7067 /* SBI offsets */ 7068 #define SBI_SSCDIVINTPHASE6 0x0600 7069 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) 7070 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 7071 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) 7072 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 7073 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 7074 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 7075 #define SBI_SSCCTL 0x020c 7076 #define SBI_SSCCTL6 0x060C 7077 #define SBI_SSCCTL_PATHALT (1<<3) 7078 #define SBI_SSCCTL_DISABLE (1<<0) 7079 #define SBI_SSCAUXDIV6 0x0610 7080 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 7081 #define SBI_DBUFF0 0x2a00 7082 #define SBI_GEN0 0x1f00 7083 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) 7084 7085 /* LPT PIXCLK_GATE */ 7086 #define PIXCLK_GATE 0xC6020 7087 #define PIXCLK_GATE_UNGATE (1<<0) 7088 #define PIXCLK_GATE_GATE (0<<0) 7089 7090 /* SPLL */ 7091 #define SPLL_CTL 0x46020 7092 #define SPLL_PLL_ENABLE (1<<31) 7093 #define SPLL_PLL_SSC (1<<28) 7094 #define SPLL_PLL_NON_SSC (2<<28) 7095 #define SPLL_PLL_LCPLL (3<<28) 7096 #define SPLL_PLL_REF_MASK (3<<28) 7097 #define SPLL_PLL_FREQ_810MHz (0<<26) 7098 #define SPLL_PLL_FREQ_1350MHz (1<<26) 7099 #define SPLL_PLL_FREQ_2700MHz (2<<26) 7100 #define SPLL_PLL_FREQ_MASK (3<<26) 7101 7102 /* WRPLL */ 7103 #define WRPLL_CTL1 0x46040 7104 #define WRPLL_CTL2 0x46060 7105 #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2) 7106 #define WRPLL_PLL_ENABLE (1<<31) 7107 #define WRPLL_PLL_SSC (1<<28) 7108 #define WRPLL_PLL_NON_SSC (2<<28) 7109 #define WRPLL_PLL_LCPLL (3<<28) 7110 #define WRPLL_PLL_REF_MASK (3<<28) 7111 /* WRPLL divider programming */ 7112 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 7113 #define WRPLL_DIVIDER_REF_MASK (0xff) 7114 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 7115 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) 7116 #define WRPLL_DIVIDER_POST_SHIFT 8 7117 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 7118 #define WRPLL_DIVIDER_FB_SHIFT 16 7119 #define WRPLL_DIVIDER_FB_MASK (0xff<<16) 7120 7121 /* Port clock selection */ 7122 #define PORT_CLK_SEL_A 0x46100 7123 #define PORT_CLK_SEL_B 0x46104 7124 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) 7125 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 7126 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 7127 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 7128 #define PORT_CLK_SEL_SPLL (3<<29) 7129 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) 7130 #define PORT_CLK_SEL_WRPLL1 (4<<29) 7131 #define PORT_CLK_SEL_WRPLL2 (5<<29) 7132 #define PORT_CLK_SEL_NONE (7<<29) 7133 #define PORT_CLK_SEL_MASK (7<<29) 7134 7135 /* Transcoder clock selection */ 7136 #define TRANS_CLK_SEL_A 0x46140 7137 #define TRANS_CLK_SEL_B 0x46144 7138 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) 7139 /* For each transcoder, we need to select the corresponding port clock */ 7140 #define TRANS_CLK_SEL_DISABLED (0x0<<29) 7141 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) 7142 7143 #define TRANSA_MSA_MISC 0x60410 7144 #define TRANSB_MSA_MISC 0x61410 7145 #define TRANSC_MSA_MISC 0x62410 7146 #define TRANS_EDP_MSA_MISC 0x6f410 7147 #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC) 7148 7149 #define TRANS_MSA_SYNC_CLK (1<<0) 7150 #define TRANS_MSA_6_BPC (0<<5) 7151 #define TRANS_MSA_8_BPC (1<<5) 7152 #define TRANS_MSA_10_BPC (2<<5) 7153 #define TRANS_MSA_12_BPC (3<<5) 7154 #define TRANS_MSA_16_BPC (4<<5) 7155 7156 /* LCPLL Control */ 7157 #define LCPLL_CTL 0x130040 7158 #define LCPLL_PLL_DISABLE (1<<31) 7159 #define LCPLL_PLL_LOCK (1<<30) 7160 #define LCPLL_CLK_FREQ_MASK (3<<26) 7161 #define LCPLL_CLK_FREQ_450 (0<<26) 7162 #define LCPLL_CLK_FREQ_54O_BDW (1<<26) 7163 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) 7164 #define LCPLL_CLK_FREQ_675_BDW (3<<26) 7165 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 7166 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 7167 #define LCPLL_POWER_DOWN_ALLOW (1<<22) 7168 #define LCPLL_CD_SOURCE_FCLK (1<<21) 7169 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) 7170 7171 /* 7172 * SKL Clocks 7173 */ 7174 7175 /* CDCLK_CTL */ 7176 #define CDCLK_CTL 0x46000 7177 #define CDCLK_FREQ_SEL_MASK (3<<26) 7178 #define CDCLK_FREQ_450_432 (0<<26) 7179 #define CDCLK_FREQ_540 (1<<26) 7180 #define CDCLK_FREQ_337_308 (2<<26) 7181 #define CDCLK_FREQ_675_617 (3<<26) 7182 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 7183 7184 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22) 7185 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22) 7186 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22) 7187 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) 7188 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) 7189 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) 7190 7191 /* LCPLL_CTL */ 7192 #define LCPLL1_CTL 0x46010 7193 #define LCPLL2_CTL 0x46014 7194 #define LCPLL_PLL_ENABLE (1<<31) 7195 7196 /* DPLL control1 */ 7197 #define DPLL_CTRL1 0x6C058 7198 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) 7199 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) 7200 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) 7201 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1) 7202 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) 7203 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) 7204 #define DPLL_CTRL1_LINK_RATE_2700 0 7205 #define DPLL_CTRL1_LINK_RATE_1350 1 7206 #define DPLL_CTRL1_LINK_RATE_810 2 7207 #define DPLL_CTRL1_LINK_RATE_1620 3 7208 #define DPLL_CTRL1_LINK_RATE_1080 4 7209 #define DPLL_CTRL1_LINK_RATE_2160 5 7210 7211 /* DPLL control2 */ 7212 #define DPLL_CTRL2 0x6C05C 7213 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15)) 7214 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) 7215 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) 7216 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1)) 7217 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) 7218 7219 /* DPLL Status */ 7220 #define DPLL_STATUS 0x6C060 7221 #define DPLL_LOCK(id) (1<<((id)*8)) 7222 7223 /* DPLL cfg */ 7224 #define DPLL1_CFGCR1 0x6C040 7225 #define DPLL2_CFGCR1 0x6C048 7226 #define DPLL3_CFGCR1 0x6C050 7227 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) 7228 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) 7229 #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9) 7230 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 7231 7232 #define DPLL1_CFGCR2 0x6C044 7233 #define DPLL2_CFGCR2 0x6C04C 7234 #define DPLL3_CFGCR2 0x6C054 7235 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) 7236 #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8) 7237 #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7) 7238 #define DPLL_CFGCR2_KDIV_MASK (3<<5) 7239 #define DPLL_CFGCR2_KDIV(x) (x<<5) 7240 #define DPLL_CFGCR2_KDIV_5 (0<<5) 7241 #define DPLL_CFGCR2_KDIV_2 (1<<5) 7242 #define DPLL_CFGCR2_KDIV_3 (2<<5) 7243 #define DPLL_CFGCR2_KDIV_1 (3<<5) 7244 #define DPLL_CFGCR2_PDIV_MASK (7<<2) 7245 #define DPLL_CFGCR2_PDIV(x) (x<<2) 7246 #define DPLL_CFGCR2_PDIV_1 (0<<2) 7247 #define DPLL_CFGCR2_PDIV_2 (1<<2) 7248 #define DPLL_CFGCR2_PDIV_3 (2<<2) 7249 #define DPLL_CFGCR2_PDIV_7 (4<<2) 7250 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 7251 7252 #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8) 7253 #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8) 7254 7255 /* BXT display engine PLL */ 7256 #define BXT_DE_PLL_CTL 0x6d000 7257 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 7258 #define BXT_DE_PLL_RATIO_MASK 0xff 7259 7260 #define BXT_DE_PLL_ENABLE 0x46070 7261 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 7262 #define BXT_DE_PLL_LOCK (1 << 30) 7263 7264 /* GEN9 DC */ 7265 #define DC_STATE_EN 0x45504 7266 #define DC_STATE_EN_UPTO_DC5 (1<<0) 7267 #define DC_STATE_EN_DC9 (1<<3) 7268 7269 /* 7270 * SKL DC 7271 */ 7272 #define DC_STATE_EN 0x45504 7273 #define DC_STATE_EN_UPTO_DC5 (1<<0) 7274 #define DC_STATE_EN_UPTO_DC6 (2<<0) 7275 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 7276 7277 #define DC_STATE_DEBUG 0x45520 7278 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) 7279 7280 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 7281 * since on HSW we can't write to it using I915_WRITE. */ 7282 #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 7283 #define D_COMP_BDW 0x138144 7284 #define D_COMP_RCOMP_IN_PROGRESS (1<<9) 7285 #define D_COMP_COMP_FORCE (1<<8) 7286 #define D_COMP_COMP_DISABLE (1<<0) 7287 7288 /* Pipe WM_LINETIME - watermark line time */ 7289 #define PIPE_WM_LINETIME_A 0x45270 7290 #define PIPE_WM_LINETIME_B 0x45274 7291 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ 7292 PIPE_WM_LINETIME_B) 7293 #define PIPE_WM_LINETIME_MASK (0x1ff) 7294 #define PIPE_WM_LINETIME_TIME(x) ((x)) 7295 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 7296 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 7297 7298 /* SFUSE_STRAP */ 7299 #define SFUSE_STRAP 0xc2014 7300 #define SFUSE_STRAP_FUSE_LOCK (1<<13) 7301 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) 7302 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 7303 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 7304 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 7305 7306 #define WM_MISC 0x45260 7307 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 7308 7309 #define WM_DBG 0x45280 7310 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 7311 #define WM_DBG_DISALLOW_MAXFIFO (1<<1) 7312 #define WM_DBG_DISALLOW_SPRITE (1<<2) 7313 7314 /* pipe CSC */ 7315 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 7316 #define _PIPE_A_CSC_COEFF_BY 0x49014 7317 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 7318 #define _PIPE_A_CSC_COEFF_BU 0x4901c 7319 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 7320 #define _PIPE_A_CSC_COEFF_BV 0x49024 7321 #define _PIPE_A_CSC_MODE 0x49028 7322 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 7323 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 7324 #define CSC_MODE_YUV_TO_RGB (1 << 0) 7325 #define _PIPE_A_CSC_PREOFF_HI 0x49030 7326 #define _PIPE_A_CSC_PREOFF_ME 0x49034 7327 #define _PIPE_A_CSC_PREOFF_LO 0x49038 7328 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 7329 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 7330 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 7331 7332 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 7333 #define _PIPE_B_CSC_COEFF_BY 0x49114 7334 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 7335 #define _PIPE_B_CSC_COEFF_BU 0x4911c 7336 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 7337 #define _PIPE_B_CSC_COEFF_BV 0x49124 7338 #define _PIPE_B_CSC_MODE 0x49128 7339 #define _PIPE_B_CSC_PREOFF_HI 0x49130 7340 #define _PIPE_B_CSC_PREOFF_ME 0x49134 7341 #define _PIPE_B_CSC_PREOFF_LO 0x49138 7342 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 7343 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 7344 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 7345 7346 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 7347 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 7348 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 7349 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 7350 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 7351 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 7352 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 7353 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 7354 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 7355 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 7356 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 7357 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 7358 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 7359 7360 /* MIPI DSI registers */ 7361 7362 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ 7363 7364 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 7365 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 7366 #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 7367 #define DPI_ENABLE (1 << 31) /* A + C */ 7368 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 7369 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 7370 #define DUAL_LINK_MODE_SHIFT 26 7371 #define DUAL_LINK_MODE_MASK (1 << 26) 7372 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 7373 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 7374 #define DITHERING_ENABLE (1 << 25) /* A + C */ 7375 #define FLOPPED_HSTX (1 << 23) 7376 #define DE_INVERT (1 << 19) /* XXX */ 7377 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 7378 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 7379 #define AFE_LATCHOUT (1 << 17) 7380 #define LP_OUTPUT_HOLD (1 << 16) 7381 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 7382 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 7383 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 7384 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 7385 #define CSB_SHIFT 9 7386 #define CSB_MASK (3 << 9) 7387 #define CSB_20MHZ (0 << 9) 7388 #define CSB_10MHZ (1 << 9) 7389 #define CSB_40MHZ (2 << 9) 7390 #define BANDGAP_MASK (1 << 8) 7391 #define BANDGAP_PNW_CIRCUIT (0 << 8) 7392 #define BANDGAP_LNC_CIRCUIT (1 << 8) 7393 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 7394 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 7395 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 7396 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 7397 #define TEARING_EFFECT_MASK (3 << 2) 7398 #define TEARING_EFFECT_OFF (0 << 2) 7399 #define TEARING_EFFECT_DSI (1 << 2) 7400 #define TEARING_EFFECT_GPIO (2 << 2) 7401 #define LANE_CONFIGURATION_SHIFT 0 7402 #define LANE_CONFIGURATION_MASK (3 << 0) 7403 #define LANE_CONFIGURATION_4LANE (0 << 0) 7404 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 7405 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 7406 7407 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 7408 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 7409 #define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \ 7410 _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 7411 #define TEARING_EFFECT_DELAY_SHIFT 0 7412 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 7413 7414 /* XXX: all bits reserved */ 7415 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 7416 7417 /* MIPI DSI Controller and D-PHY registers */ 7418 7419 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 7420 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 7421 #define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \ 7422 _MIPIC_DEVICE_READY) 7423 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 7424 #define ULPS_STATE_MASK (3 << 1) 7425 #define ULPS_STATE_ENTER (2 << 1) 7426 #define ULPS_STATE_EXIT (1 << 1) 7427 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 7428 #define DEVICE_READY (1 << 0) 7429 7430 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 7431 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 7432 #define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \ 7433 _MIPIC_INTR_STAT) 7434 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 7435 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 7436 #define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \ 7437 _MIPIC_INTR_EN) 7438 #define TEARING_EFFECT (1 << 31) 7439 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 7440 #define GEN_READ_DATA_AVAIL (1 << 29) 7441 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 7442 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 7443 #define RX_PROT_VIOLATION (1 << 26) 7444 #define RX_INVALID_TX_LENGTH (1 << 25) 7445 #define ACK_WITH_NO_ERROR (1 << 24) 7446 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 7447 #define LP_RX_TIMEOUT (1 << 22) 7448 #define HS_TX_TIMEOUT (1 << 21) 7449 #define DPI_FIFO_UNDERRUN (1 << 20) 7450 #define LOW_CONTENTION (1 << 19) 7451 #define HIGH_CONTENTION (1 << 18) 7452 #define TXDSI_VC_ID_INVALID (1 << 17) 7453 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 7454 #define TXCHECKSUM_ERROR (1 << 15) 7455 #define TXECC_MULTIBIT_ERROR (1 << 14) 7456 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 7457 #define TXFALSE_CONTROL_ERROR (1 << 12) 7458 #define RXDSI_VC_ID_INVALID (1 << 11) 7459 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 7460 #define RXCHECKSUM_ERROR (1 << 9) 7461 #define RXECC_MULTIBIT_ERROR (1 << 8) 7462 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 7463 #define RXFALSE_CONTROL_ERROR (1 << 6) 7464 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 7465 #define RX_LP_TX_SYNC_ERROR (1 << 4) 7466 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 7467 #define RXEOT_SYNC_ERROR (1 << 2) 7468 #define RXSOT_SYNC_ERROR (1 << 1) 7469 #define RXSOT_ERROR (1 << 0) 7470 7471 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 7472 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 7473 #define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \ 7474 _MIPIC_DSI_FUNC_PRG) 7475 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 7476 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 7477 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 7478 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 7479 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 7480 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 7481 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 7482 #define VID_MODE_FORMAT_MASK (0xf << 7) 7483 #define VID_MODE_NOT_SUPPORTED (0 << 7) 7484 #define VID_MODE_FORMAT_RGB565 (1 << 7) 7485 #define VID_MODE_FORMAT_RGB666 (2 << 7) 7486 #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) 7487 #define VID_MODE_FORMAT_RGB888 (4 << 7) 7488 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 7489 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 7490 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 7491 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 7492 #define DATA_LANES_PRG_REG_SHIFT 0 7493 #define DATA_LANES_PRG_REG_MASK (7 << 0) 7494 7495 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 7496 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 7497 #define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \ 7498 _MIPIC_HS_TX_TIMEOUT) 7499 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 7500 7501 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 7502 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 7503 #define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \ 7504 _MIPIC_LP_RX_TIMEOUT) 7505 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 7506 7507 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 7508 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 7509 #define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \ 7510 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 7511 #define TURN_AROUND_TIMEOUT_MASK 0x3f 7512 7513 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 7514 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 7515 #define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \ 7516 _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 7517 #define DEVICE_RESET_TIMER_MASK 0xffff 7518 7519 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 7520 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 7521 #define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \ 7522 _MIPIC_DPI_RESOLUTION) 7523 #define VERTICAL_ADDRESS_SHIFT 16 7524 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 7525 #define HORIZONTAL_ADDRESS_SHIFT 0 7526 #define HORIZONTAL_ADDRESS_MASK 0xffff 7527 7528 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 7529 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 7530 #define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \ 7531 _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 7532 #define DBI_FIFO_EMPTY_HALF (0 << 0) 7533 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 7534 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 7535 7536 /* regs below are bits 15:0 */ 7537 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 7538 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 7539 #define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ 7540 _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 7541 7542 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 7543 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 7544 #define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \ 7545 _MIPIC_HBP_COUNT) 7546 7547 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 7548 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 7549 #define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \ 7550 _MIPIC_HFP_COUNT) 7551 7552 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 7553 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 7554 #define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \ 7555 _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 7556 7557 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 7558 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 7559 #define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ 7560 _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 7561 7562 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 7563 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 7564 #define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \ 7565 _MIPIC_VBP_COUNT) 7566 7567 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 7568 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 7569 #define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \ 7570 _MIPIC_VFP_COUNT) 7571 7572 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 7573 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 7574 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \ 7575 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 7576 7577 /* regs above are bits 15:0 */ 7578 7579 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 7580 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 7581 #define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \ 7582 _MIPIC_DPI_CONTROL) 7583 #define DPI_LP_MODE (1 << 6) 7584 #define BACKLIGHT_OFF (1 << 5) 7585 #define BACKLIGHT_ON (1 << 4) 7586 #define COLOR_MODE_OFF (1 << 3) 7587 #define COLOR_MODE_ON (1 << 2) 7588 #define TURN_ON (1 << 1) 7589 #define SHUTDOWN (1 << 0) 7590 7591 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 7592 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 7593 #define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \ 7594 _MIPIC_DPI_DATA) 7595 #define COMMAND_BYTE_SHIFT 0 7596 #define COMMAND_BYTE_MASK (0x3f << 0) 7597 7598 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 7599 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 7600 #define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \ 7601 _MIPIC_INIT_COUNT) 7602 #define MASTER_INIT_TIMER_SHIFT 0 7603 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 7604 7605 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 7606 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 7607 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \ 7608 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 7609 #define MAX_RETURN_PKT_SIZE_SHIFT 0 7610 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 7611 7612 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 7613 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 7614 #define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \ 7615 _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 7616 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 7617 #define DISABLE_VIDEO_BTA (1 << 3) 7618 #define IP_TG_CONFIG (1 << 2) 7619 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 7620 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 7621 #define VIDEO_MODE_BURST (3 << 0) 7622 7623 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 7624 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 7625 #define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \ 7626 _MIPIC_EOT_DISABLE) 7627 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 7628 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 7629 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 7630 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 7631 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 7632 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 7633 #define CLOCKSTOP (1 << 1) 7634 #define EOT_DISABLE (1 << 0) 7635 7636 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 7637 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 7638 #define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \ 7639 _MIPIC_LP_BYTECLK) 7640 #define LP_BYTECLK_SHIFT 0 7641 #define LP_BYTECLK_MASK (0xffff << 0) 7642 7643 /* bits 31:0 */ 7644 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 7645 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 7646 #define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \ 7647 _MIPIC_LP_GEN_DATA) 7648 7649 /* bits 31:0 */ 7650 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 7651 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 7652 #define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \ 7653 _MIPIC_HS_GEN_DATA) 7654 7655 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 7656 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 7657 #define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \ 7658 _MIPIC_LP_GEN_CTRL) 7659 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 7660 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 7661 #define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \ 7662 _MIPIC_HS_GEN_CTRL) 7663 #define LONG_PACKET_WORD_COUNT_SHIFT 8 7664 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 7665 #define SHORT_PACKET_PARAM_SHIFT 8 7666 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 7667 #define VIRTUAL_CHANNEL_SHIFT 6 7668 #define VIRTUAL_CHANNEL_MASK (3 << 6) 7669 #define DATA_TYPE_SHIFT 0 7670 #define DATA_TYPE_MASK (3f << 0) 7671 /* data type values, see include/video/mipi_display.h */ 7672 7673 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 7674 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 7675 #define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \ 7676 _MIPIC_GEN_FIFO_STAT) 7677 #define DPI_FIFO_EMPTY (1 << 28) 7678 #define DBI_FIFO_EMPTY (1 << 27) 7679 #define LP_CTRL_FIFO_EMPTY (1 << 26) 7680 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 7681 #define LP_CTRL_FIFO_FULL (1 << 24) 7682 #define HS_CTRL_FIFO_EMPTY (1 << 18) 7683 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 7684 #define HS_CTRL_FIFO_FULL (1 << 16) 7685 #define LP_DATA_FIFO_EMPTY (1 << 10) 7686 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 7687 #define LP_DATA_FIFO_FULL (1 << 8) 7688 #define HS_DATA_FIFO_EMPTY (1 << 2) 7689 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 7690 #define HS_DATA_FIFO_FULL (1 << 0) 7691 7692 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 7693 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 7694 #define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \ 7695 _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 7696 #define DBI_HS_LP_MODE_MASK (1 << 0) 7697 #define DBI_LP_MODE (1 << 0) 7698 #define DBI_HS_MODE (0 << 0) 7699 7700 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 7701 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 7702 #define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \ 7703 _MIPIC_DPHY_PARAM) 7704 #define EXIT_ZERO_COUNT_SHIFT 24 7705 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 7706 #define TRAIL_COUNT_SHIFT 16 7707 #define TRAIL_COUNT_MASK (0x1f << 16) 7708 #define CLK_ZERO_COUNT_SHIFT 8 7709 #define CLK_ZERO_COUNT_MASK (0xff << 8) 7710 #define PREPARE_COUNT_SHIFT 0 7711 #define PREPARE_COUNT_MASK (0x3f << 0) 7712 7713 /* bits 31:0 */ 7714 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 7715 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 7716 #define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \ 7717 _MIPIC_DBI_BW_CTRL) 7718 7719 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ 7720 + 0xb088) 7721 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ 7722 + 0xb888) 7723 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \ 7724 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 7725 #define LP_HS_SSW_CNT_SHIFT 16 7726 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 7727 #define HS_LP_PWR_SW_CNT_SHIFT 0 7728 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 7729 7730 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 7731 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 7732 #define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \ 7733 _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 7734 #define STOP_STATE_STALL_COUNTER_SHIFT 0 7735 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 7736 7737 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 7738 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 7739 #define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \ 7740 _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 7741 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 7742 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 7743 #define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \ 7744 _MIPIC_INTR_EN_REG_1) 7745 #define RX_CONTENTION_DETECTED (1 << 0) 7746 7747 /* XXX: only pipe A ?!? */ 7748 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 7749 #define DBI_TYPEC_ENABLE (1 << 31) 7750 #define DBI_TYPEC_WIP (1 << 30) 7751 #define DBI_TYPEC_OPTION_SHIFT 28 7752 #define DBI_TYPEC_OPTION_MASK (3 << 28) 7753 #define DBI_TYPEC_FREQ_SHIFT 24 7754 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 7755 #define DBI_TYPEC_OVERRIDE (1 << 8) 7756 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 7757 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 7758 7759 7760 /* MIPI adapter registers */ 7761 7762 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 7763 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 7764 #define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \ 7765 _MIPIC_CTRL) 7766 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 7767 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 7768 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 7769 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 7770 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 7771 #define READ_REQUEST_PRIORITY_SHIFT 3 7772 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 7773 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 7774 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 7775 #define RGB_FLIP_TO_BGR (1 << 2) 7776 7777 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 7778 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 7779 #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \ 7780 _MIPIC_DATA_ADDRESS) 7781 #define DATA_MEM_ADDRESS_SHIFT 5 7782 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 7783 #define DATA_VALID (1 << 0) 7784 7785 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 7786 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 7787 #define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \ 7788 _MIPIC_DATA_LENGTH) 7789 #define DATA_LENGTH_SHIFT 0 7790 #define DATA_LENGTH_MASK (0xfffff << 0) 7791 7792 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 7793 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 7794 #define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \ 7795 _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 7796 #define COMMAND_MEM_ADDRESS_SHIFT 5 7797 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 7798 #define AUTO_PWG_ENABLE (1 << 2) 7799 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 7800 #define COMMAND_VALID (1 << 0) 7801 7802 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 7803 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 7804 #define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \ 7805 _MIPIC_COMMAND_LENGTH) 7806 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 7807 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 7808 7809 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 7810 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 7811 #define MIPI_READ_DATA_RETURN(port, n) \ 7812 (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \ 7813 + 4 * (n)) /* n: 0...7 */ 7814 7815 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 7816 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 7817 #define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \ 7818 _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 7819 #define READ_DATA_VALID(n) (1 << (n)) 7820 7821 /* For UMS only (deprecated): */ 7822 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) 7823 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) 7824 7825 #endif /* _I915_REG_H_ */ 7826