1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 typedef struct { 29 uint32_t reg; 30 } i915_reg_t; 31 32 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) 33 34 #define INVALID_MMIO_REG _MMIO(0) 35 36 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg) 37 { 38 return reg.reg; 39 } 40 41 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) 42 { 43 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); 44 } 45 46 static inline bool i915_mmio_reg_valid(i915_reg_t reg) 47 { 48 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); 49 } 50 51 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 52 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 53 #define _PLANE(plane, a, b) _PIPE(plane, a, b) 54 #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) 55 #define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a))) 56 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 57 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 58 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 59 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ 60 (pipe) == PIPE_B ? (b) : (c)) 61 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c)) 62 #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ 63 (port) == PORT_B ? (b) : (c)) 64 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c)) 65 66 #define _MASKED_FIELD(mask, value) ({ \ 67 if (__builtin_constant_p(mask)) \ 68 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 69 if (__builtin_constant_p(value)) \ 70 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 71 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 72 BUILD_BUG_ON_MSG((value) & ~(mask), \ 73 "Incorrect value for mask"); \ 74 (mask) << 16 | (value); }) 75 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 76 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 77 78 79 80 /* PCI config space */ 81 82 #define MCHBAR_I915 0x44 83 #define MCHBAR_I965 0x48 84 #define MCHBAR_SIZE (4 * 4096) 85 86 #define DEVEN 0x54 87 #define DEVEN_MCHBAR_EN (1 << 28) 88 89 #define BSM 0x5c 90 #if 0 /* fix from upstream */ 91 #define BSM_MASK (0xFFFF << 20) 92 #else 93 #define BSM_MASK (-(1u << 20)) 94 #endif 95 96 #define HPLLCC 0xc0 /* 85x only */ 97 #define GC_CLOCK_CONTROL_MASK (0x7 << 0) 98 #define GC_CLOCK_133_200 (0 << 0) 99 #define GC_CLOCK_100_200 (1 << 0) 100 #define GC_CLOCK_100_133 (2 << 0) 101 #define GC_CLOCK_133_266 (3 << 0) 102 #define GC_CLOCK_133_200_2 (4 << 0) 103 #define GC_CLOCK_133_266_2 (5 << 0) 104 #define GC_CLOCK_166_266 (6 << 0) 105 #define GC_CLOCK_166_250 (7 << 0) 106 107 #define I915_GDRST 0xc0 /* PCI config register */ 108 #define GRDOM_FULL (0 << 2) 109 #define GRDOM_RENDER (1 << 2) 110 #define GRDOM_MEDIA (3 << 2) 111 #define GRDOM_MASK (3 << 2) 112 #define GRDOM_RESET_STATUS (1 << 1) 113 #define GRDOM_RESET_ENABLE (1 << 0) 114 115 #define GCDGMBUS 0xcc 116 117 #define GCFGC2 0xda 118 #define GCFGC 0xf0 /* 915+ only */ 119 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 120 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 121 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 122 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 123 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 124 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 125 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 126 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 127 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 128 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 129 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 130 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 131 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 132 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 133 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 134 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 135 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 136 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 137 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 138 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 139 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 140 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 141 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 142 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 143 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 144 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 145 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 146 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 147 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 148 149 #define ASLE 0xe4 150 #define ASLS 0xfc 151 152 #define SWSCI 0xe8 153 #define SWSCI_SCISEL (1 << 15) 154 #define SWSCI_GSSCIE (1 << 0) 155 156 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 157 158 159 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) 160 #define ILK_GRDOM_FULL (0<<1) 161 #define ILK_GRDOM_RENDER (1<<1) 162 #define ILK_GRDOM_MEDIA (3<<1) 163 #define ILK_GRDOM_MASK (3<<1) 164 #define ILK_GRDOM_RESET_ENABLE (1<<0) 165 166 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 167 #define GEN6_MBC_SNPCR_SHIFT 21 168 #define GEN6_MBC_SNPCR_MASK (3<<21) 169 #define GEN6_MBC_SNPCR_MAX (0<<21) 170 #define GEN6_MBC_SNPCR_MED (1<<21) 171 #define GEN6_MBC_SNPCR_LOW (2<<21) 172 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 173 174 #define VLV_G3DCTL _MMIO(0x9024) 175 #define VLV_GSCKGCTL _MMIO(0x9028) 176 177 #define GEN6_MBCTL _MMIO(0x0907c) 178 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 179 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 180 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 181 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 182 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 183 184 #define GEN6_GDRST _MMIO(0x941c) 185 #define GEN6_GRDOM_FULL (1 << 0) 186 #define GEN6_GRDOM_RENDER (1 << 1) 187 #define GEN6_GRDOM_MEDIA (1 << 2) 188 #define GEN6_GRDOM_BLT (1 << 3) 189 #define GEN6_GRDOM_VECS (1 << 4) 190 #define GEN9_GRDOM_GUC (1 << 5) 191 #define GEN8_GRDOM_MEDIA2 (1 << 7) 192 193 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228) 194 #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518) 195 #define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base+0x220) 196 #define PP_DIR_DCLV_2G 0xffffffff 197 198 #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4) 199 #define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8) 200 201 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) 202 #define GEN8_RPCS_ENABLE (1 << 31) 203 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 204 #define GEN8_RPCS_S_CNT_SHIFT 15 205 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 206 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 207 #define GEN8_RPCS_SS_CNT_SHIFT 8 208 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 209 #define GEN8_RPCS_EU_MAX_SHIFT 4 210 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 211 #define GEN8_RPCS_EU_MIN_SHIFT 0 212 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 213 214 #define GAM_ECOCHK _MMIO(0x4090) 215 #define BDW_DISABLE_HDC_INVALIDATION (1<<25) 216 #define ECOCHK_SNB_BIT (1<<10) 217 #define ECOCHK_DIS_TLB (1<<8) 218 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) 219 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 220 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 221 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) 222 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) 223 #define ECOCHK_PPGTT_UC_HSW (0x1<<3) 224 #define ECOCHK_PPGTT_WT_HSW (0x2<<3) 225 #define ECOCHK_PPGTT_WB_HSW (0x3<<3) 226 227 #define GEN8_CONFIG0 _MMIO(0xD00) 228 #define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1) 229 230 #define GAC_ECO_BITS _MMIO(0x14090) 231 #define ECOBITS_SNB_BIT (1<<13) 232 #define ECOBITS_PPGTT_CACHE64B (3<<8) 233 #define ECOBITS_PPGTT_CACHE4B (0<<8) 234 235 #define GAB_CTL _MMIO(0x24000) 236 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 237 238 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 239 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 240 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 241 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 242 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 243 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 244 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 245 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 246 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 247 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 248 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 249 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 250 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 251 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 252 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 253 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 254 255 /* VGA stuff */ 256 257 #define VGA_ST01_MDA 0x3ba 258 #define VGA_ST01_CGA 0x3da 259 260 #define _VGA_MSR_WRITE _MMIO(0x3c2) 261 #define VGA_MSR_WRITE 0x3c2 262 #define VGA_MSR_READ 0x3cc 263 #define VGA_MSR_MEM_EN (1<<1) 264 #define VGA_MSR_CGA_MODE (1<<0) 265 266 #define VGA_SR_INDEX 0x3c4 267 #define SR01 1 268 #define VGA_SR_DATA 0x3c5 269 270 #define VGA_AR_INDEX 0x3c0 271 #define VGA_AR_VID_EN (1<<5) 272 #define VGA_AR_DATA_WRITE 0x3c0 273 #define VGA_AR_DATA_READ 0x3c1 274 275 #define VGA_GR_INDEX 0x3ce 276 #define VGA_GR_DATA 0x3cf 277 /* GR05 */ 278 #define VGA_GR_MEM_READ_MODE_SHIFT 3 279 #define VGA_GR_MEM_READ_MODE_PLANE 1 280 /* GR06 */ 281 #define VGA_GR_MEM_MODE_MASK 0xc 282 #define VGA_GR_MEM_MODE_SHIFT 2 283 #define VGA_GR_MEM_A0000_AFFFF 0 284 #define VGA_GR_MEM_A0000_BFFFF 1 285 #define VGA_GR_MEM_B0000_B7FFF 2 286 #define VGA_GR_MEM_B0000_BFFFF 3 287 288 #define VGA_DACMASK 0x3c6 289 #define VGA_DACRX 0x3c7 290 #define VGA_DACWX 0x3c8 291 #define VGA_DACDATA 0x3c9 292 293 #define VGA_CR_INDEX_MDA 0x3b4 294 #define VGA_CR_DATA_MDA 0x3b5 295 #define VGA_CR_INDEX_CGA 0x3d4 296 #define VGA_CR_DATA_CGA 0x3d5 297 298 /* 299 * Instruction field definitions used by the command parser 300 */ 301 #define INSTR_CLIENT_SHIFT 29 302 #define INSTR_CLIENT_MASK 0xE0000000 303 #define INSTR_MI_CLIENT 0x0 304 #define INSTR_BC_CLIENT 0x2 305 #define INSTR_RC_CLIENT 0x3 306 #define INSTR_SUBCLIENT_SHIFT 27 307 #define INSTR_SUBCLIENT_MASK 0x18000000 308 #define INSTR_MEDIA_SUBCLIENT 0x2 309 #define INSTR_26_TO_24_MASK 0x7000000 310 #define INSTR_26_TO_24_SHIFT 24 311 312 /* 313 * Memory interface instructions used by the kernel 314 */ 315 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 316 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ 317 #define MI_GLOBAL_GTT (1<<22) 318 319 #define MI_NOOP MI_INSTR(0, 0) 320 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 321 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 322 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 323 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 324 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 325 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 326 #define MI_FLUSH MI_INSTR(0x04, 0) 327 #define MI_READ_FLUSH (1 << 0) 328 #define MI_EXE_FLUSH (1 << 1) 329 #define MI_NO_WRITE_FLUSH (1 << 2) 330 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 331 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 332 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 333 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 334 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 335 #define MI_ARB_ENABLE (1<<0) 336 #define MI_ARB_DISABLE (0<<0) 337 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 338 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 339 #define MI_SUSPEND_FLUSH_EN (1<<0) 340 #define MI_SET_APPID MI_INSTR(0x0e, 0) 341 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 342 #define MI_OVERLAY_CONTINUE (0x0<<21) 343 #define MI_OVERLAY_ON (0x1<<21) 344 #define MI_OVERLAY_OFF (0x2<<21) 345 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 346 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 347 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 348 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 349 /* IVB has funny definitions for which plane to flip. */ 350 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 351 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 352 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 353 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 354 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 355 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 356 /* SKL ones */ 357 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) 358 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) 359 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) 360 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) 361 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) 362 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) 363 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) 364 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) 365 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) 366 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ 367 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 368 #define MI_SEMAPHORE_UPDATE (1<<21) 369 #define MI_SEMAPHORE_COMPARE (1<<20) 370 #define MI_SEMAPHORE_REGISTER (1<<18) 371 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 372 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 373 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 374 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 375 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 376 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 377 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 378 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 379 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 380 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 381 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 382 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 383 #define MI_SEMAPHORE_SYNC_INVALID (3<<16) 384 #define MI_SEMAPHORE_SYNC_MASK (3<<16) 385 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 386 #define MI_MM_SPACE_GTT (1<<8) 387 #define MI_MM_SPACE_PHYSICAL (0<<8) 388 #define MI_SAVE_EXT_STATE_EN (1<<3) 389 #define MI_RESTORE_EXT_STATE_EN (1<<2) 390 #define MI_FORCE_RESTORE (1<<1) 391 #define MI_RESTORE_INHIBIT (1<<0) 392 #define HSW_MI_RS_SAVE_STATE_EN (1<<3) 393 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2) 394 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ 395 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) 396 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ 397 #define MI_SEMAPHORE_POLL (1<<15) 398 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) 399 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 400 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) 401 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ 402 #define MI_USE_GGTT (1 << 22) /* g4x+ */ 403 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 404 #define MI_STORE_DWORD_INDEX_SHIFT 2 405 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 406 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 407 * simply ignores the register load under certain conditions. 408 * - One can actually load arbitrary many arbitrary registers: Simply issue x 409 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 410 */ 411 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) 412 #define MI_LRI_FORCE_POSTED (1<<12) 413 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) 414 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2) 415 #define MI_SRM_LRM_GLOBAL_GTT (1<<22) 416 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 417 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 418 #define MI_INVALIDATE_TLB (1<<18) 419 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 420 #define MI_FLUSH_DW_OP_MASK (3<<14) 421 #define MI_FLUSH_DW_NOTIFY (1<<8) 422 #define MI_INVALIDATE_BSD (1<<7) 423 #define MI_FLUSH_DW_USE_GTT (1<<2) 424 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 425 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1) 426 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) 427 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 428 #define MI_BATCH_NON_SECURE (1) 429 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 430 #define MI_BATCH_NON_SECURE_I965 (1<<8) 431 #define MI_BATCH_PPGTT_HSW (1<<8) 432 #define MI_BATCH_NON_SECURE_HSW (1<<13) 433 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 434 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 435 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) 436 #define MI_BATCH_RESOURCE_STREAMER (1<<10) 437 438 #define MI_PREDICATE_SRC0 _MMIO(0x2400) 439 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) 440 #define MI_PREDICATE_SRC1 _MMIO(0x2408) 441 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) 442 443 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) 444 #define LOWER_SLICE_ENABLED (1<<0) 445 #define LOWER_SLICE_DISABLED (0<<0) 446 447 /* 448 * 3D instructions used by the kernel 449 */ 450 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 451 452 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4) 453 #define GEN9_MEDIA_POOL_ENABLE (1 << 31) 454 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 455 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 456 #define SC_UPDATE_SCISSOR (0x1<<1) 457 #define SC_ENABLE_MASK (0x1<<0) 458 #define SC_ENABLE (0x1<<0) 459 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 460 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 461 #define SCI_YMIN_MASK (0xffff<<16) 462 #define SCI_XMIN_MASK (0xffff<<0) 463 #define SCI_YMAX_MASK (0xffff<<16) 464 #define SCI_XMAX_MASK (0xffff<<0) 465 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 466 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 467 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 468 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 469 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 470 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 471 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 472 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 473 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 474 475 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) 476 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 477 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 478 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 479 #define BLT_WRITE_A (2<<20) 480 #define BLT_WRITE_RGB (1<<20) 481 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) 482 #define BLT_DEPTH_8 (0<<24) 483 #define BLT_DEPTH_16_565 (1<<24) 484 #define BLT_DEPTH_16_1555 (2<<24) 485 #define BLT_DEPTH_32 (3<<24) 486 #define BLT_ROP_SRC_COPY (0xcc<<16) 487 #define BLT_ROP_COLOR_COPY (0xf0<<16) 488 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 489 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 490 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 491 #define ASYNC_FLIP (1<<22) 492 #define DISPLAY_PLANE_A (0<<20) 493 #define DISPLAY_PLANE_B (1<<20) 494 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) 495 #define PIPE_CONTROL_FLUSH_L3 (1<<27) 496 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 497 #define PIPE_CONTROL_MMIO_WRITE (1<<23) 498 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 499 #define PIPE_CONTROL_CS_STALL (1<<20) 500 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 501 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) 502 #define PIPE_CONTROL_QW_WRITE (1<<14) 503 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) 504 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 505 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 506 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 507 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 508 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 509 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 510 #define PIPE_CONTROL_NOTIFY (1<<8) 511 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ 512 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) 513 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 514 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 515 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 516 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 517 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 518 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 519 520 /* 521 * Commands used only by the command parser 522 */ 523 #define MI_SET_PREDICATE MI_INSTR(0x01, 0) 524 #define MI_ARB_CHECK MI_INSTR(0x05, 0) 525 #define MI_RS_CONTROL MI_INSTR(0x06, 0) 526 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) 527 #define MI_PREDICATE MI_INSTR(0x0C, 0) 528 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) 529 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) 530 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) 531 #define MI_URB_CLEAR MI_INSTR(0x19, 0) 532 #define MI_UPDATE_GTT MI_INSTR(0x23, 0) 533 #define MI_CLFLUSH MI_INSTR(0x27, 0) 534 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) 535 #define MI_REPORT_PERF_COUNT_GGTT (1<<0) 536 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) 537 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) 538 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) 539 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) 540 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) 541 542 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) 543 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) 544 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) 545 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) 546 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) 547 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) 548 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ 549 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) 550 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ 551 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) 552 #define GFX_OP_3DSTATE_SO_DECL_LIST \ 553 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) 554 555 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ 556 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) 557 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ 558 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) 559 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ 560 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) 561 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ 562 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) 563 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ 564 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) 565 566 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) 567 568 #define COLOR_BLT ((0x2<<29)|(0x40<<22)) 569 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) 570 571 /* 572 * Registers used only by the command parser 573 */ 574 #define BCS_SWCTRL _MMIO(0x22200) 575 576 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 577 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 578 #define HS_INVOCATION_COUNT _MMIO(0x2300) 579 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 580 #define DS_INVOCATION_COUNT _MMIO(0x2308) 581 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 582 #define IA_VERTICES_COUNT _MMIO(0x2310) 583 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 584 #define IA_PRIMITIVES_COUNT _MMIO(0x2318) 585 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 586 #define VS_INVOCATION_COUNT _MMIO(0x2320) 587 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 588 #define GS_INVOCATION_COUNT _MMIO(0x2328) 589 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 590 #define GS_PRIMITIVES_COUNT _MMIO(0x2330) 591 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 592 #define CL_INVOCATION_COUNT _MMIO(0x2338) 593 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 594 #define CL_PRIMITIVES_COUNT _MMIO(0x2340) 595 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 596 #define PS_INVOCATION_COUNT _MMIO(0x2348) 597 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 598 #define PS_DEPTH_COUNT _MMIO(0x2350) 599 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 600 601 /* There are the 4 64-bit counter registers, one for each stream output */ 602 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 603 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 604 605 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 606 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 607 608 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 609 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 610 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 611 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 612 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) 613 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 614 615 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 616 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 617 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 618 619 /* There are the 16 64-bit CS General Purpose Registers */ 620 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) 621 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) 622 623 #define OACONTROL _MMIO(0x2360) 624 625 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 626 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 627 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 628 629 /* 630 * Reset registers 631 */ 632 #define DEBUG_RESET_I830 _MMIO(0x6070) 633 #define DEBUG_RESET_FULL (1<<7) 634 #define DEBUG_RESET_RENDER (1<<8) 635 #define DEBUG_RESET_DISPLAY (1<<9) 636 637 /* 638 * IOSF sideband 639 */ 640 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 641 #define IOSF_DEVFN_SHIFT 24 642 #define IOSF_OPCODE_SHIFT 16 643 #define IOSF_PORT_SHIFT 8 644 #define IOSF_BYTE_ENABLES_SHIFT 4 645 #define IOSF_BAR_SHIFT 1 646 #define IOSF_SB_BUSY (1<<0) 647 #define IOSF_PORT_BUNIT 0x03 648 #define IOSF_PORT_PUNIT 0x04 649 #define IOSF_PORT_NC 0x11 650 #define IOSF_PORT_DPIO 0x12 651 #define IOSF_PORT_GPIO_NC 0x13 652 #define IOSF_PORT_CCK 0x14 653 #define IOSF_PORT_DPIO_2 0x1a 654 #define IOSF_PORT_FLISDSI 0x1b 655 #define IOSF_PORT_GPIO_SC 0x48 656 #define IOSF_PORT_GPIO_SUS 0xa8 657 #define IOSF_PORT_CCU 0xa9 658 #define CHV_IOSF_PORT_GPIO_N 0x13 659 #define CHV_IOSF_PORT_GPIO_SE 0x48 660 #define CHV_IOSF_PORT_GPIO_E 0xa8 661 #define CHV_IOSF_PORT_GPIO_SW 0xb2 662 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 663 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 664 665 /* See configdb bunit SB addr map */ 666 #define BUNIT_REG_BISOC 0x11 667 668 #define PUNIT_REG_DSPFREQ 0x36 669 #define DSPFREQSTAT_SHIFT_CHV 24 670 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 671 #define DSPFREQGUAR_SHIFT_CHV 8 672 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 673 #define DSPFREQSTAT_SHIFT 30 674 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 675 #define DSPFREQGUAR_SHIFT 14 676 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 677 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 678 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 679 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 680 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 681 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 682 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 683 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 684 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 685 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 686 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 687 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 688 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 689 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 690 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 691 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 692 693 /* See the PUNIT HAS v0.8 for the below bits */ 694 enum punit_power_well { 695 /* These numbers are fixed and must match the position of the pw bits */ 696 PUNIT_POWER_WELL_RENDER = 0, 697 PUNIT_POWER_WELL_MEDIA = 1, 698 PUNIT_POWER_WELL_DISP2D = 3, 699 PUNIT_POWER_WELL_DPIO_CMN_BC = 5, 700 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, 701 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, 702 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, 703 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, 704 PUNIT_POWER_WELL_DPIO_RX0 = 10, 705 PUNIT_POWER_WELL_DPIO_RX1 = 11, 706 PUNIT_POWER_WELL_DPIO_CMN_D = 12, 707 708 /* Not actual bit groups. Used as IDs for lookup_power_well() */ 709 PUNIT_POWER_WELL_ALWAYS_ON, 710 }; 711 712 enum skl_disp_power_wells { 713 /* These numbers are fixed and must match the position of the pw bits */ 714 SKL_DISP_PW_MISC_IO, 715 SKL_DISP_PW_DDI_A_E, 716 SKL_DISP_PW_DDI_B, 717 SKL_DISP_PW_DDI_C, 718 SKL_DISP_PW_DDI_D, 719 SKL_DISP_PW_1 = 14, 720 SKL_DISP_PW_2, 721 722 /* Not actual bit groups. Used as IDs for lookup_power_well() */ 723 SKL_DISP_PW_ALWAYS_ON, 724 SKL_DISP_PW_DC_OFF, 725 726 BXT_DPIO_CMN_A, 727 BXT_DPIO_CMN_BC, 728 }; 729 730 #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) 731 #define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) 732 733 #define PUNIT_REG_PWRGT_CTRL 0x60 734 #define PUNIT_REG_PWRGT_STATUS 0x61 735 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) 736 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) 737 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) 738 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) 739 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) 740 741 #define PUNIT_REG_GPU_LFM 0xd3 742 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 743 #define PUNIT_REG_GPU_FREQ_STS 0xd8 744 #define GPLLENABLE (1<<4) 745 #define GENFREQSTATUS (1<<0) 746 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 747 #define PUNIT_REG_CZ_TIMESTAMP 0xce 748 749 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 750 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 751 752 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 753 #define FB_GFX_FREQ_FUSE_MASK 0xff 754 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 755 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 756 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 757 758 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 759 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 760 761 #define PUNIT_REG_DDR_SETUP2 0x139 762 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 763 #define FORCE_DDR_LOW_FREQ (1 << 1) 764 #define FORCE_DDR_HIGH_FREQ (1 << 0) 765 766 #define PUNIT_GPU_STATUS_REG 0xdb 767 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 768 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 769 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 770 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 771 772 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf 773 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 774 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 775 776 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 777 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 778 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 779 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 780 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 781 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 782 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 783 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 784 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 785 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 786 787 #define VLV_TURBO_SOC_OVERRIDE 0x04 788 #define VLV_OVERRIDE_EN 1 789 #define VLV_SOC_TDP_EN (1 << 1) 790 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 791 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 792 793 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 794 795 /* vlv2 north clock has */ 796 #define CCK_FUSE_REG 0x8 797 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 798 #define CCK_REG_DSI_PLL_FUSE 0x44 799 #define CCK_REG_DSI_PLL_CONTROL 0x48 800 #define DSI_PLL_VCO_EN (1 << 31) 801 #define DSI_PLL_LDO_GATE (1 << 30) 802 #define DSI_PLL_P1_POST_DIV_SHIFT 17 803 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 804 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 805 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 806 #define DSI_PLL_MUX_MASK (3 << 9) 807 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 808 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 809 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 810 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 811 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 812 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 813 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 814 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 815 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 816 #define DSI_PLL_LOCK (1 << 0) 817 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 818 #define DSI_PLL_LFSR (1 << 31) 819 #define DSI_PLL_FRACTION_EN (1 << 30) 820 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 821 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 822 #define DSI_PLL_USYNC_CNT_SHIFT 18 823 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 824 #define DSI_PLL_N1_DIV_SHIFT 16 825 #define DSI_PLL_N1_DIV_MASK (3 << 16) 826 #define DSI_PLL_M1_DIV_SHIFT 0 827 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 828 #define CCK_CZ_CLOCK_CONTROL 0x62 829 #define CCK_GPLL_CLOCK_CONTROL 0x67 830 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 831 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 832 #define CCK_TRUNK_FORCE_ON (1 << 17) 833 #define CCK_TRUNK_FORCE_OFF (1 << 16) 834 #define CCK_FREQUENCY_STATUS (0x1f << 8) 835 #define CCK_FREQUENCY_STATUS_SHIFT 8 836 #define CCK_FREQUENCY_VALUES (0x1f << 0) 837 838 /** 839 * DOC: DPIO 840 * 841 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI 842 * ports. DPIO is the name given to such a display PHY. These PHYs 843 * don't follow the standard programming model using direct MMIO 844 * registers, and instead their registers must be accessed trough IOSF 845 * sideband. VLV has one such PHY for driving ports B and C, and CHV 846 * adds another PHY for driving port D. Each PHY responds to specific 847 * IOSF-SB port. 848 * 849 * Each display PHY is made up of one or two channels. Each channel 850 * houses a common lane part which contains the PLL and other common 851 * logic. CH0 common lane also contains the IOSF-SB logic for the 852 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 853 * must be running when any DPIO registers are accessed. 854 * 855 * In addition to having their own registers, the PHYs are also 856 * controlled through some dedicated signals from the display 857 * controller. These include PLL reference clock enable, PLL enable, 858 * and CRI clock selection, for example. 859 * 860 * Eeach channel also has two splines (also called data lanes), and 861 * each spline is made up of one Physical Access Coding Sub-Layer 862 * (PCS) block and two TX lanes. So each channel has two PCS blocks 863 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 864 * data/clock pairs depending on the output type. 865 * 866 * Additionally the PHY also contains an AUX lane with AUX blocks 867 * for each channel. This is used for DP AUX communication, but 868 * this fact isn't really relevant for the driver since AUX is 869 * controlled from the display controller side. No DPIO registers 870 * need to be accessed during AUX communication, 871 * 872 * Generally on VLV/CHV the common lane corresponds to the pipe and 873 * the spline (PCS/TX) corresponds to the port. 874 * 875 * For dual channel PHY (VLV/CHV): 876 * 877 * pipe A == CMN/PLL/REF CH0 878 * 879 * pipe B == CMN/PLL/REF CH1 880 * 881 * port B == PCS/TX CH0 882 * 883 * port C == PCS/TX CH1 884 * 885 * This is especially important when we cross the streams 886 * ie. drive port B with pipe B, or port C with pipe A. 887 * 888 * For single channel PHY (CHV): 889 * 890 * pipe C == CMN/PLL/REF CH0 891 * 892 * port D == PCS/TX CH0 893 * 894 * On BXT the entire PHY channel corresponds to the port. That means 895 * the PLL is also now associated with the port rather than the pipe, 896 * and so the clock needs to be routed to the appropriate transcoder. 897 * Port A PLL is directly connected to transcoder EDP and port B/C 898 * PLLs can be routed to any transcoder A/B/C. 899 * 900 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 901 * digital port D (CHV) or port A (BXT). :: 902 * 903 * 904 * Dual channel PHY (VLV/CHV/BXT) 905 * --------------------------------- 906 * | CH0 | CH1 | 907 * | CMN/PLL/REF | CMN/PLL/REF | 908 * |---------------|---------------| Display PHY 909 * | PCS01 | PCS23 | PCS01 | PCS23 | 910 * |-------|-------|-------|-------| 911 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 912 * --------------------------------- 913 * | DDI0 | DDI1 | DP/HDMI ports 914 * --------------------------------- 915 * 916 * Single channel PHY (CHV/BXT) 917 * ----------------- 918 * | CH0 | 919 * | CMN/PLL/REF | 920 * |---------------| Display PHY 921 * | PCS01 | PCS23 | 922 * |-------|-------| 923 * |TX0|TX1|TX2|TX3| 924 * ----------------- 925 * | DDI2 | DP/HDMI port 926 * ----------------- 927 */ 928 #define DPIO_DEVFN 0 929 930 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 931 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 932 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 933 #define DPIO_SFR_BYPASS (1<<1) 934 #define DPIO_CMNRST (1<<0) 935 936 #define DPIO_PHY(pipe) ((pipe) >> 1) 937 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 938 939 /* 940 * Per pipe/PLL DPIO regs 941 */ 942 #define _VLV_PLL_DW3_CH0 0x800c 943 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 944 #define DPIO_POST_DIV_DAC 0 945 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 946 #define DPIO_POST_DIV_LVDS1 2 947 #define DPIO_POST_DIV_LVDS2 3 948 #define DPIO_K_SHIFT (24) /* 4 bits */ 949 #define DPIO_P1_SHIFT (21) /* 3 bits */ 950 #define DPIO_P2_SHIFT (16) /* 5 bits */ 951 #define DPIO_N_SHIFT (12) /* 4 bits */ 952 #define DPIO_ENABLE_CALIBRATION (1<<11) 953 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 954 #define DPIO_M2DIV_MASK 0xff 955 #define _VLV_PLL_DW3_CH1 0x802c 956 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 957 958 #define _VLV_PLL_DW5_CH0 0x8014 959 #define DPIO_REFSEL_OVERRIDE 27 960 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 961 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 962 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 963 #define DPIO_PLL_REFCLK_SEL_MASK 3 964 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 965 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 966 #define _VLV_PLL_DW5_CH1 0x8034 967 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 968 969 #define _VLV_PLL_DW7_CH0 0x801c 970 #define _VLV_PLL_DW7_CH1 0x803c 971 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 972 973 #define _VLV_PLL_DW8_CH0 0x8040 974 #define _VLV_PLL_DW8_CH1 0x8060 975 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 976 977 #define VLV_PLL_DW9_BCAST 0xc044 978 #define _VLV_PLL_DW9_CH0 0x8044 979 #define _VLV_PLL_DW9_CH1 0x8064 980 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 981 982 #define _VLV_PLL_DW10_CH0 0x8048 983 #define _VLV_PLL_DW10_CH1 0x8068 984 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 985 986 #define _VLV_PLL_DW11_CH0 0x804c 987 #define _VLV_PLL_DW11_CH1 0x806c 988 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 989 990 /* Spec for ref block start counts at DW10 */ 991 #define VLV_REF_DW13 0x80ac 992 993 #define VLV_CMN_DW0 0x8100 994 995 /* 996 * Per DDI channel DPIO regs 997 */ 998 999 #define _VLV_PCS_DW0_CH0 0x8200 1000 #define _VLV_PCS_DW0_CH1 0x8400 1001 #define DPIO_PCS_TX_LANE2_RESET (1<<16) 1002 #define DPIO_PCS_TX_LANE1_RESET (1<<7) 1003 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) 1004 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) 1005 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 1006 1007 #define _VLV_PCS01_DW0_CH0 0x200 1008 #define _VLV_PCS23_DW0_CH0 0x400 1009 #define _VLV_PCS01_DW0_CH1 0x2600 1010 #define _VLV_PCS23_DW0_CH1 0x2800 1011 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 1012 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 1013 1014 #define _VLV_PCS_DW1_CH0 0x8204 1015 #define _VLV_PCS_DW1_CH1 0x8404 1016 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) 1017 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 1018 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 1019 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 1020 #define DPIO_PCS_CLK_SOFT_RESET (1<<5) 1021 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 1022 1023 #define _VLV_PCS01_DW1_CH0 0x204 1024 #define _VLV_PCS23_DW1_CH0 0x404 1025 #define _VLV_PCS01_DW1_CH1 0x2604 1026 #define _VLV_PCS23_DW1_CH1 0x2804 1027 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 1028 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 1029 1030 #define _VLV_PCS_DW8_CH0 0x8220 1031 #define _VLV_PCS_DW8_CH1 0x8420 1032 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 1033 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 1034 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 1035 1036 #define _VLV_PCS01_DW8_CH0 0x0220 1037 #define _VLV_PCS23_DW8_CH0 0x0420 1038 #define _VLV_PCS01_DW8_CH1 0x2620 1039 #define _VLV_PCS23_DW8_CH1 0x2820 1040 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 1041 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 1042 1043 #define _VLV_PCS_DW9_CH0 0x8224 1044 #define _VLV_PCS_DW9_CH1 0x8424 1045 #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) 1046 #define DPIO_PCS_TX2MARGIN_000 (0<<13) 1047 #define DPIO_PCS_TX2MARGIN_101 (1<<13) 1048 #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) 1049 #define DPIO_PCS_TX1MARGIN_000 (0<<10) 1050 #define DPIO_PCS_TX1MARGIN_101 (1<<10) 1051 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 1052 1053 #define _VLV_PCS01_DW9_CH0 0x224 1054 #define _VLV_PCS23_DW9_CH0 0x424 1055 #define _VLV_PCS01_DW9_CH1 0x2624 1056 #define _VLV_PCS23_DW9_CH1 0x2824 1057 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 1058 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 1059 1060 #define _CHV_PCS_DW10_CH0 0x8228 1061 #define _CHV_PCS_DW10_CH1 0x8428 1062 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) 1063 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) 1064 #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) 1065 #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) 1066 #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) 1067 #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) 1068 #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) 1069 #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) 1070 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 1071 1072 #define _VLV_PCS01_DW10_CH0 0x0228 1073 #define _VLV_PCS23_DW10_CH0 0x0428 1074 #define _VLV_PCS01_DW10_CH1 0x2628 1075 #define _VLV_PCS23_DW10_CH1 0x2828 1076 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 1077 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 1078 1079 #define _VLV_PCS_DW11_CH0 0x822c 1080 #define _VLV_PCS_DW11_CH1 0x842c 1081 #define DPIO_TX2_STAGGER_MASK(x) ((x)<<24) 1082 #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) 1083 #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) 1084 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) 1085 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 1086 1087 #define _VLV_PCS01_DW11_CH0 0x022c 1088 #define _VLV_PCS23_DW11_CH0 0x042c 1089 #define _VLV_PCS01_DW11_CH1 0x262c 1090 #define _VLV_PCS23_DW11_CH1 0x282c 1091 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 1092 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 1093 1094 #define _VLV_PCS01_DW12_CH0 0x0230 1095 #define _VLV_PCS23_DW12_CH0 0x0430 1096 #define _VLV_PCS01_DW12_CH1 0x2630 1097 #define _VLV_PCS23_DW12_CH1 0x2830 1098 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 1099 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 1100 1101 #define _VLV_PCS_DW12_CH0 0x8230 1102 #define _VLV_PCS_DW12_CH1 0x8430 1103 #define DPIO_TX2_STAGGER_MULT(x) ((x)<<20) 1104 #define DPIO_TX1_STAGGER_MULT(x) ((x)<<16) 1105 #define DPIO_TX1_STAGGER_MASK(x) ((x)<<8) 1106 #define DPIO_LANESTAGGER_STRAP_OVRD (1<<6) 1107 #define DPIO_LANESTAGGER_STRAP(x) ((x)<<0) 1108 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 1109 1110 #define _VLV_PCS_DW14_CH0 0x8238 1111 #define _VLV_PCS_DW14_CH1 0x8438 1112 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 1113 1114 #define _VLV_PCS_DW23_CH0 0x825c 1115 #define _VLV_PCS_DW23_CH1 0x845c 1116 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 1117 1118 #define _VLV_TX_DW2_CH0 0x8288 1119 #define _VLV_TX_DW2_CH1 0x8488 1120 #define DPIO_SWING_MARGIN000_SHIFT 16 1121 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 1122 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 1123 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 1124 1125 #define _VLV_TX_DW3_CH0 0x828c 1126 #define _VLV_TX_DW3_CH1 0x848c 1127 /* The following bit for CHV phy */ 1128 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) 1129 #define DPIO_SWING_MARGIN101_SHIFT 16 1130 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 1131 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 1132 1133 #define _VLV_TX_DW4_CH0 0x8290 1134 #define _VLV_TX_DW4_CH1 0x8490 1135 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 1136 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 1137 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 1138 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 1139 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 1140 1141 #define _VLV_TX3_DW4_CH0 0x690 1142 #define _VLV_TX3_DW4_CH1 0x2a90 1143 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 1144 1145 #define _VLV_TX_DW5_CH0 0x8294 1146 #define _VLV_TX_DW5_CH1 0x8494 1147 #define DPIO_TX_OCALINIT_EN (1<<31) 1148 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 1149 1150 #define _VLV_TX_DW11_CH0 0x82ac 1151 #define _VLV_TX_DW11_CH1 0x84ac 1152 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 1153 1154 #define _VLV_TX_DW14_CH0 0x82b8 1155 #define _VLV_TX_DW14_CH1 0x84b8 1156 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 1157 1158 /* CHV dpPhy registers */ 1159 #define _CHV_PLL_DW0_CH0 0x8000 1160 #define _CHV_PLL_DW0_CH1 0x8180 1161 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 1162 1163 #define _CHV_PLL_DW1_CH0 0x8004 1164 #define _CHV_PLL_DW1_CH1 0x8184 1165 #define DPIO_CHV_N_DIV_SHIFT 8 1166 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 1167 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 1168 1169 #define _CHV_PLL_DW2_CH0 0x8008 1170 #define _CHV_PLL_DW2_CH1 0x8188 1171 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 1172 1173 #define _CHV_PLL_DW3_CH0 0x800c 1174 #define _CHV_PLL_DW3_CH1 0x818c 1175 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 1176 #define DPIO_CHV_FIRST_MOD (0 << 8) 1177 #define DPIO_CHV_SECOND_MOD (1 << 8) 1178 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 1179 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 1180 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 1181 1182 #define _CHV_PLL_DW6_CH0 0x8018 1183 #define _CHV_PLL_DW6_CH1 0x8198 1184 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 1185 #define DPIO_CHV_INT_COEFF_SHIFT 8 1186 #define DPIO_CHV_PROP_COEFF_SHIFT 0 1187 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 1188 1189 #define _CHV_PLL_DW8_CH0 0x8020 1190 #define _CHV_PLL_DW8_CH1 0x81A0 1191 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 1192 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 1193 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 1194 1195 #define _CHV_PLL_DW9_CH0 0x8024 1196 #define _CHV_PLL_DW9_CH1 0x81A4 1197 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 1198 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 1199 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 1200 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 1201 1202 #define _CHV_CMN_DW0_CH0 0x8100 1203 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 1204 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 1205 #define DPIO_ALLDL_POWERDOWN (1 << 1) 1206 #define DPIO_ANYDL_POWERDOWN (1 << 0) 1207 1208 #define _CHV_CMN_DW5_CH0 0x8114 1209 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1210 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1211 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1212 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 1213 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1214 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1215 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 1216 #define CHV_BUFLEFTENA1_MASK (3 << 22) 1217 1218 #define _CHV_CMN_DW13_CH0 0x8134 1219 #define _CHV_CMN_DW0_CH1 0x8080 1220 #define DPIO_CHV_S1_DIV_SHIFT 21 1221 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1222 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1223 #define DPIO_CHV_K_DIV_SHIFT 4 1224 #define DPIO_PLL_FREQLOCK (1 << 1) 1225 #define DPIO_PLL_LOCK (1 << 0) 1226 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1227 1228 #define _CHV_CMN_DW14_CH0 0x8138 1229 #define _CHV_CMN_DW1_CH1 0x8084 1230 #define DPIO_AFC_RECAL (1 << 14) 1231 #define DPIO_DCLKP_EN (1 << 13) 1232 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1233 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1234 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1235 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1236 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1237 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1238 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1239 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1240 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1241 1242 #define _CHV_CMN_DW19_CH0 0x814c 1243 #define _CHV_CMN_DW6_CH1 0x8098 1244 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 1245 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 1246 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 1247 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1248 1249 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1250 1251 #define CHV_CMN_DW28 0x8170 1252 #define DPIO_CL1POWERDOWNEN (1 << 23) 1253 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 1254 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 1255 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 1256 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 1257 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 1258 1259 #define CHV_CMN_DW30 0x8178 1260 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 1261 #define DPIO_LRC_BYPASS (1 << 3) 1262 1263 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1264 (lane) * 0x200 + (offset)) 1265 1266 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1267 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1268 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1269 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1270 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1271 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1272 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1273 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1274 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1275 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1276 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1277 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1278 #define DPIO_FRC_LATENCY_SHFIT 8 1279 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1280 #define DPIO_UPAR_SHIFT 30 1281 1282 /* BXT PHY registers */ 1283 #define _BXT_PHY(phy, a, b) _MMIO_PIPE((phy), (a), (b)) 1284 1285 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 1286 #define GT_DISPLAY_POWER_ON(phy) (1 << (phy)) 1287 1288 #define _BXT_PHY_CTL_DDI_A 0x64C00 1289 #define _BXT_PHY_CTL_DDI_B 0x64C10 1290 #define _BXT_PHY_CTL_DDI_C 0x64C20 1291 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 1292 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 1293 #define BXT_PHY_LANE_ENABLED (1 << 8) 1294 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 1295 _BXT_PHY_CTL_DDI_B) 1296 1297 #define _PHY_CTL_FAMILY_EDP 0x64C80 1298 #define _PHY_CTL_FAMILY_DDI 0x64C90 1299 #define COMMON_RESET_DIS (1 << 31) 1300 #define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \ 1301 _PHY_CTL_FAMILY_EDP) 1302 1303 /* BXT PHY PLL registers */ 1304 #define _PORT_PLL_A 0x46074 1305 #define _PORT_PLL_B 0x46078 1306 #define _PORT_PLL_C 0x4607c 1307 #define PORT_PLL_ENABLE (1 << 31) 1308 #define PORT_PLL_LOCK (1 << 30) 1309 #define PORT_PLL_REF_SEL (1 << 27) 1310 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 1311 1312 #define _PORT_PLL_EBB_0_A 0x162034 1313 #define _PORT_PLL_EBB_0_B 0x6C034 1314 #define _PORT_PLL_EBB_0_C 0x6C340 1315 #define PORT_PLL_P1_SHIFT 13 1316 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) 1317 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) 1318 #define PORT_PLL_P2_SHIFT 8 1319 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) 1320 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) 1321 #define BXT_PORT_PLL_EBB_0(port) _MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \ 1322 _PORT_PLL_EBB_0_B, \ 1323 _PORT_PLL_EBB_0_C) 1324 1325 #define _PORT_PLL_EBB_4_A 0x162038 1326 #define _PORT_PLL_EBB_4_B 0x6C038 1327 #define _PORT_PLL_EBB_4_C 0x6C344 1328 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 1329 #define PORT_PLL_RECALIBRATE (1 << 14) 1330 #define BXT_PORT_PLL_EBB_4(port) _MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \ 1331 _PORT_PLL_EBB_4_B, \ 1332 _PORT_PLL_EBB_4_C) 1333 1334 #define _PORT_PLL_0_A 0x162100 1335 #define _PORT_PLL_0_B 0x6C100 1336 #define _PORT_PLL_0_C 0x6C380 1337 /* PORT_PLL_0_A */ 1338 #define PORT_PLL_M2_MASK 0xFF 1339 /* PORT_PLL_1_A */ 1340 #define PORT_PLL_N_SHIFT 8 1341 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) 1342 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) 1343 /* PORT_PLL_2_A */ 1344 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 1345 /* PORT_PLL_3_A */ 1346 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 1347 /* PORT_PLL_6_A */ 1348 #define PORT_PLL_PROP_COEFF_MASK 0xF 1349 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 1350 #define PORT_PLL_INT_COEFF(x) ((x) << 8) 1351 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 1352 #define PORT_PLL_GAIN_CTL(x) ((x) << 16) 1353 /* PORT_PLL_8_A */ 1354 #define PORT_PLL_TARGET_CNT_MASK 0x3FF 1355 /* PORT_PLL_9_A */ 1356 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 1357 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) 1358 /* PORT_PLL_10_A */ 1359 #define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) 1360 #define PORT_PLL_DCO_AMP_DEFAULT 15 1361 #define PORT_PLL_DCO_AMP_MASK 0x3c00 1362 #define PORT_PLL_DCO_AMP(x) ((x)<<10) 1363 #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ 1364 _PORT_PLL_0_B, \ 1365 _PORT_PLL_0_C) 1366 #define BXT_PORT_PLL(port, idx) _MMIO(_PORT_PLL_BASE(port) + (idx) * 4) 1367 1368 /* BXT PHY common lane registers */ 1369 #define _PORT_CL1CM_DW0_A 0x162000 1370 #define _PORT_CL1CM_DW0_BC 0x6C000 1371 #define PHY_POWER_GOOD (1 << 16) 1372 #define PHY_RESERVED (1 << 7) 1373 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ 1374 _PORT_CL1CM_DW0_A) 1375 1376 #define _PORT_CL1CM_DW9_A 0x162024 1377 #define _PORT_CL1CM_DW9_BC 0x6C024 1378 #define IREF0RC_OFFSET_SHIFT 8 1379 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 1380 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \ 1381 _PORT_CL1CM_DW9_A) 1382 1383 #define _PORT_CL1CM_DW10_A 0x162028 1384 #define _PORT_CL1CM_DW10_BC 0x6C028 1385 #define IREF1RC_OFFSET_SHIFT 8 1386 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1387 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \ 1388 _PORT_CL1CM_DW10_A) 1389 1390 #define _PORT_CL1CM_DW28_A 0x162070 1391 #define _PORT_CL1CM_DW28_BC 0x6C070 1392 #define OCL1_POWER_DOWN_EN (1 << 23) 1393 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 1394 #define SUS_CLK_CONFIG 0x3 1395 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \ 1396 _PORT_CL1CM_DW28_A) 1397 1398 #define _PORT_CL1CM_DW30_A 0x162078 1399 #define _PORT_CL1CM_DW30_BC 0x6C078 1400 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1401 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \ 1402 _PORT_CL1CM_DW30_A) 1403 1404 /* Defined for PHY0 only */ 1405 #define BXT_PORT_CL2CM_DW6_BC _MMIO(0x6C358) 1406 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 1407 1408 /* BXT PHY Ref registers */ 1409 #define _PORT_REF_DW3_A 0x16218C 1410 #define _PORT_REF_DW3_BC 0x6C18C 1411 #define GRC_DONE (1 << 22) 1412 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \ 1413 _PORT_REF_DW3_A) 1414 1415 #define _PORT_REF_DW6_A 0x162198 1416 #define _PORT_REF_DW6_BC 0x6C198 1417 #define GRC_CODE_SHIFT 24 1418 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 1419 #define GRC_CODE_FAST_SHIFT 16 1420 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 1421 #define GRC_CODE_SLOW_SHIFT 8 1422 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 1423 #define GRC_CODE_NOM_MASK 0xFF 1424 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \ 1425 _PORT_REF_DW6_A) 1426 1427 #define _PORT_REF_DW8_A 0x1621A0 1428 #define _PORT_REF_DW8_BC 0x6C1A0 1429 #define GRC_DIS (1 << 15) 1430 #define GRC_RDY_OVRD (1 << 1) 1431 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \ 1432 _PORT_REF_DW8_A) 1433 1434 /* BXT PHY PCS registers */ 1435 #define _PORT_PCS_DW10_LN01_A 0x162428 1436 #define _PORT_PCS_DW10_LN01_B 0x6C428 1437 #define _PORT_PCS_DW10_LN01_C 0x6C828 1438 #define _PORT_PCS_DW10_GRP_A 0x162C28 1439 #define _PORT_PCS_DW10_GRP_B 0x6CC28 1440 #define _PORT_PCS_DW10_GRP_C 0x6CE28 1441 #define BXT_PORT_PCS_DW10_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \ 1442 _PORT_PCS_DW10_LN01_B, \ 1443 _PORT_PCS_DW10_LN01_C) 1444 #define BXT_PORT_PCS_DW10_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A, \ 1445 _PORT_PCS_DW10_GRP_B, \ 1446 _PORT_PCS_DW10_GRP_C) 1447 #define TX2_SWING_CALC_INIT (1 << 31) 1448 #define TX1_SWING_CALC_INIT (1 << 30) 1449 1450 #define _PORT_PCS_DW12_LN01_A 0x162430 1451 #define _PORT_PCS_DW12_LN01_B 0x6C430 1452 #define _PORT_PCS_DW12_LN01_C 0x6C830 1453 #define _PORT_PCS_DW12_LN23_A 0x162630 1454 #define _PORT_PCS_DW12_LN23_B 0x6C630 1455 #define _PORT_PCS_DW12_LN23_C 0x6CA30 1456 #define _PORT_PCS_DW12_GRP_A 0x162c30 1457 #define _PORT_PCS_DW12_GRP_B 0x6CC30 1458 #define _PORT_PCS_DW12_GRP_C 0x6CE30 1459 #define LANESTAGGER_STRAP_OVRD (1 << 6) 1460 #define LANE_STAGGER_MASK 0x1F 1461 #define BXT_PORT_PCS_DW12_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \ 1462 _PORT_PCS_DW12_LN01_B, \ 1463 _PORT_PCS_DW12_LN01_C) 1464 #define BXT_PORT_PCS_DW12_LN23(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \ 1465 _PORT_PCS_DW12_LN23_B, \ 1466 _PORT_PCS_DW12_LN23_C) 1467 #define BXT_PORT_PCS_DW12_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \ 1468 _PORT_PCS_DW12_GRP_B, \ 1469 _PORT_PCS_DW12_GRP_C) 1470 1471 /* BXT PHY TX registers */ 1472 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 1473 ((lane) & 1) * 0x80) 1474 1475 #define _PORT_TX_DW2_LN0_A 0x162508 1476 #define _PORT_TX_DW2_LN0_B 0x6C508 1477 #define _PORT_TX_DW2_LN0_C 0x6C908 1478 #define _PORT_TX_DW2_GRP_A 0x162D08 1479 #define _PORT_TX_DW2_GRP_B 0x6CD08 1480 #define _PORT_TX_DW2_GRP_C 0x6CF08 1481 #define BXT_PORT_TX_DW2_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW2_GRP_A, \ 1482 _PORT_TX_DW2_GRP_B, \ 1483 _PORT_TX_DW2_GRP_C) 1484 #define BXT_PORT_TX_DW2_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW2_LN0_A, \ 1485 _PORT_TX_DW2_LN0_B, \ 1486 _PORT_TX_DW2_LN0_C) 1487 #define MARGIN_000_SHIFT 16 1488 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 1489 #define UNIQ_TRANS_SCALE_SHIFT 8 1490 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 1491 1492 #define _PORT_TX_DW3_LN0_A 0x16250C 1493 #define _PORT_TX_DW3_LN0_B 0x6C50C 1494 #define _PORT_TX_DW3_LN0_C 0x6C90C 1495 #define _PORT_TX_DW3_GRP_A 0x162D0C 1496 #define _PORT_TX_DW3_GRP_B 0x6CD0C 1497 #define _PORT_TX_DW3_GRP_C 0x6CF0C 1498 #define BXT_PORT_TX_DW3_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW3_GRP_A, \ 1499 _PORT_TX_DW3_GRP_B, \ 1500 _PORT_TX_DW3_GRP_C) 1501 #define BXT_PORT_TX_DW3_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW3_LN0_A, \ 1502 _PORT_TX_DW3_LN0_B, \ 1503 _PORT_TX_DW3_LN0_C) 1504 #define SCALE_DCOMP_METHOD (1 << 26) 1505 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 1506 1507 #define _PORT_TX_DW4_LN0_A 0x162510 1508 #define _PORT_TX_DW4_LN0_B 0x6C510 1509 #define _PORT_TX_DW4_LN0_C 0x6C910 1510 #define _PORT_TX_DW4_GRP_A 0x162D10 1511 #define _PORT_TX_DW4_GRP_B 0x6CD10 1512 #define _PORT_TX_DW4_GRP_C 0x6CF10 1513 #define BXT_PORT_TX_DW4_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW4_LN0_A, \ 1514 _PORT_TX_DW4_LN0_B, \ 1515 _PORT_TX_DW4_LN0_C) 1516 #define BXT_PORT_TX_DW4_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW4_GRP_A, \ 1517 _PORT_TX_DW4_GRP_B, \ 1518 _PORT_TX_DW4_GRP_C) 1519 #define DEEMPH_SHIFT 24 1520 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 1521 1522 #define _PORT_TX_DW14_LN0_A 0x162538 1523 #define _PORT_TX_DW14_LN0_B 0x6C538 1524 #define _PORT_TX_DW14_LN0_C 0x6C938 1525 #define LATENCY_OPTIM_SHIFT 30 1526 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 1527 #define BXT_PORT_TX_DW14_LN(port, lane) _MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A, \ 1528 _PORT_TX_DW14_LN0_B, \ 1529 _PORT_TX_DW14_LN0_C) + \ 1530 _BXT_LANE_OFFSET(lane)) 1531 1532 /* UAIMI scratch pad register 1 */ 1533 #define UAIMI_SPR1 _MMIO(0x4F074) 1534 /* SKL VccIO mask */ 1535 #define SKL_VCCIO_MASK 0x1 1536 /* SKL balance leg register */ 1537 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 1538 /* I_boost values */ 1539 #define BALANCE_LEG_SHIFT(port) (8+3*(port)) 1540 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port))) 1541 /* Balance leg disable bits */ 1542 #define BALANCE_LEG_DISABLE_SHIFT 23 1543 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 1544 1545 /* 1546 * Fence registers 1547 * [0-7] @ 0x2000 gen2,gen3 1548 * [8-15] @ 0x3000 945,g33,pnv 1549 * 1550 * [0-15] @ 0x3000 gen4,gen5 1551 * 1552 * [0-15] @ 0x100000 gen6,vlv,chv 1553 * [0-31] @ 0x100000 gen7+ 1554 */ 1555 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 1556 #define I830_FENCE_START_MASK 0x07f80000 1557 #define I830_FENCE_TILING_Y_SHIFT 12 1558 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 1559 #define I830_FENCE_PITCH_SHIFT 4 1560 #define I830_FENCE_REG_VALID (1<<0) 1561 #define I915_FENCE_MAX_PITCH_VAL 4 1562 #define I830_FENCE_MAX_PITCH_VAL 6 1563 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 1564 1565 #define I915_FENCE_START_MASK 0x0ff00000 1566 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 1567 1568 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 1569 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 1570 #define I965_FENCE_PITCH_SHIFT 2 1571 #define I965_FENCE_TILING_Y_SHIFT 1 1572 #define I965_FENCE_REG_VALID (1<<0) 1573 #define I965_FENCE_MAX_PITCH_VAL 0x0400 1574 1575 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 1576 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 1577 #define GEN6_FENCE_PITCH_SHIFT 32 1578 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 1579 1580 1581 /* control register for cpu gtt access */ 1582 #define TILECTL _MMIO(0x101000) 1583 #define TILECTL_SWZCTL (1 << 0) 1584 #define TILECTL_TLBPF (1 << 1) 1585 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 1586 #define TILECTL_BACKSNOOP_DIS (1 << 3) 1587 1588 /* 1589 * Instruction and interrupt control regs 1590 */ 1591 #define PGTBL_CTL _MMIO(0x02020) 1592 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 1593 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 1594 #define PGTBL_ER _MMIO(0x02024) 1595 #define PRB0_BASE (0x2030-0x30) 1596 #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ 1597 #define PRB2_BASE (0x2050-0x30) /* gen3 */ 1598 #define SRB0_BASE (0x2100-0x30) /* gen2 */ 1599 #define SRB1_BASE (0x2110-0x30) /* gen2 */ 1600 #define SRB2_BASE (0x2120-0x30) /* 830 */ 1601 #define SRB3_BASE (0x2130-0x30) /* 830 */ 1602 #define RENDER_RING_BASE 0x02000 1603 #define BSD_RING_BASE 0x04000 1604 #define GEN6_BSD_RING_BASE 0x12000 1605 #define GEN8_BSD2_RING_BASE 0x1c000 1606 #define VEBOX_RING_BASE 0x1a000 1607 #define BLT_RING_BASE 0x22000 1608 #define RING_TAIL(base) _MMIO((base)+0x30) 1609 #define RING_HEAD(base) _MMIO((base)+0x34) 1610 #define RING_START(base) _MMIO((base)+0x38) 1611 #define RING_CTL(base) _MMIO((base)+0x3c) 1612 #define RING_SYNC_0(base) _MMIO((base)+0x40) 1613 #define RING_SYNC_1(base) _MMIO((base)+0x44) 1614 #define RING_SYNC_2(base) _MMIO((base)+0x48) 1615 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 1616 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 1617 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 1618 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 1619 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 1620 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 1621 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 1622 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 1623 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 1624 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 1625 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 1626 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 1627 #define GEN6_NOSYNC INVALID_MMIO_REG 1628 #define RING_PSMI_CTL(base) _MMIO((base)+0x50) 1629 #define RING_MAX_IDLE(base) _MMIO((base)+0x54) 1630 #define RING_HWS_PGA(base) _MMIO((base)+0x80) 1631 #define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080) 1632 #define RING_RESET_CTL(base) _MMIO((base)+0xd0) 1633 #define RESET_CTL_REQUEST_RESET (1 << 0) 1634 #define RESET_CTL_READY_TO_RESET (1 << 1) 1635 1636 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 1637 #define GTT_CACHE_EN_ALL 0xF0007FFF 1638 #define GEN7_WR_WATERMARK _MMIO(0x4028) 1639 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 1640 #define ARB_MODE _MMIO(0x4030) 1641 #define ARB_MODE_SWIZZLE_SNB (1<<4) 1642 #define ARB_MODE_SWIZZLE_IVB (1<<5) 1643 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 1644 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 1645 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 1646 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 1647 #define GEN7_LRA_LIMITS_REG_NUM 13 1648 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 1649 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 1650 1651 #define GAMTARBMODE _MMIO(0x04a08) 1652 #define ARB_MODE_BWGTLB_DISABLE (1<<9) 1653 #define ARB_MODE_SWIZZLE_BDW (1<<1) 1654 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) 1655 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->id) 1656 #define RING_FAULT_GTTSEL_MASK (1<<11) 1657 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 1658 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 1659 #define RING_FAULT_VALID (1<<0) 1660 #define DONE_REG _MMIO(0x40b0) 1661 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 1662 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 1663 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) 1664 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) 1665 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) 1666 #define RING_ACTHD(base) _MMIO((base)+0x74) 1667 #define RING_ACTHD_UDW(base) _MMIO((base)+0x5c) 1668 #define RING_NOPID(base) _MMIO((base)+0x94) 1669 #define RING_IMR(base) _MMIO((base)+0xa8) 1670 #define RING_HWSTAM(base) _MMIO((base)+0x98) 1671 #define RING_TIMESTAMP(base) _MMIO((base)+0x358) 1672 #define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4) 1673 #define TAIL_ADDR 0x001FFFF8 1674 #define HEAD_WRAP_COUNT 0xFFE00000 1675 #define HEAD_WRAP_ONE 0x00200000 1676 #define HEAD_ADDR 0x001FFFFC 1677 #define RING_NR_PAGES 0x001FF000 1678 #define RING_REPORT_MASK 0x00000006 1679 #define RING_REPORT_64K 0x00000002 1680 #define RING_REPORT_128K 0x00000004 1681 #define RING_NO_REPORT 0x00000000 1682 #define RING_VALID_MASK 0x00000001 1683 #define RING_VALID 0x00000001 1684 #define RING_INVALID 0x00000000 1685 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 1686 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 1687 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 1688 1689 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4) 1690 #define RING_MAX_NONPRIV_SLOTS 12 1691 1692 #define GEN7_TLB_RD_ADDR _MMIO(0x4700) 1693 1694 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) 1695 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18) 1696 1697 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 1698 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28) 1699 1700 #if 0 1701 #define PRB0_TAIL _MMIO(0x2030) 1702 #define PRB0_HEAD _MMIO(0x2034) 1703 #define PRB0_START _MMIO(0x2038) 1704 #define PRB0_CTL _MMIO(0x203c) 1705 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ 1706 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ 1707 #define PRB1_START _MMIO(0x2048) /* 915+ only */ 1708 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ 1709 #endif 1710 #define IPEIR_I965 _MMIO(0x2064) 1711 #define IPEHR_I965 _MMIO(0x2068) 1712 #define GEN7_SC_INSTDONE _MMIO(0x7100) 1713 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 1714 #define GEN7_ROW_INSTDONE _MMIO(0xe164) 1715 #define I915_NUM_INSTDONE_REG 4 1716 #define RING_IPEIR(base) _MMIO((base)+0x64) 1717 #define RING_IPEHR(base) _MMIO((base)+0x68) 1718 /* 1719 * On GEN4, only the render ring INSTDONE exists and has a different 1720 * layout than the GEN7+ version. 1721 * The GEN2 counterpart of this register is GEN2_INSTDONE. 1722 */ 1723 #define RING_INSTDONE(base) _MMIO((base)+0x6c) 1724 #define RING_INSTPS(base) _MMIO((base)+0x70) 1725 #define RING_DMA_FADD(base) _MMIO((base)+0x78) 1726 #define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */ 1727 #define RING_INSTPM(base) _MMIO((base)+0xc0) 1728 #define RING_MI_MODE(base) _MMIO((base)+0x9c) 1729 #define INSTPS _MMIO(0x2070) /* 965+ only */ 1730 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 1731 #define ACTHD_I965 _MMIO(0x2074) 1732 #define HWS_PGA _MMIO(0x2080) 1733 #define HWS_ADDRESS_MASK 0xfffff000 1734 #define HWS_START_ADDRESS_SHIFT 4 1735 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 1736 #define PWRCTX_EN (1<<0) 1737 #define IPEIR _MMIO(0x2088) 1738 #define IPEHR _MMIO(0x208c) 1739 #define GEN2_INSTDONE _MMIO(0x2090) 1740 #define NOPID _MMIO(0x2094) 1741 #define HWSTAM _MMIO(0x2098) 1742 #define DMA_FADD_I8XX _MMIO(0x20d0) 1743 #define RING_BBSTATE(base) _MMIO((base)+0x110) 1744 #define RING_BB_PPGTT (1 << 5) 1745 #define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */ 1746 #define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */ 1747 #define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */ 1748 #define RING_BBADDR(base) _MMIO((base)+0x140) 1749 #define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */ 1750 #define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */ 1751 #define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */ 1752 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */ 1753 #define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */ 1754 1755 #define ERROR_GEN6 _MMIO(0x40a0) 1756 #define GEN7_ERR_INT _MMIO(0x44040) 1757 #define ERR_INT_POISON (1<<31) 1758 #define ERR_INT_MMIO_UNCLAIMED (1<<13) 1759 #define ERR_INT_PIPE_CRC_DONE_C (1<<8) 1760 #define ERR_INT_FIFO_UNDERRUN_C (1<<6) 1761 #define ERR_INT_PIPE_CRC_DONE_B (1<<5) 1762 #define ERR_INT_FIFO_UNDERRUN_B (1<<3) 1763 #define ERR_INT_PIPE_CRC_DONE_A (1<<2) 1764 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3)) 1765 #define ERR_INT_FIFO_UNDERRUN_A (1<<0) 1766 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) 1767 1768 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 1769 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 1770 1771 #define FPGA_DBG _MMIO(0x42300) 1772 #define FPGA_DBG_RM_NOCLAIM (1<<31) 1773 1774 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 1775 #define CLAIM_ER_CLR (1 << 31) 1776 #define CLAIM_ER_OVERFLOW (1 << 16) 1777 #define CLAIM_ER_CTR_MASK 0xffff 1778 1779 #define DERRMR _MMIO(0x44050) 1780 /* Note that HBLANK events are reserved on bdw+ */ 1781 #define DERRMR_PIPEA_SCANLINE (1<<0) 1782 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) 1783 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) 1784 #define DERRMR_PIPEA_VBLANK (1<<3) 1785 #define DERRMR_PIPEA_HBLANK (1<<5) 1786 #define DERRMR_PIPEB_SCANLINE (1<<8) 1787 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) 1788 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) 1789 #define DERRMR_PIPEB_VBLANK (1<<11) 1790 #define DERRMR_PIPEB_HBLANK (1<<13) 1791 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1792 #define DERRMR_PIPEC_SCANLINE (1<<14) 1793 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) 1794 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) 1795 #define DERRMR_PIPEC_VBLANK (1<<21) 1796 #define DERRMR_PIPEC_HBLANK (1<<22) 1797 1798 1799 /* GM45+ chicken bits -- debug workaround bits that may be required 1800 * for various sorts of correct behavior. The top 16 bits of each are 1801 * the enables for writing to the corresponding low bit. 1802 */ 1803 #define _3D_CHICKEN _MMIO(0x2084) 1804 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 1805 #define _3D_CHICKEN2 _MMIO(0x208c) 1806 /* Disables pipelining of read flushes past the SF-WIZ interface. 1807 * Required on all Ironlake steppings according to the B-Spec, but the 1808 * particular danger of not doing so is not specified. 1809 */ 1810 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 1811 #define _3D_CHICKEN3 _MMIO(0x2090) 1812 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 1813 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 1814 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ 1815 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 1816 1817 #define MI_MODE _MMIO(0x209c) 1818 # define VS_TIMER_DISPATCH (1 << 6) 1819 # define MI_FLUSH_ENABLE (1 << 12) 1820 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 1821 # define MODE_IDLE (1 << 9) 1822 # define STOP_RING (1 << 8) 1823 1824 #define GEN6_GT_MODE _MMIO(0x20d0) 1825 #define GEN7_GT_MODE _MMIO(0x7008) 1826 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 1827 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 1828 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 1829 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 1830 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 1831 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 1832 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 1833 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 1834 1835 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 1836 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) 1837 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 1838 1839 /* WaClearTdlStateAckDirtyBits */ 1840 #define GEN8_STATE_ACK _MMIO(0x20F0) 1841 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) 1842 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 1843 #define GEN9_STATE_ACK_TDL0 (1 << 12) 1844 #define GEN9_STATE_ACK_TDL1 (1 << 13) 1845 #define GEN9_STATE_ACK_TDL2 (1 << 14) 1846 #define GEN9_STATE_ACK_TDL3 (1 << 15) 1847 #define GEN9_SUBSLICE_TDL_ACK_BITS \ 1848 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 1849 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 1850 1851 #define GFX_MODE _MMIO(0x2520) 1852 #define GFX_MODE_GEN7 _MMIO(0x229c) 1853 #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base+0x29c) 1854 #define GFX_RUN_LIST_ENABLE (1<<15) 1855 #define GFX_INTERRUPT_STEERING (1<<14) 1856 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) 1857 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 1858 #define GFX_REPLAY_MODE (1<<11) 1859 #define GFX_PSMI_GRANULARITY (1<<10) 1860 #define GFX_PPGTT_ENABLE (1<<9) 1861 #define GEN8_GFX_PPGTT_48B (1<<7) 1862 1863 #define GFX_FORWARD_VBLANK_MASK (3<<5) 1864 #define GFX_FORWARD_VBLANK_NEVER (0<<5) 1865 #define GFX_FORWARD_VBLANK_ALWAYS (1<<5) 1866 #define GFX_FORWARD_VBLANK_COND (2<<5) 1867 1868 #define VLV_DISPLAY_BASE 0x180000 1869 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 1870 #define BXT_MIPI_BASE 0x60000 1871 1872 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 1873 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 1874 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 1875 #define IER _MMIO(0x20a0) 1876 #define IIR _MMIO(0x20a4) 1877 #define IMR _MMIO(0x20a8) 1878 #define ISR _MMIO(0x20ac) 1879 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 1880 #define GINT_DIS (1<<22) 1881 #define GCFG_DIS (1<<8) 1882 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 1883 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 1884 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 1885 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 1886 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 1887 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 1888 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 1889 #define VLV_PCBR_ADDR_SHIFT 12 1890 1891 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ 1892 #define EIR _MMIO(0x20b0) 1893 #define EMR _MMIO(0x20b4) 1894 #define ESR _MMIO(0x20b8) 1895 #define GM45_ERROR_PAGE_TABLE (1<<5) 1896 #define GM45_ERROR_MEM_PRIV (1<<4) 1897 #define I915_ERROR_PAGE_TABLE (1<<4) 1898 #define GM45_ERROR_CP_PRIV (1<<3) 1899 #define I915_ERROR_MEMORY_REFRESH (1<<1) 1900 #define I915_ERROR_INSTRUCTION (1<<0) 1901 #define INSTPM _MMIO(0x20c0) 1902 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 1903 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts 1904 will not assert AGPBUSY# and will only 1905 be delivered when out of C3. */ 1906 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 1907 #define INSTPM_TLB_INVALIDATE (1<<9) 1908 #define INSTPM_SYNC_FLUSH (1<<5) 1909 #define ACTHD _MMIO(0x20c8) 1910 #define MEM_MODE _MMIO(0x20cc) 1911 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ 1912 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ 1913 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ 1914 #define FW_BLC _MMIO(0x20d8) 1915 #define FW_BLC2 _MMIO(0x20dc) 1916 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 1917 #define FW_BLC_SELF_EN_MASK (1<<31) 1918 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 1919 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 1920 #define MM_BURST_LENGTH 0x00700000 1921 #define MM_FIFO_WATERMARK 0x0001F000 1922 #define LM_BURST_LENGTH 0x00000700 1923 #define LM_FIFO_WATERMARK 0x0000001F 1924 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 1925 1926 /* Make render/texture TLB fetches lower priorty than associated data 1927 * fetches. This is not turned on by default 1928 */ 1929 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1930 1931 /* Isoch request wait on GTT enable (Display A/B/C streams). 1932 * Make isoch requests stall on the TLB update. May cause 1933 * display underruns (test mode only) 1934 */ 1935 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1936 1937 /* Block grant count for isoch requests when block count is 1938 * set to a finite value. 1939 */ 1940 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1941 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1942 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1943 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1944 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1945 1946 /* Enable render writes to complete in C2/C3/C4 power states. 1947 * If this isn't enabled, render writes are prevented in low 1948 * power states. That seems bad to me. 1949 */ 1950 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1951 1952 /* This acknowledges an async flip immediately instead 1953 * of waiting for 2TLB fetches. 1954 */ 1955 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1956 1957 /* Enables non-sequential data reads through arbiter 1958 */ 1959 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1960 1961 /* Disable FSB snooping of cacheable write cycles from binner/render 1962 * command stream 1963 */ 1964 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1965 1966 /* Arbiter time slice for non-isoch streams */ 1967 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1968 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1969 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1970 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1971 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1972 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1973 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1974 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1975 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1976 1977 /* Low priority grace period page size */ 1978 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1979 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1980 1981 /* Disable display A/B trickle feed */ 1982 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1983 1984 /* Set display plane priority */ 1985 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1986 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1987 1988 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 1989 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1990 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1991 1992 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 1993 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 1994 #define CM0_IZ_OPT_DISABLE (1<<6) 1995 #define CM0_ZR_OPT_DISABLE (1<<5) 1996 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 1997 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 1998 #define CM0_COLOR_EVICT_DISABLE (1<<3) 1999 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 2000 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 2001 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 2002 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 2003 #define GFX_FLSH_CNTL_EN (1<<0) 2004 #define ECOSKPD _MMIO(0x21d0) 2005 #define ECO_GATING_CX_ONLY (1<<3) 2006 #define ECO_FLIP_DONE (1<<0) 2007 2008 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 2009 #define RC_OP_FLUSH_ENABLE (1<<0) 2010 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) 2011 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 2012 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 2013 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) 2014 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1) 2015 2016 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) 2017 #define GEN6_BLITTER_LOCK_SHIFT 16 2018 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 2019 2020 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) 2021 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 2022 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 2023 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) 2024 2025 /* Fuse readout registers for GT */ 2026 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) 2027 #define CHV_FGT_DISABLE_SS0 (1 << 10) 2028 #define CHV_FGT_DISABLE_SS1 (1 << 11) 2029 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 2030 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 2031 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 2032 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 2033 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 2034 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 2035 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 2036 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 2037 2038 #define GEN8_FUSE2 _MMIO(0x9120) 2039 #define GEN8_F2_SS_DIS_SHIFT 21 2040 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 2041 #define GEN8_F2_S_ENA_SHIFT 25 2042 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 2043 2044 #define GEN9_F2_SS_DIS_SHIFT 20 2045 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 2046 2047 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 2048 #define GEN8_EU_DIS0_S0_MASK 0xffffff 2049 #define GEN8_EU_DIS0_S1_SHIFT 24 2050 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 2051 2052 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 2053 #define GEN8_EU_DIS1_S1_MASK 0xffff 2054 #define GEN8_EU_DIS1_S2_SHIFT 16 2055 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 2056 2057 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 2058 #define GEN8_EU_DIS2_S2_MASK 0xff 2059 2060 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4) 2061 2062 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) 2063 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 2064 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 2065 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 2066 #define GEN6_BSD_GO_INDICATOR (1 << 4) 2067 2068 /* On modern GEN architectures interrupt control consists of two sets 2069 * of registers. The first set pertains to the ring generating the 2070 * interrupt. The second control is for the functional block generating the 2071 * interrupt. These are PM, GT, DE, etc. 2072 * 2073 * Luckily *knocks on wood* all the ring interrupt bits match up with the 2074 * GT interrupt bits, so we don't need to duplicate the defines. 2075 * 2076 * These defines should cover us well from SNB->HSW with minor exceptions 2077 * it can also work on ILK. 2078 */ 2079 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 2080 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 2081 #define GT_BLT_USER_INTERRUPT (1 << 22) 2082 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 2083 #define GT_BSD_USER_INTERRUPT (1 << 12) 2084 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 2085 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 2086 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 2087 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 2088 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 2089 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 2090 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 2091 #define GT_RENDER_USER_INTERRUPT (1 << 0) 2092 2093 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 2094 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 2095 2096 #define GT_PARITY_ERROR(dev) \ 2097 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 2098 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 2099 2100 /* These are all the "old" interrupts */ 2101 #define ILK_BSD_USER_INTERRUPT (1<<5) 2102 2103 #define I915_PM_INTERRUPT (1<<31) 2104 #define I915_ISP_INTERRUPT (1<<22) 2105 #define I915_LPE_PIPE_B_INTERRUPT (1<<21) 2106 #define I915_LPE_PIPE_A_INTERRUPT (1<<20) 2107 #define I915_MIPIC_INTERRUPT (1<<19) 2108 #define I915_MIPIA_INTERRUPT (1<<18) 2109 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 2110 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 2111 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) 2112 #define I915_MASTER_ERROR_INTERRUPT (1<<15) 2113 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 2114 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) 2115 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 2116 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) 2117 #define I915_HWB_OOM_INTERRUPT (1<<13) 2118 #define I915_LPE_PIPE_C_INTERRUPT (1<<12) 2119 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 2120 #define I915_MISC_INTERRUPT (1<<11) 2121 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 2122 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) 2123 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 2124 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) 2125 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 2126 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) 2127 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 2128 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 2129 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 2130 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 2131 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 2132 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) 2133 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) 2134 #define I915_DEBUG_INTERRUPT (1<<2) 2135 #define I915_WINVALID_INTERRUPT (1<<1) 2136 #define I915_USER_INTERRUPT (1<<1) 2137 #define I915_ASLE_INTERRUPT (1<<0) 2138 #define I915_BSD_USER_INTERRUPT (1<<25) 2139 2140 #define GEN6_BSD_RNCID _MMIO(0x12198) 2141 2142 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 2143 #define GEN7_FF_SCHED_MASK 0x0077070 2144 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 2145 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 2146 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 2147 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 2148 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 2149 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 2150 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 2151 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 2152 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 2153 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 2154 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 2155 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 2156 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 2157 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 2158 2159 /* 2160 * Framebuffer compression (915+ only) 2161 */ 2162 2163 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 2164 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 2165 #define FBC_CONTROL _MMIO(0x3208) 2166 #define FBC_CTL_EN (1<<31) 2167 #define FBC_CTL_PERIODIC (1<<30) 2168 #define FBC_CTL_INTERVAL_SHIFT (16) 2169 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 2170 #define FBC_CTL_C3_IDLE (1<<13) 2171 #define FBC_CTL_STRIDE_SHIFT (5) 2172 #define FBC_CTL_FENCENO_SHIFT (0) 2173 #define FBC_COMMAND _MMIO(0x320c) 2174 #define FBC_CMD_COMPRESS (1<<0) 2175 #define FBC_STATUS _MMIO(0x3210) 2176 #define FBC_STAT_COMPRESSING (1<<31) 2177 #define FBC_STAT_COMPRESSED (1<<30) 2178 #define FBC_STAT_MODIFIED (1<<29) 2179 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 2180 #define FBC_CONTROL2 _MMIO(0x3214) 2181 #define FBC_CTL_FENCE_DBL (0<<4) 2182 #define FBC_CTL_IDLE_IMM (0<<2) 2183 #define FBC_CTL_IDLE_FULL (1<<2) 2184 #define FBC_CTL_IDLE_LINE (2<<2) 2185 #define FBC_CTL_IDLE_DEBUG (3<<2) 2186 #define FBC_CTL_CPU_FENCE (1<<1) 2187 #define FBC_CTL_PLANE(plane) ((plane)<<0) 2188 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ 2189 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) 2190 2191 #define FBC_STATUS2 _MMIO(0x43214) 2192 #define FBC_COMPRESSION_MASK 0x7ff 2193 2194 #define FBC_LL_SIZE (1536) 2195 2196 #define FBC_LLC_READ_CTRL _MMIO(0x9044) 2197 #define FBC_LLC_FULLY_OPEN (1<<30) 2198 2199 /* Framebuffer compression for GM45+ */ 2200 #define DPFC_CB_BASE _MMIO(0x3200) 2201 #define DPFC_CONTROL _MMIO(0x3208) 2202 #define DPFC_CTL_EN (1<<31) 2203 #define DPFC_CTL_PLANE(plane) ((plane)<<30) 2204 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) 2205 #define DPFC_CTL_FENCE_EN (1<<29) 2206 #define IVB_DPFC_CTL_FENCE_EN (1<<28) 2207 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 2208 #define DPFC_SR_EN (1<<10) 2209 #define DPFC_CTL_LIMIT_1X (0<<6) 2210 #define DPFC_CTL_LIMIT_2X (1<<6) 2211 #define DPFC_CTL_LIMIT_4X (2<<6) 2212 #define DPFC_RECOMP_CTL _MMIO(0x320c) 2213 #define DPFC_RECOMP_STALL_EN (1<<27) 2214 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 2215 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 2216 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 2217 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 2218 #define DPFC_STATUS _MMIO(0x3210) 2219 #define DPFC_INVAL_SEG_SHIFT (16) 2220 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 2221 #define DPFC_COMP_SEG_SHIFT (0) 2222 #define DPFC_COMP_SEG_MASK (0x000003ff) 2223 #define DPFC_STATUS2 _MMIO(0x3214) 2224 #define DPFC_FENCE_YOFF _MMIO(0x3218) 2225 #define DPFC_CHICKEN _MMIO(0x3224) 2226 #define DPFC_HT_MODIFY (1<<31) 2227 2228 /* Framebuffer compression for Ironlake */ 2229 #define ILK_DPFC_CB_BASE _MMIO(0x43200) 2230 #define ILK_DPFC_CONTROL _MMIO(0x43208) 2231 #define FBC_CTL_FALSE_COLOR (1<<10) 2232 /* The bit 28-8 is reserved */ 2233 #define DPFC_RESERVED (0x1FFFFF00) 2234 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) 2235 #define ILK_DPFC_STATUS _MMIO(0x43210) 2236 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) 2237 #define ILK_DPFC_CHICKEN _MMIO(0x43224) 2238 #define ILK_DPFC_DISABLE_DUMMY0 (1<<8) 2239 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23) 2240 #define ILK_FBC_RT_BASE _MMIO(0x2128) 2241 #define ILK_FBC_RT_VALID (1<<0) 2242 #define SNB_FBC_FRONT_BUFFER (1<<1) 2243 2244 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 2245 #define ILK_FBCQ_DIS (1<<22) 2246 #define ILK_PABSTRETCH_DIS (1<<21) 2247 2248 2249 /* 2250 * Framebuffer compression for Sandybridge 2251 * 2252 * The following two registers are of type GTTMMADR 2253 */ 2254 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 2255 #define SNB_CPU_FENCE_ENABLE (1<<29) 2256 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 2257 2258 /* Framebuffer compression for Ivybridge */ 2259 #define IVB_FBC_RT_BASE _MMIO(0x7020) 2260 2261 #define IPS_CTL _MMIO(0x43408) 2262 #define IPS_ENABLE (1 << 31) 2263 2264 #define MSG_FBC_REND_STATE _MMIO(0x50380) 2265 #define FBC_REND_NUKE (1<<2) 2266 #define FBC_REND_CACHE_CLEAN (1<<1) 2267 2268 /* 2269 * GPIO regs 2270 */ 2271 #define GPIOA _MMIO(0x5010) 2272 #define GPIOB _MMIO(0x5014) 2273 #define GPIOC _MMIO(0x5018) 2274 #define GPIOD _MMIO(0x501c) 2275 #define GPIOE _MMIO(0x5020) 2276 #define GPIOF _MMIO(0x5024) 2277 #define GPIOG _MMIO(0x5028) 2278 #define GPIOH _MMIO(0x502c) 2279 # define GPIO_CLOCK_DIR_MASK (1 << 0) 2280 # define GPIO_CLOCK_DIR_IN (0 << 1) 2281 # define GPIO_CLOCK_DIR_OUT (1 << 1) 2282 # define GPIO_CLOCK_VAL_MASK (1 << 2) 2283 # define GPIO_CLOCK_VAL_OUT (1 << 3) 2284 # define GPIO_CLOCK_VAL_IN (1 << 4) 2285 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 2286 # define GPIO_DATA_DIR_MASK (1 << 8) 2287 # define GPIO_DATA_DIR_IN (0 << 9) 2288 # define GPIO_DATA_DIR_OUT (1 << 9) 2289 # define GPIO_DATA_VAL_MASK (1 << 10) 2290 # define GPIO_DATA_VAL_OUT (1 << 11) 2291 # define GPIO_DATA_VAL_IN (1 << 12) 2292 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 2293 2294 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 2295 #define GMBUS_RATE_100KHZ (0<<8) 2296 #define GMBUS_RATE_50KHZ (1<<8) 2297 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 2298 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 2299 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 2300 #define GMBUS_PIN_DISABLED 0 2301 #define GMBUS_PIN_SSC 1 2302 #define GMBUS_PIN_VGADDC 2 2303 #define GMBUS_PIN_PANEL 3 2304 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ 2305 #define GMBUS_PIN_DPC 4 /* HDMIC */ 2306 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ 2307 #define GMBUS_PIN_DPD 6 /* HDMID */ 2308 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ 2309 #define GMBUS_PIN_1_BXT 1 2310 #define GMBUS_PIN_2_BXT 2 2311 #define GMBUS_PIN_3_BXT 3 2312 #define GMBUS_NUM_PINS 7 /* including 0 */ 2313 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 2314 #define GMBUS_SW_CLR_INT (1<<31) 2315 #define GMBUS_SW_RDY (1<<30) 2316 #define GMBUS_ENT (1<<29) /* enable timeout */ 2317 #define GMBUS_CYCLE_NONE (0<<25) 2318 #define GMBUS_CYCLE_WAIT (1<<25) 2319 #define GMBUS_CYCLE_INDEX (2<<25) 2320 #define GMBUS_CYCLE_STOP (4<<25) 2321 #define GMBUS_BYTE_COUNT_SHIFT 16 2322 #define GMBUS_BYTE_COUNT_MAX 256U 2323 #define GMBUS_SLAVE_INDEX_SHIFT 8 2324 #define GMBUS_SLAVE_ADDR_SHIFT 1 2325 #define GMBUS_SLAVE_READ (1<<0) 2326 #define GMBUS_SLAVE_WRITE (0<<0) 2327 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 2328 #define GMBUS_INUSE (1<<15) 2329 #define GMBUS_HW_WAIT_PHASE (1<<14) 2330 #define GMBUS_STALL_TIMEOUT (1<<13) 2331 #define GMBUS_INT (1<<12) 2332 #define GMBUS_HW_RDY (1<<11) 2333 #define GMBUS_SATOER (1<<10) 2334 #define GMBUS_ACTIVE (1<<9) 2335 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 2336 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 2337 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 2338 #define GMBUS_NAK_EN (1<<3) 2339 #define GMBUS_IDLE_EN (1<<2) 2340 #define GMBUS_HW_WAIT_EN (1<<1) 2341 #define GMBUS_HW_RDY_EN (1<<0) 2342 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 2343 #define GMBUS_2BYTE_INDEX_EN (1<<31) 2344 2345 /* 2346 * Clock control & power management 2347 */ 2348 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) 2349 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) 2350 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) 2351 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 2352 2353 #define VGA0 _MMIO(0x6000) 2354 #define VGA1 _MMIO(0x6004) 2355 #define VGA_PD _MMIO(0x6010) 2356 #define VGA0_PD_P2_DIV_4 (1 << 7) 2357 #define VGA0_PD_P1_DIV_2 (1 << 5) 2358 #define VGA0_PD_P1_SHIFT 0 2359 #define VGA0_PD_P1_MASK (0x1f << 0) 2360 #define VGA1_PD_P2_DIV_4 (1 << 15) 2361 #define VGA1_PD_P1_DIV_2 (1 << 13) 2362 #define VGA1_PD_P1_SHIFT 8 2363 #define VGA1_PD_P1_MASK (0x1f << 8) 2364 #define DPLL_VCO_ENABLE (1 << 31) 2365 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 2366 #define DPLL_DVO_2X_MODE (1 << 30) 2367 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 2368 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 2369 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 2370 #define DPLL_VGA_MODE_DIS (1 << 28) 2371 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 2372 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 2373 #define DPLL_MODE_MASK (3 << 26) 2374 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 2375 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 2376 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 2377 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 2378 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 2379 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 2380 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 2381 #define DPLL_LOCK_VLV (1<<15) 2382 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) 2383 #define DPLL_INTEGRATED_REF_CLK_VLV (1<<13) 2384 #define DPLL_SSC_REF_CLK_CHV (1<<13) 2385 #define DPLL_PORTC_READY_MASK (0xf << 4) 2386 #define DPLL_PORTB_READY_MASK (0xf) 2387 2388 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 2389 2390 /* Additional CHV pll/phy registers */ 2391 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 2392 #define DPLL_PORTD_READY_MASK (0xf) 2393 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 2394 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27)) 2395 #define PHY_LDO_DELAY_0NS 0x0 2396 #define PHY_LDO_DELAY_200NS 0x1 2397 #define PHY_LDO_DELAY_600NS 0x2 2398 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23)) 2399 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11)) 2400 #define PHY_CH_SU_PSR 0x1 2401 #define PHY_CH_DEEP_PSR 0x7 2402 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) 2403 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 2404 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 2405 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) 2406 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch)))) 2407 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline)))) 2408 2409 /* 2410 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 2411 * this field (only one bit may be set). 2412 */ 2413 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 2414 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 2415 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 2416 /* i830, required in DVO non-gang */ 2417 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 2418 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 2419 #define PLL_REF_INPUT_DREFCLK (0 << 13) 2420 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 2421 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 2422 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 2423 #define PLL_REF_INPUT_MASK (3 << 13) 2424 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 2425 /* Ironlake */ 2426 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 2427 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 2428 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 2429 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 2430 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 2431 2432 /* 2433 * Parallel to Serial Load Pulse phase selection. 2434 * Selects the phase for the 10X DPLL clock for the PCIe 2435 * digital display port. The range is 4 to 13; 10 or more 2436 * is just a flip delay. The default is 6 2437 */ 2438 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 2439 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 2440 /* 2441 * SDVO multiplier for 945G/GM. Not used on 965. 2442 */ 2443 #define SDVO_MULTIPLIER_MASK 0x000000ff 2444 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 2445 #define SDVO_MULTIPLIER_SHIFT_VGA 0 2446 2447 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) 2448 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) 2449 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) 2450 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 2451 2452 /* 2453 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 2454 * 2455 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 2456 */ 2457 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 2458 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 2459 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 2460 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 2461 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 2462 /* 2463 * SDVO/UDI pixel multiplier. 2464 * 2465 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 2466 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 2467 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 2468 * dummy bytes in the datastream at an increased clock rate, with both sides of 2469 * the link knowing how many bytes are fill. 2470 * 2471 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 2472 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 2473 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 2474 * through an SDVO command. 2475 * 2476 * This register field has values of multiplication factor minus 1, with 2477 * a maximum multiplier of 5 for SDVO. 2478 */ 2479 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 2480 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 2481 /* 2482 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 2483 * This best be set to the default value (3) or the CRT won't work. No, 2484 * I don't entirely understand what this does... 2485 */ 2486 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 2487 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 2488 2489 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 2490 2491 #define _FPA0 0x6040 2492 #define _FPA1 0x6044 2493 #define _FPB0 0x6048 2494 #define _FPB1 0x604c 2495 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 2496 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 2497 #define FP_N_DIV_MASK 0x003f0000 2498 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 2499 #define FP_N_DIV_SHIFT 16 2500 #define FP_M1_DIV_MASK 0x00003f00 2501 #define FP_M1_DIV_SHIFT 8 2502 #define FP_M2_DIV_MASK 0x0000003f 2503 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 2504 #define FP_M2_DIV_SHIFT 0 2505 #define DPLL_TEST _MMIO(0x606c) 2506 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 2507 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 2508 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 2509 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 2510 #define DPLLB_TEST_N_BYPASS (1 << 19) 2511 #define DPLLB_TEST_M_BYPASS (1 << 18) 2512 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 2513 #define DPLLA_TEST_N_BYPASS (1 << 3) 2514 #define DPLLA_TEST_M_BYPASS (1 << 2) 2515 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 2516 #define D_STATE _MMIO(0x6104) 2517 #define DSTATE_GFX_RESET_I830 (1<<6) 2518 #define DSTATE_PLL_D3_OFF (1<<3) 2519 #define DSTATE_GFX_CLOCK_GATING (1<<1) 2520 #define DSTATE_DOT_CLOCK_GATING (1<<0) 2521 #define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) 2522 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 2523 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 2524 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 2525 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 2526 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 2527 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 2528 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 2529 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 2530 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 2531 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 2532 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 2533 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 2534 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 2535 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 2536 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 2537 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 2538 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 2539 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 2540 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 2541 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 2542 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 2543 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 2544 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 2545 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 2546 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 2547 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 2548 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 2549 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 2550 /* 2551 * This bit must be set on the 830 to prevent hangs when turning off the 2552 * overlay scaler. 2553 */ 2554 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 2555 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 2556 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 2557 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 2558 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 2559 2560 #define RENCLK_GATE_D1 _MMIO(0x6204) 2561 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 2562 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 2563 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 2564 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 2565 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 2566 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 2567 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 2568 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 2569 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 2570 /* This bit must be unset on 855,865 */ 2571 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 2572 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 2573 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 2574 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 2575 /* This bit must be set on 855,865. */ 2576 # define SV_CLOCK_GATE_DISABLE (1 << 0) 2577 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 2578 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 2579 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 2580 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 2581 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 2582 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 2583 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 2584 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 2585 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 2586 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 2587 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 2588 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 2589 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 2590 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 2591 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 2592 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 2593 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 2594 2595 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 2596 /* This bit must always be set on 965G/965GM */ 2597 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 2598 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 2599 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 2600 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 2601 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 2602 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 2603 /* This bit must always be set on 965G */ 2604 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 2605 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 2606 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 2607 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 2608 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 2609 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 2610 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 2611 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 2612 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 2613 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 2614 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 2615 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 2616 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 2617 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 2618 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 2619 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 2620 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 2621 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 2622 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 2623 2624 #define RENCLK_GATE_D2 _MMIO(0x6208) 2625 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 2626 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 2627 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 2628 2629 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 2630 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 2631 2632 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 2633 #define DEUC _MMIO(0x6214) /* CRL only */ 2634 2635 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 2636 #define FW_CSPWRDWNEN (1<<15) 2637 2638 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 2639 2640 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 2641 #define CDCLK_FREQ_SHIFT 4 2642 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 2643 #define CZCLK_FREQ_MASK 0xf 2644 2645 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 2646 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 2647 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 2648 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 2649 #define PFI_CREDIT_RESEND (1 << 27) 2650 #define VGA_FAST_MODE_DISABLE (1 << 14) 2651 2652 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 2653 2654 /* 2655 * Palette regs 2656 */ 2657 #define PALETTE_A_OFFSET 0xa000 2658 #define PALETTE_B_OFFSET 0xa800 2659 #define CHV_PALETTE_C_OFFSET 0xc000 2660 #define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \ 2661 dev_priv->info.display_mmio_offset + (i) * 4) 2662 2663 /* MCH MMIO space */ 2664 2665 /* 2666 * MCHBAR mirror. 2667 * 2668 * This mirrors the MCHBAR MMIO space whose location is determined by 2669 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 2670 * every way. It is not accessible from the CP register read instructions. 2671 * 2672 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 2673 * just read. 2674 */ 2675 #define MCHBAR_MIRROR_BASE 0x10000 2676 2677 #define MCHBAR_MIRROR_BASE_SNB 0x140000 2678 2679 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) 2680 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) 2681 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) 2682 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) 2683 2684 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 2685 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) 2686 2687 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 2688 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) 2689 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 2690 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 2691 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 2692 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 2693 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 2694 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 2695 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) 2696 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 2697 2698 /* Pineview MCH register contains DDR3 setting */ 2699 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) 2700 #define CSHRDDR3CTL_DDR3 (1 << 2) 2701 2702 /* 965 MCH register controlling DRAM channel configuration */ 2703 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) 2704 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) 2705 2706 /* snb MCH registers for reading the DRAM channel configuration */ 2707 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) 2708 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) 2709 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 2710 #define MAD_DIMM_ECC_MASK (0x3 << 24) 2711 #define MAD_DIMM_ECC_OFF (0x0 << 24) 2712 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 2713 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 2714 #define MAD_DIMM_ECC_ON (0x3 << 24) 2715 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 2716 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 2717 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 2718 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 2719 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 2720 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 2721 #define MAD_DIMM_A_SELECT (0x1 << 16) 2722 /* DIMM sizes are in multiples of 256mb. */ 2723 #define MAD_DIMM_B_SIZE_SHIFT 8 2724 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 2725 #define MAD_DIMM_A_SIZE_SHIFT 0 2726 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 2727 2728 /* snb MCH registers for priority tuning */ 2729 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) 2730 #define MCH_SSKPD_WM0_MASK 0x3f 2731 #define MCH_SSKPD_WM0_VAL 0xc 2732 2733 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) 2734 2735 /* Clocking configuration register */ 2736 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) 2737 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 2738 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 2739 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 2740 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 2741 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 2742 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 2743 /* Note, below two are guess */ 2744 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 2745 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 2746 #define CLKCFG_FSB_MASK (7 << 0) 2747 #define CLKCFG_MEM_533 (1 << 4) 2748 #define CLKCFG_MEM_667 (2 << 4) 2749 #define CLKCFG_MEM_800 (3 << 4) 2750 #define CLKCFG_MEM_MASK (7 << 4) 2751 2752 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) 2753 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) 2754 2755 #define TSC1 _MMIO(0x11001) 2756 #define TSE (1<<0) 2757 #define TR1 _MMIO(0x11006) 2758 #define TSFS _MMIO(0x11020) 2759 #define TSFS_SLOPE_MASK 0x0000ff00 2760 #define TSFS_SLOPE_SHIFT 8 2761 #define TSFS_INTR_MASK 0x000000ff 2762 2763 #define CRSTANDVID _MMIO(0x11100) 2764 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 2765 #define PXVFREQ_PX_MASK 0x7f000000 2766 #define PXVFREQ_PX_SHIFT 24 2767 #define VIDFREQ_BASE _MMIO(0x11110) 2768 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 2769 #define VIDFREQ2 _MMIO(0x11114) 2770 #define VIDFREQ3 _MMIO(0x11118) 2771 #define VIDFREQ4 _MMIO(0x1111c) 2772 #define VIDFREQ_P0_MASK 0x1f000000 2773 #define VIDFREQ_P0_SHIFT 24 2774 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 2775 #define VIDFREQ_P0_CSCLK_SHIFT 20 2776 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 2777 #define VIDFREQ_P0_CRCLK_SHIFT 16 2778 #define VIDFREQ_P1_MASK 0x00001f00 2779 #define VIDFREQ_P1_SHIFT 8 2780 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 2781 #define VIDFREQ_P1_CSCLK_SHIFT 4 2782 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 2783 #define INTTOEXT_BASE_ILK _MMIO(0x11300) 2784 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 2785 #define INTTOEXT_MAP3_SHIFT 24 2786 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 2787 #define INTTOEXT_MAP2_SHIFT 16 2788 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 2789 #define INTTOEXT_MAP1_SHIFT 8 2790 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 2791 #define INTTOEXT_MAP0_SHIFT 0 2792 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 2793 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 2794 #define MEMCTL_CMD_MASK 0xe000 2795 #define MEMCTL_CMD_SHIFT 13 2796 #define MEMCTL_CMD_RCLK_OFF 0 2797 #define MEMCTL_CMD_RCLK_ON 1 2798 #define MEMCTL_CMD_CHFREQ 2 2799 #define MEMCTL_CMD_CHVID 3 2800 #define MEMCTL_CMD_VMMOFF 4 2801 #define MEMCTL_CMD_VMMON 5 2802 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 2803 when command complete */ 2804 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 2805 #define MEMCTL_FREQ_SHIFT 8 2806 #define MEMCTL_SFCAVM (1<<7) 2807 #define MEMCTL_TGT_VID_MASK 0x007f 2808 #define MEMIHYST _MMIO(0x1117c) 2809 #define MEMINTREN _MMIO(0x11180) /* 16 bits */ 2810 #define MEMINT_RSEXIT_EN (1<<8) 2811 #define MEMINT_CX_SUPR_EN (1<<7) 2812 #define MEMINT_CONT_BUSY_EN (1<<6) 2813 #define MEMINT_AVG_BUSY_EN (1<<5) 2814 #define MEMINT_EVAL_CHG_EN (1<<4) 2815 #define MEMINT_MON_IDLE_EN (1<<3) 2816 #define MEMINT_UP_EVAL_EN (1<<2) 2817 #define MEMINT_DOWN_EVAL_EN (1<<1) 2818 #define MEMINT_SW_CMD_EN (1<<0) 2819 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 2820 #define MEM_RSEXIT_MASK 0xc000 2821 #define MEM_RSEXIT_SHIFT 14 2822 #define MEM_CONT_BUSY_MASK 0x3000 2823 #define MEM_CONT_BUSY_SHIFT 12 2824 #define MEM_AVG_BUSY_MASK 0x0c00 2825 #define MEM_AVG_BUSY_SHIFT 10 2826 #define MEM_EVAL_CHG_MASK 0x0300 2827 #define MEM_EVAL_BUSY_SHIFT 8 2828 #define MEM_MON_IDLE_MASK 0x00c0 2829 #define MEM_MON_IDLE_SHIFT 6 2830 #define MEM_UP_EVAL_MASK 0x0030 2831 #define MEM_UP_EVAL_SHIFT 4 2832 #define MEM_DOWN_EVAL_MASK 0x000c 2833 #define MEM_DOWN_EVAL_SHIFT 2 2834 #define MEM_SW_CMD_MASK 0x0003 2835 #define MEM_INT_STEER_GFX 0 2836 #define MEM_INT_STEER_CMR 1 2837 #define MEM_INT_STEER_SMI 2 2838 #define MEM_INT_STEER_SCI 3 2839 #define MEMINTRSTS _MMIO(0x11184) 2840 #define MEMINT_RSEXIT (1<<7) 2841 #define MEMINT_CONT_BUSY (1<<6) 2842 #define MEMINT_AVG_BUSY (1<<5) 2843 #define MEMINT_EVAL_CHG (1<<4) 2844 #define MEMINT_MON_IDLE (1<<3) 2845 #define MEMINT_UP_EVAL (1<<2) 2846 #define MEMINT_DOWN_EVAL (1<<1) 2847 #define MEMINT_SW_CMD (1<<0) 2848 #define MEMMODECTL _MMIO(0x11190) 2849 #define MEMMODE_BOOST_EN (1<<31) 2850 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 2851 #define MEMMODE_BOOST_FREQ_SHIFT 24 2852 #define MEMMODE_IDLE_MODE_MASK 0x00030000 2853 #define MEMMODE_IDLE_MODE_SHIFT 16 2854 #define MEMMODE_IDLE_MODE_EVAL 0 2855 #define MEMMODE_IDLE_MODE_CONT 1 2856 #define MEMMODE_HWIDLE_EN (1<<15) 2857 #define MEMMODE_SWMODE_EN (1<<14) 2858 #define MEMMODE_RCLK_GATE (1<<13) 2859 #define MEMMODE_HW_UPDATE (1<<12) 2860 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 2861 #define MEMMODE_FSTART_SHIFT 8 2862 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 2863 #define MEMMODE_FMAX_SHIFT 4 2864 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 2865 #define RCBMAXAVG _MMIO(0x1119c) 2866 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 2867 #define SWMEMCMD_RENDER_OFF (0 << 13) 2868 #define SWMEMCMD_RENDER_ON (1 << 13) 2869 #define SWMEMCMD_SWFREQ (2 << 13) 2870 #define SWMEMCMD_TARVID (3 << 13) 2871 #define SWMEMCMD_VRM_OFF (4 << 13) 2872 #define SWMEMCMD_VRM_ON (5 << 13) 2873 #define CMDSTS (1<<12) 2874 #define SFCAVM (1<<11) 2875 #define SWFREQ_MASK 0x0380 /* P0-7 */ 2876 #define SWFREQ_SHIFT 7 2877 #define TARVID_MASK 0x001f 2878 #define MEMSTAT_CTG _MMIO(0x111a0) 2879 #define RCBMINAVG _MMIO(0x111a0) 2880 #define RCUPEI _MMIO(0x111b0) 2881 #define RCDNEI _MMIO(0x111b4) 2882 #define RSTDBYCTL _MMIO(0x111b8) 2883 #define RS1EN (1<<31) 2884 #define RS2EN (1<<30) 2885 #define RS3EN (1<<29) 2886 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 2887 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 2888 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 2889 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 2890 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 2891 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 2892 #define RSX_STATUS_MASK (7<<20) 2893 #define RSX_STATUS_ON (0<<20) 2894 #define RSX_STATUS_RC1 (1<<20) 2895 #define RSX_STATUS_RC1E (2<<20) 2896 #define RSX_STATUS_RS1 (3<<20) 2897 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 2898 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 2899 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 2900 #define RSX_STATUS_RSVD2 (7<<20) 2901 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 2902 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 2903 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 2904 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 2905 #define RS1CONTSAV_MASK (3<<14) 2906 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 2907 #define RS1CONTSAV_RSVD (1<<14) 2908 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 2909 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 2910 #define NORMSLEXLAT_MASK (3<<12) 2911 #define SLOW_RS123 (0<<12) 2912 #define SLOW_RS23 (1<<12) 2913 #define SLOW_RS3 (2<<12) 2914 #define NORMAL_RS123 (3<<12) 2915 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 2916 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 2917 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 2918 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 2919 #define RS_CSTATE_MASK (3<<4) 2920 #define RS_CSTATE_C367_RS1 (0<<4) 2921 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 2922 #define RS_CSTATE_RSVD (2<<4) 2923 #define RS_CSTATE_C367_RS2 (3<<4) 2924 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 2925 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 2926 #define VIDCTL _MMIO(0x111c0) 2927 #define VIDSTS _MMIO(0x111c8) 2928 #define VIDSTART _MMIO(0x111cc) /* 8 bits */ 2929 #define MEMSTAT_ILK _MMIO(0x111f8) 2930 #define MEMSTAT_VID_MASK 0x7f00 2931 #define MEMSTAT_VID_SHIFT 8 2932 #define MEMSTAT_PSTATE_MASK 0x00f8 2933 #define MEMSTAT_PSTATE_SHIFT 3 2934 #define MEMSTAT_MON_ACTV (1<<2) 2935 #define MEMSTAT_SRC_CTL_MASK 0x0003 2936 #define MEMSTAT_SRC_CTL_CORE 0 2937 #define MEMSTAT_SRC_CTL_TRB 1 2938 #define MEMSTAT_SRC_CTL_THM 2 2939 #define MEMSTAT_SRC_CTL_STDBY 3 2940 #define RCPREVBSYTUPAVG _MMIO(0x113b8) 2941 #define RCPREVBSYTDNAVG _MMIO(0x113bc) 2942 #define PMMISC _MMIO(0x11214) 2943 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 2944 #define SDEW _MMIO(0x1124c) 2945 #define CSIEW0 _MMIO(0x11250) 2946 #define CSIEW1 _MMIO(0x11254) 2947 #define CSIEW2 _MMIO(0x11258) 2948 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 2949 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 2950 #define MCHAFE _MMIO(0x112c0) 2951 #define CSIEC _MMIO(0x112e0) 2952 #define DMIEC _MMIO(0x112e4) 2953 #define DDREC _MMIO(0x112e8) 2954 #define PEG0EC _MMIO(0x112ec) 2955 #define PEG1EC _MMIO(0x112f0) 2956 #define GFXEC _MMIO(0x112f4) 2957 #define RPPREVBSYTUPAVG _MMIO(0x113b8) 2958 #define RPPREVBSYTDNAVG _MMIO(0x113bc) 2959 #define ECR _MMIO(0x11600) 2960 #define ECR_GPFE (1<<31) 2961 #define ECR_IMONE (1<<30) 2962 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 2963 #define OGW0 _MMIO(0x11608) 2964 #define OGW1 _MMIO(0x1160c) 2965 #define EG0 _MMIO(0x11610) 2966 #define EG1 _MMIO(0x11614) 2967 #define EG2 _MMIO(0x11618) 2968 #define EG3 _MMIO(0x1161c) 2969 #define EG4 _MMIO(0x11620) 2970 #define EG5 _MMIO(0x11624) 2971 #define EG6 _MMIO(0x11628) 2972 #define EG7 _MMIO(0x1162c) 2973 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 2974 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 2975 #define LCFUSE02 _MMIO(0x116c0) 2976 #define LCFUSE_HIV_MASK 0x000000ff 2977 #define CSIPLL0 _MMIO(0x12c10) 2978 #define DDRMPLL1 _MMIO(0X12c20) 2979 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 2980 2981 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 2982 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 2983 2984 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) 2985 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) 2986 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) 2987 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) 2988 #define BXT_RP_STATE_CAP _MMIO(0x138170) 2989 2990 /* 2991 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS 2992 * 8300) freezing up around GPU hangs. Looks as if even 2993 * scheduling/timer interrupts start misbehaving if the RPS 2994 * EI/thresholds are "bad", leading to a very sluggish or even 2995 * frozen machine. 2996 */ 2997 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25) 2998 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) 2999 #define INTERVAL_0_833_US(us) (((us) * 6) / 5) 3000 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ 3001 (IS_BROXTON(dev_priv) ? \ 3002 INTERVAL_0_833_US(us) : \ 3003 INTERVAL_1_33_US(us)) : \ 3004 INTERVAL_1_28_US(us)) 3005 3006 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100) 3007 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) 3008 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) 3009 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \ 3010 (IS_BROXTON(dev_priv) ? \ 3011 INTERVAL_0_833_TO_US(interval) : \ 3012 INTERVAL_1_33_TO_US(interval)) : \ 3013 INTERVAL_1_28_TO_US(interval)) 3014 3015 /* 3016 * Logical Context regs 3017 */ 3018 #define CCID _MMIO(0x2180) 3019 #define CCID_EN (1<<0) 3020 /* 3021 * Notes on SNB/IVB/VLV context size: 3022 * - Power context is saved elsewhere (LLC or stolen) 3023 * - Ring/execlist context is saved on SNB, not on IVB 3024 * - Extended context size already includes render context size 3025 * - We always need to follow the extended context size. 3026 * SNB BSpec has comments indicating that we should use the 3027 * render context size instead if execlists are disabled, but 3028 * based on empirical testing that's just nonsense. 3029 * - Pipelined/VF state is saved on SNB/IVB respectively 3030 * - GT1 size just indicates how much of render context 3031 * doesn't need saving on GT1 3032 */ 3033 #define CXT_SIZE _MMIO(0x21a0) 3034 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 3035 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 3036 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 3037 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 3038 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 3039 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 3040 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 3041 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 3042 #define GEN7_CXT_SIZE _MMIO(0x21a8) 3043 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 3044 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 3045 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 3046 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 3047 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 3048 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 3049 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 3050 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 3051 /* Haswell does have the CXT_SIZE register however it does not appear to be 3052 * valid. Now, docs explain in dwords what is in the context object. The full 3053 * size is 70720 bytes, however, the power context and execlist context will 3054 * never be saved (power context is stored elsewhere, and execlists don't work 3055 * on HSW) - so the final size, including the extra state required for the 3056 * Resource Streamer, is 66944 bytes, which rounds to 17 pages. 3057 */ 3058 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 3059 /* Same as Haswell, but 72064 bytes now. */ 3060 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) 3061 3062 enum { 3063 INTEL_ADVANCED_CONTEXT = 0, 3064 INTEL_LEGACY_32B_CONTEXT, 3065 INTEL_ADVANCED_AD_CONTEXT, 3066 INTEL_LEGACY_64B_CONTEXT 3067 }; 3068 3069 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 3070 #define GEN8_CTX_ADDRESSING_MODE(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\ 3071 INTEL_LEGACY_64B_CONTEXT : \ 3072 INTEL_LEGACY_32B_CONTEXT) 3073 3074 #define CHV_CLK_CTL1 _MMIO(0x101100) 3075 #define VLV_CLK_CTL2 _MMIO(0x101104) 3076 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 3077 3078 /* 3079 * Overlay regs 3080 */ 3081 3082 #define OVADD _MMIO(0x30000) 3083 #define DOVSTA _MMIO(0x30008) 3084 #define OC_BUF (0x3<<20) 3085 #define OGAMC5 _MMIO(0x30010) 3086 #define OGAMC4 _MMIO(0x30014) 3087 #define OGAMC3 _MMIO(0x30018) 3088 #define OGAMC2 _MMIO(0x3001c) 3089 #define OGAMC1 _MMIO(0x30020) 3090 #define OGAMC0 _MMIO(0x30024) 3091 3092 /* 3093 * GEN9 clock gating regs 3094 */ 3095 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 3096 #define PWM2_GATING_DIS (1 << 14) 3097 #define PWM1_GATING_DIS (1 << 13) 3098 3099 /* 3100 * Display engine regs 3101 */ 3102 3103 /* Pipe A CRC regs */ 3104 #define _PIPE_CRC_CTL_A 0x60050 3105 #define PIPE_CRC_ENABLE (1 << 31) 3106 /* ivb+ source selection */ 3107 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 3108 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 3109 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 3110 /* ilk+ source selection */ 3111 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 3112 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 3113 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 3114 /* embedded DP port on the north display block, reserved on ivb */ 3115 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 3116 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 3117 /* vlv source selection */ 3118 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 3119 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 3120 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 3121 /* with DP port the pipe source is invalid */ 3122 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 3123 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 3124 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 3125 /* gen3+ source selection */ 3126 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 3127 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 3128 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 3129 /* with DP/TV port the pipe source is invalid */ 3130 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 3131 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 3132 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 3133 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 3134 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 3135 /* gen2 doesn't have source selection bits */ 3136 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 3137 3138 #define _PIPE_CRC_RES_1_A_IVB 0x60064 3139 #define _PIPE_CRC_RES_2_A_IVB 0x60068 3140 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 3141 #define _PIPE_CRC_RES_4_A_IVB 0x60070 3142 #define _PIPE_CRC_RES_5_A_IVB 0x60074 3143 3144 #define _PIPE_CRC_RES_RED_A 0x60060 3145 #define _PIPE_CRC_RES_GREEN_A 0x60064 3146 #define _PIPE_CRC_RES_BLUE_A 0x60068 3147 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 3148 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 3149 3150 /* Pipe B CRC regs */ 3151 #define _PIPE_CRC_RES_1_B_IVB 0x61064 3152 #define _PIPE_CRC_RES_2_B_IVB 0x61068 3153 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 3154 #define _PIPE_CRC_RES_4_B_IVB 0x61070 3155 #define _PIPE_CRC_RES_5_B_IVB 0x61074 3156 3157 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 3158 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 3159 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 3160 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 3161 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 3162 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 3163 3164 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 3165 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 3166 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 3167 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 3168 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 3169 3170 /* Pipe A timing regs */ 3171 #define _HTOTAL_A 0x60000 3172 #define _HBLANK_A 0x60004 3173 #define _HSYNC_A 0x60008 3174 #define _VTOTAL_A 0x6000c 3175 #define _VBLANK_A 0x60010 3176 #define _VSYNC_A 0x60014 3177 #define _PIPEASRC 0x6001c 3178 #define _BCLRPAT_A 0x60020 3179 #define _VSYNCSHIFT_A 0x60028 3180 #define _PIPE_MULT_A 0x6002c 3181 3182 /* Pipe B timing regs */ 3183 #define _HTOTAL_B 0x61000 3184 #define _HBLANK_B 0x61004 3185 #define _HSYNC_B 0x61008 3186 #define _VTOTAL_B 0x6100c 3187 #define _VBLANK_B 0x61010 3188 #define _VSYNC_B 0x61014 3189 #define _PIPEBSRC 0x6101c 3190 #define _BCLRPAT_B 0x61020 3191 #define _VSYNCSHIFT_B 0x61028 3192 #define _PIPE_MULT_B 0x6102c 3193 3194 #define TRANSCODER_A_OFFSET 0x60000 3195 #define TRANSCODER_B_OFFSET 0x61000 3196 #define TRANSCODER_C_OFFSET 0x62000 3197 #define CHV_TRANSCODER_C_OFFSET 0x63000 3198 #define TRANSCODER_EDP_OFFSET 0x6f000 3199 3200 #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ 3201 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ 3202 dev_priv->info.display_mmio_offset) 3203 3204 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 3205 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 3206 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 3207 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 3208 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 3209 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 3210 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 3211 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 3212 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 3213 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 3214 3215 /* VLV eDP PSR registers */ 3216 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) 3217 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) 3218 #define VLV_EDP_PSR_ENABLE (1<<0) 3219 #define VLV_EDP_PSR_RESET (1<<1) 3220 #define VLV_EDP_PSR_MODE_MASK (7<<2) 3221 #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) 3222 #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) 3223 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) 3224 #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) 3225 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) 3226 #define VLV_EDP_PSR_DBL_FRAME (1<<10) 3227 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) 3228 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 3229 #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB) 3230 3231 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) 3232 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) 3233 #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) 3234 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) 3235 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) 3236 #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB) 3237 3238 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) 3239 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) 3240 #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) 3241 #define VLV_EDP_PSR_CURR_STATE_MASK 7 3242 #define VLV_EDP_PSR_DISABLED (0<<0) 3243 #define VLV_EDP_PSR_INACTIVE (1<<0) 3244 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) 3245 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) 3246 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) 3247 #define VLV_EDP_PSR_EXIT (5<<0) 3248 #define VLV_EDP_PSR_IN_TRANS (1<<7) 3249 #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB) 3250 3251 /* HSW+ eDP PSR registers */ 3252 #define HSW_EDP_PSR_BASE 0x64800 3253 #define BDW_EDP_PSR_BASE 0x6f800 3254 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) 3255 #define EDP_PSR_ENABLE (1<<31) 3256 #define BDW_PSR_SINGLE_FRAME (1<<30) 3257 #define EDP_PSR_LINK_STANDBY (1<<27) 3258 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) 3259 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) 3260 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) 3261 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) 3262 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) 3263 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 3264 #define EDP_PSR_SKIP_AUX_EXIT (1<<12) 3265 #define EDP_PSR_TP1_TP2_SEL (0<<11) 3266 #define EDP_PSR_TP1_TP3_SEL (1<<11) 3267 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) 3268 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) 3269 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) 3270 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) 3271 #define EDP_PSR_TP1_TIME_500us (0<<4) 3272 #define EDP_PSR_TP1_TIME_100us (1<<4) 3273 #define EDP_PSR_TP1_TIME_2500us (2<<4) 3274 #define EDP_PSR_TP1_TIME_0us (3<<4) 3275 #define EDP_PSR_IDLE_FRAME_SHIFT 0 3276 3277 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) 3278 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ 3279 3280 #define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40) 3281 #define EDP_PSR_STATUS_STATE_MASK (7<<29) 3282 #define EDP_PSR_STATUS_STATE_IDLE (0<<29) 3283 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) 3284 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) 3285 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) 3286 #define EDP_PSR_STATUS_STATE_BUFON (4<<29) 3287 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) 3288 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) 3289 #define EDP_PSR_STATUS_LINK_MASK (3<<26) 3290 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) 3291 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) 3292 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) 3293 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 3294 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 3295 #define EDP_PSR_STATUS_COUNT_SHIFT 16 3296 #define EDP_PSR_STATUS_COUNT_MASK 0xf 3297 #define EDP_PSR_STATUS_AUX_ERROR (1<<15) 3298 #define EDP_PSR_STATUS_AUX_SENDING (1<<12) 3299 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) 3300 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) 3301 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) 3302 #define EDP_PSR_STATUS_IDLE_MASK 0xf 3303 3304 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) 3305 #define EDP_PSR_PERF_CNT_MASK 0xffffff 3306 3307 #define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60) 3308 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) 3309 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) 3310 #define EDP_PSR_DEBUG_MASK_HPD (1<<25) 3311 3312 #define EDP_PSR2_CTL _MMIO(0x6f900) 3313 #define EDP_PSR2_ENABLE (1<<31) 3314 #define EDP_SU_TRACK_ENABLE (1<<30) 3315 #define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) 3316 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) 3317 #define EDP_PSR2_TP2_TIME_500 (0<<8) 3318 #define EDP_PSR2_TP2_TIME_100 (1<<8) 3319 #define EDP_PSR2_TP2_TIME_2500 (2<<8) 3320 #define EDP_PSR2_TP2_TIME_50 (3<<8) 3321 #define EDP_PSR2_TP2_TIME_MASK (3<<8) 3322 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 3323 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) 3324 #define EDP_PSR2_IDLE_MASK 0xf 3325 3326 /* VGA port control */ 3327 #define ADPA _MMIO(0x61100) 3328 #define PCH_ADPA _MMIO(0xe1100) 3329 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 3330 3331 #define ADPA_DAC_ENABLE (1<<31) 3332 #define ADPA_DAC_DISABLE 0 3333 #define ADPA_PIPE_SELECT_MASK (1<<30) 3334 #define ADPA_PIPE_A_SELECT 0 3335 #define ADPA_PIPE_B_SELECT (1<<30) 3336 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 3337 /* CPT uses bits 29:30 for pch transcoder select */ 3338 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3339 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3340 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3341 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3342 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3343 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3344 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3345 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3346 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3347 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3348 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3349 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3350 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3351 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3352 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3353 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3354 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3355 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3356 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3357 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 3358 #define ADPA_SETS_HVPOLARITY 0 3359 #define ADPA_VSYNC_CNTL_DISABLE (1<<10) 3360 #define ADPA_VSYNC_CNTL_ENABLE 0 3361 #define ADPA_HSYNC_CNTL_DISABLE (1<<11) 3362 #define ADPA_HSYNC_CNTL_ENABLE 0 3363 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 3364 #define ADPA_VSYNC_ACTIVE_LOW 0 3365 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 3366 #define ADPA_HSYNC_ACTIVE_LOW 0 3367 #define ADPA_DPMS_MASK (~(3<<10)) 3368 #define ADPA_DPMS_ON (0<<10) 3369 #define ADPA_DPMS_SUSPEND (1<<10) 3370 #define ADPA_DPMS_STANDBY (2<<10) 3371 #define ADPA_DPMS_OFF (3<<10) 3372 3373 3374 /* Hotplug control (945+ only) */ 3375 #define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110) 3376 #define PORTB_HOTPLUG_INT_EN (1 << 29) 3377 #define PORTC_HOTPLUG_INT_EN (1 << 28) 3378 #define PORTD_HOTPLUG_INT_EN (1 << 27) 3379 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 3380 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 3381 #define TV_HOTPLUG_INT_EN (1 << 18) 3382 #define CRT_HOTPLUG_INT_EN (1 << 9) 3383 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 3384 PORTC_HOTPLUG_INT_EN | \ 3385 PORTD_HOTPLUG_INT_EN | \ 3386 SDVOC_HOTPLUG_INT_EN | \ 3387 SDVOB_HOTPLUG_INT_EN | \ 3388 CRT_HOTPLUG_INT_EN) 3389 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 3390 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 3391 /* must use period 64 on GM45 according to docs */ 3392 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 3393 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 3394 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 3395 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 3396 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 3397 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 3398 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 3399 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 3400 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 3401 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 3402 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 3403 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 3404 3405 #define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114) 3406 /* 3407 * HDMI/DP bits are g4x+ 3408 * 3409 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 3410 * Please check the detailed lore in the commit message for for experimental 3411 * evidence. 3412 */ 3413 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 3414 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 3415 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 3416 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 3417 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 3418 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 3419 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 3420 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 3421 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 3422 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 3423 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 3424 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 3425 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 3426 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 3427 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 3428 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 3429 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 3430 /* CRT/TV common between gen3+ */ 3431 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 3432 #define TV_HOTPLUG_INT_STATUS (1 << 10) 3433 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 3434 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 3435 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 3436 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 3437 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 3438 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 3439 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 3440 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 3441 3442 /* SDVO is different across gen3/4 */ 3443 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 3444 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 3445 /* 3446 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 3447 * since reality corrobates that they're the same as on gen3. But keep these 3448 * bits here (and the comment!) to help any other lost wanderers back onto the 3449 * right tracks. 3450 */ 3451 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 3452 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 3453 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 3454 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 3455 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 3456 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 3457 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 3458 PORTB_HOTPLUG_INT_STATUS | \ 3459 PORTC_HOTPLUG_INT_STATUS | \ 3460 PORTD_HOTPLUG_INT_STATUS) 3461 3462 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 3463 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 3464 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 3465 PORTB_HOTPLUG_INT_STATUS | \ 3466 PORTC_HOTPLUG_INT_STATUS | \ 3467 PORTD_HOTPLUG_INT_STATUS) 3468 3469 /* SDVO and HDMI port control. 3470 * The same register may be used for SDVO or HDMI */ 3471 #define _GEN3_SDVOB 0x61140 3472 #define _GEN3_SDVOC 0x61160 3473 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 3474 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 3475 #define GEN4_HDMIB GEN3_SDVOB 3476 #define GEN4_HDMIC GEN3_SDVOC 3477 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 3478 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 3479 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 3480 #define PCH_SDVOB _MMIO(0xe1140) 3481 #define PCH_HDMIB PCH_SDVOB 3482 #define PCH_HDMIC _MMIO(0xe1150) 3483 #define PCH_HDMID _MMIO(0xe1160) 3484 3485 #define PORT_DFT_I9XX _MMIO(0x61150) 3486 #define DC_BALANCE_RESET (1 << 25) 3487 #define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154) 3488 #define DC_BALANCE_RESET_VLV (1 << 31) 3489 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 3490 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ 3491 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 3492 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 3493 3494 /* Gen 3 SDVO bits: */ 3495 #define SDVO_ENABLE (1 << 31) 3496 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 3497 #define SDVO_PIPE_SEL_MASK (1 << 30) 3498 #define SDVO_PIPE_B_SELECT (1 << 30) 3499 #define SDVO_STALL_SELECT (1 << 29) 3500 #define SDVO_INTERRUPT_ENABLE (1 << 26) 3501 /* 3502 * 915G/GM SDVO pixel multiplier. 3503 * Programmed value is multiplier - 1, up to 5x. 3504 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 3505 */ 3506 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 3507 #define SDVO_PORT_MULTIPLY_SHIFT 23 3508 #define SDVO_PHASE_SELECT_MASK (15 << 19) 3509 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 3510 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 3511 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 3512 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 3513 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 3514 #define SDVO_DETECTED (1 << 2) 3515 /* Bits to be preserved when writing */ 3516 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 3517 SDVO_INTERRUPT_ENABLE) 3518 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 3519 3520 /* Gen 4 SDVO/HDMI bits: */ 3521 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 3522 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 3523 #define SDVO_ENCODING_SDVO (0 << 10) 3524 #define SDVO_ENCODING_HDMI (2 << 10) 3525 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 3526 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 3527 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 3528 #define SDVO_AUDIO_ENABLE (1 << 6) 3529 /* VSYNC/HSYNC bits new with 965, default is to be set */ 3530 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 3531 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 3532 3533 /* Gen 5 (IBX) SDVO/HDMI bits: */ 3534 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 3535 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 3536 3537 /* Gen 6 (CPT) SDVO/HDMI bits: */ 3538 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 3539 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 3540 3541 /* CHV SDVO/HDMI bits: */ 3542 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 3543 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 3544 3545 3546 /* DVO port control */ 3547 #define _DVOA 0x61120 3548 #define DVOA _MMIO(_DVOA) 3549 #define _DVOB 0x61140 3550 #define DVOB _MMIO(_DVOB) 3551 #define _DVOC 0x61160 3552 #define DVOC _MMIO(_DVOC) 3553 #define DVO_ENABLE (1 << 31) 3554 #define DVO_PIPE_B_SELECT (1 << 30) 3555 #define DVO_PIPE_STALL_UNUSED (0 << 28) 3556 #define DVO_PIPE_STALL (1 << 28) 3557 #define DVO_PIPE_STALL_TV (2 << 28) 3558 #define DVO_PIPE_STALL_MASK (3 << 28) 3559 #define DVO_USE_VGA_SYNC (1 << 15) 3560 #define DVO_DATA_ORDER_I740 (0 << 14) 3561 #define DVO_DATA_ORDER_FP (1 << 14) 3562 #define DVO_VSYNC_DISABLE (1 << 11) 3563 #define DVO_HSYNC_DISABLE (1 << 10) 3564 #define DVO_VSYNC_TRISTATE (1 << 9) 3565 #define DVO_HSYNC_TRISTATE (1 << 8) 3566 #define DVO_BORDER_ENABLE (1 << 7) 3567 #define DVO_DATA_ORDER_GBRG (1 << 6) 3568 #define DVO_DATA_ORDER_RGGB (0 << 6) 3569 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 3570 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 3571 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 3572 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 3573 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 3574 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 3575 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 3576 #define DVO_PRESERVE_MASK (0x7<<24) 3577 #define DVOA_SRCDIM _MMIO(0x61124) 3578 #define DVOB_SRCDIM _MMIO(0x61144) 3579 #define DVOC_SRCDIM _MMIO(0x61164) 3580 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 3581 #define DVO_SRCDIM_VERTICAL_SHIFT 0 3582 3583 /* LVDS port control */ 3584 #define LVDS _MMIO(0x61180) 3585 /* 3586 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 3587 * the DPLL semantics change when the LVDS is assigned to that pipe. 3588 */ 3589 #define LVDS_PORT_EN (1 << 31) 3590 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 3591 #define LVDS_PIPEB_SELECT (1 << 30) 3592 #define LVDS_PIPE_MASK (1 << 30) 3593 #define LVDS_PIPE(pipe) ((pipe) << 30) 3594 /* LVDS dithering flag on 965/g4x platform */ 3595 #define LVDS_ENABLE_DITHER (1 << 25) 3596 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 3597 #define LVDS_VSYNC_POLARITY (1 << 21) 3598 #define LVDS_HSYNC_POLARITY (1 << 20) 3599 3600 /* Enable border for unscaled (or aspect-scaled) display */ 3601 #define LVDS_BORDER_ENABLE (1 << 15) 3602 /* 3603 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 3604 * pixel. 3605 */ 3606 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 3607 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 3608 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 3609 /* 3610 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 3611 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 3612 * on. 3613 */ 3614 #define LVDS_A3_POWER_MASK (3 << 6) 3615 #define LVDS_A3_POWER_DOWN (0 << 6) 3616 #define LVDS_A3_POWER_UP (3 << 6) 3617 /* 3618 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 3619 * is set. 3620 */ 3621 #define LVDS_CLKB_POWER_MASK (3 << 4) 3622 #define LVDS_CLKB_POWER_DOWN (0 << 4) 3623 #define LVDS_CLKB_POWER_UP (3 << 4) 3624 /* 3625 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 3626 * setting for whether we are in dual-channel mode. The B3 pair will 3627 * additionally only be powered up when LVDS_A3_POWER_UP is set. 3628 */ 3629 #define LVDS_B0B3_POWER_MASK (3 << 2) 3630 #define LVDS_B0B3_POWER_DOWN (0 << 2) 3631 #define LVDS_B0B3_POWER_UP (3 << 2) 3632 3633 /* Video Data Island Packet control */ 3634 #define VIDEO_DIP_DATA _MMIO(0x61178) 3635 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 3636 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 3637 * of the infoframe structure specified by CEA-861. */ 3638 #define VIDEO_DIP_DATA_SIZE 32 3639 #define VIDEO_DIP_VSC_DATA_SIZE 36 3640 #define VIDEO_DIP_CTL _MMIO(0x61170) 3641 /* Pre HSW: */ 3642 #define VIDEO_DIP_ENABLE (1 << 31) 3643 #define VIDEO_DIP_PORT(port) ((port) << 29) 3644 #define VIDEO_DIP_PORT_MASK (3 << 29) 3645 #define VIDEO_DIP_ENABLE_GCP (1 << 25) 3646 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 3647 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 3648 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 3649 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 3650 #define VIDEO_DIP_SELECT_AVI (0 << 19) 3651 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 3652 #define VIDEO_DIP_SELECT_SPD (3 << 19) 3653 #define VIDEO_DIP_SELECT_MASK (3 << 19) 3654 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 3655 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 3656 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 3657 #define VIDEO_DIP_FREQ_MASK (3 << 16) 3658 /* HSW and later: */ 3659 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 3660 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 3661 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 3662 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 3663 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 3664 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 3665 3666 /* Panel power sequencing */ 3667 #define PP_STATUS _MMIO(0x61200) 3668 #define PP_ON (1 << 31) 3669 /* 3670 * Indicates that all dependencies of the panel are on: 3671 * 3672 * - PLL enabled 3673 * - pipe enabled 3674 * - LVDS/DVOB/DVOC on 3675 */ 3676 #define PP_READY (1 << 30) 3677 #define PP_SEQUENCE_NONE (0 << 28) 3678 #define PP_SEQUENCE_POWER_UP (1 << 28) 3679 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 3680 #define PP_SEQUENCE_MASK (3 << 28) 3681 #define PP_SEQUENCE_SHIFT 28 3682 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 3683 #define PP_SEQUENCE_STATE_MASK 0x0000000f 3684 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 3685 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 3686 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 3687 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 3688 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 3689 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 3690 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 3691 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 3692 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 3693 #define PP_CONTROL _MMIO(0x61204) 3694 #define POWER_TARGET_ON (1 << 0) 3695 #define PP_ON_DELAYS _MMIO(0x61208) 3696 #define PP_OFF_DELAYS _MMIO(0x6120c) 3697 #define PP_DIVISOR _MMIO(0x61210) 3698 3699 /* Panel fitting */ 3700 #define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230) 3701 #define PFIT_ENABLE (1 << 31) 3702 #define PFIT_PIPE_MASK (3 << 29) 3703 #define PFIT_PIPE_SHIFT 29 3704 #define VERT_INTERP_DISABLE (0 << 10) 3705 #define VERT_INTERP_BILINEAR (1 << 10) 3706 #define VERT_INTERP_MASK (3 << 10) 3707 #define VERT_AUTO_SCALE (1 << 9) 3708 #define HORIZ_INTERP_DISABLE (0 << 6) 3709 #define HORIZ_INTERP_BILINEAR (1 << 6) 3710 #define HORIZ_INTERP_MASK (3 << 6) 3711 #define HORIZ_AUTO_SCALE (1 << 5) 3712 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 3713 #define PFIT_FILTER_FUZZY (0 << 24) 3714 #define PFIT_SCALING_AUTO (0 << 26) 3715 #define PFIT_SCALING_PROGRAMMED (1 << 26) 3716 #define PFIT_SCALING_PILLAR (2 << 26) 3717 #define PFIT_SCALING_LETTER (3 << 26) 3718 #define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234) 3719 /* Pre-965 */ 3720 #define PFIT_VERT_SCALE_SHIFT 20 3721 #define PFIT_VERT_SCALE_MASK 0xfff00000 3722 #define PFIT_HORIZ_SCALE_SHIFT 4 3723 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 3724 /* 965+ */ 3725 #define PFIT_VERT_SCALE_SHIFT_965 16 3726 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 3727 #define PFIT_HORIZ_SCALE_SHIFT_965 0 3728 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 3729 3730 #define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238) 3731 3732 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) 3733 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) 3734 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 3735 _VLV_BLC_PWM_CTL2_B) 3736 3737 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) 3738 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) 3739 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 3740 _VLV_BLC_PWM_CTL_B) 3741 3742 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) 3743 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) 3744 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 3745 _VLV_BLC_HIST_CTL_B) 3746 3747 /* Backlight control */ 3748 #define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ 3749 #define BLM_PWM_ENABLE (1 << 31) 3750 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 3751 #define BLM_PIPE_SELECT (1 << 29) 3752 #define BLM_PIPE_SELECT_IVB (3 << 29) 3753 #define BLM_PIPE_A (0 << 29) 3754 #define BLM_PIPE_B (1 << 29) 3755 #define BLM_PIPE_C (2 << 29) /* ivb + */ 3756 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 3757 #define BLM_TRANSCODER_B BLM_PIPE_B 3758 #define BLM_TRANSCODER_C BLM_PIPE_C 3759 #define BLM_TRANSCODER_EDP (3 << 29) 3760 #define BLM_PIPE(pipe) ((pipe) << 29) 3761 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 3762 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 3763 #define BLM_PHASE_IN_ENABLE (1 << 25) 3764 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 3765 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 3766 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 3767 #define BLM_PHASE_IN_COUNT_SHIFT (8) 3768 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 3769 #define BLM_PHASE_IN_INCR_SHIFT (0) 3770 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 3771 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) 3772 /* 3773 * This is the most significant 15 bits of the number of backlight cycles in a 3774 * complete cycle of the modulated backlight control. 3775 * 3776 * The actual value is this field multiplied by two. 3777 */ 3778 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 3779 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 3780 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 3781 /* 3782 * This is the number of cycles out of the backlight modulation cycle for which 3783 * the backlight is on. 3784 * 3785 * This field must be no greater than the number of cycles in the complete 3786 * backlight modulation cycle. 3787 */ 3788 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 3789 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 3790 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 3791 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 3792 3793 #define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260) 3794 #define BLM_HISTOGRAM_ENABLE (1 << 31) 3795 3796 /* New registers for PCH-split platforms. Safe where new bits show up, the 3797 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 3798 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 3799 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 3800 3801 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 3802 3803 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 3804 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 3805 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 3806 #define BLM_PCH_PWM_ENABLE (1 << 31) 3807 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 3808 #define BLM_PCH_POLARITY (1 << 29) 3809 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 3810 3811 #define UTIL_PIN_CTL _MMIO(0x48400) 3812 #define UTIL_PIN_ENABLE (1 << 31) 3813 3814 #define UTIL_PIN_PIPE(x) ((x) << 29) 3815 #define UTIL_PIN_PIPE_MASK (3 << 29) 3816 #define UTIL_PIN_MODE_PWM (1 << 24) 3817 #define UTIL_PIN_MODE_MASK (0xf << 24) 3818 #define UTIL_PIN_POLARITY (1 << 22) 3819 3820 /* BXT backlight register definition. */ 3821 #define _BXT_BLC_PWM_CTL1 0xC8250 3822 #define BXT_BLC_PWM_ENABLE (1 << 31) 3823 #define BXT_BLC_PWM_POLARITY (1 << 29) 3824 #define _BXT_BLC_PWM_FREQ1 0xC8254 3825 #define _BXT_BLC_PWM_DUTY1 0xC8258 3826 3827 #define _BXT_BLC_PWM_CTL2 0xC8350 3828 #define _BXT_BLC_PWM_FREQ2 0xC8354 3829 #define _BXT_BLC_PWM_DUTY2 0xC8358 3830 3831 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 3832 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 3833 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 3834 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 3835 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 3836 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 3837 3838 #define PCH_GTC_CTL _MMIO(0xe7000) 3839 #define PCH_GTC_ENABLE (1 << 31) 3840 3841 /* TV port control */ 3842 #define TV_CTL _MMIO(0x68000) 3843 /* Enables the TV encoder */ 3844 # define TV_ENC_ENABLE (1 << 31) 3845 /* Sources the TV encoder input from pipe B instead of A. */ 3846 # define TV_ENC_PIPEB_SELECT (1 << 30) 3847 /* Outputs composite video (DAC A only) */ 3848 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 3849 /* Outputs SVideo video (DAC B/C) */ 3850 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 3851 /* Outputs Component video (DAC A/B/C) */ 3852 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 3853 /* Outputs Composite and SVideo (DAC A/B/C) */ 3854 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 3855 # define TV_TRILEVEL_SYNC (1 << 21) 3856 /* Enables slow sync generation (945GM only) */ 3857 # define TV_SLOW_SYNC (1 << 20) 3858 /* Selects 4x oversampling for 480i and 576p */ 3859 # define TV_OVERSAMPLE_4X (0 << 18) 3860 /* Selects 2x oversampling for 720p and 1080i */ 3861 # define TV_OVERSAMPLE_2X (1 << 18) 3862 /* Selects no oversampling for 1080p */ 3863 # define TV_OVERSAMPLE_NONE (2 << 18) 3864 /* Selects 8x oversampling */ 3865 # define TV_OVERSAMPLE_8X (3 << 18) 3866 /* Selects progressive mode rather than interlaced */ 3867 # define TV_PROGRESSIVE (1 << 17) 3868 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 3869 # define TV_PAL_BURST (1 << 16) 3870 /* Field for setting delay of Y compared to C */ 3871 # define TV_YC_SKEW_MASK (7 << 12) 3872 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 3873 # define TV_ENC_SDP_FIX (1 << 11) 3874 /* 3875 * Enables a fix for the 915GM only. 3876 * 3877 * Not sure what it does. 3878 */ 3879 # define TV_ENC_C0_FIX (1 << 10) 3880 /* Bits that must be preserved by software */ 3881 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 3882 # define TV_FUSE_STATE_MASK (3 << 4) 3883 /* Read-only state that reports all features enabled */ 3884 # define TV_FUSE_STATE_ENABLED (0 << 4) 3885 /* Read-only state that reports that Macrovision is disabled in hardware*/ 3886 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 3887 /* Read-only state that reports that TV-out is disabled in hardware. */ 3888 # define TV_FUSE_STATE_DISABLED (2 << 4) 3889 /* Normal operation */ 3890 # define TV_TEST_MODE_NORMAL (0 << 0) 3891 /* Encoder test pattern 1 - combo pattern */ 3892 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 3893 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 3894 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 3895 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 3896 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 3897 /* Encoder test pattern 4 - random noise */ 3898 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 3899 /* Encoder test pattern 5 - linear color ramps */ 3900 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 3901 /* 3902 * This test mode forces the DACs to 50% of full output. 3903 * 3904 * This is used for load detection in combination with TVDAC_SENSE_MASK 3905 */ 3906 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 3907 # define TV_TEST_MODE_MASK (7 << 0) 3908 3909 #define TV_DAC _MMIO(0x68004) 3910 # define TV_DAC_SAVE 0x00ffff00 3911 /* 3912 * Reports that DAC state change logic has reported change (RO). 3913 * 3914 * This gets cleared when TV_DAC_STATE_EN is cleared 3915 */ 3916 # define TVDAC_STATE_CHG (1 << 31) 3917 # define TVDAC_SENSE_MASK (7 << 28) 3918 /* Reports that DAC A voltage is above the detect threshold */ 3919 # define TVDAC_A_SENSE (1 << 30) 3920 /* Reports that DAC B voltage is above the detect threshold */ 3921 # define TVDAC_B_SENSE (1 << 29) 3922 /* Reports that DAC C voltage is above the detect threshold */ 3923 # define TVDAC_C_SENSE (1 << 28) 3924 /* 3925 * Enables DAC state detection logic, for load-based TV detection. 3926 * 3927 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 3928 * to off, for load detection to work. 3929 */ 3930 # define TVDAC_STATE_CHG_EN (1 << 27) 3931 /* Sets the DAC A sense value to high */ 3932 # define TVDAC_A_SENSE_CTL (1 << 26) 3933 /* Sets the DAC B sense value to high */ 3934 # define TVDAC_B_SENSE_CTL (1 << 25) 3935 /* Sets the DAC C sense value to high */ 3936 # define TVDAC_C_SENSE_CTL (1 << 24) 3937 /* Overrides the ENC_ENABLE and DAC voltage levels */ 3938 # define DAC_CTL_OVERRIDE (1 << 7) 3939 /* Sets the slew rate. Must be preserved in software */ 3940 # define ENC_TVDAC_SLEW_FAST (1 << 6) 3941 # define DAC_A_1_3_V (0 << 4) 3942 # define DAC_A_1_1_V (1 << 4) 3943 # define DAC_A_0_7_V (2 << 4) 3944 # define DAC_A_MASK (3 << 4) 3945 # define DAC_B_1_3_V (0 << 2) 3946 # define DAC_B_1_1_V (1 << 2) 3947 # define DAC_B_0_7_V (2 << 2) 3948 # define DAC_B_MASK (3 << 2) 3949 # define DAC_C_1_3_V (0 << 0) 3950 # define DAC_C_1_1_V (1 << 0) 3951 # define DAC_C_0_7_V (2 << 0) 3952 # define DAC_C_MASK (3 << 0) 3953 3954 /* 3955 * CSC coefficients are stored in a floating point format with 9 bits of 3956 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3957 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3958 * -1 (0x3) being the only legal negative value. 3959 */ 3960 #define TV_CSC_Y _MMIO(0x68010) 3961 # define TV_RY_MASK 0x07ff0000 3962 # define TV_RY_SHIFT 16 3963 # define TV_GY_MASK 0x00000fff 3964 # define TV_GY_SHIFT 0 3965 3966 #define TV_CSC_Y2 _MMIO(0x68014) 3967 # define TV_BY_MASK 0x07ff0000 3968 # define TV_BY_SHIFT 16 3969 /* 3970 * Y attenuation for component video. 3971 * 3972 * Stored in 1.9 fixed point. 3973 */ 3974 # define TV_AY_MASK 0x000003ff 3975 # define TV_AY_SHIFT 0 3976 3977 #define TV_CSC_U _MMIO(0x68018) 3978 # define TV_RU_MASK 0x07ff0000 3979 # define TV_RU_SHIFT 16 3980 # define TV_GU_MASK 0x000007ff 3981 # define TV_GU_SHIFT 0 3982 3983 #define TV_CSC_U2 _MMIO(0x6801c) 3984 # define TV_BU_MASK 0x07ff0000 3985 # define TV_BU_SHIFT 16 3986 /* 3987 * U attenuation for component video. 3988 * 3989 * Stored in 1.9 fixed point. 3990 */ 3991 # define TV_AU_MASK 0x000003ff 3992 # define TV_AU_SHIFT 0 3993 3994 #define TV_CSC_V _MMIO(0x68020) 3995 # define TV_RV_MASK 0x0fff0000 3996 # define TV_RV_SHIFT 16 3997 # define TV_GV_MASK 0x000007ff 3998 # define TV_GV_SHIFT 0 3999 4000 #define TV_CSC_V2 _MMIO(0x68024) 4001 # define TV_BV_MASK 0x07ff0000 4002 # define TV_BV_SHIFT 16 4003 /* 4004 * V attenuation for component video. 4005 * 4006 * Stored in 1.9 fixed point. 4007 */ 4008 # define TV_AV_MASK 0x000007ff 4009 # define TV_AV_SHIFT 0 4010 4011 #define TV_CLR_KNOBS _MMIO(0x68028) 4012 /* 2s-complement brightness adjustment */ 4013 # define TV_BRIGHTNESS_MASK 0xff000000 4014 # define TV_BRIGHTNESS_SHIFT 24 4015 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 4016 # define TV_CONTRAST_MASK 0x00ff0000 4017 # define TV_CONTRAST_SHIFT 16 4018 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 4019 # define TV_SATURATION_MASK 0x0000ff00 4020 # define TV_SATURATION_SHIFT 8 4021 /* Hue adjustment, as an integer phase angle in degrees */ 4022 # define TV_HUE_MASK 0x000000ff 4023 # define TV_HUE_SHIFT 0 4024 4025 #define TV_CLR_LEVEL _MMIO(0x6802c) 4026 /* Controls the DAC level for black */ 4027 # define TV_BLACK_LEVEL_MASK 0x01ff0000 4028 # define TV_BLACK_LEVEL_SHIFT 16 4029 /* Controls the DAC level for blanking */ 4030 # define TV_BLANK_LEVEL_MASK 0x000001ff 4031 # define TV_BLANK_LEVEL_SHIFT 0 4032 4033 #define TV_H_CTL_1 _MMIO(0x68030) 4034 /* Number of pixels in the hsync. */ 4035 # define TV_HSYNC_END_MASK 0x1fff0000 4036 # define TV_HSYNC_END_SHIFT 16 4037 /* Total number of pixels minus one in the line (display and blanking). */ 4038 # define TV_HTOTAL_MASK 0x00001fff 4039 # define TV_HTOTAL_SHIFT 0 4040 4041 #define TV_H_CTL_2 _MMIO(0x68034) 4042 /* Enables the colorburst (needed for non-component color) */ 4043 # define TV_BURST_ENA (1 << 31) 4044 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 4045 # define TV_HBURST_START_SHIFT 16 4046 # define TV_HBURST_START_MASK 0x1fff0000 4047 /* Length of the colorburst */ 4048 # define TV_HBURST_LEN_SHIFT 0 4049 # define TV_HBURST_LEN_MASK 0x0001fff 4050 4051 #define TV_H_CTL_3 _MMIO(0x68038) 4052 /* End of hblank, measured in pixels minus one from start of hsync */ 4053 # define TV_HBLANK_END_SHIFT 16 4054 # define TV_HBLANK_END_MASK 0x1fff0000 4055 /* Start of hblank, measured in pixels minus one from start of hsync */ 4056 # define TV_HBLANK_START_SHIFT 0 4057 # define TV_HBLANK_START_MASK 0x0001fff 4058 4059 #define TV_V_CTL_1 _MMIO(0x6803c) 4060 /* XXX */ 4061 # define TV_NBR_END_SHIFT 16 4062 # define TV_NBR_END_MASK 0x07ff0000 4063 /* XXX */ 4064 # define TV_VI_END_F1_SHIFT 8 4065 # define TV_VI_END_F1_MASK 0x00003f00 4066 /* XXX */ 4067 # define TV_VI_END_F2_SHIFT 0 4068 # define TV_VI_END_F2_MASK 0x0000003f 4069 4070 #define TV_V_CTL_2 _MMIO(0x68040) 4071 /* Length of vsync, in half lines */ 4072 # define TV_VSYNC_LEN_MASK 0x07ff0000 4073 # define TV_VSYNC_LEN_SHIFT 16 4074 /* Offset of the start of vsync in field 1, measured in one less than the 4075 * number of half lines. 4076 */ 4077 # define TV_VSYNC_START_F1_MASK 0x00007f00 4078 # define TV_VSYNC_START_F1_SHIFT 8 4079 /* 4080 * Offset of the start of vsync in field 2, measured in one less than the 4081 * number of half lines. 4082 */ 4083 # define TV_VSYNC_START_F2_MASK 0x0000007f 4084 # define TV_VSYNC_START_F2_SHIFT 0 4085 4086 #define TV_V_CTL_3 _MMIO(0x68044) 4087 /* Enables generation of the equalization signal */ 4088 # define TV_EQUAL_ENA (1 << 31) 4089 /* Length of vsync, in half lines */ 4090 # define TV_VEQ_LEN_MASK 0x007f0000 4091 # define TV_VEQ_LEN_SHIFT 16 4092 /* Offset of the start of equalization in field 1, measured in one less than 4093 * the number of half lines. 4094 */ 4095 # define TV_VEQ_START_F1_MASK 0x0007f00 4096 # define TV_VEQ_START_F1_SHIFT 8 4097 /* 4098 * Offset of the start of equalization in field 2, measured in one less than 4099 * the number of half lines. 4100 */ 4101 # define TV_VEQ_START_F2_MASK 0x000007f 4102 # define TV_VEQ_START_F2_SHIFT 0 4103 4104 #define TV_V_CTL_4 _MMIO(0x68048) 4105 /* 4106 * Offset to start of vertical colorburst, measured in one less than the 4107 * number of lines from vertical start. 4108 */ 4109 # define TV_VBURST_START_F1_MASK 0x003f0000 4110 # define TV_VBURST_START_F1_SHIFT 16 4111 /* 4112 * Offset to the end of vertical colorburst, measured in one less than the 4113 * number of lines from the start of NBR. 4114 */ 4115 # define TV_VBURST_END_F1_MASK 0x000000ff 4116 # define TV_VBURST_END_F1_SHIFT 0 4117 4118 #define TV_V_CTL_5 _MMIO(0x6804c) 4119 /* 4120 * Offset to start of vertical colorburst, measured in one less than the 4121 * number of lines from vertical start. 4122 */ 4123 # define TV_VBURST_START_F2_MASK 0x003f0000 4124 # define TV_VBURST_START_F2_SHIFT 16 4125 /* 4126 * Offset to the end of vertical colorburst, measured in one less than the 4127 * number of lines from the start of NBR. 4128 */ 4129 # define TV_VBURST_END_F2_MASK 0x000000ff 4130 # define TV_VBURST_END_F2_SHIFT 0 4131 4132 #define TV_V_CTL_6 _MMIO(0x68050) 4133 /* 4134 * Offset to start of vertical colorburst, measured in one less than the 4135 * number of lines from vertical start. 4136 */ 4137 # define TV_VBURST_START_F3_MASK 0x003f0000 4138 # define TV_VBURST_START_F3_SHIFT 16 4139 /* 4140 * Offset to the end of vertical colorburst, measured in one less than the 4141 * number of lines from the start of NBR. 4142 */ 4143 # define TV_VBURST_END_F3_MASK 0x000000ff 4144 # define TV_VBURST_END_F3_SHIFT 0 4145 4146 #define TV_V_CTL_7 _MMIO(0x68054) 4147 /* 4148 * Offset to start of vertical colorburst, measured in one less than the 4149 * number of lines from vertical start. 4150 */ 4151 # define TV_VBURST_START_F4_MASK 0x003f0000 4152 # define TV_VBURST_START_F4_SHIFT 16 4153 /* 4154 * Offset to the end of vertical colorburst, measured in one less than the 4155 * number of lines from the start of NBR. 4156 */ 4157 # define TV_VBURST_END_F4_MASK 0x000000ff 4158 # define TV_VBURST_END_F4_SHIFT 0 4159 4160 #define TV_SC_CTL_1 _MMIO(0x68060) 4161 /* Turns on the first subcarrier phase generation DDA */ 4162 # define TV_SC_DDA1_EN (1 << 31) 4163 /* Turns on the first subcarrier phase generation DDA */ 4164 # define TV_SC_DDA2_EN (1 << 30) 4165 /* Turns on the first subcarrier phase generation DDA */ 4166 # define TV_SC_DDA3_EN (1 << 29) 4167 /* Sets the subcarrier DDA to reset frequency every other field */ 4168 # define TV_SC_RESET_EVERY_2 (0 << 24) 4169 /* Sets the subcarrier DDA to reset frequency every fourth field */ 4170 # define TV_SC_RESET_EVERY_4 (1 << 24) 4171 /* Sets the subcarrier DDA to reset frequency every eighth field */ 4172 # define TV_SC_RESET_EVERY_8 (2 << 24) 4173 /* Sets the subcarrier DDA to never reset the frequency */ 4174 # define TV_SC_RESET_NEVER (3 << 24) 4175 /* Sets the peak amplitude of the colorburst.*/ 4176 # define TV_BURST_LEVEL_MASK 0x00ff0000 4177 # define TV_BURST_LEVEL_SHIFT 16 4178 /* Sets the increment of the first subcarrier phase generation DDA */ 4179 # define TV_SCDDA1_INC_MASK 0x00000fff 4180 # define TV_SCDDA1_INC_SHIFT 0 4181 4182 #define TV_SC_CTL_2 _MMIO(0x68064) 4183 /* Sets the rollover for the second subcarrier phase generation DDA */ 4184 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 4185 # define TV_SCDDA2_SIZE_SHIFT 16 4186 /* Sets the increent of the second subcarrier phase generation DDA */ 4187 # define TV_SCDDA2_INC_MASK 0x00007fff 4188 # define TV_SCDDA2_INC_SHIFT 0 4189 4190 #define TV_SC_CTL_3 _MMIO(0x68068) 4191 /* Sets the rollover for the third subcarrier phase generation DDA */ 4192 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 4193 # define TV_SCDDA3_SIZE_SHIFT 16 4194 /* Sets the increent of the third subcarrier phase generation DDA */ 4195 # define TV_SCDDA3_INC_MASK 0x00007fff 4196 # define TV_SCDDA3_INC_SHIFT 0 4197 4198 #define TV_WIN_POS _MMIO(0x68070) 4199 /* X coordinate of the display from the start of horizontal active */ 4200 # define TV_XPOS_MASK 0x1fff0000 4201 # define TV_XPOS_SHIFT 16 4202 /* Y coordinate of the display from the start of vertical active (NBR) */ 4203 # define TV_YPOS_MASK 0x00000fff 4204 # define TV_YPOS_SHIFT 0 4205 4206 #define TV_WIN_SIZE _MMIO(0x68074) 4207 /* Horizontal size of the display window, measured in pixels*/ 4208 # define TV_XSIZE_MASK 0x1fff0000 4209 # define TV_XSIZE_SHIFT 16 4210 /* 4211 * Vertical size of the display window, measured in pixels. 4212 * 4213 * Must be even for interlaced modes. 4214 */ 4215 # define TV_YSIZE_MASK 0x00000fff 4216 # define TV_YSIZE_SHIFT 0 4217 4218 #define TV_FILTER_CTL_1 _MMIO(0x68080) 4219 /* 4220 * Enables automatic scaling calculation. 4221 * 4222 * If set, the rest of the registers are ignored, and the calculated values can 4223 * be read back from the register. 4224 */ 4225 # define TV_AUTO_SCALE (1 << 31) 4226 /* 4227 * Disables the vertical filter. 4228 * 4229 * This is required on modes more than 1024 pixels wide */ 4230 # define TV_V_FILTER_BYPASS (1 << 29) 4231 /* Enables adaptive vertical filtering */ 4232 # define TV_VADAPT (1 << 28) 4233 # define TV_VADAPT_MODE_MASK (3 << 26) 4234 /* Selects the least adaptive vertical filtering mode */ 4235 # define TV_VADAPT_MODE_LEAST (0 << 26) 4236 /* Selects the moderately adaptive vertical filtering mode */ 4237 # define TV_VADAPT_MODE_MODERATE (1 << 26) 4238 /* Selects the most adaptive vertical filtering mode */ 4239 # define TV_VADAPT_MODE_MOST (3 << 26) 4240 /* 4241 * Sets the horizontal scaling factor. 4242 * 4243 * This should be the fractional part of the horizontal scaling factor divided 4244 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 4245 * 4246 * (src width - 1) / ((oversample * dest width) - 1) 4247 */ 4248 # define TV_HSCALE_FRAC_MASK 0x00003fff 4249 # define TV_HSCALE_FRAC_SHIFT 0 4250 4251 #define TV_FILTER_CTL_2 _MMIO(0x68084) 4252 /* 4253 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 4254 * 4255 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 4256 */ 4257 # define TV_VSCALE_INT_MASK 0x00038000 4258 # define TV_VSCALE_INT_SHIFT 15 4259 /* 4260 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 4261 * 4262 * \sa TV_VSCALE_INT_MASK 4263 */ 4264 # define TV_VSCALE_FRAC_MASK 0x00007fff 4265 # define TV_VSCALE_FRAC_SHIFT 0 4266 4267 #define TV_FILTER_CTL_3 _MMIO(0x68088) 4268 /* 4269 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 4270 * 4271 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 4272 * 4273 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 4274 */ 4275 # define TV_VSCALE_IP_INT_MASK 0x00038000 4276 # define TV_VSCALE_IP_INT_SHIFT 15 4277 /* 4278 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 4279 * 4280 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 4281 * 4282 * \sa TV_VSCALE_IP_INT_MASK 4283 */ 4284 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 4285 # define TV_VSCALE_IP_FRAC_SHIFT 0 4286 4287 #define TV_CC_CONTROL _MMIO(0x68090) 4288 # define TV_CC_ENABLE (1 << 31) 4289 /* 4290 * Specifies which field to send the CC data in. 4291 * 4292 * CC data is usually sent in field 0. 4293 */ 4294 # define TV_CC_FID_MASK (1 << 27) 4295 # define TV_CC_FID_SHIFT 27 4296 /* Sets the horizontal position of the CC data. Usually 135. */ 4297 # define TV_CC_HOFF_MASK 0x03ff0000 4298 # define TV_CC_HOFF_SHIFT 16 4299 /* Sets the vertical position of the CC data. Usually 21 */ 4300 # define TV_CC_LINE_MASK 0x0000003f 4301 # define TV_CC_LINE_SHIFT 0 4302 4303 #define TV_CC_DATA _MMIO(0x68094) 4304 # define TV_CC_RDY (1 << 31) 4305 /* Second word of CC data to be transmitted. */ 4306 # define TV_CC_DATA_2_MASK 0x007f0000 4307 # define TV_CC_DATA_2_SHIFT 16 4308 /* First word of CC data to be transmitted. */ 4309 # define TV_CC_DATA_1_MASK 0x0000007f 4310 # define TV_CC_DATA_1_SHIFT 0 4311 4312 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 4313 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 4314 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 4315 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 4316 4317 /* Display Port */ 4318 #define DP_A _MMIO(0x64000) /* eDP */ 4319 #define DP_B _MMIO(0x64100) 4320 #define DP_C _MMIO(0x64200) 4321 #define DP_D _MMIO(0x64300) 4322 4323 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 4324 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 4325 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 4326 4327 #define DP_PORT_EN (1 << 31) 4328 #define DP_PIPEB_SELECT (1 << 30) 4329 #define DP_PIPE_MASK (1 << 30) 4330 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) 4331 #define DP_PIPE_MASK_CHV (3 << 16) 4332 4333 /* Link training mode - select a suitable mode for each stage */ 4334 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 4335 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 4336 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 4337 #define DP_LINK_TRAIN_OFF (3 << 28) 4338 #define DP_LINK_TRAIN_MASK (3 << 28) 4339 #define DP_LINK_TRAIN_SHIFT 28 4340 #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) 4341 #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) 4342 4343 /* CPT Link training mode */ 4344 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 4345 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 4346 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 4347 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 4348 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 4349 #define DP_LINK_TRAIN_SHIFT_CPT 8 4350 4351 /* Signal voltages. These are mostly controlled by the other end */ 4352 #define DP_VOLTAGE_0_4 (0 << 25) 4353 #define DP_VOLTAGE_0_6 (1 << 25) 4354 #define DP_VOLTAGE_0_8 (2 << 25) 4355 #define DP_VOLTAGE_1_2 (3 << 25) 4356 #define DP_VOLTAGE_MASK (7 << 25) 4357 #define DP_VOLTAGE_SHIFT 25 4358 4359 /* Signal pre-emphasis levels, like voltages, the other end tells us what 4360 * they want 4361 */ 4362 #define DP_PRE_EMPHASIS_0 (0 << 22) 4363 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 4364 #define DP_PRE_EMPHASIS_6 (2 << 22) 4365 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 4366 #define DP_PRE_EMPHASIS_MASK (7 << 22) 4367 #define DP_PRE_EMPHASIS_SHIFT 22 4368 4369 /* How many wires to use. I guess 3 was too hard */ 4370 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 4371 #define DP_PORT_WIDTH_MASK (7 << 19) 4372 #define DP_PORT_WIDTH_SHIFT 19 4373 4374 /* Mystic DPCD version 1.1 special mode */ 4375 #define DP_ENHANCED_FRAMING (1 << 18) 4376 4377 /* eDP */ 4378 #define DP_PLL_FREQ_270MHZ (0 << 16) 4379 #define DP_PLL_FREQ_162MHZ (1 << 16) 4380 #define DP_PLL_FREQ_MASK (3 << 16) 4381 4382 /* locked once port is enabled */ 4383 #define DP_PORT_REVERSAL (1 << 15) 4384 4385 /* eDP */ 4386 #define DP_PLL_ENABLE (1 << 14) 4387 4388 /* sends the clock on lane 15 of the PEG for debug */ 4389 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 4390 4391 #define DP_SCRAMBLING_DISABLE (1 << 12) 4392 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 4393 4394 /* limit RGB values to avoid confusing TVs */ 4395 #define DP_COLOR_RANGE_16_235 (1 << 8) 4396 4397 /* Turn on the audio link */ 4398 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 4399 4400 /* vs and hs sync polarity */ 4401 #define DP_SYNC_VS_HIGH (1 << 4) 4402 #define DP_SYNC_HS_HIGH (1 << 3) 4403 4404 /* A fantasy */ 4405 #define DP_DETECTED (1 << 2) 4406 4407 /* The aux channel provides a way to talk to the 4408 * signal sink for DDC etc. Max packet size supported 4409 * is 20 bytes in each direction, hence the 5 fixed 4410 * data registers 4411 */ 4412 #define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010) 4413 #define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) 4414 #define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) 4415 #define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) 4416 #define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) 4417 #define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) 4418 4419 #define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110) 4420 #define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) 4421 #define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) 4422 #define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) 4423 #define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) 4424 #define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) 4425 4426 #define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210) 4427 #define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) 4428 #define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) 4429 #define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) 4430 #define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) 4431 #define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) 4432 4433 #define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310) 4434 #define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) 4435 #define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) 4436 #define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) 4437 #define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) 4438 #define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) 4439 4440 #define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 4441 #define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 4442 4443 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 4444 #define DP_AUX_CH_CTL_DONE (1 << 30) 4445 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 4446 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 4447 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 4448 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 4449 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 4450 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 4451 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 4452 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 4453 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 4454 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 4455 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 4456 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 4457 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 4458 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 4459 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 4460 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 4461 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 4462 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 4463 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 4464 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 4465 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 4466 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 4467 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 4468 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 4469 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 4470 4471 /* 4472 * Computing GMCH M and N values for the Display Port link 4473 * 4474 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 4475 * 4476 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 4477 * 4478 * The GMCH value is used internally 4479 * 4480 * bytes_per_pixel is the number of bytes coming out of the plane, 4481 * which is after the LUTs, so we want the bytes for our color format. 4482 * For our current usage, this is always 3, one byte for R, G and B. 4483 */ 4484 #define _PIPEA_DATA_M_G4X 0x70050 4485 #define _PIPEB_DATA_M_G4X 0x71050 4486 4487 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 4488 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 4489 #define TU_SIZE_SHIFT 25 4490 #define TU_SIZE_MASK (0x3f << 25) 4491 4492 #define DATA_LINK_M_N_MASK (0xffffff) 4493 #define DATA_LINK_N_MAX (0x800000) 4494 4495 #define _PIPEA_DATA_N_G4X 0x70054 4496 #define _PIPEB_DATA_N_G4X 0x71054 4497 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 4498 4499 /* 4500 * Computing Link M and N values for the Display Port link 4501 * 4502 * Link M / N = pixel_clock / ls_clk 4503 * 4504 * (the DP spec calls pixel_clock the 'strm_clk') 4505 * 4506 * The Link value is transmitted in the Main Stream 4507 * Attributes and VB-ID. 4508 */ 4509 4510 #define _PIPEA_LINK_M_G4X 0x70060 4511 #define _PIPEB_LINK_M_G4X 0x71060 4512 #define PIPEA_DP_LINK_M_MASK (0xffffff) 4513 4514 #define _PIPEA_LINK_N_G4X 0x70064 4515 #define _PIPEB_LINK_N_G4X 0x71064 4516 #define PIPEA_DP_LINK_N_MASK (0xffffff) 4517 4518 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 4519 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 4520 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 4521 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 4522 4523 /* Display & cursor control */ 4524 4525 /* Pipe A */ 4526 #define _PIPEADSL 0x70000 4527 #define DSL_LINEMASK_GEN2 0x00000fff 4528 #define DSL_LINEMASK_GEN3 0x00001fff 4529 #define _PIPEACONF 0x70008 4530 #define PIPECONF_ENABLE (1<<31) 4531 #define PIPECONF_DISABLE 0 4532 #define PIPECONF_DOUBLE_WIDE (1<<30) 4533 #define I965_PIPECONF_ACTIVE (1<<30) 4534 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ 4535 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 4536 #define PIPECONF_SINGLE_WIDE 0 4537 #define PIPECONF_PIPE_UNLOCKED 0 4538 #define PIPECONF_PIPE_LOCKED (1<<25) 4539 #define PIPECONF_PALETTE 0 4540 #define PIPECONF_GAMMA (1<<24) 4541 #define PIPECONF_FORCE_BORDER (1<<25) 4542 #define PIPECONF_INTERLACE_MASK (7 << 21) 4543 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 4544 /* Note that pre-gen3 does not support interlaced display directly. Panel 4545 * fitting must be disabled on pre-ilk for interlaced. */ 4546 #define PIPECONF_PROGRESSIVE (0 << 21) 4547 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 4548 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 4549 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 4550 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 4551 /* Ironlake and later have a complete new set of values for interlaced. PFIT 4552 * means panel fitter required, PF means progressive fetch, DBL means power 4553 * saving pixel doubling. */ 4554 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 4555 #define PIPECONF_INTERLACED_ILK (3 << 21) 4556 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 4557 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 4558 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 4559 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 4560 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 4561 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) 4562 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 4563 #define PIPECONF_BPC_MASK (0x7 << 5) 4564 #define PIPECONF_8BPC (0<<5) 4565 #define PIPECONF_10BPC (1<<5) 4566 #define PIPECONF_6BPC (2<<5) 4567 #define PIPECONF_12BPC (3<<5) 4568 #define PIPECONF_DITHER_EN (1<<4) 4569 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 4570 #define PIPECONF_DITHER_TYPE_SP (0<<2) 4571 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 4572 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 4573 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 4574 #define _PIPEASTAT 0x70024 4575 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 4576 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) 4577 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 4578 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 4579 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) 4580 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 4581 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 4582 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 4583 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 4584 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 4585 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 4586 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) 4587 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 4588 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 4589 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 4590 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) 4591 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) 4592 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 4593 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 4594 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) 4595 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 4596 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 4597 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 4598 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) 4599 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) 4600 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 4601 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 4602 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) 4603 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 4604 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) 4605 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 4606 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 4607 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 4608 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 4609 #define PIPE_A_PSR_STATUS_VLV (1UL<<6) 4610 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 4611 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 4612 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 4613 #define PIPE_B_PSR_STATUS_VLV (1UL<<3) 4614 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) 4615 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 4616 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 4617 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) 4618 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 4619 #define PIPE_HBLANK_INT_STATUS (1UL<<0) 4620 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 4621 4622 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 4623 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 4624 4625 #define PIPE_A_OFFSET 0x70000 4626 #define PIPE_B_OFFSET 0x71000 4627 #define PIPE_C_OFFSET 0x72000 4628 #define CHV_PIPE_C_OFFSET 0x74000 4629 /* 4630 * There's actually no pipe EDP. Some pipe registers have 4631 * simply shifted from the pipe to the transcoder, while 4632 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 4633 * to access such registers in transcoder EDP. 4634 */ 4635 #define PIPE_EDP_OFFSET 0x7f000 4636 4637 #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ 4638 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ 4639 dev_priv->info.display_mmio_offset) 4640 4641 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 4642 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 4643 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 4644 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 4645 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 4646 4647 #define _PIPE_MISC_A 0x70030 4648 #define _PIPE_MISC_B 0x71030 4649 #define PIPEMISC_DITHER_BPC_MASK (7<<5) 4650 #define PIPEMISC_DITHER_8_BPC (0<<5) 4651 #define PIPEMISC_DITHER_10_BPC (1<<5) 4652 #define PIPEMISC_DITHER_6_BPC (2<<5) 4653 #define PIPEMISC_DITHER_12_BPC (3<<5) 4654 #define PIPEMISC_DITHER_ENABLE (1<<4) 4655 #define PIPEMISC_DITHER_TYPE_MASK (3<<2) 4656 #define PIPEMISC_DITHER_TYPE_SP (0<<2) 4657 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 4658 4659 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 4660 #define PIPEB_LINE_COMPARE_INT_EN (1<<29) 4661 #define PIPEB_HLINE_INT_EN (1<<28) 4662 #define PIPEB_VBLANK_INT_EN (1<<27) 4663 #define SPRITED_FLIP_DONE_INT_EN (1<<26) 4664 #define SPRITEC_FLIP_DONE_INT_EN (1<<25) 4665 #define PLANEB_FLIP_DONE_INT_EN (1<<24) 4666 #define PIPE_PSR_INT_EN (1<<22) 4667 #define PIPEA_LINE_COMPARE_INT_EN (1<<21) 4668 #define PIPEA_HLINE_INT_EN (1<<20) 4669 #define PIPEA_VBLANK_INT_EN (1<<19) 4670 #define SPRITEB_FLIP_DONE_INT_EN (1<<18) 4671 #define SPRITEA_FLIP_DONE_INT_EN (1<<17) 4672 #define PLANEA_FLIPDONE_INT_EN (1<<16) 4673 #define PIPEC_LINE_COMPARE_INT_EN (1<<13) 4674 #define PIPEC_HLINE_INT_EN (1<<12) 4675 #define PIPEC_VBLANK_INT_EN (1<<11) 4676 #define SPRITEF_FLIPDONE_INT_EN (1<<10) 4677 #define SPRITEE_FLIPDONE_INT_EN (1<<9) 4678 #define PLANEC_FLIPDONE_INT_EN (1<<8) 4679 4680 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 4681 #define SPRITEF_INVALID_GTT_INT_EN (1<<27) 4682 #define SPRITEE_INVALID_GTT_INT_EN (1<<26) 4683 #define PLANEC_INVALID_GTT_INT_EN (1<<25) 4684 #define CURSORC_INVALID_GTT_INT_EN (1<<24) 4685 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 4686 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 4687 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 4688 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 4689 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 4690 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 4691 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 4692 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 4693 #define DPINVGTT_EN_MASK 0xff0000 4694 #define DPINVGTT_EN_MASK_CHV 0xfff0000 4695 #define SPRITEF_INVALID_GTT_STATUS (1<<11) 4696 #define SPRITEE_INVALID_GTT_STATUS (1<<10) 4697 #define PLANEC_INVALID_GTT_STATUS (1<<9) 4698 #define CURSORC_INVALID_GTT_STATUS (1<<8) 4699 #define CURSORB_INVALID_GTT_STATUS (1<<7) 4700 #define CURSORA_INVALID_GTT_STATUS (1<<6) 4701 #define SPRITED_INVALID_GTT_STATUS (1<<5) 4702 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 4703 #define PLANEB_INVALID_GTT_STATUS (1<<3) 4704 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 4705 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 4706 #define PLANEA_INVALID_GTT_STATUS (1<<0) 4707 #define DPINVGTT_STATUS_MASK 0xff 4708 #define DPINVGTT_STATUS_MASK_CHV 0xfff 4709 4710 #define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030) 4711 #define DSPARB_CSTART_MASK (0x7f << 7) 4712 #define DSPARB_CSTART_SHIFT 7 4713 #define DSPARB_BSTART_MASK (0x7f) 4714 #define DSPARB_BSTART_SHIFT 0 4715 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 4716 #define DSPARB_AEND_SHIFT 0 4717 #define DSPARB_SPRITEA_SHIFT_VLV 0 4718 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 4719 #define DSPARB_SPRITEB_SHIFT_VLV 8 4720 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 4721 #define DSPARB_SPRITEC_SHIFT_VLV 16 4722 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 4723 #define DSPARB_SPRITED_SHIFT_VLV 24 4724 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 4725 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 4726 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 4727 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 4728 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 4729 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 4730 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 4731 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 4732 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 4733 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 4734 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 4735 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 4736 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 4737 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 4738 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 4739 #define DSPARB_SPRITEE_SHIFT_VLV 0 4740 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 4741 #define DSPARB_SPRITEF_SHIFT_VLV 8 4742 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 4743 4744 /* pnv/gen4/g4x/vlv/chv */ 4745 #define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034) 4746 #define DSPFW_SR_SHIFT 23 4747 #define DSPFW_SR_MASK (0x1ff<<23) 4748 #define DSPFW_CURSORB_SHIFT 16 4749 #define DSPFW_CURSORB_MASK (0x3f<<16) 4750 #define DSPFW_PLANEB_SHIFT 8 4751 #define DSPFW_PLANEB_MASK (0x7f<<8) 4752 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ 4753 #define DSPFW_PLANEA_SHIFT 0 4754 #define DSPFW_PLANEA_MASK (0x7f<<0) 4755 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ 4756 #define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038) 4757 #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ 4758 #define DSPFW_FBC_SR_SHIFT 28 4759 #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ 4760 #define DSPFW_FBC_HPLL_SR_SHIFT 24 4761 #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ 4762 #define DSPFW_SPRITEB_SHIFT (16) 4763 #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ 4764 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ 4765 #define DSPFW_CURSORA_SHIFT 8 4766 #define DSPFW_CURSORA_MASK (0x3f<<8) 4767 #define DSPFW_PLANEC_OLD_SHIFT 0 4768 #define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */ 4769 #define DSPFW_SPRITEA_SHIFT 0 4770 #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ 4771 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ 4772 #define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c) 4773 #define DSPFW_HPLL_SR_EN (1<<31) 4774 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 4775 #define DSPFW_CURSOR_SR_SHIFT 24 4776 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 4777 #define DSPFW_HPLL_CURSOR_SHIFT 16 4778 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 4779 #define DSPFW_HPLL_SR_SHIFT 0 4780 #define DSPFW_HPLL_SR_MASK (0x1ff<<0) 4781 4782 /* vlv/chv */ 4783 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 4784 #define DSPFW_SPRITEB_WM1_SHIFT 16 4785 #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) 4786 #define DSPFW_CURSORA_WM1_SHIFT 8 4787 #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) 4788 #define DSPFW_SPRITEA_WM1_SHIFT 0 4789 #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) 4790 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 4791 #define DSPFW_PLANEB_WM1_SHIFT 24 4792 #define DSPFW_PLANEB_WM1_MASK (0xff<<24) 4793 #define DSPFW_PLANEA_WM1_SHIFT 16 4794 #define DSPFW_PLANEA_WM1_MASK (0xff<<16) 4795 #define DSPFW_CURSORB_WM1_SHIFT 8 4796 #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) 4797 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 4798 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) 4799 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 4800 #define DSPFW_SR_WM1_SHIFT 0 4801 #define DSPFW_SR_WM1_MASK (0x1ff<<0) 4802 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 4803 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 4804 #define DSPFW_SPRITED_WM1_SHIFT 24 4805 #define DSPFW_SPRITED_WM1_MASK (0xff<<24) 4806 #define DSPFW_SPRITED_SHIFT 16 4807 #define DSPFW_SPRITED_MASK_VLV (0xff<<16) 4808 #define DSPFW_SPRITEC_WM1_SHIFT 8 4809 #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) 4810 #define DSPFW_SPRITEC_SHIFT 0 4811 #define DSPFW_SPRITEC_MASK_VLV (0xff<<0) 4812 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 4813 #define DSPFW_SPRITEF_WM1_SHIFT 24 4814 #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) 4815 #define DSPFW_SPRITEF_SHIFT 16 4816 #define DSPFW_SPRITEF_MASK_VLV (0xff<<16) 4817 #define DSPFW_SPRITEE_WM1_SHIFT 8 4818 #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) 4819 #define DSPFW_SPRITEE_SHIFT 0 4820 #define DSPFW_SPRITEE_MASK_VLV (0xff<<0) 4821 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 4822 #define DSPFW_PLANEC_WM1_SHIFT 24 4823 #define DSPFW_PLANEC_WM1_MASK (0xff<<24) 4824 #define DSPFW_PLANEC_SHIFT 16 4825 #define DSPFW_PLANEC_MASK_VLV (0xff<<16) 4826 #define DSPFW_CURSORC_WM1_SHIFT 8 4827 #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) 4828 #define DSPFW_CURSORC_SHIFT 0 4829 #define DSPFW_CURSORC_MASK (0x3f<<0) 4830 4831 /* vlv/chv high order bits */ 4832 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 4833 #define DSPFW_SR_HI_SHIFT 24 4834 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 4835 #define DSPFW_SPRITEF_HI_SHIFT 23 4836 #define DSPFW_SPRITEF_HI_MASK (1<<23) 4837 #define DSPFW_SPRITEE_HI_SHIFT 22 4838 #define DSPFW_SPRITEE_HI_MASK (1<<22) 4839 #define DSPFW_PLANEC_HI_SHIFT 21 4840 #define DSPFW_PLANEC_HI_MASK (1<<21) 4841 #define DSPFW_SPRITED_HI_SHIFT 20 4842 #define DSPFW_SPRITED_HI_MASK (1<<20) 4843 #define DSPFW_SPRITEC_HI_SHIFT 16 4844 #define DSPFW_SPRITEC_HI_MASK (1<<16) 4845 #define DSPFW_PLANEB_HI_SHIFT 12 4846 #define DSPFW_PLANEB_HI_MASK (1<<12) 4847 #define DSPFW_SPRITEB_HI_SHIFT 8 4848 #define DSPFW_SPRITEB_HI_MASK (1<<8) 4849 #define DSPFW_SPRITEA_HI_SHIFT 4 4850 #define DSPFW_SPRITEA_HI_MASK (1<<4) 4851 #define DSPFW_PLANEA_HI_SHIFT 0 4852 #define DSPFW_PLANEA_HI_MASK (1<<0) 4853 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 4854 #define DSPFW_SR_WM1_HI_SHIFT 24 4855 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */ 4856 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 4857 #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) 4858 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 4859 #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) 4860 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 4861 #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) 4862 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 4863 #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) 4864 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 4865 #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) 4866 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 4867 #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) 4868 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 4869 #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) 4870 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 4871 #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) 4872 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 4873 #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) 4874 4875 /* drain latency register values*/ 4876 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 4877 #define DDL_CURSOR_SHIFT 24 4878 #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) 4879 #define DDL_PLANE_SHIFT 0 4880 #define DDL_PRECISION_HIGH (1<<7) 4881 #define DDL_PRECISION_LOW (0<<7) 4882 #define DRAIN_LATENCY_MASK 0x7f 4883 4884 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 4885 #define CBR_PND_DEADLINE_DISABLE (1<<31) 4886 #define CBR_PWM_CLOCK_MUX_SELECT (1<<30) 4887 4888 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 4889 #define CBR_DPLLBMD_PIPE_C (1<<29) 4890 #define CBR_DPLLBMD_PIPE_B (1<<18) 4891 4892 /* FIFO watermark sizes etc */ 4893 #define G4X_FIFO_LINE_SIZE 64 4894 #define I915_FIFO_LINE_SIZE 64 4895 #define I830_FIFO_LINE_SIZE 32 4896 4897 #define VALLEYVIEW_FIFO_SIZE 255 4898 #define G4X_FIFO_SIZE 127 4899 #define I965_FIFO_SIZE 512 4900 #define I945_FIFO_SIZE 127 4901 #define I915_FIFO_SIZE 95 4902 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 4903 #define I830_FIFO_SIZE 95 4904 4905 #define VALLEYVIEW_MAX_WM 0xff 4906 #define G4X_MAX_WM 0x3f 4907 #define I915_MAX_WM 0x3f 4908 4909 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4910 #define PINEVIEW_FIFO_LINE_SIZE 64 4911 #define PINEVIEW_MAX_WM 0x1ff 4912 #define PINEVIEW_DFT_WM 0x3f 4913 #define PINEVIEW_DFT_HPLLOFF_WM 0 4914 #define PINEVIEW_GUARD_WM 10 4915 #define PINEVIEW_CURSOR_FIFO 64 4916 #define PINEVIEW_CURSOR_MAX_WM 0x3f 4917 #define PINEVIEW_CURSOR_DFT_WM 0 4918 #define PINEVIEW_CURSOR_GUARD_WM 5 4919 4920 #define VALLEYVIEW_CURSOR_MAX_WM 64 4921 #define I965_CURSOR_FIFO 64 4922 #define I965_CURSOR_MAX_WM 32 4923 #define I965_CURSOR_DFT_WM 8 4924 4925 /* Watermark register definitions for SKL */ 4926 #define _CUR_WM_A_0 0x70140 4927 #define _CUR_WM_B_0 0x71140 4928 #define _PLANE_WM_1_A_0 0x70240 4929 #define _PLANE_WM_1_B_0 0x71240 4930 #define _PLANE_WM_2_A_0 0x70340 4931 #define _PLANE_WM_2_B_0 0x71340 4932 #define _PLANE_WM_TRANS_1_A_0 0x70268 4933 #define _PLANE_WM_TRANS_1_B_0 0x71268 4934 #define _PLANE_WM_TRANS_2_A_0 0x70368 4935 #define _PLANE_WM_TRANS_2_B_0 0x71368 4936 #define _CUR_WM_TRANS_A_0 0x70168 4937 #define _CUR_WM_TRANS_B_0 0x71168 4938 #define PLANE_WM_EN (1 << 31) 4939 #define PLANE_WM_LINES_SHIFT 14 4940 #define PLANE_WM_LINES_MASK 0x1f 4941 #define PLANE_WM_BLOCKS_MASK 0x3ff 4942 4943 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 4944 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 4945 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) 4946 4947 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 4948 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 4949 #define _PLANE_WM_BASE(pipe, plane) \ 4950 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 4951 #define PLANE_WM(pipe, plane, level) \ 4952 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 4953 #define _PLANE_WM_TRANS_1(pipe) \ 4954 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) 4955 #define _PLANE_WM_TRANS_2(pipe) \ 4956 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) 4957 #define PLANE_WM_TRANS(pipe, plane) \ 4958 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 4959 4960 /* define the Watermark register on Ironlake */ 4961 #define WM0_PIPEA_ILK _MMIO(0x45100) 4962 #define WM0_PIPE_PLANE_MASK (0xffff<<16) 4963 #define WM0_PIPE_PLANE_SHIFT 16 4964 #define WM0_PIPE_SPRITE_MASK (0xff<<8) 4965 #define WM0_PIPE_SPRITE_SHIFT 8 4966 #define WM0_PIPE_CURSOR_MASK (0xff) 4967 4968 #define WM0_PIPEB_ILK _MMIO(0x45104) 4969 #define WM0_PIPEC_IVB _MMIO(0x45200) 4970 #define WM1_LP_ILK _MMIO(0x45108) 4971 #define WM1_LP_SR_EN (1<<31) 4972 #define WM1_LP_LATENCY_SHIFT 24 4973 #define WM1_LP_LATENCY_MASK (0x7f<<24) 4974 #define WM1_LP_FBC_MASK (0xf<<20) 4975 #define WM1_LP_FBC_SHIFT 20 4976 #define WM1_LP_FBC_SHIFT_BDW 19 4977 #define WM1_LP_SR_MASK (0x7ff<<8) 4978 #define WM1_LP_SR_SHIFT 8 4979 #define WM1_LP_CURSOR_MASK (0xff) 4980 #define WM2_LP_ILK _MMIO(0x4510c) 4981 #define WM2_LP_EN (1<<31) 4982 #define WM3_LP_ILK _MMIO(0x45110) 4983 #define WM3_LP_EN (1<<31) 4984 #define WM1S_LP_ILK _MMIO(0x45120) 4985 #define WM2S_LP_IVB _MMIO(0x45124) 4986 #define WM3S_LP_IVB _MMIO(0x45128) 4987 #define WM1S_LP_EN (1<<31) 4988 4989 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 4990 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 4991 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 4992 4993 /* Memory latency timer register */ 4994 #define MLTR_ILK _MMIO(0x11222) 4995 #define MLTR_WM1_SHIFT 0 4996 #define MLTR_WM2_SHIFT 8 4997 /* the unit of memory self-refresh latency time is 0.5us */ 4998 #define ILK_SRLT_MASK 0x3f 4999 5000 5001 /* the address where we get all kinds of latency value */ 5002 #define SSKPD _MMIO(0x5d10) 5003 #define SSKPD_WM_MASK 0x3f 5004 #define SSKPD_WM0_SHIFT 0 5005 #define SSKPD_WM1_SHIFT 8 5006 #define SSKPD_WM2_SHIFT 16 5007 #define SSKPD_WM3_SHIFT 24 5008 5009 /* 5010 * The two pipe frame counter registers are not synchronized, so 5011 * reading a stable value is somewhat tricky. The following code 5012 * should work: 5013 * 5014 * do { 5015 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 5016 * PIPE_FRAME_HIGH_SHIFT; 5017 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 5018 * PIPE_FRAME_LOW_SHIFT); 5019 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 5020 * PIPE_FRAME_HIGH_SHIFT); 5021 * } while (high1 != high2); 5022 * frame = (high1 << 8) | low1; 5023 */ 5024 #define _PIPEAFRAMEHIGH 0x70040 5025 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 5026 #define PIPE_FRAME_HIGH_SHIFT 0 5027 #define _PIPEAFRAMEPIXEL 0x70044 5028 #define PIPE_FRAME_LOW_MASK 0xff000000 5029 #define PIPE_FRAME_LOW_SHIFT 24 5030 #define PIPE_PIXEL_MASK 0x00ffffff 5031 #define PIPE_PIXEL_SHIFT 0 5032 /* GM45+ just has to be different */ 5033 #define _PIPEA_FRMCOUNT_G4X 0x70040 5034 #define _PIPEA_FLIPCOUNT_G4X 0x70044 5035 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 5036 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 5037 5038 /* Cursor A & B regs */ 5039 #define _CURACNTR 0x70080 5040 /* Old style CUR*CNTR flags (desktop 8xx) */ 5041 #define CURSOR_ENABLE 0x80000000 5042 #define CURSOR_GAMMA_ENABLE 0x40000000 5043 #define CURSOR_STRIDE_SHIFT 28 5044 #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 5045 #define CURSOR_PIPE_CSC_ENABLE (1<<24) 5046 #define CURSOR_FORMAT_SHIFT 24 5047 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 5048 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 5049 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 5050 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 5051 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 5052 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 5053 /* New style CUR*CNTR flags */ 5054 #define CURSOR_MODE 0x27 5055 #define CURSOR_MODE_DISABLE 0x00 5056 #define CURSOR_MODE_128_32B_AX 0x02 5057 #define CURSOR_MODE_256_32B_AX 0x03 5058 #define CURSOR_MODE_64_32B_AX 0x07 5059 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) 5060 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) 5061 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 5062 #define MCURSOR_PIPE_SELECT (1 << 28) 5063 #define MCURSOR_PIPE_A 0x00 5064 #define MCURSOR_PIPE_B (1 << 28) 5065 #define MCURSOR_GAMMA_ENABLE (1 << 26) 5066 #define CURSOR_ROTATE_180 (1<<15) 5067 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 5068 #define _CURABASE 0x70084 5069 #define _CURAPOS 0x70088 5070 #define CURSOR_POS_MASK 0x007FF 5071 #define CURSOR_POS_SIGN 0x8000 5072 #define CURSOR_X_SHIFT 0 5073 #define CURSOR_Y_SHIFT 16 5074 #define CURSIZE _MMIO(0x700a0) 5075 #define _CURBCNTR 0x700c0 5076 #define _CURBBASE 0x700c4 5077 #define _CURBPOS 0x700c8 5078 5079 #define _CURBCNTR_IVB 0x71080 5080 #define _CURBBASE_IVB 0x71084 5081 #define _CURBPOS_IVB 0x71088 5082 5083 #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ 5084 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ 5085 dev_priv->info.display_mmio_offset) 5086 5087 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 5088 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 5089 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 5090 5091 #define CURSOR_A_OFFSET 0x70080 5092 #define CURSOR_B_OFFSET 0x700c0 5093 #define CHV_CURSOR_C_OFFSET 0x700e0 5094 #define IVB_CURSOR_B_OFFSET 0x71080 5095 #define IVB_CURSOR_C_OFFSET 0x72080 5096 5097 /* Display A control */ 5098 #define _DSPACNTR 0x70180 5099 #define DISPLAY_PLANE_ENABLE (1<<31) 5100 #define DISPLAY_PLANE_DISABLE 0 5101 #define DISPPLANE_GAMMA_ENABLE (1<<30) 5102 #define DISPPLANE_GAMMA_DISABLE 0 5103 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 5104 #define DISPPLANE_YUV422 (0x0<<26) 5105 #define DISPPLANE_8BPP (0x2<<26) 5106 #define DISPPLANE_BGRA555 (0x3<<26) 5107 #define DISPPLANE_BGRX555 (0x4<<26) 5108 #define DISPPLANE_BGRX565 (0x5<<26) 5109 #define DISPPLANE_BGRX888 (0x6<<26) 5110 #define DISPPLANE_BGRA888 (0x7<<26) 5111 #define DISPPLANE_RGBX101010 (0x8<<26) 5112 #define DISPPLANE_RGBA101010 (0x9<<26) 5113 #define DISPPLANE_BGRX101010 (0xa<<26) 5114 #define DISPPLANE_RGBX161616 (0xc<<26) 5115 #define DISPPLANE_RGBX888 (0xe<<26) 5116 #define DISPPLANE_RGBA888 (0xf<<26) 5117 #define DISPPLANE_STEREO_ENABLE (1<<25) 5118 #define DISPPLANE_STEREO_DISABLE 0 5119 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) 5120 #define DISPPLANE_SEL_PIPE_SHIFT 24 5121 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 5122 #define DISPPLANE_SEL_PIPE_A 0 5123 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 5124 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 5125 #define DISPPLANE_SRC_KEY_DISABLE 0 5126 #define DISPPLANE_LINE_DOUBLE (1<<20) 5127 #define DISPPLANE_NO_LINE_DOUBLE 0 5128 #define DISPPLANE_STEREO_POLARITY_FIRST 0 5129 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 5130 #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ 5131 #define DISPPLANE_ROTATE_180 (1<<15) 5132 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 5133 #define DISPPLANE_TILED (1<<10) 5134 #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ 5135 #define _DSPAADDR 0x70184 5136 #define _DSPASTRIDE 0x70188 5137 #define _DSPAPOS 0x7018C /* reserved */ 5138 #define _DSPASIZE 0x70190 5139 #define _DSPASURF 0x7019C /* 965+ only */ 5140 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 5141 #define _DSPAOFFSET 0x701A4 /* HSW */ 5142 #define _DSPASURFLIVE 0x701AC 5143 5144 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 5145 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 5146 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 5147 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 5148 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 5149 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 5150 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 5151 #define DSPLINOFF(plane) DSPADDR(plane) 5152 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 5153 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 5154 5155 /* CHV pipe B blender and primary plane */ 5156 #define _CHV_BLEND_A 0x60a00 5157 #define CHV_BLEND_LEGACY (0<<30) 5158 #define CHV_BLEND_ANDROID (1<<30) 5159 #define CHV_BLEND_MPO (2<<30) 5160 #define CHV_BLEND_MASK (3<<30) 5161 #define _CHV_CANVAS_A 0x60a04 5162 #define _PRIMPOS_A 0x60a08 5163 #define _PRIMSIZE_A 0x60a0c 5164 #define _PRIMCNSTALPHA_A 0x60a10 5165 #define PRIM_CONST_ALPHA_ENABLE (1<<31) 5166 5167 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 5168 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 5169 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 5170 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 5171 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 5172 5173 /* Display/Sprite base address macros */ 5174 #define DISP_BASEADDR_MASK (0xfffff000) 5175 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 5176 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 5177 5178 /* 5179 * VBIOS flags 5180 * gen2: 5181 * [00:06] alm,mgm 5182 * [10:16] all 5183 * [30:32] alm,mgm 5184 * gen3+: 5185 * [00:0f] all 5186 * [10:1f] all 5187 * [30:32] all 5188 */ 5189 #define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) 5190 #define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) 5191 #define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) 5192 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 5193 5194 /* Pipe B */ 5195 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) 5196 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) 5197 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) 5198 #define _PIPEBFRAMEHIGH 0x71040 5199 #define _PIPEBFRAMEPIXEL 0x71044 5200 #define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) 5201 #define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044) 5202 5203 5204 /* Display B control */ 5205 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) 5206 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 5207 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 5208 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 5209 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 5210 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) 5211 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) 5212 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) 5213 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) 5214 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) 5215 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) 5216 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) 5217 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) 5218 5219 /* Sprite A control */ 5220 #define _DVSACNTR 0x72180 5221 #define DVS_ENABLE (1<<31) 5222 #define DVS_GAMMA_ENABLE (1<<30) 5223 #define DVS_PIXFORMAT_MASK (3<<25) 5224 #define DVS_FORMAT_YUV422 (0<<25) 5225 #define DVS_FORMAT_RGBX101010 (1<<25) 5226 #define DVS_FORMAT_RGBX888 (2<<25) 5227 #define DVS_FORMAT_RGBX161616 (3<<25) 5228 #define DVS_PIPE_CSC_ENABLE (1<<24) 5229 #define DVS_SOURCE_KEY (1<<22) 5230 #define DVS_RGB_ORDER_XBGR (1<<20) 5231 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 5232 #define DVS_YUV_ORDER_YUYV (0<<16) 5233 #define DVS_YUV_ORDER_UYVY (1<<16) 5234 #define DVS_YUV_ORDER_YVYU (2<<16) 5235 #define DVS_YUV_ORDER_VYUY (3<<16) 5236 #define DVS_ROTATE_180 (1<<15) 5237 #define DVS_DEST_KEY (1<<2) 5238 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 5239 #define DVS_TILED (1<<10) 5240 #define _DVSALINOFF 0x72184 5241 #define _DVSASTRIDE 0x72188 5242 #define _DVSAPOS 0x7218c 5243 #define _DVSASIZE 0x72190 5244 #define _DVSAKEYVAL 0x72194 5245 #define _DVSAKEYMSK 0x72198 5246 #define _DVSASURF 0x7219c 5247 #define _DVSAKEYMAXVAL 0x721a0 5248 #define _DVSATILEOFF 0x721a4 5249 #define _DVSASURFLIVE 0x721ac 5250 #define _DVSASCALE 0x72204 5251 #define DVS_SCALE_ENABLE (1<<31) 5252 #define DVS_FILTER_MASK (3<<29) 5253 #define DVS_FILTER_MEDIUM (0<<29) 5254 #define DVS_FILTER_ENHANCING (1<<29) 5255 #define DVS_FILTER_SOFTENING (2<<29) 5256 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 5257 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 5258 #define _DVSAGAMC 0x72300 5259 5260 #define _DVSBCNTR 0x73180 5261 #define _DVSBLINOFF 0x73184 5262 #define _DVSBSTRIDE 0x73188 5263 #define _DVSBPOS 0x7318c 5264 #define _DVSBSIZE 0x73190 5265 #define _DVSBKEYVAL 0x73194 5266 #define _DVSBKEYMSK 0x73198 5267 #define _DVSBSURF 0x7319c 5268 #define _DVSBKEYMAXVAL 0x731a0 5269 #define _DVSBTILEOFF 0x731a4 5270 #define _DVSBSURFLIVE 0x731ac 5271 #define _DVSBSCALE 0x73204 5272 #define _DVSBGAMC 0x73300 5273 5274 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 5275 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 5276 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 5277 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 5278 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 5279 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 5280 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 5281 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 5282 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 5283 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 5284 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 5285 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 5286 5287 #define _SPRA_CTL 0x70280 5288 #define SPRITE_ENABLE (1<<31) 5289 #define SPRITE_GAMMA_ENABLE (1<<30) 5290 #define SPRITE_PIXFORMAT_MASK (7<<25) 5291 #define SPRITE_FORMAT_YUV422 (0<<25) 5292 #define SPRITE_FORMAT_RGBX101010 (1<<25) 5293 #define SPRITE_FORMAT_RGBX888 (2<<25) 5294 #define SPRITE_FORMAT_RGBX161616 (3<<25) 5295 #define SPRITE_FORMAT_YUV444 (4<<25) 5296 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 5297 #define SPRITE_PIPE_CSC_ENABLE (1<<24) 5298 #define SPRITE_SOURCE_KEY (1<<22) 5299 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 5300 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 5301 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 5302 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 5303 #define SPRITE_YUV_ORDER_YUYV (0<<16) 5304 #define SPRITE_YUV_ORDER_UYVY (1<<16) 5305 #define SPRITE_YUV_ORDER_YVYU (2<<16) 5306 #define SPRITE_YUV_ORDER_VYUY (3<<16) 5307 #define SPRITE_ROTATE_180 (1<<15) 5308 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 5309 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 5310 #define SPRITE_TILED (1<<10) 5311 #define SPRITE_DEST_KEY (1<<2) 5312 #define _SPRA_LINOFF 0x70284 5313 #define _SPRA_STRIDE 0x70288 5314 #define _SPRA_POS 0x7028c 5315 #define _SPRA_SIZE 0x70290 5316 #define _SPRA_KEYVAL 0x70294 5317 #define _SPRA_KEYMSK 0x70298 5318 #define _SPRA_SURF 0x7029c 5319 #define _SPRA_KEYMAX 0x702a0 5320 #define _SPRA_TILEOFF 0x702a4 5321 #define _SPRA_OFFSET 0x702a4 5322 #define _SPRA_SURFLIVE 0x702ac 5323 #define _SPRA_SCALE 0x70304 5324 #define SPRITE_SCALE_ENABLE (1<<31) 5325 #define SPRITE_FILTER_MASK (3<<29) 5326 #define SPRITE_FILTER_MEDIUM (0<<29) 5327 #define SPRITE_FILTER_ENHANCING (1<<29) 5328 #define SPRITE_FILTER_SOFTENING (2<<29) 5329 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 5330 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 5331 #define _SPRA_GAMC 0x70400 5332 5333 #define _SPRB_CTL 0x71280 5334 #define _SPRB_LINOFF 0x71284 5335 #define _SPRB_STRIDE 0x71288 5336 #define _SPRB_POS 0x7128c 5337 #define _SPRB_SIZE 0x71290 5338 #define _SPRB_KEYVAL 0x71294 5339 #define _SPRB_KEYMSK 0x71298 5340 #define _SPRB_SURF 0x7129c 5341 #define _SPRB_KEYMAX 0x712a0 5342 #define _SPRB_TILEOFF 0x712a4 5343 #define _SPRB_OFFSET 0x712a4 5344 #define _SPRB_SURFLIVE 0x712ac 5345 #define _SPRB_SCALE 0x71304 5346 #define _SPRB_GAMC 0x71400 5347 5348 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 5349 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 5350 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 5351 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 5352 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 5353 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 5354 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 5355 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 5356 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 5357 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 5358 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 5359 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 5360 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 5361 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 5362 5363 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 5364 #define SP_ENABLE (1<<31) 5365 #define SP_GAMMA_ENABLE (1<<30) 5366 #define SP_PIXFORMAT_MASK (0xf<<26) 5367 #define SP_FORMAT_YUV422 (0<<26) 5368 #define SP_FORMAT_BGR565 (5<<26) 5369 #define SP_FORMAT_BGRX8888 (6<<26) 5370 #define SP_FORMAT_BGRA8888 (7<<26) 5371 #define SP_FORMAT_RGBX1010102 (8<<26) 5372 #define SP_FORMAT_RGBA1010102 (9<<26) 5373 #define SP_FORMAT_RGBX8888 (0xe<<26) 5374 #define SP_FORMAT_RGBA8888 (0xf<<26) 5375 #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ 5376 #define SP_SOURCE_KEY (1<<22) 5377 #define SP_YUV_BYTE_ORDER_MASK (3<<16) 5378 #define SP_YUV_ORDER_YUYV (0<<16) 5379 #define SP_YUV_ORDER_UYVY (1<<16) 5380 #define SP_YUV_ORDER_YVYU (2<<16) 5381 #define SP_YUV_ORDER_VYUY (3<<16) 5382 #define SP_ROTATE_180 (1<<15) 5383 #define SP_TILED (1<<10) 5384 #define SP_MIRROR (1<<8) /* CHV pipe B */ 5385 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 5386 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 5387 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 5388 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 5389 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 5390 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 5391 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 5392 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 5393 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 5394 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 5395 #define SP_CONST_ALPHA_ENABLE (1<<31) 5396 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 5397 5398 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 5399 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 5400 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 5401 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 5402 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 5403 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 5404 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 5405 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 5406 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 5407 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 5408 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 5409 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 5410 5411 #define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR) 5412 #define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF) 5413 #define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE) 5414 #define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS) 5415 #define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE) 5416 #define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL) 5417 #define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK) 5418 #define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF) 5419 #define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 5420 #define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF) 5421 #define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA) 5422 #define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC) 5423 5424 /* 5425 * CHV pipe B sprite CSC 5426 * 5427 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 5428 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 5429 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 5430 */ 5431 #define SPCSCYGOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000) 5432 #define SPCSCCBOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000) 5433 #define SPCSCCROFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000) 5434 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 5435 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 5436 5437 #define SPCSCC01(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000) 5438 #define SPCSCC23(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000) 5439 #define SPCSCC45(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000) 5440 #define SPCSCC67(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000) 5441 #define SPCSCC8(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000) 5442 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 5443 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 5444 5445 #define SPCSCYGICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000) 5446 #define SPCSCCBICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000) 5447 #define SPCSCCRICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000) 5448 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 5449 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 5450 5451 #define SPCSCYGOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000) 5452 #define SPCSCCBOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000) 5453 #define SPCSCCROCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000) 5454 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 5455 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 5456 5457 /* Skylake plane registers */ 5458 5459 #define _PLANE_CTL_1_A 0x70180 5460 #define _PLANE_CTL_2_A 0x70280 5461 #define _PLANE_CTL_3_A 0x70380 5462 #define PLANE_CTL_ENABLE (1 << 31) 5463 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) 5464 #define PLANE_CTL_FORMAT_MASK (0xf << 24) 5465 #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) 5466 #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) 5467 #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) 5468 #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) 5469 #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) 5470 #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) 5471 #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) 5472 #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) 5473 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) 5474 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 5475 #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) 5476 #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) 5477 #define PLANE_CTL_ORDER_BGRX (0 << 20) 5478 #define PLANE_CTL_ORDER_RGBX (1 << 20) 5479 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 5480 #define PLANE_CTL_YUV422_YUYV ( 0 << 16) 5481 #define PLANE_CTL_YUV422_UYVY ( 1 << 16) 5482 #define PLANE_CTL_YUV422_YVYU ( 2 << 16) 5483 #define PLANE_CTL_YUV422_VYUY ( 3 << 16) 5484 #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) 5485 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 5486 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) 5487 #define PLANE_CTL_TILED_MASK (0x7 << 10) 5488 #define PLANE_CTL_TILED_LINEAR ( 0 << 10) 5489 #define PLANE_CTL_TILED_X ( 1 << 10) 5490 #define PLANE_CTL_TILED_Y ( 4 << 10) 5491 #define PLANE_CTL_TILED_YF ( 5 << 10) 5492 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) 5493 #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) 5494 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) 5495 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) 5496 #define PLANE_CTL_ROTATE_MASK 0x3 5497 #define PLANE_CTL_ROTATE_0 0x0 5498 #define PLANE_CTL_ROTATE_90 0x1 5499 #define PLANE_CTL_ROTATE_180 0x2 5500 #define PLANE_CTL_ROTATE_270 0x3 5501 #define _PLANE_STRIDE_1_A 0x70188 5502 #define _PLANE_STRIDE_2_A 0x70288 5503 #define _PLANE_STRIDE_3_A 0x70388 5504 #define _PLANE_POS_1_A 0x7018c 5505 #define _PLANE_POS_2_A 0x7028c 5506 #define _PLANE_POS_3_A 0x7038c 5507 #define _PLANE_SIZE_1_A 0x70190 5508 #define _PLANE_SIZE_2_A 0x70290 5509 #define _PLANE_SIZE_3_A 0x70390 5510 #define _PLANE_SURF_1_A 0x7019c 5511 #define _PLANE_SURF_2_A 0x7029c 5512 #define _PLANE_SURF_3_A 0x7039c 5513 #define _PLANE_OFFSET_1_A 0x701a4 5514 #define _PLANE_OFFSET_2_A 0x702a4 5515 #define _PLANE_OFFSET_3_A 0x703a4 5516 #define _PLANE_KEYVAL_1_A 0x70194 5517 #define _PLANE_KEYVAL_2_A 0x70294 5518 #define _PLANE_KEYMSK_1_A 0x70198 5519 #define _PLANE_KEYMSK_2_A 0x70298 5520 #define _PLANE_KEYMAX_1_A 0x701a0 5521 #define _PLANE_KEYMAX_2_A 0x702a0 5522 #define _PLANE_BUF_CFG_1_A 0x7027c 5523 #define _PLANE_BUF_CFG_2_A 0x7037c 5524 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 5525 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 5526 5527 #define _PLANE_CTL_1_B 0x71180 5528 #define _PLANE_CTL_2_B 0x71280 5529 #define _PLANE_CTL_3_B 0x71380 5530 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 5531 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 5532 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 5533 #define PLANE_CTL(pipe, plane) \ 5534 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 5535 5536 #define _PLANE_STRIDE_1_B 0x71188 5537 #define _PLANE_STRIDE_2_B 0x71288 5538 #define _PLANE_STRIDE_3_B 0x71388 5539 #define _PLANE_STRIDE_1(pipe) \ 5540 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 5541 #define _PLANE_STRIDE_2(pipe) \ 5542 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 5543 #define _PLANE_STRIDE_3(pipe) \ 5544 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 5545 #define PLANE_STRIDE(pipe, plane) \ 5546 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 5547 5548 #define _PLANE_POS_1_B 0x7118c 5549 #define _PLANE_POS_2_B 0x7128c 5550 #define _PLANE_POS_3_B 0x7138c 5551 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 5552 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 5553 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 5554 #define PLANE_POS(pipe, plane) \ 5555 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 5556 5557 #define _PLANE_SIZE_1_B 0x71190 5558 #define _PLANE_SIZE_2_B 0x71290 5559 #define _PLANE_SIZE_3_B 0x71390 5560 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 5561 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 5562 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 5563 #define PLANE_SIZE(pipe, plane) \ 5564 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 5565 5566 #define _PLANE_SURF_1_B 0x7119c 5567 #define _PLANE_SURF_2_B 0x7129c 5568 #define _PLANE_SURF_3_B 0x7139c 5569 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 5570 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 5571 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 5572 #define PLANE_SURF(pipe, plane) \ 5573 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 5574 5575 #define _PLANE_OFFSET_1_B 0x711a4 5576 #define _PLANE_OFFSET_2_B 0x712a4 5577 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 5578 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 5579 #define PLANE_OFFSET(pipe, plane) \ 5580 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 5581 5582 #define _PLANE_KEYVAL_1_B 0x71194 5583 #define _PLANE_KEYVAL_2_B 0x71294 5584 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 5585 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 5586 #define PLANE_KEYVAL(pipe, plane) \ 5587 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 5588 5589 #define _PLANE_KEYMSK_1_B 0x71198 5590 #define _PLANE_KEYMSK_2_B 0x71298 5591 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 5592 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 5593 #define PLANE_KEYMSK(pipe, plane) \ 5594 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 5595 5596 #define _PLANE_KEYMAX_1_B 0x711a0 5597 #define _PLANE_KEYMAX_2_B 0x712a0 5598 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 5599 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 5600 #define PLANE_KEYMAX(pipe, plane) \ 5601 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 5602 5603 #define _PLANE_BUF_CFG_1_B 0x7127c 5604 #define _PLANE_BUF_CFG_2_B 0x7137c 5605 #define _PLANE_BUF_CFG_1(pipe) \ 5606 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 5607 #define _PLANE_BUF_CFG_2(pipe) \ 5608 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 5609 #define PLANE_BUF_CFG(pipe, plane) \ 5610 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 5611 5612 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 5613 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 5614 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 5615 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 5616 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 5617 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 5618 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 5619 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 5620 5621 /* SKL new cursor registers */ 5622 #define _CUR_BUF_CFG_A 0x7017c 5623 #define _CUR_BUF_CFG_B 0x7117c 5624 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 5625 5626 /* VBIOS regs */ 5627 #define VGACNTRL _MMIO(0x71400) 5628 # define VGA_DISP_DISABLE (1 << 31) 5629 # define VGA_2X_MODE (1 << 30) 5630 # define VGA_PIPE_B_SELECT (1 << 29) 5631 5632 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 5633 5634 /* Ironlake */ 5635 5636 #define CPU_VGACNTRL _MMIO(0x41000) 5637 5638 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 5639 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 5640 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 5641 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 5642 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 5643 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 5644 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 5645 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 5646 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 5647 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 5648 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 5649 5650 /* refresh rate hardware control */ 5651 #define RR_HW_CTL _MMIO(0x45300) 5652 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 5653 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 5654 5655 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 5656 #define FDI_PLL_FB_CLOCK_MASK 0xff 5657 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 5658 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 5659 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 5660 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 5661 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 5662 5663 #define PCH_3DCGDIS0 _MMIO(0x46020) 5664 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 5665 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 5666 5667 #define PCH_3DCGDIS1 _MMIO(0x46024) 5668 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 5669 5670 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 5671 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 5672 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 5673 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 5674 5675 5676 #define _PIPEA_DATA_M1 0x60030 5677 #define PIPE_DATA_M1_OFFSET 0 5678 #define _PIPEA_DATA_N1 0x60034 5679 #define PIPE_DATA_N1_OFFSET 0 5680 5681 #define _PIPEA_DATA_M2 0x60038 5682 #define PIPE_DATA_M2_OFFSET 0 5683 #define _PIPEA_DATA_N2 0x6003c 5684 #define PIPE_DATA_N2_OFFSET 0 5685 5686 #define _PIPEA_LINK_M1 0x60040 5687 #define PIPE_LINK_M1_OFFSET 0 5688 #define _PIPEA_LINK_N1 0x60044 5689 #define PIPE_LINK_N1_OFFSET 0 5690 5691 #define _PIPEA_LINK_M2 0x60048 5692 #define PIPE_LINK_M2_OFFSET 0 5693 #define _PIPEA_LINK_N2 0x6004c 5694 #define PIPE_LINK_N2_OFFSET 0 5695 5696 /* PIPEB timing regs are same start from 0x61000 */ 5697 5698 #define _PIPEB_DATA_M1 0x61030 5699 #define _PIPEB_DATA_N1 0x61034 5700 #define _PIPEB_DATA_M2 0x61038 5701 #define _PIPEB_DATA_N2 0x6103c 5702 #define _PIPEB_LINK_M1 0x61040 5703 #define _PIPEB_LINK_N1 0x61044 5704 #define _PIPEB_LINK_M2 0x61048 5705 #define _PIPEB_LINK_N2 0x6104c 5706 5707 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 5708 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 5709 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 5710 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 5711 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 5712 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 5713 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 5714 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 5715 5716 /* CPU panel fitter */ 5717 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 5718 #define _PFA_CTL_1 0x68080 5719 #define _PFB_CTL_1 0x68880 5720 #define PF_ENABLE (1<<31) 5721 #define PF_PIPE_SEL_MASK_IVB (3<<29) 5722 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 5723 #define PF_FILTER_MASK (3<<23) 5724 #define PF_FILTER_PROGRAMMED (0<<23) 5725 #define PF_FILTER_MED_3x3 (1<<23) 5726 #define PF_FILTER_EDGE_ENHANCE (2<<23) 5727 #define PF_FILTER_EDGE_SOFTEN (3<<23) 5728 #define _PFA_WIN_SZ 0x68074 5729 #define _PFB_WIN_SZ 0x68874 5730 #define _PFA_WIN_POS 0x68070 5731 #define _PFB_WIN_POS 0x68870 5732 #define _PFA_VSCALE 0x68084 5733 #define _PFB_VSCALE 0x68884 5734 #define _PFA_HSCALE 0x68090 5735 #define _PFB_HSCALE 0x68890 5736 5737 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 5738 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 5739 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 5740 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 5741 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 5742 5743 #define _PSA_CTL 0x68180 5744 #define _PSB_CTL 0x68980 5745 #define PS_ENABLE (1<<31) 5746 #define _PSA_WIN_SZ 0x68174 5747 #define _PSB_WIN_SZ 0x68974 5748 #define _PSA_WIN_POS 0x68170 5749 #define _PSB_WIN_POS 0x68970 5750 5751 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 5752 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 5753 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 5754 5755 /* 5756 * Skylake scalers 5757 */ 5758 #define _PS_1A_CTRL 0x68180 5759 #define _PS_2A_CTRL 0x68280 5760 #define _PS_1B_CTRL 0x68980 5761 #define _PS_2B_CTRL 0x68A80 5762 #define _PS_1C_CTRL 0x69180 5763 #define PS_SCALER_EN (1 << 31) 5764 #define PS_SCALER_MODE_MASK (3 << 28) 5765 #define PS_SCALER_MODE_DYN (0 << 28) 5766 #define PS_SCALER_MODE_HQ (1 << 28) 5767 #define PS_PLANE_SEL_MASK (7 << 25) 5768 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 5769 #define PS_FILTER_MASK (3 << 23) 5770 #define PS_FILTER_MEDIUM (0 << 23) 5771 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 5772 #define PS_FILTER_BILINEAR (3 << 23) 5773 #define PS_VERT3TAP (1 << 21) 5774 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 5775 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 5776 #define PS_PWRUP_PROGRESS (1 << 17) 5777 #define PS_V_FILTER_BYPASS (1 << 8) 5778 #define PS_VADAPT_EN (1 << 7) 5779 #define PS_VADAPT_MODE_MASK (3 << 5) 5780 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 5781 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 5782 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 5783 5784 #define _PS_PWR_GATE_1A 0x68160 5785 #define _PS_PWR_GATE_2A 0x68260 5786 #define _PS_PWR_GATE_1B 0x68960 5787 #define _PS_PWR_GATE_2B 0x68A60 5788 #define _PS_PWR_GATE_1C 0x69160 5789 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 5790 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 5791 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 5792 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 5793 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 5794 #define PS_PWR_GATE_SLPEN_8 0 5795 #define PS_PWR_GATE_SLPEN_16 1 5796 #define PS_PWR_GATE_SLPEN_24 2 5797 #define PS_PWR_GATE_SLPEN_32 3 5798 5799 #define _PS_WIN_POS_1A 0x68170 5800 #define _PS_WIN_POS_2A 0x68270 5801 #define _PS_WIN_POS_1B 0x68970 5802 #define _PS_WIN_POS_2B 0x68A70 5803 #define _PS_WIN_POS_1C 0x69170 5804 5805 #define _PS_WIN_SZ_1A 0x68174 5806 #define _PS_WIN_SZ_2A 0x68274 5807 #define _PS_WIN_SZ_1B 0x68974 5808 #define _PS_WIN_SZ_2B 0x68A74 5809 #define _PS_WIN_SZ_1C 0x69174 5810 5811 #define _PS_VSCALE_1A 0x68184 5812 #define _PS_VSCALE_2A 0x68284 5813 #define _PS_VSCALE_1B 0x68984 5814 #define _PS_VSCALE_2B 0x68A84 5815 #define _PS_VSCALE_1C 0x69184 5816 5817 #define _PS_HSCALE_1A 0x68190 5818 #define _PS_HSCALE_2A 0x68290 5819 #define _PS_HSCALE_1B 0x68990 5820 #define _PS_HSCALE_2B 0x68A90 5821 #define _PS_HSCALE_1C 0x69190 5822 5823 #define _PS_VPHASE_1A 0x68188 5824 #define _PS_VPHASE_2A 0x68288 5825 #define _PS_VPHASE_1B 0x68988 5826 #define _PS_VPHASE_2B 0x68A88 5827 #define _PS_VPHASE_1C 0x69188 5828 5829 #define _PS_HPHASE_1A 0x68194 5830 #define _PS_HPHASE_2A 0x68294 5831 #define _PS_HPHASE_1B 0x68994 5832 #define _PS_HPHASE_2B 0x68A94 5833 #define _PS_HPHASE_1C 0x69194 5834 5835 #define _PS_ECC_STAT_1A 0x681D0 5836 #define _PS_ECC_STAT_2A 0x682D0 5837 #define _PS_ECC_STAT_1B 0x689D0 5838 #define _PS_ECC_STAT_2B 0x68AD0 5839 #define _PS_ECC_STAT_1C 0x691D0 5840 5841 #define _ID(id, a, b) ((a) + (id)*((b)-(a))) 5842 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 5843 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 5844 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 5845 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 5846 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 5847 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 5848 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 5849 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 5850 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 5851 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 5852 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 5853 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 5854 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5855 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 5856 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 5857 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5858 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 5859 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 5860 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5861 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 5862 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 5863 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5864 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 5865 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 5866 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 5867 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 5868 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 5869 5870 /* legacy palette */ 5871 #define _LGC_PALETTE_A 0x4a000 5872 #define _LGC_PALETTE_B 0x4a800 5873 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 5874 5875 #define _GAMMA_MODE_A 0x4a480 5876 #define _GAMMA_MODE_B 0x4ac80 5877 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 5878 #define GAMMA_MODE_MODE_MASK (3 << 0) 5879 #define GAMMA_MODE_MODE_8BIT (0 << 0) 5880 #define GAMMA_MODE_MODE_10BIT (1 << 0) 5881 #define GAMMA_MODE_MODE_12BIT (2 << 0) 5882 #define GAMMA_MODE_MODE_SPLIT (3 << 0) 5883 5884 /* DMC/CSR */ 5885 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) 5886 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 5887 #define CSR_HTP_ADDR_SKL 0x00500034 5888 #define CSR_SSP_BASE _MMIO(0x8F074) 5889 #define CSR_HTP_SKL _MMIO(0x8F004) 5890 #define CSR_LAST_WRITE _MMIO(0x8F034) 5891 #define CSR_LAST_WRITE_VALUE 0xc003b400 5892 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 5893 #define CSR_MMIO_START_RANGE 0x80000 5894 #define CSR_MMIO_END_RANGE 0x8FFFF 5895 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) 5896 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) 5897 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) 5898 5899 /* interrupts */ 5900 #define DE_MASTER_IRQ_CONTROL (1 << 31) 5901 #define DE_SPRITEB_FLIP_DONE (1 << 29) 5902 #define DE_SPRITEA_FLIP_DONE (1 << 28) 5903 #define DE_PLANEB_FLIP_DONE (1 << 27) 5904 #define DE_PLANEA_FLIP_DONE (1 << 26) 5905 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 5906 #define DE_PCU_EVENT (1 << 25) 5907 #define DE_GTT_FAULT (1 << 24) 5908 #define DE_POISON (1 << 23) 5909 #define DE_PERFORM_COUNTER (1 << 22) 5910 #define DE_PCH_EVENT (1 << 21) 5911 #define DE_AUX_CHANNEL_A (1 << 20) 5912 #define DE_DP_A_HOTPLUG (1 << 19) 5913 #define DE_GSE (1 << 18) 5914 #define DE_PIPEB_VBLANK (1 << 15) 5915 #define DE_PIPEB_EVEN_FIELD (1 << 14) 5916 #define DE_PIPEB_ODD_FIELD (1 << 13) 5917 #define DE_PIPEB_LINE_COMPARE (1 << 12) 5918 #define DE_PIPEB_VSYNC (1 << 11) 5919 #define DE_PIPEB_CRC_DONE (1 << 10) 5920 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 5921 #define DE_PIPEA_VBLANK (1 << 7) 5922 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) 5923 #define DE_PIPEA_EVEN_FIELD (1 << 6) 5924 #define DE_PIPEA_ODD_FIELD (1 << 5) 5925 #define DE_PIPEA_LINE_COMPARE (1 << 4) 5926 #define DE_PIPEA_VSYNC (1 << 3) 5927 #define DE_PIPEA_CRC_DONE (1 << 2) 5928 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) 5929 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 5930 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) 5931 5932 /* More Ivybridge lolz */ 5933 #define DE_ERR_INT_IVB (1<<30) 5934 #define DE_GSE_IVB (1<<29) 5935 #define DE_PCH_EVENT_IVB (1<<28) 5936 #define DE_DP_A_HOTPLUG_IVB (1<<27) 5937 #define DE_AUX_CHANNEL_A_IVB (1<<26) 5938 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 5939 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 5940 #define DE_PIPEC_VBLANK_IVB (1<<10) 5941 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 5942 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 5943 #define DE_PIPEB_VBLANK_IVB (1<<5) 5944 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 5945 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 5946 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) 5947 #define DE_PIPEA_VBLANK_IVB (1<<0) 5948 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 5949 5950 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 5951 #define MASTER_INTERRUPT_ENABLE (1<<31) 5952 5953 #define DEISR _MMIO(0x44000) 5954 #define DEIMR _MMIO(0x44004) 5955 #define DEIIR _MMIO(0x44008) 5956 #define DEIER _MMIO(0x4400c) 5957 5958 #define GTISR _MMIO(0x44010) 5959 #define GTIMR _MMIO(0x44014) 5960 #define GTIIR _MMIO(0x44018) 5961 #define GTIER _MMIO(0x4401c) 5962 5963 #define GEN8_MASTER_IRQ _MMIO(0x44200) 5964 #define GEN8_MASTER_IRQ_CONTROL (1<<31) 5965 #define GEN8_PCU_IRQ (1<<30) 5966 #define GEN8_DE_PCH_IRQ (1<<23) 5967 #define GEN8_DE_MISC_IRQ (1<<22) 5968 #define GEN8_DE_PORT_IRQ (1<<20) 5969 #define GEN8_DE_PIPE_C_IRQ (1<<18) 5970 #define GEN8_DE_PIPE_B_IRQ (1<<17) 5971 #define GEN8_DE_PIPE_A_IRQ (1<<16) 5972 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe))) 5973 #define GEN8_GT_VECS_IRQ (1<<6) 5974 #define GEN8_GT_PM_IRQ (1<<4) 5975 #define GEN8_GT_VCS2_IRQ (1<<3) 5976 #define GEN8_GT_VCS1_IRQ (1<<2) 5977 #define GEN8_GT_BCS_IRQ (1<<1) 5978 #define GEN8_GT_RCS_IRQ (1<<0) 5979 5980 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 5981 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 5982 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 5983 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 5984 5985 #define GEN8_RCS_IRQ_SHIFT 0 5986 #define GEN8_BCS_IRQ_SHIFT 16 5987 #define GEN8_VCS1_IRQ_SHIFT 0 5988 #define GEN8_VCS2_IRQ_SHIFT 16 5989 #define GEN8_VECS_IRQ_SHIFT 0 5990 #define GEN8_WD_IRQ_SHIFT 16 5991 5992 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 5993 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 5994 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 5995 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 5996 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5997 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5998 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5999 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 6000 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 6001 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 6002 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 6003 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 6004 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 6005 #define GEN8_PIPE_VSYNC (1 << 1) 6006 #define GEN8_PIPE_VBLANK (1 << 0) 6007 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 6008 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 6009 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 6010 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 6011 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 6012 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 6013 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 6014 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 6015 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 6016 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 6017 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 6018 (GEN8_PIPE_CURSOR_FAULT | \ 6019 GEN8_PIPE_SPRITE_FAULT | \ 6020 GEN8_PIPE_PRIMARY_FAULT) 6021 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 6022 (GEN9_PIPE_CURSOR_FAULT | \ 6023 GEN9_PIPE_PLANE4_FAULT | \ 6024 GEN9_PIPE_PLANE3_FAULT | \ 6025 GEN9_PIPE_PLANE2_FAULT | \ 6026 GEN9_PIPE_PLANE1_FAULT) 6027 6028 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 6029 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 6030 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 6031 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 6032 #define GEN9_AUX_CHANNEL_D (1 << 27) 6033 #define GEN9_AUX_CHANNEL_C (1 << 26) 6034 #define GEN9_AUX_CHANNEL_B (1 << 25) 6035 #define BXT_DE_PORT_HP_DDIC (1 << 5) 6036 #define BXT_DE_PORT_HP_DDIB (1 << 4) 6037 #define BXT_DE_PORT_HP_DDIA (1 << 3) 6038 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ 6039 BXT_DE_PORT_HP_DDIB | \ 6040 BXT_DE_PORT_HP_DDIC) 6041 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 6042 #define BXT_DE_PORT_GMBUS (1 << 1) 6043 #define GEN8_AUX_CHANNEL_A (1 << 0) 6044 6045 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 6046 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 6047 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 6048 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 6049 #define GEN8_DE_MISC_GSE (1 << 27) 6050 6051 #define GEN8_PCU_ISR _MMIO(0x444e0) 6052 #define GEN8_PCU_IMR _MMIO(0x444e4) 6053 #define GEN8_PCU_IIR _MMIO(0x444e8) 6054 #define GEN8_PCU_IER _MMIO(0x444ec) 6055 6056 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 6057 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 6058 #define ILK_ELPIN_409_SELECT (1 << 25) 6059 #define ILK_DPARB_GATE (1<<22) 6060 #define ILK_VSDPFD_FULL (1<<21) 6061 #define FUSE_STRAP _MMIO(0x42014) 6062 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 6063 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 6064 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 6065 #define IVB_PIPE_C_DISABLE (1 << 28) 6066 #define ILK_HDCP_DISABLE (1 << 25) 6067 #define ILK_eDP_A_DISABLE (1 << 24) 6068 #define HSW_CDCLK_LIMIT (1 << 24) 6069 #define ILK_DESKTOP (1 << 23) 6070 6071 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 6072 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 6073 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 6074 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 6075 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 6076 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 6077 6078 #define IVB_CHICKEN3 _MMIO(0x4200c) 6079 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 6080 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 6081 6082 #define CHICKEN_PAR1_1 _MMIO(0x42080) 6083 #define DPA_MASK_VBLANK_SRD (1 << 15) 6084 #define FORCE_ARB_IDLE_PLANES (1 << 14) 6085 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 6086 6087 #define CHICKEN_PAR2_1 _MMIO(0x42090) 6088 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 6089 6090 #define _CHICKEN_PIPESL_1_A 0x420b0 6091 #define _CHICKEN_PIPESL_1_B 0x420b4 6092 #define HSW_FBCQ_DIS (1 << 22) 6093 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 6094 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 6095 6096 #define DISP_ARB_CTL _MMIO(0x45000) 6097 #define DISP_FBC_MEMORY_WAKE (1<<31) 6098 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 6099 #define DISP_FBC_WM_DIS (1<<15) 6100 #define DISP_ARB_CTL2 _MMIO(0x45004) 6101 #define DISP_DATA_PARTITION_5_6 (1<<6) 6102 #define DBUF_CTL _MMIO(0x45008) 6103 #define DBUF_POWER_REQUEST (1<<31) 6104 #define DBUF_POWER_STATE (1<<30) 6105 #define GEN7_MSG_CTL _MMIO(0x45010) 6106 #define WAIT_FOR_PCH_RESET_ACK (1<<1) 6107 #define WAIT_FOR_PCH_FLR_ACK (1<<0) 6108 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 6109 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) 6110 6111 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 6112 #define MASK_WAKEMEM (1<<13) 6113 6114 #define SKL_DFSM _MMIO(0x51000) 6115 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 6116 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 6117 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 6118 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 6119 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 6120 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 6121 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 6122 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 6123 6124 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 6125 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14) 6126 6127 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 6128 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) 6129 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1<<10) 6130 6131 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 6132 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) 6133 #define GEN8_CS_CHICKEN1 _MMIO(0x2580) 6134 6135 /* GEN7 chicken */ 6136 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 6137 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 6138 # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) 6139 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 6140 # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12) 6141 # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8) 6142 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) 6143 6144 #define HIZ_CHICKEN _MMIO(0x7018) 6145 # define CHV_HZ_8X8_MODE_IN_1X (1<<15) 6146 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3) 6147 6148 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) 6149 #define DISABLE_PIXEL_MASK_CAMMING (1<<14) 6150 6151 #define GEN7_L3SQCREG1 _MMIO(0xB010) 6152 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 6153 6154 #define GEN8_L3SQCREG1 _MMIO(0xB100) 6155 /* 6156 * Note that on CHV the following has an off-by-one error wrt. to BSpec. 6157 * Using the formula in BSpec leads to a hang, while the formula here works 6158 * fine and matches the formulas for all other platforms. A BSpec change 6159 * request has been filed to clarify this. 6160 */ 6161 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) 6162 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) 6163 6164 #define GEN7_L3CNTLREG1 _MMIO(0xB01C) 6165 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 6166 #define GEN7_L3AGDIS (1<<19) 6167 #define GEN7_L3CNTLREG2 _MMIO(0xB020) 6168 #define GEN7_L3CNTLREG3 _MMIO(0xB024) 6169 6170 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) 6171 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 6172 6173 #define GEN7_L3SQCREG4 _MMIO(0xb034) 6174 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 6175 6176 #define GEN8_L3SQCREG4 _MMIO(0xb118) 6177 #define GEN8_LQSC_RO_PERF_DIS (1<<27) 6178 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21) 6179 6180 /* GEN8 chicken */ 6181 #define HDC_CHICKEN0 _MMIO(0x7300) 6182 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) 6183 #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) 6184 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) 6185 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) 6186 #define HDC_FORCE_NON_COHERENT (1<<4) 6187 #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) 6188 6189 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 6190 6191 /* GEN9 chicken */ 6192 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) 6193 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) 6194 6195 /* WaCatErrorRejectionIssue */ 6196 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 6197 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 6198 6199 #define HSW_SCRATCH1 _MMIO(0xb038) 6200 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 6201 6202 #define BDW_SCRATCH1 _MMIO(0xb11c) 6203 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2) 6204 6205 /* PCH */ 6206 6207 /* south display engine interrupt: IBX */ 6208 #define SDE_AUDIO_POWER_D (1 << 27) 6209 #define SDE_AUDIO_POWER_C (1 << 26) 6210 #define SDE_AUDIO_POWER_B (1 << 25) 6211 #define SDE_AUDIO_POWER_SHIFT (25) 6212 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 6213 #define SDE_GMBUS (1 << 24) 6214 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 6215 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 6216 #define SDE_AUDIO_HDCP_MASK (3 << 22) 6217 #define SDE_AUDIO_TRANSB (1 << 21) 6218 #define SDE_AUDIO_TRANSA (1 << 20) 6219 #define SDE_AUDIO_TRANS_MASK (3 << 20) 6220 #define SDE_POISON (1 << 19) 6221 /* 18 reserved */ 6222 #define SDE_FDI_RXB (1 << 17) 6223 #define SDE_FDI_RXA (1 << 16) 6224 #define SDE_FDI_MASK (3 << 16) 6225 #define SDE_AUXD (1 << 15) 6226 #define SDE_AUXC (1 << 14) 6227 #define SDE_AUXB (1 << 13) 6228 #define SDE_AUX_MASK (7 << 13) 6229 /* 12 reserved */ 6230 #define SDE_CRT_HOTPLUG (1 << 11) 6231 #define SDE_PORTD_HOTPLUG (1 << 10) 6232 #define SDE_PORTC_HOTPLUG (1 << 9) 6233 #define SDE_PORTB_HOTPLUG (1 << 8) 6234 #define SDE_SDVOB_HOTPLUG (1 << 6) 6235 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 6236 SDE_SDVOB_HOTPLUG | \ 6237 SDE_PORTB_HOTPLUG | \ 6238 SDE_PORTC_HOTPLUG | \ 6239 SDE_PORTD_HOTPLUG) 6240 #define SDE_TRANSB_CRC_DONE (1 << 5) 6241 #define SDE_TRANSB_CRC_ERR (1 << 4) 6242 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 6243 #define SDE_TRANSA_CRC_DONE (1 << 2) 6244 #define SDE_TRANSA_CRC_ERR (1 << 1) 6245 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 6246 #define SDE_TRANS_MASK (0x3f) 6247 6248 /* south display engine interrupt: CPT/PPT */ 6249 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 6250 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 6251 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 6252 #define SDE_AUDIO_POWER_SHIFT_CPT 29 6253 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 6254 #define SDE_AUXD_CPT (1 << 27) 6255 #define SDE_AUXC_CPT (1 << 26) 6256 #define SDE_AUXB_CPT (1 << 25) 6257 #define SDE_AUX_MASK_CPT (7 << 25) 6258 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 6259 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 6260 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 6261 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 6262 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 6263 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 6264 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 6265 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 6266 SDE_SDVOB_HOTPLUG_CPT | \ 6267 SDE_PORTD_HOTPLUG_CPT | \ 6268 SDE_PORTC_HOTPLUG_CPT | \ 6269 SDE_PORTB_HOTPLUG_CPT) 6270 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 6271 SDE_PORTD_HOTPLUG_CPT | \ 6272 SDE_PORTC_HOTPLUG_CPT | \ 6273 SDE_PORTB_HOTPLUG_CPT | \ 6274 SDE_PORTA_HOTPLUG_SPT) 6275 #define SDE_GMBUS_CPT (1 << 17) 6276 #define SDE_ERROR_CPT (1 << 16) 6277 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 6278 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 6279 #define SDE_FDI_RXC_CPT (1 << 8) 6280 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 6281 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 6282 #define SDE_FDI_RXB_CPT (1 << 4) 6283 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 6284 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 6285 #define SDE_FDI_RXA_CPT (1 << 0) 6286 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 6287 SDE_AUDIO_CP_REQ_B_CPT | \ 6288 SDE_AUDIO_CP_REQ_A_CPT) 6289 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 6290 SDE_AUDIO_CP_CHG_B_CPT | \ 6291 SDE_AUDIO_CP_CHG_A_CPT) 6292 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 6293 SDE_FDI_RXB_CPT | \ 6294 SDE_FDI_RXA_CPT) 6295 6296 #define SDEISR _MMIO(0xc4000) 6297 #define SDEIMR _MMIO(0xc4004) 6298 #define SDEIIR _MMIO(0xc4008) 6299 #define SDEIER _MMIO(0xc400c) 6300 6301 #define SERR_INT _MMIO(0xc4040) 6302 #define SERR_INT_POISON (1<<31) 6303 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) 6304 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) 6305 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) 6306 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3)) 6307 6308 /* digital port hotplug */ 6309 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 6310 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 6311 #define BXT_DDIA_HPD_INVERT (1 << 27) 6312 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 6313 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 6314 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 6315 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 6316 #define PORTD_HOTPLUG_ENABLE (1 << 20) 6317 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 6318 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 6319 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 6320 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 6321 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 6322 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 6323 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 6324 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 6325 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 6326 #define PORTC_HOTPLUG_ENABLE (1 << 12) 6327 #define BXT_DDIC_HPD_INVERT (1 << 11) 6328 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 6329 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 6330 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 6331 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 6332 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 6333 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 6334 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 6335 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 6336 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 6337 #define PORTB_HOTPLUG_ENABLE (1 << 4) 6338 #define BXT_DDIB_HPD_INVERT (1 << 3) 6339 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 6340 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 6341 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 6342 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 6343 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 6344 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 6345 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 6346 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 6347 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 6348 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 6349 BXT_DDIB_HPD_INVERT | \ 6350 BXT_DDIC_HPD_INVERT) 6351 6352 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 6353 #define PORTE_HOTPLUG_ENABLE (1 << 4) 6354 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 6355 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 6356 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 6357 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 6358 6359 #define PCH_GPIOA _MMIO(0xc5010) 6360 #define PCH_GPIOB _MMIO(0xc5014) 6361 #define PCH_GPIOC _MMIO(0xc5018) 6362 #define PCH_GPIOD _MMIO(0xc501c) 6363 #define PCH_GPIOE _MMIO(0xc5020) 6364 #define PCH_GPIOF _MMIO(0xc5024) 6365 6366 #define PCH_GMBUS0 _MMIO(0xc5100) 6367 #define PCH_GMBUS1 _MMIO(0xc5104) 6368 #define PCH_GMBUS2 _MMIO(0xc5108) 6369 #define PCH_GMBUS3 _MMIO(0xc510c) 6370 #define PCH_GMBUS4 _MMIO(0xc5110) 6371 #define PCH_GMBUS5 _MMIO(0xc5120) 6372 6373 #define _PCH_DPLL_A 0xc6014 6374 #define _PCH_DPLL_B 0xc6018 6375 #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 6376 6377 #define _PCH_FPA0 0xc6040 6378 #define FP_CB_TUNE (0x3<<22) 6379 #define _PCH_FPA1 0xc6044 6380 #define _PCH_FPB0 0xc6048 6381 #define _PCH_FPB1 0xc604c 6382 #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 6383 #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 6384 6385 #define PCH_DPLL_TEST _MMIO(0xc606c) 6386 6387 #define PCH_DREF_CONTROL _MMIO(0xC6200) 6388 #define DREF_CONTROL_MASK 0x7fc3 6389 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 6390 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 6391 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 6392 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 6393 #define DREF_SSC_SOURCE_DISABLE (0<<11) 6394 #define DREF_SSC_SOURCE_ENABLE (2<<11) 6395 #define DREF_SSC_SOURCE_MASK (3<<11) 6396 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 6397 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 6398 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 6399 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 6400 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 6401 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 6402 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 6403 #define DREF_SSC4_DOWNSPREAD (0<<6) 6404 #define DREF_SSC4_CENTERSPREAD (1<<6) 6405 #define DREF_SSC1_DISABLE (0<<1) 6406 #define DREF_SSC1_ENABLE (1<<1) 6407 #define DREF_SSC4_DISABLE (0) 6408 #define DREF_SSC4_ENABLE (1) 6409 6410 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 6411 #define FDL_TP1_TIMER_SHIFT 12 6412 #define FDL_TP1_TIMER_MASK (3<<12) 6413 #define FDL_TP2_TIMER_SHIFT 10 6414 #define FDL_TP2_TIMER_MASK (3<<10) 6415 #define RAWCLK_FREQ_MASK 0x3ff 6416 6417 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 6418 6419 #define PCH_SSC4_PARMS _MMIO(0xc6210) 6420 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 6421 6422 #define PCH_DPLL_SEL _MMIO(0xc7000) 6423 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 6424 #define TRANS_DPLLA_SEL(pipe) 0 6425 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 6426 6427 /* transcoder */ 6428 6429 #define _PCH_TRANS_HTOTAL_A 0xe0000 6430 #define TRANS_HTOTAL_SHIFT 16 6431 #define TRANS_HACTIVE_SHIFT 0 6432 #define _PCH_TRANS_HBLANK_A 0xe0004 6433 #define TRANS_HBLANK_END_SHIFT 16 6434 #define TRANS_HBLANK_START_SHIFT 0 6435 #define _PCH_TRANS_HSYNC_A 0xe0008 6436 #define TRANS_HSYNC_END_SHIFT 16 6437 #define TRANS_HSYNC_START_SHIFT 0 6438 #define _PCH_TRANS_VTOTAL_A 0xe000c 6439 #define TRANS_VTOTAL_SHIFT 16 6440 #define TRANS_VACTIVE_SHIFT 0 6441 #define _PCH_TRANS_VBLANK_A 0xe0010 6442 #define TRANS_VBLANK_END_SHIFT 16 6443 #define TRANS_VBLANK_START_SHIFT 0 6444 #define _PCH_TRANS_VSYNC_A 0xe0014 6445 #define TRANS_VSYNC_END_SHIFT 16 6446 #define TRANS_VSYNC_START_SHIFT 0 6447 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 6448 6449 #define _PCH_TRANSA_DATA_M1 0xe0030 6450 #define _PCH_TRANSA_DATA_N1 0xe0034 6451 #define _PCH_TRANSA_DATA_M2 0xe0038 6452 #define _PCH_TRANSA_DATA_N2 0xe003c 6453 #define _PCH_TRANSA_LINK_M1 0xe0040 6454 #define _PCH_TRANSA_LINK_N1 0xe0044 6455 #define _PCH_TRANSA_LINK_M2 0xe0048 6456 #define _PCH_TRANSA_LINK_N2 0xe004c 6457 6458 /* Per-transcoder DIP controls (PCH) */ 6459 #define _VIDEO_DIP_CTL_A 0xe0200 6460 #define _VIDEO_DIP_DATA_A 0xe0208 6461 #define _VIDEO_DIP_GCP_A 0xe0210 6462 #define GCP_COLOR_INDICATION (1 << 2) 6463 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 6464 #define GCP_AV_MUTE (1 << 0) 6465 6466 #define _VIDEO_DIP_CTL_B 0xe1200 6467 #define _VIDEO_DIP_DATA_B 0xe1208 6468 #define _VIDEO_DIP_GCP_B 0xe1210 6469 6470 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 6471 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 6472 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 6473 6474 /* Per-transcoder DIP controls (VLV) */ 6475 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 6476 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 6477 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 6478 6479 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 6480 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 6481 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 6482 6483 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 6484 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 6485 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 6486 6487 #define VLV_TVIDEO_DIP_CTL(pipe) \ 6488 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 6489 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 6490 #define VLV_TVIDEO_DIP_DATA(pipe) \ 6491 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 6492 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 6493 #define VLV_TVIDEO_DIP_GCP(pipe) \ 6494 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 6495 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 6496 6497 /* Haswell DIP controls */ 6498 6499 #define _HSW_VIDEO_DIP_CTL_A 0x60200 6500 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 6501 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 6502 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 6503 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 6504 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 6505 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 6506 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 6507 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 6508 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 6509 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 6510 #define _HSW_VIDEO_DIP_GCP_A 0x60210 6511 6512 #define _HSW_VIDEO_DIP_CTL_B 0x61200 6513 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 6514 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 6515 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 6516 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 6517 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 6518 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 6519 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 6520 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 6521 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 6522 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 6523 #define _HSW_VIDEO_DIP_GCP_B 0x61210 6524 6525 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 6526 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 6527 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 6528 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 6529 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 6530 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 6531 6532 #define _HSW_STEREO_3D_CTL_A 0x70020 6533 #define S3D_ENABLE (1<<31) 6534 #define _HSW_STEREO_3D_CTL_B 0x71020 6535 6536 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 6537 6538 #define _PCH_TRANS_HTOTAL_B 0xe1000 6539 #define _PCH_TRANS_HBLANK_B 0xe1004 6540 #define _PCH_TRANS_HSYNC_B 0xe1008 6541 #define _PCH_TRANS_VTOTAL_B 0xe100c 6542 #define _PCH_TRANS_VBLANK_B 0xe1010 6543 #define _PCH_TRANS_VSYNC_B 0xe1014 6544 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 6545 6546 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 6547 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 6548 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 6549 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 6550 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 6551 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 6552 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 6553 6554 #define _PCH_TRANSB_DATA_M1 0xe1030 6555 #define _PCH_TRANSB_DATA_N1 0xe1034 6556 #define _PCH_TRANSB_DATA_M2 0xe1038 6557 #define _PCH_TRANSB_DATA_N2 0xe103c 6558 #define _PCH_TRANSB_LINK_M1 0xe1040 6559 #define _PCH_TRANSB_LINK_N1 0xe1044 6560 #define _PCH_TRANSB_LINK_M2 0xe1048 6561 #define _PCH_TRANSB_LINK_N2 0xe104c 6562 6563 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 6564 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 6565 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 6566 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 6567 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 6568 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 6569 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 6570 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 6571 6572 #define _PCH_TRANSACONF 0xf0008 6573 #define _PCH_TRANSBCONF 0xf1008 6574 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 6575 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 6576 #define TRANS_DISABLE (0<<31) 6577 #define TRANS_ENABLE (1<<31) 6578 #define TRANS_STATE_MASK (1<<30) 6579 #define TRANS_STATE_DISABLE (0<<30) 6580 #define TRANS_STATE_ENABLE (1<<30) 6581 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 6582 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 6583 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 6584 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 6585 #define TRANS_INTERLACE_MASK (7<<21) 6586 #define TRANS_PROGRESSIVE (0<<21) 6587 #define TRANS_INTERLACED (3<<21) 6588 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 6589 #define TRANS_8BPC (0<<5) 6590 #define TRANS_10BPC (1<<5) 6591 #define TRANS_6BPC (2<<5) 6592 #define TRANS_12BPC (3<<5) 6593 6594 #define _TRANSA_CHICKEN1 0xf0060 6595 #define _TRANSB_CHICKEN1 0xf1060 6596 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 6597 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10) 6598 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 6599 #define _TRANSA_CHICKEN2 0xf0064 6600 #define _TRANSB_CHICKEN2 0xf1064 6601 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 6602 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 6603 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) 6604 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) 6605 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) 6606 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) 6607 6608 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 6609 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 6610 #define FDIA_PHASE_SYNC_SHIFT_EN 18 6611 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 6612 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 6613 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 6614 #define SPT_PWM_GRANULARITY (1<<0) 6615 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 6616 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 6617 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 6618 #define LPT_PWM_GRANULARITY (1<<5) 6619 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 6620 6621 #define _FDI_RXA_CHICKEN 0xc200c 6622 #define _FDI_RXB_CHICKEN 0xc2010 6623 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 6624 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 6625 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 6626 6627 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 6628 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 6629 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 6630 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 6631 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 6632 6633 /* CPU: FDI_TX */ 6634 #define _FDI_TXA_CTL 0x60100 6635 #define _FDI_TXB_CTL 0x61100 6636 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 6637 #define FDI_TX_DISABLE (0<<31) 6638 #define FDI_TX_ENABLE (1<<31) 6639 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 6640 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 6641 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 6642 #define FDI_LINK_TRAIN_NONE (3<<28) 6643 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 6644 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 6645 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 6646 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 6647 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 6648 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 6649 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 6650 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 6651 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 6652 SNB has different settings. */ 6653 /* SNB A-stepping */ 6654 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 6655 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 6656 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 6657 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 6658 /* SNB B-stepping */ 6659 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 6660 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 6661 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 6662 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 6663 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 6664 #define FDI_DP_PORT_WIDTH_SHIFT 19 6665 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 6666 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 6667 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 6668 /* Ironlake: hardwired to 1 */ 6669 #define FDI_TX_PLL_ENABLE (1<<14) 6670 6671 /* Ivybridge has different bits for lolz */ 6672 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 6673 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 6674 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 6675 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 6676 6677 /* both Tx and Rx */ 6678 #define FDI_COMPOSITE_SYNC (1<<11) 6679 #define FDI_LINK_TRAIN_AUTO (1<<10) 6680 #define FDI_SCRAMBLING_ENABLE (0<<7) 6681 #define FDI_SCRAMBLING_DISABLE (1<<7) 6682 6683 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 6684 #define _FDI_RXA_CTL 0xf000c 6685 #define _FDI_RXB_CTL 0xf100c 6686 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 6687 #define FDI_RX_ENABLE (1<<31) 6688 /* train, dp width same as FDI_TX */ 6689 #define FDI_FS_ERRC_ENABLE (1<<27) 6690 #define FDI_FE_ERRC_ENABLE (1<<26) 6691 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 6692 #define FDI_8BPC (0<<16) 6693 #define FDI_10BPC (1<<16) 6694 #define FDI_6BPC (2<<16) 6695 #define FDI_12BPC (3<<16) 6696 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) 6697 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 6698 #define FDI_RX_PLL_ENABLE (1<<13) 6699 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 6700 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 6701 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 6702 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 6703 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 6704 #define FDI_PCDCLK (1<<4) 6705 /* CPT */ 6706 #define FDI_AUTO_TRAINING (1<<10) 6707 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 6708 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 6709 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 6710 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 6711 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 6712 6713 #define _FDI_RXA_MISC 0xf0010 6714 #define _FDI_RXB_MISC 0xf1010 6715 #define FDI_RX_PWRDN_LANE1_MASK (3<<26) 6716 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 6717 #define FDI_RX_PWRDN_LANE0_MASK (3<<24) 6718 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 6719 #define FDI_RX_TP1_TO_TP2_48 (2<<20) 6720 #define FDI_RX_TP1_TO_TP2_64 (3<<20) 6721 #define FDI_RX_FDI_DELAY_90 (0x90<<0) 6722 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 6723 6724 #define _FDI_RXA_TUSIZE1 0xf0030 6725 #define _FDI_RXA_TUSIZE2 0xf0038 6726 #define _FDI_RXB_TUSIZE1 0xf1030 6727 #define _FDI_RXB_TUSIZE2 0xf1038 6728 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 6729 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 6730 6731 /* FDI_RX interrupt register format */ 6732 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 6733 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 6734 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 6735 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 6736 #define FDI_RX_FS_CODE_ERR (1<<6) 6737 #define FDI_RX_FE_CODE_ERR (1<<5) 6738 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 6739 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 6740 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 6741 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 6742 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 6743 6744 #define _FDI_RXA_IIR 0xf0014 6745 #define _FDI_RXA_IMR 0xf0018 6746 #define _FDI_RXB_IIR 0xf1014 6747 #define _FDI_RXB_IMR 0xf1018 6748 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 6749 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 6750 6751 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 6752 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 6753 6754 #define PCH_LVDS _MMIO(0xe1180) 6755 #define LVDS_DETECTED (1 << 1) 6756 6757 /* vlv has 2 sets of panel control regs. */ 6758 #define _PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) 6759 #define _PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) 6760 #define _PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) 6761 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) 6762 #define _PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) 6763 #define _PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) 6764 6765 #define _PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) 6766 #define _PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) 6767 #define _PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) 6768 #define _PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) 6769 #define _PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) 6770 6771 #define VLV_PIPE_PP_STATUS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS) 6772 #define VLV_PIPE_PP_CONTROL(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL) 6773 #define VLV_PIPE_PP_ON_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS) 6774 #define VLV_PIPE_PP_OFF_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS) 6775 #define VLV_PIPE_PP_DIVISOR(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR) 6776 6777 #define _PCH_PP_STATUS 0xc7200 6778 #define _PCH_PP_CONTROL 0xc7204 6779 #define PANEL_UNLOCK_REGS (0xabcd << 16) 6780 #define PANEL_UNLOCK_MASK (0xffff << 16) 6781 #define BXT_POWER_CYCLE_DELAY_MASK (0x1f0) 6782 #define BXT_POWER_CYCLE_DELAY_SHIFT 4 6783 #define EDP_FORCE_VDD (1 << 3) 6784 #define EDP_BLC_ENABLE (1 << 2) 6785 #define PANEL_POWER_RESET (1 << 1) 6786 #define PANEL_POWER_OFF (0 << 0) 6787 #define PANEL_POWER_ON (1 << 0) 6788 #define _PCH_PP_ON_DELAYS 0xc7208 6789 #define PANEL_PORT_SELECT_MASK (3 << 30) 6790 #define PANEL_PORT_SELECT_LVDS (0 << 30) 6791 #define PANEL_PORT_SELECT_DPA (1 << 30) 6792 #define PANEL_PORT_SELECT_DPC (2 << 30) 6793 #define PANEL_PORT_SELECT_DPD (3 << 30) 6794 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 6795 #define PANEL_POWER_UP_DELAY_SHIFT 16 6796 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 6797 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 6798 6799 #define _PCH_PP_OFF_DELAYS 0xc720c 6800 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 6801 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 6802 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 6803 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 6804 6805 #define _PCH_PP_DIVISOR 0xc7210 6806 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 6807 #define PP_REFERENCE_DIVIDER_SHIFT 8 6808 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 6809 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 6810 6811 #define PCH_PP_STATUS _MMIO(_PCH_PP_STATUS) 6812 #define PCH_PP_CONTROL _MMIO(_PCH_PP_CONTROL) 6813 #define PCH_PP_ON_DELAYS _MMIO(_PCH_PP_ON_DELAYS) 6814 #define PCH_PP_OFF_DELAYS _MMIO(_PCH_PP_OFF_DELAYS) 6815 #define PCH_PP_DIVISOR _MMIO(_PCH_PP_DIVISOR) 6816 6817 /* BXT PPS changes - 2nd set of PPS registers */ 6818 #define _BXT_PP_STATUS2 0xc7300 6819 #define _BXT_PP_CONTROL2 0xc7304 6820 #define _BXT_PP_ON_DELAYS2 0xc7308 6821 #define _BXT_PP_OFF_DELAYS2 0xc730c 6822 6823 #define BXT_PP_STATUS(n) _MMIO_PIPE(n, _PCH_PP_STATUS, _BXT_PP_STATUS2) 6824 #define BXT_PP_CONTROL(n) _MMIO_PIPE(n, _PCH_PP_CONTROL, _BXT_PP_CONTROL2) 6825 #define BXT_PP_ON_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2) 6826 #define BXT_PP_OFF_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2) 6827 6828 #define _PCH_DP_B 0xe4100 6829 #define PCH_DP_B _MMIO(_PCH_DP_B) 6830 #define _PCH_DPB_AUX_CH_CTL 0xe4110 6831 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 6832 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 6833 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 6834 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 6835 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 6836 6837 #define _PCH_DP_C 0xe4200 6838 #define PCH_DP_C _MMIO(_PCH_DP_C) 6839 #define _PCH_DPC_AUX_CH_CTL 0xe4210 6840 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 6841 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 6842 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 6843 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 6844 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 6845 6846 #define _PCH_DP_D 0xe4300 6847 #define PCH_DP_D _MMIO(_PCH_DP_D) 6848 #define _PCH_DPD_AUX_CH_CTL 0xe4310 6849 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 6850 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 6851 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 6852 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 6853 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 6854 6855 #define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 6856 #define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 6857 6858 /* CPT */ 6859 #define PORT_TRANS_A_SEL_CPT 0 6860 #define PORT_TRANS_B_SEL_CPT (1<<29) 6861 #define PORT_TRANS_C_SEL_CPT (2<<29) 6862 #define PORT_TRANS_SEL_MASK (3<<29) 6863 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 6864 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 6865 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 6866 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) 6867 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) 6868 6869 #define _TRANS_DP_CTL_A 0xe0300 6870 #define _TRANS_DP_CTL_B 0xe1300 6871 #define _TRANS_DP_CTL_C 0xe2300 6872 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 6873 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 6874 #define TRANS_DP_PORT_SEL_B (0<<29) 6875 #define TRANS_DP_PORT_SEL_C (1<<29) 6876 #define TRANS_DP_PORT_SEL_D (2<<29) 6877 #define TRANS_DP_PORT_SEL_NONE (3<<29) 6878 #define TRANS_DP_PORT_SEL_MASK (3<<29) 6879 #define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B) 6880 #define TRANS_DP_AUDIO_ONLY (1<<26) 6881 #define TRANS_DP_ENH_FRAMING (1<<18) 6882 #define TRANS_DP_8BPC (0<<9) 6883 #define TRANS_DP_10BPC (1<<9) 6884 #define TRANS_DP_6BPC (2<<9) 6885 #define TRANS_DP_12BPC (3<<9) 6886 #define TRANS_DP_BPC_MASK (3<<9) 6887 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 6888 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 6889 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 6890 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 6891 #define TRANS_DP_SYNC_MASK (3<<3) 6892 6893 /* SNB eDP training params */ 6894 /* SNB A-stepping */ 6895 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 6896 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 6897 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 6898 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 6899 /* SNB B-stepping */ 6900 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 6901 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 6902 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 6903 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 6904 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 6905 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 6906 6907 /* IVB */ 6908 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 6909 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 6910 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 6911 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 6912 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 6913 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 6914 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) 6915 6916 /* legacy values */ 6917 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 6918 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 6919 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 6920 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 6921 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 6922 6923 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 6924 6925 #define VLV_PMWGICZ _MMIO(0x1300a4) 6926 6927 #define RC6_LOCATION _MMIO(0xD40) 6928 #define RC6_CTX_IN_DRAM (1 << 0) 6929 #define RC6_CTX_BASE _MMIO(0xD48) 6930 #define RC6_CTX_BASE_MASK 0xFFFFFFF0 6931 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) 6932 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) 6933 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) 6934 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) 6935 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) 6936 #define IDLE_TIME_MASK 0xFFFFF 6937 #define FORCEWAKE _MMIO(0xA18C) 6938 #define FORCEWAKE_VLV _MMIO(0x1300b0) 6939 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 6940 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 6941 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 6942 #define FORCEWAKE_ACK_HSW _MMIO(0x130044) 6943 #define FORCEWAKE_ACK _MMIO(0x130090) 6944 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 6945 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 6946 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 6947 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 6948 6949 #define VLV_GTLC_PW_STATUS _MMIO(0x130094) 6950 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 6951 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 6952 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 6953 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 6954 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 6955 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 6956 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 6957 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) 6958 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) 6959 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) 6960 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) 6961 #define FORCEWAKE_KERNEL 0x1 6962 #define FORCEWAKE_USER 0x2 6963 #define FORCEWAKE_MT_ACK _MMIO(0x130040) 6964 #define ECOBUS _MMIO(0xa180) 6965 #define FORCEWAKE_MT_ENABLE (1<<5) 6966 #define VLV_SPAREG2H _MMIO(0xA194) 6967 6968 #define GTFIFODBG _MMIO(0x120000) 6969 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) 6970 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) 6971 #define GT_FIFO_SBDROPERR (1<<6) 6972 #define GT_FIFO_BLOBDROPERR (1<<5) 6973 #define GT_FIFO_SB_READ_ABORTERR (1<<4) 6974 #define GT_FIFO_DROPERR (1<<3) 6975 #define GT_FIFO_OVFERR (1<<2) 6976 #define GT_FIFO_IAWRERR (1<<1) 6977 #define GT_FIFO_IARDERR (1<<0) 6978 6979 #define GTFIFOCTL _MMIO(0x120008) 6980 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 6981 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 6982 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 6983 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 6984 6985 #define HSW_IDICR _MMIO(0x9008) 6986 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 6987 #define HSW_EDRAM_CAP _MMIO(0x120010) 6988 #define EDRAM_ENABLED 0x1 6989 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 6990 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 6991 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 6992 6993 #define GEN6_UCGCTL1 _MMIO(0x9400) 6994 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) 6995 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 6996 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 6997 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 6998 6999 #define GEN6_UCGCTL2 _MMIO(0x9404) 7000 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 7001 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 7002 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 7003 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 7004 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 7005 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 7006 7007 #define GEN6_UCGCTL3 _MMIO(0x9408) 7008 7009 #define GEN7_UCGCTL4 _MMIO(0x940c) 7010 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 7011 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14) 7012 7013 #define GEN6_RCGCTL1 _MMIO(0x9410) 7014 #define GEN6_RCGCTL2 _MMIO(0x9414) 7015 #define GEN6_RSTCTL _MMIO(0x9420) 7016 7017 #define GEN8_UCGCTL6 _MMIO(0x9430) 7018 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) 7019 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) 7020 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28) 7021 7022 #define GEN6_GFXPAUSE _MMIO(0xA000) 7023 #define GEN6_RPNSWREQ _MMIO(0xA008) 7024 #define GEN6_TURBO_DISABLE (1<<31) 7025 #define GEN6_FREQUENCY(x) ((x)<<25) 7026 #define HSW_FREQUENCY(x) ((x)<<24) 7027 #define GEN9_FREQUENCY(x) ((x)<<23) 7028 #define GEN6_OFFSET(x) ((x)<<19) 7029 #define GEN6_AGGRESSIVE_TURBO (0<<15) 7030 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) 7031 #define GEN6_RC_CONTROL _MMIO(0xA090) 7032 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 7033 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 7034 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 7035 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 7036 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 7037 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) 7038 #define GEN7_RC_CTL_TO_MODE (1<<28) 7039 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 7040 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 7041 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) 7042 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) 7043 #define GEN6_RPSTAT1 _MMIO(0xA01C) 7044 #define GEN6_CAGF_SHIFT 8 7045 #define HSW_CAGF_SHIFT 7 7046 #define GEN9_CAGF_SHIFT 23 7047 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 7048 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 7049 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) 7050 #define GEN6_RP_CONTROL _MMIO(0xA024) 7051 #define GEN6_RP_MEDIA_TURBO (1<<11) 7052 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 7053 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 7054 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 7055 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 7056 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 7057 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 7058 #define GEN6_RP_ENABLE (1<<7) 7059 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 7060 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 7061 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 7062 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) 7063 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 7064 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) 7065 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) 7066 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) 7067 #define GEN6_CURICONT_MASK 0xffffff 7068 #define GEN6_RP_CUR_UP _MMIO(0xA054) 7069 #define GEN6_CURBSYTAVG_MASK 0xffffff 7070 #define GEN6_RP_PREV_UP _MMIO(0xA058) 7071 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) 7072 #define GEN6_CURIAVG_MASK 0xffffff 7073 #define GEN6_RP_CUR_DOWN _MMIO(0xA060) 7074 #define GEN6_RP_PREV_DOWN _MMIO(0xA064) 7075 #define GEN6_RP_UP_EI _MMIO(0xA068) 7076 #define GEN6_RP_DOWN_EI _MMIO(0xA06C) 7077 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) 7078 #define GEN6_RPDEUHWTC _MMIO(0xA080) 7079 #define GEN6_RPDEUC _MMIO(0xA084) 7080 #define GEN6_RPDEUCSW _MMIO(0xA088) 7081 #define GEN6_RC_STATE _MMIO(0xA094) 7082 #define RC_SW_TARGET_STATE_SHIFT 16 7083 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) 7084 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) 7085 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) 7086 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) 7087 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) 7088 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) 7089 #define GEN6_RC_SLEEP _MMIO(0xA0B0) 7090 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) 7091 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) 7092 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) 7093 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) 7094 #define VLV_RCEDATA _MMIO(0xA0BC) 7095 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) 7096 #define GEN6_PMINTRMSK _MMIO(0xA168) 7097 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) 7098 #define GEN8_MISC_CTRL0 _MMIO(0xA180) 7099 #define VLV_PWRDWNUPCTL _MMIO(0xA294) 7100 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) 7101 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) 7102 #define GEN9_PG_ENABLE _MMIO(0xA210) 7103 #define GEN9_RENDER_PG_ENABLE (1<<0) 7104 #define GEN9_MEDIA_PG_ENABLE (1<<1) 7105 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248) 7106 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250) 7107 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C) 7108 7109 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 7110 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 7111 #define PIXEL_OVERLAP_CNT_SHIFT 30 7112 7113 #define GEN6_PMISR _MMIO(0x44020) 7114 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 7115 #define GEN6_PMIIR _MMIO(0x44028) 7116 #define GEN6_PMIER _MMIO(0x4402C) 7117 #define GEN6_PM_MBOX_EVENT (1<<25) 7118 #define GEN6_PM_THERMAL_EVENT (1<<24) 7119 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 7120 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 7121 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 7122 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 7123 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 7124 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 7125 GEN6_PM_RP_DOWN_THRESHOLD | \ 7126 GEN6_PM_RP_DOWN_TIMEOUT) 7127 7128 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) 7129 #define GEN7_GT_SCRATCH_REG_NUM 8 7130 7131 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 7132 #define VLV_GFX_CLK_STATUS_BIT (1<<3) 7133 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) 7134 7135 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 7136 #define VLV_COUNTER_CONTROL _MMIO(0x138104) 7137 #define VLV_COUNT_RANGE_HIGH (1<<15) 7138 #define VLV_MEDIA_RC0_COUNT_EN (1<<5) 7139 #define VLV_RENDER_RC0_COUNT_EN (1<<4) 7140 #define VLV_MEDIA_RC6_COUNT_EN (1<<1) 7141 #define VLV_RENDER_RC6_COUNT_EN (1<<0) 7142 #define GEN6_GT_GFX_RC6 _MMIO(0x138108) 7143 #define VLV_GT_RENDER_RC6 _MMIO(0x138108) 7144 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) 7145 7146 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) 7147 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 7148 #define VLV_RENDER_C0_COUNT _MMIO(0x138118) 7149 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) 7150 7151 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 7152 #define GEN6_PCODE_READY (1<<31) 7153 #define GEN6_PCODE_ERROR_MASK 0xFF 7154 #define GEN6_PCODE_SUCCESS 0x0 7155 #define GEN6_PCODE_ILLEGAL_CMD 0x1 7156 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 7157 #define GEN6_PCODE_TIMEOUT 0x3 7158 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 7159 #define GEN7_PCODE_TIMEOUT 0x2 7160 #define GEN7_PCODE_ILLEGAL_DATA 0x3 7161 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 7162 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 7163 #define GEN6_PCODE_READ_RC6VIDS 0x5 7164 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 7165 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 7166 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 7167 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 7168 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 7169 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 7170 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 7171 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 7172 #define SKL_PCODE_CDCLK_CONTROL 0x7 7173 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 7174 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 7175 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 7176 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 7177 #define GEN6_READ_OC_PARAMS 0xc 7178 #define GEN6_PCODE_READ_D_COMP 0x10 7179 #define GEN6_PCODE_WRITE_D_COMP 0x11 7180 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 7181 #define DISPLAY_IPS_CONTROL 0x19 7182 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 7183 #define GEN9_PCODE_SAGV_CONTROL 0x21 7184 #define GEN9_SAGV_DISABLE 0x0 7185 #define GEN9_SAGV_IS_DISABLED 0x1 7186 #define GEN9_SAGV_ENABLE 0x3 7187 #define GEN6_PCODE_DATA _MMIO(0x138128) 7188 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 7189 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 7190 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 7191 7192 #define GEN6_GT_CORE_STATUS _MMIO(0x138060) 7193 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 7194 #define GEN6_RCn_MASK 7 7195 #define GEN6_RC0 0 7196 #define GEN6_RC3 2 7197 #define GEN6_RC6 3 7198 #define GEN6_RC7 4 7199 7200 #define GEN8_GT_SLICE_INFO _MMIO(0x138064) 7201 #define GEN8_LSLICESTAT_MASK 0x7 7202 7203 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 7204 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 7205 #define CHV_SS_PG_ENABLE (1<<1) 7206 #define CHV_EU08_PG_ENABLE (1<<9) 7207 #define CHV_EU19_PG_ENABLE (1<<17) 7208 #define CHV_EU210_PG_ENABLE (1<<25) 7209 7210 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 7211 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 7212 #define CHV_EU311_PG_ENABLE (1<<1) 7213 7214 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4) 7215 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 7216 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2)) 7217 7218 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8) 7219 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8) 7220 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 7221 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 7222 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 7223 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 7224 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 7225 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 7226 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 7227 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 7228 7229 #define GEN7_MISCCPCTL _MMIO(0x9424) 7230 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 7231 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2) 7232 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4) 7233 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6) 7234 7235 #define GEN8_GARBCNTL _MMIO(0xB004) 7236 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7) 7237 7238 /* IVYBRIDGE DPF */ 7239 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 7240 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 7241 #define GEN7_PARITY_ERROR_VALID (1<<13) 7242 #define GEN7_L3CDERRST1_BANK_MASK (3<<11) 7243 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 7244 #define GEN7_PARITY_ERROR_ROW(reg) \ 7245 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 7246 #define GEN7_PARITY_ERROR_BANK(reg) \ 7247 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 7248 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 7249 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 7250 #define GEN7_L3CDERRST1_ENABLE (1<<7) 7251 7252 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) 7253 #define GEN7_L3LOG_SIZE 0x80 7254 7255 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 7256 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) 7257 #define GEN7_MAX_PS_THREAD_DEP (8<<12) 7258 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) 7259 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) 7260 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 7261 7262 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) 7263 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) 7264 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3) 7265 7266 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) 7267 #define FLOW_CONTROL_ENABLE (1<<15) 7268 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) 7269 #define STALL_DOP_GATING_DISABLE (1<<5) 7270 7271 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 7272 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 7273 #define DOP_CLOCK_GATING_DISABLE (1<<0) 7274 7275 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 7276 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 7277 7278 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) 7279 #define GEN8_ST_PO_DISABLE (1<<13) 7280 7281 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) 7282 #define HSW_SAMPLE_C_PERFORMANCE (1<<9) 7283 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 7284 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) 7285 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 7286 7287 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) 7288 #define GEN9_ENABLE_YV12_BUGFIX (1<<4) 7289 #define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2) 7290 7291 /* Audio */ 7292 #define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020) 7293 #define INTEL_AUDIO_DEVCL 0x808629FB 7294 #define INTEL_AUDIO_DEVBLC 0x80862801 7295 #define INTEL_AUDIO_DEVCTG 0x80862802 7296 7297 #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 7298 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 7299 #define G4X_ELDV_DEVCTG (1 << 14) 7300 #define G4X_ELD_ADDR_MASK (0xf << 5) 7301 #define G4X_ELD_ACK (1 << 4) 7302 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 7303 7304 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 7305 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 7306 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 7307 _IBX_HDMIW_HDMIEDID_B) 7308 #define _IBX_AUD_CNTL_ST_A 0xE20B4 7309 #define _IBX_AUD_CNTL_ST_B 0xE21B4 7310 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 7311 _IBX_AUD_CNTL_ST_B) 7312 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 7313 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 7314 #define IBX_ELD_ACK (1 << 4) 7315 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 7316 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 7317 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 7318 7319 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 7320 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 7321 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 7322 #define _CPT_AUD_CNTL_ST_A 0xE50B4 7323 #define _CPT_AUD_CNTL_ST_B 0xE51B4 7324 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 7325 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 7326 7327 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 7328 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 7329 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 7330 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 7331 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 7332 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 7333 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 7334 7335 /* These are the 4 32-bit write offset registers for each stream 7336 * output buffer. It determines the offset from the 7337 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 7338 */ 7339 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 7340 7341 #define _IBX_AUD_CONFIG_A 0xe2000 7342 #define _IBX_AUD_CONFIG_B 0xe2100 7343 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 7344 #define _CPT_AUD_CONFIG_A 0xe5000 7345 #define _CPT_AUD_CONFIG_B 0xe5100 7346 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 7347 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 7348 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 7349 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 7350 7351 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 7352 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 7353 #define AUD_CONFIG_UPPER_N_SHIFT 20 7354 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 7355 #define AUD_CONFIG_LOWER_N_SHIFT 4 7356 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 7357 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 7358 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 7359 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 7360 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 7361 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 7362 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 7363 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 7364 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 7365 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 7366 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 7367 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 7368 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 7369 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 7370 7371 /* HSW Audio */ 7372 #define _HSW_AUD_CONFIG_A 0x65000 7373 #define _HSW_AUD_CONFIG_B 0x65100 7374 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 7375 7376 #define _HSW_AUD_MISC_CTRL_A 0x65010 7377 #define _HSW_AUD_MISC_CTRL_B 0x65110 7378 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 7379 7380 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 7381 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 7382 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 7383 7384 /* Audio Digital Converter */ 7385 #define _HSW_AUD_DIG_CNVT_1 0x65080 7386 #define _HSW_AUD_DIG_CNVT_2 0x65180 7387 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 7388 #define DIP_PORT_SEL_MASK 0x3 7389 7390 #define _HSW_AUD_EDID_DATA_A 0x65050 7391 #define _HSW_AUD_EDID_DATA_B 0x65150 7392 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 7393 7394 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 7395 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 7396 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 7397 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 7398 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 7399 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 7400 7401 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 7402 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 7403 7404 /* HSW Power Wells */ 7405 #define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */ 7406 #define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ 7407 #define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ 7408 #define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ 7409 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) 7410 #define HSW_PWR_WELL_STATE_ENABLED (1<<30) 7411 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 7412 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 7413 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 7414 #define HSW_PWR_WELL_FORCE_ON (1<<19) 7415 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 7416 7417 /* SKL Fuse Status */ 7418 #define SKL_FUSE_STATUS _MMIO(0x42000) 7419 #define SKL_FUSE_DOWNLOAD_STATUS (1<<31) 7420 #define SKL_FUSE_PG0_DIST_STATUS (1<<27) 7421 #define SKL_FUSE_PG1_DIST_STATUS (1<<26) 7422 #define SKL_FUSE_PG2_DIST_STATUS (1<<25) 7423 7424 /* Per-pipe DDI Function Control */ 7425 #define _TRANS_DDI_FUNC_CTL_A 0x60400 7426 #define _TRANS_DDI_FUNC_CTL_B 0x61400 7427 #define _TRANS_DDI_FUNC_CTL_C 0x62400 7428 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 7429 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 7430 7431 #define TRANS_DDI_FUNC_ENABLE (1<<31) 7432 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 7433 #define TRANS_DDI_PORT_MASK (7<<28) 7434 #define TRANS_DDI_PORT_SHIFT 28 7435 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) 7436 #define TRANS_DDI_PORT_NONE (0<<28) 7437 #define TRANS_DDI_MODE_SELECT_MASK (7<<24) 7438 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 7439 #define TRANS_DDI_MODE_SELECT_DVI (1<<24) 7440 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 7441 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 7442 #define TRANS_DDI_MODE_SELECT_FDI (4<<24) 7443 #define TRANS_DDI_BPC_MASK (7<<20) 7444 #define TRANS_DDI_BPC_8 (0<<20) 7445 #define TRANS_DDI_BPC_10 (1<<20) 7446 #define TRANS_DDI_BPC_6 (2<<20) 7447 #define TRANS_DDI_BPC_12 (3<<20) 7448 #define TRANS_DDI_PVSYNC (1<<17) 7449 #define TRANS_DDI_PHSYNC (1<<16) 7450 #define TRANS_DDI_EDP_INPUT_MASK (7<<12) 7451 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 7452 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 7453 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 7454 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 7455 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) 7456 #define TRANS_DDI_BFI_ENABLE (1<<4) 7457 7458 /* DisplayPort Transport Control */ 7459 #define _DP_TP_CTL_A 0x64040 7460 #define _DP_TP_CTL_B 0x64140 7461 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 7462 #define DP_TP_CTL_ENABLE (1<<31) 7463 #define DP_TP_CTL_MODE_SST (0<<27) 7464 #define DP_TP_CTL_MODE_MST (1<<27) 7465 #define DP_TP_CTL_FORCE_ACT (1<<25) 7466 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 7467 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 7468 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 7469 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 7470 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 7471 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 7472 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 7473 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 7474 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 7475 7476 /* DisplayPort Transport Status */ 7477 #define _DP_TP_STATUS_A 0x64044 7478 #define _DP_TP_STATUS_B 0x64144 7479 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 7480 #define DP_TP_STATUS_IDLE_DONE (1<<25) 7481 #define DP_TP_STATUS_ACT_SENT (1<<24) 7482 #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) 7483 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 7484 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 7485 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 7486 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 7487 7488 /* DDI Buffer Control */ 7489 #define _DDI_BUF_CTL_A 0x64000 7490 #define _DDI_BUF_CTL_B 0x64100 7491 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 7492 #define DDI_BUF_CTL_ENABLE (1<<31) 7493 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 7494 #define DDI_BUF_EMP_MASK (0xf<<24) 7495 #define DDI_BUF_PORT_REVERSAL (1<<16) 7496 #define DDI_BUF_IS_IDLE (1<<7) 7497 #define DDI_A_4_LANES (1<<4) 7498 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 7499 #define DDI_PORT_WIDTH_MASK (7 << 1) 7500 #define DDI_PORT_WIDTH_SHIFT 1 7501 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 7502 7503 /* DDI Buffer Translations */ 7504 #define _DDI_BUF_TRANS_A 0x64E00 7505 #define _DDI_BUF_TRANS_B 0x64E60 7506 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 7507 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 7508 7509 /* Sideband Interface (SBI) is programmed indirectly, via 7510 * SBI_ADDR, which contains the register offset; and SBI_DATA, 7511 * which contains the payload */ 7512 #define SBI_ADDR _MMIO(0xC6000) 7513 #define SBI_DATA _MMIO(0xC6004) 7514 #define SBI_CTL_STAT _MMIO(0xC6008) 7515 #define SBI_CTL_DEST_ICLK (0x0<<16) 7516 #define SBI_CTL_DEST_MPHY (0x1<<16) 7517 #define SBI_CTL_OP_IORD (0x2<<8) 7518 #define SBI_CTL_OP_IOWR (0x3<<8) 7519 #define SBI_CTL_OP_CRRD (0x6<<8) 7520 #define SBI_CTL_OP_CRWR (0x7<<8) 7521 #define SBI_RESPONSE_FAIL (0x1<<1) 7522 #define SBI_RESPONSE_SUCCESS (0x0<<1) 7523 #define SBI_BUSY (0x1<<0) 7524 #define SBI_READY (0x0<<0) 7525 7526 /* SBI offsets */ 7527 #define SBI_SSCDIVINTPHASE 0x0200 7528 #define SBI_SSCDIVINTPHASE6 0x0600 7529 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 7530 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1) 7531 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 7532 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 7533 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8) 7534 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 7535 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 7536 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 7537 #define SBI_SSCDITHPHASE 0x0204 7538 #define SBI_SSCCTL 0x020c 7539 #define SBI_SSCCTL6 0x060C 7540 #define SBI_SSCCTL_PATHALT (1<<3) 7541 #define SBI_SSCCTL_DISABLE (1<<0) 7542 #define SBI_SSCAUXDIV6 0x0610 7543 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 7544 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4) 7545 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 7546 #define SBI_DBUFF0 0x2a00 7547 #define SBI_GEN0 0x1f00 7548 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) 7549 7550 /* LPT PIXCLK_GATE */ 7551 #define PIXCLK_GATE _MMIO(0xC6020) 7552 #define PIXCLK_GATE_UNGATE (1<<0) 7553 #define PIXCLK_GATE_GATE (0<<0) 7554 7555 /* SPLL */ 7556 #define SPLL_CTL _MMIO(0x46020) 7557 #define SPLL_PLL_ENABLE (1<<31) 7558 #define SPLL_PLL_SSC (1<<28) 7559 #define SPLL_PLL_NON_SSC (2<<28) 7560 #define SPLL_PLL_LCPLL (3<<28) 7561 #define SPLL_PLL_REF_MASK (3<<28) 7562 #define SPLL_PLL_FREQ_810MHz (0<<26) 7563 #define SPLL_PLL_FREQ_1350MHz (1<<26) 7564 #define SPLL_PLL_FREQ_2700MHz (2<<26) 7565 #define SPLL_PLL_FREQ_MASK (3<<26) 7566 7567 /* WRPLL */ 7568 #define _WRPLL_CTL1 0x46040 7569 #define _WRPLL_CTL2 0x46060 7570 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 7571 #define WRPLL_PLL_ENABLE (1<<31) 7572 #define WRPLL_PLL_SSC (1<<28) 7573 #define WRPLL_PLL_NON_SSC (2<<28) 7574 #define WRPLL_PLL_LCPLL (3<<28) 7575 #define WRPLL_PLL_REF_MASK (3<<28) 7576 /* WRPLL divider programming */ 7577 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 7578 #define WRPLL_DIVIDER_REF_MASK (0xff) 7579 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 7580 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) 7581 #define WRPLL_DIVIDER_POST_SHIFT 8 7582 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 7583 #define WRPLL_DIVIDER_FB_SHIFT 16 7584 #define WRPLL_DIVIDER_FB_MASK (0xff<<16) 7585 7586 /* Port clock selection */ 7587 #define _PORT_CLK_SEL_A 0x46100 7588 #define _PORT_CLK_SEL_B 0x46104 7589 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 7590 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 7591 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 7592 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 7593 #define PORT_CLK_SEL_SPLL (3<<29) 7594 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) 7595 #define PORT_CLK_SEL_WRPLL1 (4<<29) 7596 #define PORT_CLK_SEL_WRPLL2 (5<<29) 7597 #define PORT_CLK_SEL_NONE (7<<29) 7598 #define PORT_CLK_SEL_MASK (7<<29) 7599 7600 /* Transcoder clock selection */ 7601 #define _TRANS_CLK_SEL_A 0x46140 7602 #define _TRANS_CLK_SEL_B 0x46144 7603 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 7604 /* For each transcoder, we need to select the corresponding port clock */ 7605 #define TRANS_CLK_SEL_DISABLED (0x0<<29) 7606 #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) 7607 7608 #define CDCLK_FREQ _MMIO(0x46200) 7609 7610 #define _TRANSA_MSA_MISC 0x60410 7611 #define _TRANSB_MSA_MISC 0x61410 7612 #define _TRANSC_MSA_MISC 0x62410 7613 #define _TRANS_EDP_MSA_MISC 0x6f410 7614 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 7615 7616 #define TRANS_MSA_SYNC_CLK (1<<0) 7617 #define TRANS_MSA_6_BPC (0<<5) 7618 #define TRANS_MSA_8_BPC (1<<5) 7619 #define TRANS_MSA_10_BPC (2<<5) 7620 #define TRANS_MSA_12_BPC (3<<5) 7621 #define TRANS_MSA_16_BPC (4<<5) 7622 7623 /* LCPLL Control */ 7624 #define LCPLL_CTL _MMIO(0x130040) 7625 #define LCPLL_PLL_DISABLE (1<<31) 7626 #define LCPLL_PLL_LOCK (1<<30) 7627 #define LCPLL_CLK_FREQ_MASK (3<<26) 7628 #define LCPLL_CLK_FREQ_450 (0<<26) 7629 #define LCPLL_CLK_FREQ_54O_BDW (1<<26) 7630 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) 7631 #define LCPLL_CLK_FREQ_675_BDW (3<<26) 7632 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 7633 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24) 7634 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 7635 #define LCPLL_POWER_DOWN_ALLOW (1<<22) 7636 #define LCPLL_CD_SOURCE_FCLK (1<<21) 7637 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) 7638 7639 /* 7640 * SKL Clocks 7641 */ 7642 7643 /* CDCLK_CTL */ 7644 #define CDCLK_CTL _MMIO(0x46000) 7645 #define CDCLK_FREQ_SEL_MASK (3<<26) 7646 #define CDCLK_FREQ_450_432 (0<<26) 7647 #define CDCLK_FREQ_540 (1<<26) 7648 #define CDCLK_FREQ_337_308 (2<<26) 7649 #define CDCLK_FREQ_675_617 (3<<26) 7650 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22) 7651 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22) 7652 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22) 7653 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) 7654 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) 7655 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20) 7656 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 7657 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) 7658 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 7659 7660 /* LCPLL_CTL */ 7661 #define LCPLL1_CTL _MMIO(0x46010) 7662 #define LCPLL2_CTL _MMIO(0x46014) 7663 #define LCPLL_PLL_ENABLE (1<<31) 7664 7665 /* DPLL control1 */ 7666 #define DPLL_CTRL1 _MMIO(0x6C058) 7667 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) 7668 #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) 7669 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) 7670 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1) 7671 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) 7672 #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) 7673 #define DPLL_CTRL1_LINK_RATE_2700 0 7674 #define DPLL_CTRL1_LINK_RATE_1350 1 7675 #define DPLL_CTRL1_LINK_RATE_810 2 7676 #define DPLL_CTRL1_LINK_RATE_1620 3 7677 #define DPLL_CTRL1_LINK_RATE_1080 4 7678 #define DPLL_CTRL1_LINK_RATE_2160 5 7679 7680 /* DPLL control2 */ 7681 #define DPLL_CTRL2 _MMIO(0x6C05C) 7682 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15)) 7683 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) 7684 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) 7685 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1)) 7686 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) 7687 7688 /* DPLL Status */ 7689 #define DPLL_STATUS _MMIO(0x6C060) 7690 #define DPLL_LOCK(id) (1<<((id)*8)) 7691 7692 /* DPLL cfg */ 7693 #define _DPLL1_CFGCR1 0x6C040 7694 #define _DPLL2_CFGCR1 0x6C048 7695 #define _DPLL3_CFGCR1 0x6C050 7696 #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) 7697 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) 7698 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9) 7699 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 7700 7701 #define _DPLL1_CFGCR2 0x6C044 7702 #define _DPLL2_CFGCR2 0x6C04C 7703 #define _DPLL3_CFGCR2 0x6C054 7704 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) 7705 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8) 7706 #define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7) 7707 #define DPLL_CFGCR2_KDIV_MASK (3<<5) 7708 #define DPLL_CFGCR2_KDIV(x) ((x)<<5) 7709 #define DPLL_CFGCR2_KDIV_5 (0<<5) 7710 #define DPLL_CFGCR2_KDIV_2 (1<<5) 7711 #define DPLL_CFGCR2_KDIV_3 (2<<5) 7712 #define DPLL_CFGCR2_KDIV_1 (3<<5) 7713 #define DPLL_CFGCR2_PDIV_MASK (7<<2) 7714 #define DPLL_CFGCR2_PDIV(x) ((x)<<2) 7715 #define DPLL_CFGCR2_PDIV_1 (0<<2) 7716 #define DPLL_CFGCR2_PDIV_2 (1<<2) 7717 #define DPLL_CFGCR2_PDIV_3 (2<<2) 7718 #define DPLL_CFGCR2_PDIV_7 (4<<2) 7719 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 7720 7721 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 7722 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 7723 7724 /* BXT display engine PLL */ 7725 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 7726 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 7727 #define BXT_DE_PLL_RATIO_MASK 0xff 7728 7729 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 7730 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 7731 #define BXT_DE_PLL_LOCK (1 << 30) 7732 7733 /* GEN9 DC */ 7734 #define DC_STATE_EN _MMIO(0x45504) 7735 #define DC_STATE_DISABLE 0 7736 #define DC_STATE_EN_UPTO_DC5 (1<<0) 7737 #define DC_STATE_EN_DC9 (1<<3) 7738 #define DC_STATE_EN_UPTO_DC6 (2<<0) 7739 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 7740 7741 #define DC_STATE_DEBUG _MMIO(0x45520) 7742 #define DC_STATE_DEBUG_MASK_CORES (1<<0) 7743 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) 7744 7745 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 7746 * since on HSW we can't write to it using I915_WRITE. */ 7747 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 7748 #define D_COMP_BDW _MMIO(0x138144) 7749 #define D_COMP_RCOMP_IN_PROGRESS (1<<9) 7750 #define D_COMP_COMP_FORCE (1<<8) 7751 #define D_COMP_COMP_DISABLE (1<<0) 7752 7753 /* Pipe WM_LINETIME - watermark line time */ 7754 #define _PIPE_WM_LINETIME_A 0x45270 7755 #define _PIPE_WM_LINETIME_B 0x45274 7756 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B) 7757 #define PIPE_WM_LINETIME_MASK (0x1ff) 7758 #define PIPE_WM_LINETIME_TIME(x) ((x)) 7759 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 7760 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 7761 7762 /* SFUSE_STRAP */ 7763 #define SFUSE_STRAP _MMIO(0xc2014) 7764 #define SFUSE_STRAP_FUSE_LOCK (1<<13) 7765 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) 7766 #define SFUSE_STRAP_CRT_DISABLED (1<<6) 7767 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 7768 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 7769 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 7770 7771 #define WM_MISC _MMIO(0x45260) 7772 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 7773 7774 #define WM_DBG _MMIO(0x45280) 7775 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 7776 #define WM_DBG_DISALLOW_MAXFIFO (1<<1) 7777 #define WM_DBG_DISALLOW_SPRITE (1<<2) 7778 7779 /* pipe CSC */ 7780 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 7781 #define _PIPE_A_CSC_COEFF_BY 0x49014 7782 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 7783 #define _PIPE_A_CSC_COEFF_BU 0x4901c 7784 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 7785 #define _PIPE_A_CSC_COEFF_BV 0x49024 7786 #define _PIPE_A_CSC_MODE 0x49028 7787 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 7788 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 7789 #define CSC_MODE_YUV_TO_RGB (1 << 0) 7790 #define _PIPE_A_CSC_PREOFF_HI 0x49030 7791 #define _PIPE_A_CSC_PREOFF_ME 0x49034 7792 #define _PIPE_A_CSC_PREOFF_LO 0x49038 7793 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 7794 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 7795 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 7796 7797 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 7798 #define _PIPE_B_CSC_COEFF_BY 0x49114 7799 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 7800 #define _PIPE_B_CSC_COEFF_BU 0x4911c 7801 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 7802 #define _PIPE_B_CSC_COEFF_BV 0x49124 7803 #define _PIPE_B_CSC_MODE 0x49128 7804 #define _PIPE_B_CSC_PREOFF_HI 0x49130 7805 #define _PIPE_B_CSC_PREOFF_ME 0x49134 7806 #define _PIPE_B_CSC_PREOFF_LO 0x49138 7807 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 7808 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 7809 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 7810 7811 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 7812 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 7813 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 7814 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 7815 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 7816 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 7817 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 7818 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 7819 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 7820 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 7821 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 7822 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 7823 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 7824 7825 /* pipe degamma/gamma LUTs on IVB+ */ 7826 #define _PAL_PREC_INDEX_A 0x4A400 7827 #define _PAL_PREC_INDEX_B 0x4AC00 7828 #define _PAL_PREC_INDEX_C 0x4B400 7829 #define PAL_PREC_10_12_BIT (0 << 31) 7830 #define PAL_PREC_SPLIT_MODE (1 << 31) 7831 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 7832 #define _PAL_PREC_DATA_A 0x4A404 7833 #define _PAL_PREC_DATA_B 0x4AC04 7834 #define _PAL_PREC_DATA_C 0x4B404 7835 #define _PAL_PREC_GC_MAX_A 0x4A410 7836 #define _PAL_PREC_GC_MAX_B 0x4AC10 7837 #define _PAL_PREC_GC_MAX_C 0x4B410 7838 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 7839 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 7840 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 7841 7842 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 7843 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 7844 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 7845 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 7846 7847 /* pipe CSC & degamma/gamma LUTs on CHV */ 7848 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 7849 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 7850 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 7851 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 7852 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 7853 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 7854 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 7855 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 7856 #define CGM_PIPE_MODE_GAMMA (1 << 2) 7857 #define CGM_PIPE_MODE_CSC (1 << 1) 7858 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 7859 7860 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 7861 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 7862 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 7863 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 7864 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 7865 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 7866 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 7867 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 7868 7869 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 7870 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 7871 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 7872 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 7873 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 7874 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 7875 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 7876 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 7877 7878 /* MIPI DSI registers */ 7879 7880 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ 7881 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 7882 7883 /* BXT MIPI clock controls */ 7884 #define BXT_MAX_VAR_OUTPUT_KHZ 39500 7885 7886 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) 7887 #define BXT_MIPI1_DIV_SHIFT 26 7888 #define BXT_MIPI2_DIV_SHIFT 10 7889 #define BXT_MIPI_DIV_SHIFT(port) \ 7890 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ 7891 BXT_MIPI2_DIV_SHIFT) 7892 7893 /* TX control divider to select actual TX clock output from (8x/var) */ 7894 #define BXT_MIPI1_TX_ESCLK_SHIFT 26 7895 #define BXT_MIPI2_TX_ESCLK_SHIFT 10 7896 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \ 7897 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ 7898 BXT_MIPI2_TX_ESCLK_SHIFT) 7899 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) 7900 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) 7901 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ 7902 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ 7903 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) 7904 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ 7905 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) 7906 /* RX upper control divider to select actual RX clock output from 8x */ 7907 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 7908 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 7909 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ 7910 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ 7911 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) 7912 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) 7913 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) 7914 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ 7915 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ 7916 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) 7917 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ 7918 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) 7919 /* 8/3X divider to select the actual 8/3X clock output from 8x */ 7920 #define BXT_MIPI1_8X_BY3_SHIFT 19 7921 #define BXT_MIPI2_8X_BY3_SHIFT 3 7922 #define BXT_MIPI_8X_BY3_SHIFT(port) \ 7923 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ 7924 BXT_MIPI2_8X_BY3_SHIFT) 7925 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) 7926 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) 7927 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ 7928 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ 7929 BXT_MIPI2_8X_BY3_DIVIDER_MASK) 7930 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ 7931 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) 7932 /* RX lower control divider to select actual RX clock output from 8x */ 7933 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 7934 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 7935 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ 7936 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ 7937 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) 7938 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) 7939 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) 7940 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ 7941 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ 7942 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) 7943 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ 7944 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) 7945 7946 #define RX_DIVIDER_BIT_1_2 0x3 7947 #define RX_DIVIDER_BIT_3_4 0xC 7948 7949 /* BXT MIPI mode configure */ 7950 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 7951 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 7952 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 7953 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 7954 7955 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 7956 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 7957 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 7958 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 7959 7960 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 7961 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 7962 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 7963 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 7964 7965 #define BXT_DSI_PLL_CTL _MMIO(0x161000) 7966 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 7967 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 7968 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 7969 #define BXT_DSIC_16X_BY2 (1 << 10) 7970 #define BXT_DSIC_16X_BY3 (2 << 10) 7971 #define BXT_DSIC_16X_BY4 (3 << 10) 7972 #define BXT_DSIC_16X_MASK (3 << 10) 7973 #define BXT_DSIA_16X_BY2 (1 << 8) 7974 #define BXT_DSIA_16X_BY3 (2 << 8) 7975 #define BXT_DSIA_16X_BY4 (3 << 8) 7976 #define BXT_DSIA_16X_MASK (3 << 8) 7977 #define BXT_DSI_FREQ_SEL_SHIFT 8 7978 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) 7979 7980 #define BXT_DSI_PLL_RATIO_MAX 0x7D 7981 #define BXT_DSI_PLL_RATIO_MIN 0x22 7982 #define BXT_DSI_PLL_RATIO_MASK 0xFF 7983 #define BXT_REF_CLOCK_KHZ 19200 7984 7985 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) 7986 #define BXT_DSI_PLL_DO_ENABLE (1 << 31) 7987 #define BXT_DSI_PLL_LOCKED (1 << 30) 7988 7989 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 7990 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 7991 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 7992 7993 /* BXT port control */ 7994 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0 7995 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0 7996 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 7997 7998 #define DPI_ENABLE (1 << 31) /* A + C */ 7999 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 8000 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 8001 #define DUAL_LINK_MODE_SHIFT 26 8002 #define DUAL_LINK_MODE_MASK (1 << 26) 8003 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 8004 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 8005 #define DITHERING_ENABLE (1 << 25) /* A + C */ 8006 #define FLOPPED_HSTX (1 << 23) 8007 #define DE_INVERT (1 << 19) /* XXX */ 8008 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 8009 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 8010 #define AFE_LATCHOUT (1 << 17) 8011 #define LP_OUTPUT_HOLD (1 << 16) 8012 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 8013 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 8014 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 8015 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 8016 #define CSB_SHIFT 9 8017 #define CSB_MASK (3 << 9) 8018 #define CSB_20MHZ (0 << 9) 8019 #define CSB_10MHZ (1 << 9) 8020 #define CSB_40MHZ (2 << 9) 8021 #define BANDGAP_MASK (1 << 8) 8022 #define BANDGAP_PNW_CIRCUIT (0 << 8) 8023 #define BANDGAP_LNC_CIRCUIT (1 << 8) 8024 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 8025 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 8026 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 8027 #define TEARING_EFFECT_SHIFT 2 /* A + C */ 8028 #define TEARING_EFFECT_MASK (3 << 2) 8029 #define TEARING_EFFECT_OFF (0 << 2) 8030 #define TEARING_EFFECT_DSI (1 << 2) 8031 #define TEARING_EFFECT_GPIO (2 << 2) 8032 #define LANE_CONFIGURATION_SHIFT 0 8033 #define LANE_CONFIGURATION_MASK (3 << 0) 8034 #define LANE_CONFIGURATION_4LANE (0 << 0) 8035 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 8036 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 8037 8038 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 8039 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 8040 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 8041 #define TEARING_EFFECT_DELAY_SHIFT 0 8042 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 8043 8044 /* XXX: all bits reserved */ 8045 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 8046 8047 /* MIPI DSI Controller and D-PHY registers */ 8048 8049 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 8050 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 8051 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 8052 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 8053 #define ULPS_STATE_MASK (3 << 1) 8054 #define ULPS_STATE_ENTER (2 << 1) 8055 #define ULPS_STATE_EXIT (1 << 1) 8056 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 8057 #define DEVICE_READY (1 << 0) 8058 8059 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 8060 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 8061 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 8062 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 8063 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 8064 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 8065 #define TEARING_EFFECT (1 << 31) 8066 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 8067 #define GEN_READ_DATA_AVAIL (1 << 29) 8068 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 8069 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 8070 #define RX_PROT_VIOLATION (1 << 26) 8071 #define RX_INVALID_TX_LENGTH (1 << 25) 8072 #define ACK_WITH_NO_ERROR (1 << 24) 8073 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 8074 #define LP_RX_TIMEOUT (1 << 22) 8075 #define HS_TX_TIMEOUT (1 << 21) 8076 #define DPI_FIFO_UNDERRUN (1 << 20) 8077 #define LOW_CONTENTION (1 << 19) 8078 #define HIGH_CONTENTION (1 << 18) 8079 #define TXDSI_VC_ID_INVALID (1 << 17) 8080 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 8081 #define TXCHECKSUM_ERROR (1 << 15) 8082 #define TXECC_MULTIBIT_ERROR (1 << 14) 8083 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 8084 #define TXFALSE_CONTROL_ERROR (1 << 12) 8085 #define RXDSI_VC_ID_INVALID (1 << 11) 8086 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 8087 #define RXCHECKSUM_ERROR (1 << 9) 8088 #define RXECC_MULTIBIT_ERROR (1 << 8) 8089 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 8090 #define RXFALSE_CONTROL_ERROR (1 << 6) 8091 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 8092 #define RX_LP_TX_SYNC_ERROR (1 << 4) 8093 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 8094 #define RXEOT_SYNC_ERROR (1 << 2) 8095 #define RXSOT_SYNC_ERROR (1 << 1) 8096 #define RXSOT_ERROR (1 << 0) 8097 8098 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 8099 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 8100 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 8101 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 8102 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 8103 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 8104 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 8105 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 8106 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 8107 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 8108 #define VID_MODE_FORMAT_MASK (0xf << 7) 8109 #define VID_MODE_NOT_SUPPORTED (0 << 7) 8110 #define VID_MODE_FORMAT_RGB565 (1 << 7) 8111 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 8112 #define VID_MODE_FORMAT_RGB666 (3 << 7) 8113 #define VID_MODE_FORMAT_RGB888 (4 << 7) 8114 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 8115 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 8116 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 8117 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 8118 #define DATA_LANES_PRG_REG_SHIFT 0 8119 #define DATA_LANES_PRG_REG_MASK (7 << 0) 8120 8121 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 8122 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 8123 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 8124 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 8125 8126 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 8127 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 8128 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 8129 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 8130 8131 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 8132 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 8133 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 8134 #define TURN_AROUND_TIMEOUT_MASK 0x3f 8135 8136 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 8137 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 8138 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 8139 #define DEVICE_RESET_TIMER_MASK 0xffff 8140 8141 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 8142 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 8143 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 8144 #define VERTICAL_ADDRESS_SHIFT 16 8145 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 8146 #define HORIZONTAL_ADDRESS_SHIFT 0 8147 #define HORIZONTAL_ADDRESS_MASK 0xffff 8148 8149 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 8150 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 8151 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 8152 #define DBI_FIFO_EMPTY_HALF (0 << 0) 8153 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 8154 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 8155 8156 /* regs below are bits 15:0 */ 8157 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 8158 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 8159 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 8160 8161 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 8162 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 8163 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 8164 8165 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 8166 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 8167 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 8168 8169 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 8170 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 8171 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 8172 8173 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 8174 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 8175 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 8176 8177 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 8178 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 8179 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 8180 8181 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 8182 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 8183 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 8184 8185 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 8186 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 8187 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 8188 8189 /* regs above are bits 15:0 */ 8190 8191 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 8192 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 8193 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 8194 #define DPI_LP_MODE (1 << 6) 8195 #define BACKLIGHT_OFF (1 << 5) 8196 #define BACKLIGHT_ON (1 << 4) 8197 #define COLOR_MODE_OFF (1 << 3) 8198 #define COLOR_MODE_ON (1 << 2) 8199 #define TURN_ON (1 << 1) 8200 #define SHUTDOWN (1 << 0) 8201 8202 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 8203 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 8204 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 8205 #define COMMAND_BYTE_SHIFT 0 8206 #define COMMAND_BYTE_MASK (0x3f << 0) 8207 8208 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 8209 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 8210 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 8211 #define MASTER_INIT_TIMER_SHIFT 0 8212 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 8213 8214 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 8215 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 8216 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 8217 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 8218 #define MAX_RETURN_PKT_SIZE_SHIFT 0 8219 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 8220 8221 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 8222 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 8223 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 8224 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 8225 #define DISABLE_VIDEO_BTA (1 << 3) 8226 #define IP_TG_CONFIG (1 << 2) 8227 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 8228 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 8229 #define VIDEO_MODE_BURST (3 << 0) 8230 8231 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 8232 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 8233 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 8234 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 8235 #define BXT_DPHY_DEFEATURE_EN (1 << 8) 8236 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 8237 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 8238 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 8239 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 8240 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 8241 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 8242 #define CLOCKSTOP (1 << 1) 8243 #define EOT_DISABLE (1 << 0) 8244 8245 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 8246 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 8247 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 8248 #define LP_BYTECLK_SHIFT 0 8249 #define LP_BYTECLK_MASK (0xffff << 0) 8250 8251 /* bits 31:0 */ 8252 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 8253 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 8254 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 8255 8256 /* bits 31:0 */ 8257 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 8258 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 8259 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 8260 8261 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 8262 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 8263 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 8264 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 8265 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 8266 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 8267 #define LONG_PACKET_WORD_COUNT_SHIFT 8 8268 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 8269 #define SHORT_PACKET_PARAM_SHIFT 8 8270 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 8271 #define VIRTUAL_CHANNEL_SHIFT 6 8272 #define VIRTUAL_CHANNEL_MASK (3 << 6) 8273 #define DATA_TYPE_SHIFT 0 8274 #define DATA_TYPE_MASK (0x3f << 0) 8275 /* data type values, see include/video/mipi_display.h */ 8276 8277 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 8278 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 8279 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 8280 #define DPI_FIFO_EMPTY (1 << 28) 8281 #define DBI_FIFO_EMPTY (1 << 27) 8282 #define LP_CTRL_FIFO_EMPTY (1 << 26) 8283 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 8284 #define LP_CTRL_FIFO_FULL (1 << 24) 8285 #define HS_CTRL_FIFO_EMPTY (1 << 18) 8286 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 8287 #define HS_CTRL_FIFO_FULL (1 << 16) 8288 #define LP_DATA_FIFO_EMPTY (1 << 10) 8289 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 8290 #define LP_DATA_FIFO_FULL (1 << 8) 8291 #define HS_DATA_FIFO_EMPTY (1 << 2) 8292 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 8293 #define HS_DATA_FIFO_FULL (1 << 0) 8294 8295 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 8296 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 8297 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 8298 #define DBI_HS_LP_MODE_MASK (1 << 0) 8299 #define DBI_LP_MODE (1 << 0) 8300 #define DBI_HS_MODE (0 << 0) 8301 8302 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 8303 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 8304 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 8305 #define EXIT_ZERO_COUNT_SHIFT 24 8306 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 8307 #define TRAIL_COUNT_SHIFT 16 8308 #define TRAIL_COUNT_MASK (0x1f << 16) 8309 #define CLK_ZERO_COUNT_SHIFT 8 8310 #define CLK_ZERO_COUNT_MASK (0xff << 8) 8311 #define PREPARE_COUNT_SHIFT 0 8312 #define PREPARE_COUNT_MASK (0x3f << 0) 8313 8314 /* bits 31:0 */ 8315 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 8316 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 8317 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 8318 8319 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 8320 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 8321 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 8322 #define LP_HS_SSW_CNT_SHIFT 16 8323 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 8324 #define HS_LP_PWR_SW_CNT_SHIFT 0 8325 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 8326 8327 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 8328 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 8329 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 8330 #define STOP_STATE_STALL_COUNTER_SHIFT 0 8331 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 8332 8333 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 8334 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 8335 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 8336 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 8337 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 8338 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 8339 #define RX_CONTENTION_DETECTED (1 << 0) 8340 8341 /* XXX: only pipe A ?!? */ 8342 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 8343 #define DBI_TYPEC_ENABLE (1 << 31) 8344 #define DBI_TYPEC_WIP (1 << 30) 8345 #define DBI_TYPEC_OPTION_SHIFT 28 8346 #define DBI_TYPEC_OPTION_MASK (3 << 28) 8347 #define DBI_TYPEC_FREQ_SHIFT 24 8348 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 8349 #define DBI_TYPEC_OVERRIDE (1 << 8) 8350 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 8351 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 8352 8353 8354 /* MIPI adapter registers */ 8355 8356 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 8357 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 8358 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 8359 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 8360 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 8361 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 8362 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 8363 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 8364 #define READ_REQUEST_PRIORITY_SHIFT 3 8365 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 8366 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 8367 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 8368 #define RGB_FLIP_TO_BGR (1 << 2) 8369 8370 #define BXT_PIPE_SELECT_SHIFT 7 8371 #define BXT_PIPE_SELECT_MASK (7 << 7) 8372 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 8373 8374 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 8375 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 8376 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 8377 #define DATA_MEM_ADDRESS_SHIFT 5 8378 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 8379 #define DATA_VALID (1 << 0) 8380 8381 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 8382 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 8383 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 8384 #define DATA_LENGTH_SHIFT 0 8385 #define DATA_LENGTH_MASK (0xfffff << 0) 8386 8387 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 8388 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 8389 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 8390 #define COMMAND_MEM_ADDRESS_SHIFT 5 8391 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 8392 #define AUTO_PWG_ENABLE (1 << 2) 8393 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 8394 #define COMMAND_VALID (1 << 0) 8395 8396 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 8397 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 8398 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 8399 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 8400 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 8401 8402 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 8403 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 8404 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 8405 8406 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 8407 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 8408 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 8409 #define READ_DATA_VALID(n) (1 << (n)) 8410 8411 /* For UMS only (deprecated): */ 8412 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) 8413 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) 8414 8415 /* MOCS (Memory Object Control State) registers */ 8416 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 8417 8418 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */ 8419 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ 8420 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ 8421 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ 8422 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ 8423 8424 /* gamt regs */ 8425 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 8426 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 8427 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 8428 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 8429 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 8430 8431 #endif /* _I915_REG_H_ */ 8432