1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/kernel.h> 25 #include <drm/i915_component.h> 26 #include "intel_drv.h" 27 28 #include <drm/drmP.h> 29 #include <drm/drm_edid.h> 30 #include "i915_drv.h" 31 32 /** 33 * DOC: High Definition Audio over HDMI and Display Port 34 * 35 * The graphics and audio drivers together support High Definition Audio over 36 * HDMI and Display Port. The audio programming sequences are divided into audio 37 * codec and controller enable and disable sequences. The graphics driver 38 * handles the audio codec sequences, while the audio driver handles the audio 39 * controller sequences. 40 * 41 * The disable sequences must be performed before disabling the transcoder or 42 * port. The enable sequences may only be performed after enabling the 43 * transcoder and port, and after completed link training. 44 * 45 * The codec and controller sequences could be done either parallel or serial, 46 * but generally the ELDV/PD change in the codec sequence indicates to the audio 47 * driver that the controller sequence should start. Indeed, most of the 48 * co-operation between the graphics and audio drivers is handled via audio 49 * related registers. (The notable exception is the power management, not 50 * covered here.) 51 */ 52 53 static const struct { 54 int clock; 55 u32 config; 56 } hdmi_audio_clock[] = { 57 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 58 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 59 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 60 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 61 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 62 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 63 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 64 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 65 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 66 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 67 }; 68 69 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 70 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) 71 { 72 int i; 73 74 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 75 if (mode->clock == hdmi_audio_clock[i].clock) 76 break; 77 } 78 79 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 80 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); 81 i = 1; 82 } 83 84 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 85 hdmi_audio_clock[i].clock, 86 hdmi_audio_clock[i].config); 87 88 return hdmi_audio_clock[i].config; 89 } 90 91 static bool intel_eld_uptodate(struct drm_connector *connector, 92 int reg_eldv, uint32_t bits_eldv, 93 int reg_elda, uint32_t bits_elda, 94 int reg_edid) 95 { 96 struct drm_i915_private *dev_priv = connector->dev->dev_private; 97 uint8_t *eld = connector->eld; 98 uint32_t tmp; 99 int i; 100 101 tmp = I915_READ(reg_eldv); 102 tmp &= bits_eldv; 103 104 if (!tmp) 105 return false; 106 107 tmp = I915_READ(reg_elda); 108 tmp &= ~bits_elda; 109 I915_WRITE(reg_elda, tmp); 110 111 for (i = 0; i < drm_eld_size(eld) / 4; i++) 112 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 113 return false; 114 115 return true; 116 } 117 118 static void g4x_audio_codec_disable(struct intel_encoder *encoder) 119 { 120 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 121 uint32_t eldv, tmp; 122 123 DRM_DEBUG_KMS("Disable audio codec\n"); 124 125 tmp = I915_READ(G4X_AUD_VID_DID); 126 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 127 eldv = G4X_ELDV_DEVCL_DEVBLC; 128 else 129 eldv = G4X_ELDV_DEVCTG; 130 131 /* Invalidate ELD */ 132 tmp = I915_READ(G4X_AUD_CNTL_ST); 133 tmp &= ~eldv; 134 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 135 } 136 137 static void g4x_audio_codec_enable(struct drm_connector *connector, 138 struct intel_encoder *encoder, 139 struct drm_display_mode *mode) 140 { 141 struct drm_i915_private *dev_priv = connector->dev->dev_private; 142 uint8_t *eld = connector->eld; 143 uint32_t eldv; 144 uint32_t tmp; 145 int len, i; 146 147 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); 148 149 tmp = I915_READ(G4X_AUD_VID_DID); 150 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 151 eldv = G4X_ELDV_DEVCL_DEVBLC; 152 else 153 eldv = G4X_ELDV_DEVCTG; 154 155 if (intel_eld_uptodate(connector, 156 G4X_AUD_CNTL_ST, eldv, 157 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 158 G4X_HDMIW_HDMIEDID)) 159 return; 160 161 tmp = I915_READ(G4X_AUD_CNTL_ST); 162 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 163 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 164 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 165 166 len = min(drm_eld_size(eld) / 4, len); 167 DRM_DEBUG_DRIVER("ELD size %d\n", len); 168 for (i = 0; i < len; i++) 169 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 170 171 tmp = I915_READ(G4X_AUD_CNTL_ST); 172 tmp |= eldv; 173 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 174 } 175 176 static void hsw_audio_codec_disable(struct intel_encoder *encoder) 177 { 178 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 179 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 180 enum i915_pipe pipe = intel_crtc->pipe; 181 uint32_t tmp; 182 183 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); 184 185 /* Disable timestamps */ 186 tmp = I915_READ(HSW_AUD_CFG(pipe)); 187 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 188 tmp |= AUD_CONFIG_N_PROG_ENABLE; 189 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 190 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 191 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 192 tmp |= AUD_CONFIG_N_VALUE_INDEX; 193 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 194 195 /* Invalidate ELD */ 196 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 197 tmp &= ~AUDIO_ELD_VALID(pipe); 198 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); 199 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 200 } 201 202 static void hsw_audio_codec_enable(struct drm_connector *connector, 203 struct intel_encoder *encoder, 204 struct drm_display_mode *mode) 205 { 206 struct drm_i915_private *dev_priv = connector->dev->dev_private; 207 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 208 enum i915_pipe pipe = intel_crtc->pipe; 209 const uint8_t *eld = connector->eld; 210 uint32_t tmp; 211 int len, i; 212 213 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", 214 pipe_name(pipe), drm_eld_size(eld)); 215 216 /* Enable audio presence detect, invalidate ELD */ 217 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 218 tmp |= AUDIO_OUTPUT_ENABLE(pipe); 219 tmp &= ~AUDIO_ELD_VALID(pipe); 220 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 221 222 /* 223 * FIXME: We're supposed to wait for vblank here, but we have vblanks 224 * disabled during the mode set. The proper fix would be to push the 225 * rest of the setup into a vblank work item, queued here, but the 226 * infrastructure is not there yet. 227 */ 228 229 /* Reset ELD write address */ 230 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); 231 tmp &= ~IBX_ELD_ADDRESS_MASK; 232 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); 233 234 /* Up to 84 bytes of hw ELD buffer */ 235 len = min(drm_eld_size(eld), 84); 236 for (i = 0; i < len / 4; i++) 237 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const uint32_t *)eld + i)); 238 239 /* ELD valid */ 240 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 241 tmp |= AUDIO_ELD_VALID(pipe); 242 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 243 244 /* Enable timestamps */ 245 tmp = I915_READ(HSW_AUD_CFG(pipe)); 246 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 247 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 248 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 249 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 250 tmp |= AUD_CONFIG_N_VALUE_INDEX; 251 else 252 tmp |= audio_config_hdmi_pixel_clock(mode); 253 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 254 } 255 256 static void ilk_audio_codec_disable(struct intel_encoder *encoder) 257 { 258 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 259 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 260 struct intel_digital_port *intel_dig_port = 261 enc_to_dig_port(&encoder->base); 262 enum port port = intel_dig_port->port; 263 enum i915_pipe pipe = intel_crtc->pipe; 264 uint32_t tmp, eldv; 265 int aud_config; 266 int aud_cntrl_st2; 267 268 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", 269 port_name(port), pipe_name(pipe)); 270 271 if (WARN_ON(port == PORT_A)) 272 return; 273 274 if (HAS_PCH_IBX(dev_priv->dev)) { 275 aud_config = IBX_AUD_CFG(pipe); 276 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 277 } else if (IS_VALLEYVIEW(dev_priv)) { 278 aud_config = VLV_AUD_CFG(pipe); 279 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 280 } else { 281 aud_config = CPT_AUD_CFG(pipe); 282 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 283 } 284 285 /* Disable timestamps */ 286 tmp = I915_READ(aud_config); 287 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 288 tmp |= AUD_CONFIG_N_PROG_ENABLE; 289 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 290 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 291 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 292 tmp |= AUD_CONFIG_N_VALUE_INDEX; 293 I915_WRITE(aud_config, tmp); 294 295 eldv = IBX_ELD_VALID(port); 296 297 /* Invalidate ELD */ 298 tmp = I915_READ(aud_cntrl_st2); 299 tmp &= ~eldv; 300 I915_WRITE(aud_cntrl_st2, tmp); 301 } 302 303 static void ilk_audio_codec_enable(struct drm_connector *connector, 304 struct intel_encoder *encoder, 305 struct drm_display_mode *mode) 306 { 307 struct drm_i915_private *dev_priv = connector->dev->dev_private; 308 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 309 struct intel_digital_port *intel_dig_port = 310 enc_to_dig_port(&encoder->base); 311 enum port port = intel_dig_port->port; 312 enum i915_pipe pipe = intel_crtc->pipe; 313 uint8_t *eld = connector->eld; 314 uint32_t eldv; 315 uint32_t tmp; 316 int len, i; 317 int hdmiw_hdmiedid; 318 int aud_config; 319 int aud_cntl_st; 320 int aud_cntrl_st2; 321 322 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", 323 port_name(port), pipe_name(pipe), drm_eld_size(eld)); 324 325 if (WARN_ON(port == PORT_A)) 326 return; 327 328 /* 329 * FIXME: We're supposed to wait for vblank here, but we have vblanks 330 * disabled during the mode set. The proper fix would be to push the 331 * rest of the setup into a vblank work item, queued here, but the 332 * infrastructure is not there yet. 333 */ 334 335 if (HAS_PCH_IBX(connector->dev)) { 336 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 337 aud_config = IBX_AUD_CFG(pipe); 338 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 339 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 340 } else if (IS_VALLEYVIEW(connector->dev)) { 341 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 342 aud_config = VLV_AUD_CFG(pipe); 343 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 344 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 345 } else { 346 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 347 aud_config = CPT_AUD_CFG(pipe); 348 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 349 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 350 } 351 352 eldv = IBX_ELD_VALID(port); 353 354 /* Invalidate ELD */ 355 tmp = I915_READ(aud_cntrl_st2); 356 tmp &= ~eldv; 357 I915_WRITE(aud_cntrl_st2, tmp); 358 359 /* Reset ELD write address */ 360 tmp = I915_READ(aud_cntl_st); 361 tmp &= ~IBX_ELD_ADDRESS_MASK; 362 I915_WRITE(aud_cntl_st, tmp); 363 364 /* Up to 84 bytes of hw ELD buffer */ 365 len = min(drm_eld_size(eld), 84); 366 for (i = 0; i < len / 4; i++) 367 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 368 369 /* ELD valid */ 370 tmp = I915_READ(aud_cntrl_st2); 371 tmp |= eldv; 372 I915_WRITE(aud_cntrl_st2, tmp); 373 374 /* Enable timestamps */ 375 tmp = I915_READ(aud_config); 376 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 377 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 378 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 379 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 380 tmp |= AUD_CONFIG_N_VALUE_INDEX; 381 else 382 tmp |= audio_config_hdmi_pixel_clock(mode); 383 I915_WRITE(aud_config, tmp); 384 } 385 386 /** 387 * intel_audio_codec_enable - Enable the audio codec for HD audio 388 * @intel_encoder: encoder on which to enable audio 389 * 390 * The enable sequences may only be performed after enabling the transcoder and 391 * port, and after completed link training. 392 */ 393 void intel_audio_codec_enable(struct intel_encoder *intel_encoder) 394 { 395 struct drm_encoder *encoder = &intel_encoder->base; 396 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 397 struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; 398 struct drm_connector *connector; 399 struct drm_device *dev = encoder->dev; 400 struct drm_i915_private *dev_priv = dev->dev_private; 401 402 connector = drm_select_eld(encoder, mode); 403 if (!connector) 404 return; 405 406 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 407 connector->base.id, 408 connector->name, 409 connector->encoder->base.id, 410 connector->encoder->name); 411 412 /* ELD Conn_Type */ 413 connector->eld[5] &= ~(3 << 2); 414 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 415 connector->eld[5] |= (1 << 2); 416 417 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; 418 419 if (dev_priv->display.audio_codec_enable) 420 dev_priv->display.audio_codec_enable(connector, intel_encoder, mode); 421 } 422 423 /** 424 * intel_audio_codec_disable - Disable the audio codec for HD audio 425 * @encoder: encoder on which to disable audio 426 * 427 * The disable sequences must be performed before disabling the transcoder or 428 * port. 429 */ 430 void intel_audio_codec_disable(struct intel_encoder *encoder) 431 { 432 struct drm_device *dev = encoder->base.dev; 433 struct drm_i915_private *dev_priv = dev->dev_private; 434 435 if (dev_priv->display.audio_codec_disable) 436 dev_priv->display.audio_codec_disable(encoder); 437 } 438 439 /** 440 * intel_init_audio - Set up chip specific audio functions 441 * @dev: drm device 442 */ 443 void intel_init_audio(struct drm_device *dev) 444 { 445 struct drm_i915_private *dev_priv = dev->dev_private; 446 447 if (IS_G4X(dev)) { 448 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 449 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 450 } else if (IS_VALLEYVIEW(dev)) { 451 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 452 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 453 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { 454 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 455 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 456 } else if (HAS_PCH_SPLIT(dev)) { 457 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 458 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 459 } 460 } 461 462 static void i915_audio_component_get_power(struct device *dev) 463 { 464 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 465 } 466 467 static void i915_audio_component_put_power(struct device *dev) 468 { 469 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 470 } 471 472 static void i915_audio_component_codec_wake_override(struct device *dev, 473 bool enable) 474 { 475 struct drm_i915_private *dev_priv = dev_to_i915(dev); 476 u32 tmp; 477 478 if (!IS_SKYLAKE(dev_priv)) 479 return; 480 481 /* 482 * Enable/disable generating the codec wake signal, overriding the 483 * internal logic to generate the codec wake to controller. 484 */ 485 tmp = I915_READ(HSW_AUD_CHICKENBIT); 486 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 487 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 488 usleep_range(1000, 1500); 489 490 if (enable) { 491 tmp = I915_READ(HSW_AUD_CHICKENBIT); 492 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 493 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 494 usleep_range(1000, 1500); 495 } 496 } 497 498 /* Get CDCLK in kHz */ 499 static int i915_audio_component_get_cdclk_freq(struct device *dev) 500 { 501 struct drm_i915_private *dev_priv = dev_to_i915(dev); 502 int ret; 503 504 if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) 505 return -ENODEV; 506 507 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 508 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev); 509 510 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 511 512 return ret; 513 } 514 515 static const struct i915_audio_component_ops i915_audio_component_ops = { 516 .owner = THIS_MODULE, 517 .get_power = i915_audio_component_get_power, 518 .put_power = i915_audio_component_put_power, 519 .codec_wake_override = i915_audio_component_codec_wake_override, 520 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 521 }; 522 523 #if 0 524 static int i915_audio_component_bind(struct device *i915_dev, 525 struct device *hda_dev, void *data) 526 { 527 struct i915_audio_component *acomp = data; 528 529 if (WARN_ON(acomp->ops || acomp->dev)) 530 return -EEXIST; 531 532 acomp->ops = &i915_audio_component_ops; 533 acomp->dev = i915_dev; 534 535 return 0; 536 } 537 538 static void i915_audio_component_unbind(struct device *i915_dev, 539 struct device *hda_dev, void *data) 540 { 541 struct i915_audio_component *acomp = data; 542 543 acomp->ops = NULL; 544 acomp->dev = NULL; 545 } 546 547 static const struct component_ops i915_audio_component_bind_ops = { 548 .bind = i915_audio_component_bind, 549 .unbind = i915_audio_component_unbind, 550 }; 551 #endif 552 553 /** 554 * i915_audio_component_init - initialize and register the audio component 555 * @dev_priv: i915 device instance 556 * 557 * This will register with the component framework a child component which 558 * will bind dynamically to the snd_hda_intel driver's corresponding master 559 * component when the latter is registered. During binding the child 560 * initializes an instance of struct i915_audio_component which it receives 561 * from the master. The master can then start to use the interface defined by 562 * this struct. Each side can break the binding at any point by deregistering 563 * its own component after which each side's component unbind callback is 564 * called. 565 * 566 * We ignore any error during registration and continue with reduced 567 * functionality (i.e. without HDMI audio). 568 */ 569 void i915_audio_component_init(struct drm_i915_private *dev_priv) 570 { 571 #if 0 572 int ret; 573 574 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops); 575 if (ret < 0) { 576 DRM_ERROR("failed to add audio component (%d)\n", ret); 577 /* continue with reduced functionality */ 578 return; 579 } 580 #endif 581 582 dev_priv->audio_component_registered = true; 583 } 584 585 /** 586 * i915_audio_component_cleanup - deregister the audio component 587 * @dev_priv: i915 device instance 588 * 589 * Deregisters the audio component, breaking any existing binding to the 590 * corresponding snd_hda_intel driver's master component. 591 */ 592 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 593 { 594 if (!dev_priv->audio_component_registered) 595 return; 596 597 #if 0 598 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops); 599 #endif 600 dev_priv->audio_component_registered = false; 601 } 602