1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 39 /* Here's the desired hotplug mode */ 40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 41 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 42 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 43 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 44 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 45 ADPA_CRT_HOTPLUG_ENABLE) 46 47 struct intel_crt { 48 struct intel_encoder base; 49 /* DPMS state is stored in the connector, which we need in the 50 * encoder's enable/disable callbacks */ 51 struct intel_connector *connector; 52 bool force_hotplug_required; 53 i915_reg_t adpa_reg; 54 }; 55 56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 57 { 58 return container_of(encoder, struct intel_crt, base); 59 } 60 61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 62 { 63 return intel_encoder_to_crt(intel_attached_encoder(connector)); 64 } 65 66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 67 enum i915_pipe *pipe) 68 { 69 struct drm_device *dev = encoder->base.dev; 70 struct drm_i915_private *dev_priv = to_i915(dev); 71 struct intel_crt *crt = intel_encoder_to_crt(encoder); 72 enum intel_display_power_domain power_domain; 73 u32 tmp; 74 bool ret; 75 76 power_domain = intel_display_port_power_domain(encoder); 77 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 78 return false; 79 80 ret = false; 81 82 tmp = I915_READ(crt->adpa_reg); 83 84 if (!(tmp & ADPA_DAC_ENABLE)) 85 goto out; 86 87 if (HAS_PCH_CPT(dev_priv)) 88 *pipe = PORT_TO_PIPE_CPT(tmp); 89 else 90 *pipe = PORT_TO_PIPE(tmp); 91 92 ret = true; 93 out: 94 intel_display_power_put(dev_priv, power_domain); 95 96 return ret; 97 } 98 99 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 100 { 101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 102 struct intel_crt *crt = intel_encoder_to_crt(encoder); 103 u32 tmp, flags = 0; 104 105 tmp = I915_READ(crt->adpa_reg); 106 107 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 108 flags |= DRM_MODE_FLAG_PHSYNC; 109 else 110 flags |= DRM_MODE_FLAG_NHSYNC; 111 112 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 113 flags |= DRM_MODE_FLAG_PVSYNC; 114 else 115 flags |= DRM_MODE_FLAG_NVSYNC; 116 117 return flags; 118 } 119 120 static void intel_crt_get_config(struct intel_encoder *encoder, 121 struct intel_crtc_state *pipe_config) 122 { 123 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 124 125 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 126 } 127 128 static void hsw_crt_get_config(struct intel_encoder *encoder, 129 struct intel_crtc_state *pipe_config) 130 { 131 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 132 133 intel_ddi_get_config(encoder, pipe_config); 134 135 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 136 DRM_MODE_FLAG_NHSYNC | 137 DRM_MODE_FLAG_PVSYNC | 138 DRM_MODE_FLAG_NVSYNC); 139 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 140 141 pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 142 } 143 144 /* Note: The caller is required to filter out dpms modes not supported by the 145 * platform. */ 146 static void intel_crt_set_dpms(struct intel_encoder *encoder, 147 struct intel_crtc_state *crtc_state, 148 int mode) 149 { 150 struct drm_device *dev = encoder->base.dev; 151 struct drm_i915_private *dev_priv = to_i915(dev); 152 struct intel_crt *crt = intel_encoder_to_crt(encoder); 153 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 154 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; 155 u32 adpa; 156 157 if (INTEL_INFO(dev)->gen >= 5) 158 adpa = ADPA_HOTPLUG_BITS; 159 else 160 adpa = 0; 161 162 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 163 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 164 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 165 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 166 167 /* For CPT allow 3 pipe config, for others just use A or B */ 168 if (HAS_PCH_LPT(dev_priv)) 169 ; /* Those bits don't exist here */ 170 else if (HAS_PCH_CPT(dev_priv)) 171 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 172 else if (crtc->pipe == 0) 173 adpa |= ADPA_PIPE_A_SELECT; 174 else 175 adpa |= ADPA_PIPE_B_SELECT; 176 177 if (!HAS_PCH_SPLIT(dev_priv)) 178 I915_WRITE(BCLRPAT(crtc->pipe), 0); 179 180 switch (mode) { 181 case DRM_MODE_DPMS_ON: 182 adpa |= ADPA_DAC_ENABLE; 183 break; 184 case DRM_MODE_DPMS_STANDBY: 185 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 186 break; 187 case DRM_MODE_DPMS_SUSPEND: 188 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 189 break; 190 case DRM_MODE_DPMS_OFF: 191 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 192 break; 193 } 194 195 I915_WRITE(crt->adpa_reg, adpa); 196 } 197 198 static void intel_disable_crt(struct intel_encoder *encoder, 199 struct intel_crtc_state *old_crtc_state, 200 struct drm_connector_state *old_conn_state) 201 { 202 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 203 } 204 205 static void pch_disable_crt(struct intel_encoder *encoder, 206 struct intel_crtc_state *old_crtc_state, 207 struct drm_connector_state *old_conn_state) 208 { 209 } 210 211 static void pch_post_disable_crt(struct intel_encoder *encoder, 212 struct intel_crtc_state *old_crtc_state, 213 struct drm_connector_state *old_conn_state) 214 { 215 intel_disable_crt(encoder, old_crtc_state, old_conn_state); 216 } 217 218 static void hsw_post_disable_crt(struct intel_encoder *encoder, 219 struct intel_crtc_state *old_crtc_state, 220 struct drm_connector_state *old_conn_state) 221 { 222 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 223 224 pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); 225 226 lpt_disable_pch_transcoder(dev_priv); 227 lpt_disable_iclkip(dev_priv); 228 229 intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); 230 } 231 232 static void intel_enable_crt(struct intel_encoder *encoder, 233 struct intel_crtc_state *pipe_config, 234 struct drm_connector_state *conn_state) 235 { 236 intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON); 237 } 238 239 static enum drm_mode_status 240 intel_crt_mode_valid(struct drm_connector *connector, 241 struct drm_display_mode *mode) 242 { 243 struct drm_device *dev = connector->dev; 244 struct drm_i915_private *dev_priv = to_i915(dev); 245 int max_dotclk = dev_priv->max_dotclk_freq; 246 int max_clock; 247 248 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 249 return MODE_NO_DBLESCAN; 250 251 if (mode->clock < 25000) 252 return MODE_CLOCK_LOW; 253 254 if (HAS_PCH_LPT(dev_priv)) 255 max_clock = 180000; 256 else if (IS_VALLEYVIEW(dev_priv)) 257 /* 258 * 270 MHz due to current DPLL limits, 259 * DAC limit supposedly 355 MHz. 260 */ 261 max_clock = 270000; 262 else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) 263 max_clock = 400000; 264 else 265 max_clock = 350000; 266 if (mode->clock > max_clock) 267 return MODE_CLOCK_HIGH; 268 269 if (mode->clock > max_dotclk) 270 return MODE_CLOCK_HIGH; 271 272 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 273 if (HAS_PCH_LPT(dev_priv) && 274 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 275 return MODE_CLOCK_HIGH; 276 277 return MODE_OK; 278 } 279 280 static bool intel_crt_compute_config(struct intel_encoder *encoder, 281 struct intel_crtc_state *pipe_config, 282 struct drm_connector_state *conn_state) 283 { 284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 285 286 if (HAS_PCH_SPLIT(dev_priv)) 287 pipe_config->has_pch_encoder = true; 288 289 /* LPT FDI RX only supports 8bpc. */ 290 if (HAS_PCH_LPT(dev_priv)) { 291 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 292 DRM_DEBUG_KMS("LPT only supports 24bpp\n"); 293 return false; 294 } 295 296 pipe_config->pipe_bpp = 24; 297 } 298 299 /* FDI must always be 2.7 GHz */ 300 if (HAS_DDI(dev_priv)) 301 pipe_config->port_clock = 135000 * 2; 302 303 return true; 304 } 305 306 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 307 { 308 struct drm_device *dev = connector->dev; 309 struct intel_crt *crt = intel_attached_crt(connector); 310 struct drm_i915_private *dev_priv = to_i915(dev); 311 u32 adpa; 312 bool ret; 313 314 /* The first time through, trigger an explicit detection cycle */ 315 if (crt->force_hotplug_required) { 316 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); 317 u32 save_adpa; 318 319 crt->force_hotplug_required = 0; 320 321 save_adpa = adpa = I915_READ(crt->adpa_reg); 322 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 323 324 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 325 if (turn_off_dac) 326 adpa &= ~ADPA_DAC_ENABLE; 327 328 I915_WRITE(crt->adpa_reg, adpa); 329 330 if (intel_wait_for_register(dev_priv, 331 crt->adpa_reg, 332 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, 333 1000)) 334 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 335 336 if (turn_off_dac) { 337 I915_WRITE(crt->adpa_reg, save_adpa); 338 POSTING_READ(crt->adpa_reg); 339 } 340 } 341 342 /* Check the status to see if both blue and green are on now */ 343 adpa = I915_READ(crt->adpa_reg); 344 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 345 ret = true; 346 else 347 ret = false; 348 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 349 350 return ret; 351 } 352 353 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 354 { 355 struct drm_device *dev = connector->dev; 356 struct intel_crt *crt = intel_attached_crt(connector); 357 struct drm_i915_private *dev_priv = to_i915(dev); 358 bool reenable_hpd; 359 u32 adpa; 360 bool ret; 361 u32 save_adpa; 362 363 /* 364 * Doing a force trigger causes a hpd interrupt to get sent, which can 365 * get us stuck in a loop if we're polling: 366 * - We enable power wells and reset the ADPA 367 * - output_poll_exec does force probe on VGA, triggering a hpd 368 * - HPD handler waits for poll to unlock dev->mode_config.mutex 369 * - output_poll_exec shuts off the ADPA, unlocks 370 * dev->mode_config.mutex 371 * - HPD handler runs, resets ADPA and brings us back to the start 372 * 373 * Just disable HPD interrupts here to prevent this 374 */ 375 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 376 377 save_adpa = adpa = I915_READ(crt->adpa_reg); 378 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 379 380 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 381 382 I915_WRITE(crt->adpa_reg, adpa); 383 384 if (intel_wait_for_register(dev_priv, 385 crt->adpa_reg, 386 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, 387 1000)) { 388 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 389 I915_WRITE(crt->adpa_reg, save_adpa); 390 } 391 392 /* Check the status to see if both blue and green are on now */ 393 adpa = I915_READ(crt->adpa_reg); 394 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 395 ret = true; 396 else 397 ret = false; 398 399 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 400 401 if (reenable_hpd) 402 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 403 404 return ret; 405 } 406 407 /** 408 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 409 * 410 * Not for i915G/i915GM 411 * 412 * \return true if CRT is connected. 413 * \return false if CRT is disconnected. 414 */ 415 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 416 { 417 struct drm_device *dev = connector->dev; 418 struct drm_i915_private *dev_priv = to_i915(dev); 419 u32 stat; 420 bool ret = false; 421 int i, tries = 0; 422 423 if (HAS_PCH_SPLIT(dev_priv)) 424 return intel_ironlake_crt_detect_hotplug(connector); 425 426 if (IS_VALLEYVIEW(dev_priv)) 427 return valleyview_crt_detect_hotplug(connector); 428 429 /* 430 * On 4 series desktop, CRT detect sequence need to be done twice 431 * to get a reliable result. 432 */ 433 434 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) 435 tries = 2; 436 else 437 tries = 1; 438 439 for (i = 0; i < tries ; i++) { 440 /* turn on the FORCE_DETECT */ 441 i915_hotplug_interrupt_update(dev_priv, 442 CRT_HOTPLUG_FORCE_DETECT, 443 CRT_HOTPLUG_FORCE_DETECT); 444 /* wait for FORCE_DETECT to go off */ 445 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN, 446 CRT_HOTPLUG_FORCE_DETECT, 0, 447 1000)) 448 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 449 } 450 451 stat = I915_READ(PORT_HOTPLUG_STAT); 452 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 453 ret = true; 454 455 /* clear the interrupt we just generated, if any */ 456 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 457 458 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 459 460 return ret; 461 } 462 463 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 464 struct i2c_adapter *i2c) 465 { 466 struct edid *edid; 467 468 edid = drm_get_edid(connector, i2c); 469 470 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 471 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 472 intel_gmbus_force_bit(i2c, true); 473 edid = drm_get_edid(connector, i2c); 474 intel_gmbus_force_bit(i2c, false); 475 } 476 477 return edid; 478 } 479 480 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 481 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 482 struct i2c_adapter *adapter) 483 { 484 struct edid *edid; 485 int ret; 486 487 edid = intel_crt_get_edid(connector, adapter); 488 if (!edid) 489 return 0; 490 491 ret = intel_connector_update_modes(connector, edid); 492 kfree(edid); 493 494 return ret; 495 } 496 497 static bool intel_crt_detect_ddc(struct drm_connector *connector) 498 { 499 struct intel_crt *crt = intel_attached_crt(connector); 500 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); 501 struct edid *edid; 502 struct i2c_adapter *i2c; 503 504 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 505 506 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 507 edid = intel_crt_get_edid(connector, i2c); 508 509 if (edid) { 510 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 511 512 /* 513 * This may be a DVI-I connector with a shared DDC 514 * link between analog and digital outputs, so we 515 * have to check the EDID input spec of the attached device. 516 */ 517 if (!is_digital) { 518 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 519 return true; 520 } 521 522 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 523 } else { 524 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 525 } 526 527 kfree(edid); 528 529 return false; 530 } 531 532 static enum drm_connector_status 533 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) 534 { 535 struct drm_device *dev = crt->base.base.dev; 536 struct drm_i915_private *dev_priv = to_i915(dev); 537 uint32_t save_bclrpat; 538 uint32_t save_vtotal; 539 uint32_t vtotal, vactive; 540 uint32_t vsample; 541 uint32_t vblank, vblank_start, vblank_end; 542 uint32_t dsl; 543 i915_reg_t bclrpat_reg, vtotal_reg, 544 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 545 uint8_t st00; 546 enum drm_connector_status status; 547 548 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 549 550 bclrpat_reg = BCLRPAT(pipe); 551 vtotal_reg = VTOTAL(pipe); 552 vblank_reg = VBLANK(pipe); 553 vsync_reg = VSYNC(pipe); 554 pipeconf_reg = PIPECONF(pipe); 555 pipe_dsl_reg = PIPEDSL(pipe); 556 557 save_bclrpat = I915_READ(bclrpat_reg); 558 save_vtotal = I915_READ(vtotal_reg); 559 vblank = I915_READ(vblank_reg); 560 561 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 562 vactive = (save_vtotal & 0x7ff) + 1; 563 564 vblank_start = (vblank & 0xfff) + 1; 565 vblank_end = ((vblank >> 16) & 0xfff) + 1; 566 567 /* Set the border color to purple. */ 568 I915_WRITE(bclrpat_reg, 0x500050); 569 570 if (!IS_GEN2(dev_priv)) { 571 uint32_t pipeconf = I915_READ(pipeconf_reg); 572 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 573 POSTING_READ(pipeconf_reg); 574 /* Wait for next Vblank to substitue 575 * border color for Color info */ 576 intel_wait_for_vblank(dev, pipe); 577 st00 = I915_READ8(_VGA_MSR_WRITE); 578 status = ((st00 & (1 << 4)) != 0) ? 579 connector_status_connected : 580 connector_status_disconnected; 581 582 I915_WRITE(pipeconf_reg, pipeconf); 583 } else { 584 bool restore_vblank = false; 585 int count, detect; 586 587 /* 588 * If there isn't any border, add some. 589 * Yes, this will flicker 590 */ 591 if (vblank_start <= vactive && vblank_end >= vtotal) { 592 uint32_t vsync = I915_READ(vsync_reg); 593 uint32_t vsync_start = (vsync & 0xffff) + 1; 594 595 vblank_start = vsync_start; 596 I915_WRITE(vblank_reg, 597 (vblank_start - 1) | 598 ((vblank_end - 1) << 16)); 599 restore_vblank = true; 600 } 601 /* sample in the vertical border, selecting the larger one */ 602 if (vblank_start - vactive >= vtotal - vblank_end) 603 vsample = (vblank_start + vactive) >> 1; 604 else 605 vsample = (vtotal + vblank_end) >> 1; 606 607 /* 608 * Wait for the border to be displayed 609 */ 610 while (I915_READ(pipe_dsl_reg) >= vactive) 611 ; 612 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 613 ; 614 /* 615 * Watch ST00 for an entire scanline 616 */ 617 detect = 0; 618 count = 0; 619 do { 620 count++; 621 /* Read the ST00 VGA status register */ 622 st00 = I915_READ8(_VGA_MSR_WRITE); 623 if (st00 & (1 << 4)) 624 detect++; 625 } while ((I915_READ(pipe_dsl_reg) == dsl)); 626 627 /* restore vblank if necessary */ 628 if (restore_vblank) 629 I915_WRITE(vblank_reg, vblank); 630 /* 631 * If more than 3/4 of the scanline detected a monitor, 632 * then it is assumed to be present. This works even on i830, 633 * where there isn't any way to force the border color across 634 * the screen 635 */ 636 status = detect * 4 > count * 3 ? 637 connector_status_connected : 638 connector_status_disconnected; 639 } 640 641 /* Restore previous settings */ 642 I915_WRITE(bclrpat_reg, save_bclrpat); 643 644 return status; 645 } 646 647 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 648 { 649 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 650 return 1; 651 } 652 653 static const struct dmi_system_id intel_spurious_crt_detect[] = { 654 { 655 .callback = intel_spurious_crt_detect_dmi_callback, 656 .ident = "ACER ZGB", 657 .matches = { 658 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 659 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 660 }, 661 }, 662 { 663 .callback = intel_spurious_crt_detect_dmi_callback, 664 .ident = "Intel DZ77BH-55K", 665 .matches = { 666 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 667 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 668 }, 669 }, 670 { } 671 }; 672 673 static enum drm_connector_status 674 intel_crt_detect(struct drm_connector *connector, bool force) 675 { 676 struct drm_device *dev = connector->dev; 677 struct drm_i915_private *dev_priv = to_i915(dev); 678 struct intel_crt *crt = intel_attached_crt(connector); 679 struct intel_encoder *intel_encoder = &crt->base; 680 enum intel_display_power_domain power_domain; 681 enum drm_connector_status status; 682 struct intel_load_detect_pipe tmp; 683 struct drm_modeset_acquire_ctx ctx; 684 685 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 686 connector->base.id, connector->name, 687 force); 688 689 /* Skip machines without VGA that falsely report hotplug events */ 690 if (dmi_check_system(intel_spurious_crt_detect)) 691 return connector_status_disconnected; 692 693 power_domain = intel_display_port_power_domain(intel_encoder); 694 intel_display_power_get(dev_priv, power_domain); 695 696 if (I915_HAS_HOTPLUG(dev)) { 697 /* We can not rely on the HPD pin always being correctly wired 698 * up, for example many KVM do not pass it through, and so 699 * only trust an assertion that the monitor is connected. 700 */ 701 if (intel_crt_detect_hotplug(connector)) { 702 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 703 status = connector_status_connected; 704 goto out; 705 } else 706 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 707 } 708 709 if (intel_crt_detect_ddc(connector)) { 710 status = connector_status_connected; 711 goto out; 712 } 713 714 /* Load detection is broken on HPD capable machines. Whoever wants a 715 * broken monitor (without edid) to work behind a broken kvm (that fails 716 * to have the right resistors for HP detection) needs to fix this up. 717 * For now just bail out. */ 718 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { 719 status = connector_status_disconnected; 720 goto out; 721 } 722 723 if (!force) { 724 status = connector->status; 725 goto out; 726 } 727 728 drm_modeset_acquire_init(&ctx, 0); 729 730 /* for pre-945g platforms use load detect */ 731 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 732 if (intel_crt_detect_ddc(connector)) 733 status = connector_status_connected; 734 else if (INTEL_INFO(dev)->gen < 4) 735 status = intel_crt_load_detect(crt, 736 to_intel_crtc(connector->state->crtc)->pipe); 737 else if (i915.load_detect_test) 738 status = connector_status_disconnected; 739 else 740 status = connector_status_unknown; 741 intel_release_load_detect_pipe(connector, &tmp, &ctx); 742 } else 743 status = connector_status_unknown; 744 745 drm_modeset_drop_locks(&ctx); 746 drm_modeset_acquire_fini(&ctx); 747 748 out: 749 intel_display_power_put(dev_priv, power_domain); 750 return status; 751 } 752 753 static void intel_crt_destroy(struct drm_connector *connector) 754 { 755 drm_connector_cleanup(connector); 756 kfree(connector); 757 } 758 759 static int intel_crt_get_modes(struct drm_connector *connector) 760 { 761 struct drm_device *dev = connector->dev; 762 struct drm_i915_private *dev_priv = to_i915(dev); 763 struct intel_crt *crt = intel_attached_crt(connector); 764 struct intel_encoder *intel_encoder = &crt->base; 765 enum intel_display_power_domain power_domain; 766 int ret; 767 struct i2c_adapter *i2c; 768 769 power_domain = intel_display_port_power_domain(intel_encoder); 770 intel_display_power_get(dev_priv, power_domain); 771 772 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 773 ret = intel_crt_ddc_get_modes(connector, i2c); 774 if (ret || !IS_G4X(dev_priv)) 775 goto out; 776 777 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 778 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 779 ret = intel_crt_ddc_get_modes(connector, i2c); 780 781 out: 782 intel_display_power_put(dev_priv, power_domain); 783 784 return ret; 785 } 786 787 static int intel_crt_set_property(struct drm_connector *connector, 788 struct drm_property *property, 789 uint64_t value) 790 { 791 return 0; 792 } 793 794 void intel_crt_reset(struct drm_encoder *encoder) 795 { 796 struct drm_device *dev = encoder->dev; 797 struct drm_i915_private *dev_priv = to_i915(dev); 798 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 799 800 if (INTEL_INFO(dev)->gen >= 5) { 801 u32 adpa; 802 803 adpa = I915_READ(crt->adpa_reg); 804 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 805 adpa |= ADPA_HOTPLUG_BITS; 806 I915_WRITE(crt->adpa_reg, adpa); 807 POSTING_READ(crt->adpa_reg); 808 809 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 810 crt->force_hotplug_required = 1; 811 } 812 813 } 814 815 /* 816 * Routines for controlling stuff on the analog port 817 */ 818 819 static const struct drm_connector_funcs intel_crt_connector_funcs = { 820 .dpms = drm_atomic_helper_connector_dpms, 821 .detect = intel_crt_detect, 822 .fill_modes = drm_helper_probe_single_connector_modes, 823 .late_register = intel_connector_register, 824 .early_unregister = intel_connector_unregister, 825 .destroy = intel_crt_destroy, 826 .set_property = intel_crt_set_property, 827 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 828 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 829 .atomic_get_property = intel_connector_atomic_get_property, 830 }; 831 832 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 833 .mode_valid = intel_crt_mode_valid, 834 .get_modes = intel_crt_get_modes, 835 }; 836 837 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 838 .reset = intel_crt_reset, 839 .destroy = intel_encoder_destroy, 840 }; 841 842 void intel_crt_init(struct drm_device *dev) 843 { 844 struct drm_connector *connector; 845 struct intel_crt *crt; 846 struct intel_connector *intel_connector; 847 struct drm_i915_private *dev_priv = to_i915(dev); 848 i915_reg_t adpa_reg; 849 u32 adpa; 850 851 if (HAS_PCH_SPLIT(dev_priv)) 852 adpa_reg = PCH_ADPA; 853 else if (IS_VALLEYVIEW(dev_priv)) 854 adpa_reg = VLV_ADPA; 855 else 856 adpa_reg = ADPA; 857 858 adpa = I915_READ(adpa_reg); 859 if ((adpa & ADPA_DAC_ENABLE) == 0) { 860 /* 861 * On some machines (some IVB at least) CRT can be 862 * fused off, but there's no known fuse bit to 863 * indicate that. On these machine the ADPA register 864 * works normally, except the DAC enable bit won't 865 * take. So the only way to tell is attempt to enable 866 * it and see what happens. 867 */ 868 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | 869 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 870 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) 871 return; 872 I915_WRITE(adpa_reg, adpa); 873 } 874 875 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 876 if (!crt) 877 return; 878 879 intel_connector = intel_connector_alloc(); 880 if (!intel_connector) { 881 kfree(crt); 882 return; 883 } 884 885 connector = &intel_connector->base; 886 crt->connector = intel_connector; 887 drm_connector_init(dev, &intel_connector->base, 888 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 889 890 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 891 DRM_MODE_ENCODER_DAC, "CRT"); 892 893 intel_connector_attach_encoder(intel_connector, &crt->base); 894 895 crt->base.type = INTEL_OUTPUT_ANALOG; 896 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 897 if (IS_I830(dev_priv)) 898 crt->base.crtc_mask = (1 << 0); 899 else 900 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 901 902 if (IS_GEN2(dev_priv)) 903 connector->interlace_allowed = 0; 904 else 905 connector->interlace_allowed = 1; 906 connector->doublescan_allowed = 0; 907 908 crt->adpa_reg = adpa_reg; 909 910 crt->base.compute_config = intel_crt_compute_config; 911 if (HAS_PCH_SPLIT(dev_priv)) { 912 crt->base.disable = pch_disable_crt; 913 crt->base.post_disable = pch_post_disable_crt; 914 } else { 915 crt->base.disable = intel_disable_crt; 916 } 917 crt->base.enable = intel_enable_crt; 918 if (I915_HAS_HOTPLUG(dev) && 919 !dmi_check_system(intel_spurious_crt_detect)) 920 crt->base.hpd_pin = HPD_CRT; 921 if (HAS_DDI(dev_priv)) { 922 crt->base.port = PORT_E; 923 crt->base.get_config = hsw_crt_get_config; 924 crt->base.get_hw_state = intel_ddi_get_hw_state; 925 crt->base.post_disable = hsw_post_disable_crt; 926 } else { 927 crt->base.port = PORT_NONE; 928 crt->base.get_config = intel_crt_get_config; 929 crt->base.get_hw_state = intel_crt_get_hw_state; 930 } 931 intel_connector->get_hw_state = intel_connector_get_hw_state; 932 933 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 934 935 if (!I915_HAS_HOTPLUG(dev)) 936 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 937 938 /* 939 * Configure the automatic hotplug detection stuff 940 */ 941 crt->force_hotplug_required = 0; 942 943 /* 944 * TODO: find a proper way to discover whether we need to set the the 945 * polarity and link reversal bits or not, instead of relying on the 946 * BIOS. 947 */ 948 if (HAS_PCH_LPT(dev_priv)) { 949 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 950 FDI_RX_LINK_REVERSAL_OVERRIDE; 951 952 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; 953 } 954 955 intel_crt_reset(&crt->base.base); 956 } 957