1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 38 /* Here's the desired hotplug mode */ 39 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 40 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 41 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 42 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 43 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 44 ADPA_CRT_HOTPLUG_ENABLE) 45 46 struct intel_crt { 47 struct intel_encoder base; 48 /* DPMS state is stored in the connector, which we need in the 49 * encoder's enable/disable callbacks */ 50 struct intel_connector *connector; 51 bool force_hotplug_required; 52 u32 adpa_reg; 53 }; 54 55 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 56 { 57 return container_of(encoder, struct intel_crt, base); 58 } 59 60 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 61 { 62 return intel_encoder_to_crt(intel_attached_encoder(connector)); 63 } 64 65 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 66 enum i915_pipe *pipe) 67 { 68 struct drm_device *dev = encoder->base.dev; 69 struct drm_i915_private *dev_priv = dev->dev_private; 70 struct intel_crt *crt = intel_encoder_to_crt(encoder); 71 enum intel_display_power_domain power_domain; 72 u32 tmp; 73 74 power_domain = intel_display_port_power_domain(encoder); 75 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 76 return false; 77 78 tmp = I915_READ(crt->adpa_reg); 79 80 if (!(tmp & ADPA_DAC_ENABLE)) 81 return false; 82 83 if (HAS_PCH_CPT(dev)) 84 *pipe = PORT_TO_PIPE_CPT(tmp); 85 else 86 *pipe = PORT_TO_PIPE(tmp); 87 88 return true; 89 } 90 91 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 92 { 93 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 94 struct intel_crt *crt = intel_encoder_to_crt(encoder); 95 u32 tmp, flags = 0; 96 97 tmp = I915_READ(crt->adpa_reg); 98 99 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 100 flags |= DRM_MODE_FLAG_PHSYNC; 101 else 102 flags |= DRM_MODE_FLAG_NHSYNC; 103 104 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 105 flags |= DRM_MODE_FLAG_PVSYNC; 106 else 107 flags |= DRM_MODE_FLAG_NVSYNC; 108 109 return flags; 110 } 111 112 static void intel_crt_get_config(struct intel_encoder *encoder, 113 struct intel_crtc_state *pipe_config) 114 { 115 struct drm_device *dev = encoder->base.dev; 116 int dotclock; 117 118 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 119 120 dotclock = pipe_config->port_clock; 121 122 if (HAS_PCH_SPLIT(dev)) 123 ironlake_check_encoder_dotclock(pipe_config, dotclock); 124 125 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 126 } 127 128 static void hsw_crt_get_config(struct intel_encoder *encoder, 129 struct intel_crtc_state *pipe_config) 130 { 131 intel_ddi_get_config(encoder, pipe_config); 132 133 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 134 DRM_MODE_FLAG_NHSYNC | 135 DRM_MODE_FLAG_PVSYNC | 136 DRM_MODE_FLAG_NVSYNC); 137 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 138 } 139 140 static void hsw_crt_pre_enable(struct intel_encoder *encoder) 141 { 142 struct drm_device *dev = encoder->base.dev; 143 struct drm_i915_private *dev_priv = dev->dev_private; 144 145 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); 146 I915_WRITE(SPLL_CTL, 147 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); 148 POSTING_READ(SPLL_CTL); 149 udelay(20); 150 } 151 152 /* Note: The caller is required to filter out dpms modes not supported by the 153 * platform. */ 154 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 155 { 156 struct drm_device *dev = encoder->base.dev; 157 struct drm_i915_private *dev_priv = dev->dev_private; 158 struct intel_crt *crt = intel_encoder_to_crt(encoder); 159 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 160 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 161 u32 adpa; 162 163 if (INTEL_INFO(dev)->gen >= 5) 164 adpa = ADPA_HOTPLUG_BITS; 165 else 166 adpa = 0; 167 168 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 169 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 170 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 171 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 172 173 /* For CPT allow 3 pipe config, for others just use A or B */ 174 if (HAS_PCH_LPT(dev)) 175 ; /* Those bits don't exist here */ 176 else if (HAS_PCH_CPT(dev)) 177 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 178 else if (crtc->pipe == 0) 179 adpa |= ADPA_PIPE_A_SELECT; 180 else 181 adpa |= ADPA_PIPE_B_SELECT; 182 183 if (!HAS_PCH_SPLIT(dev)) 184 I915_WRITE(BCLRPAT(crtc->pipe), 0); 185 186 switch (mode) { 187 case DRM_MODE_DPMS_ON: 188 adpa |= ADPA_DAC_ENABLE; 189 break; 190 case DRM_MODE_DPMS_STANDBY: 191 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 192 break; 193 case DRM_MODE_DPMS_SUSPEND: 194 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 195 break; 196 case DRM_MODE_DPMS_OFF: 197 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 198 break; 199 } 200 201 I915_WRITE(crt->adpa_reg, adpa); 202 } 203 204 static void intel_disable_crt(struct intel_encoder *encoder) 205 { 206 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 207 } 208 209 static void pch_disable_crt(struct intel_encoder *encoder) 210 { 211 } 212 213 static void pch_post_disable_crt(struct intel_encoder *encoder) 214 { 215 intel_disable_crt(encoder); 216 } 217 218 static void hsw_crt_post_disable(struct intel_encoder *encoder) 219 { 220 struct drm_device *dev = encoder->base.dev; 221 struct drm_i915_private *dev_priv = dev->dev_private; 222 uint32_t val; 223 224 DRM_DEBUG_KMS("Disabling SPLL\n"); 225 val = I915_READ(SPLL_CTL); 226 WARN_ON(!(val & SPLL_PLL_ENABLE)); 227 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 228 POSTING_READ(SPLL_CTL); 229 } 230 231 static void intel_enable_crt(struct intel_encoder *encoder) 232 { 233 struct intel_crt *crt = intel_encoder_to_crt(encoder); 234 235 intel_crt_set_dpms(encoder, crt->connector->base.dpms); 236 } 237 238 /* Special dpms function to support cloning between dvo/sdvo/crt. */ 239 static void intel_crt_dpms(struct drm_connector *connector, int mode) 240 { 241 struct drm_device *dev = connector->dev; 242 struct intel_encoder *encoder = intel_attached_encoder(connector); 243 struct drm_crtc *crtc; 244 int old_dpms; 245 246 /* PCH platforms and VLV only support on/off. */ 247 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) 248 mode = DRM_MODE_DPMS_OFF; 249 250 if (mode == connector->dpms) 251 return; 252 253 old_dpms = connector->dpms; 254 connector->dpms = mode; 255 256 /* Only need to change hw state when actually enabled */ 257 crtc = encoder->base.crtc; 258 if (!crtc) { 259 encoder->connectors_active = false; 260 return; 261 } 262 263 /* We need the pipe to run for anything but OFF. */ 264 if (mode == DRM_MODE_DPMS_OFF) 265 encoder->connectors_active = false; 266 else 267 encoder->connectors_active = true; 268 269 /* We call connector dpms manually below in case pipe dpms doesn't 270 * change due to cloning. */ 271 if (mode < old_dpms) { 272 /* From off to on, enable the pipe first. */ 273 intel_crtc_update_dpms(crtc); 274 275 intel_crt_set_dpms(encoder, mode); 276 } else { 277 intel_crt_set_dpms(encoder, mode); 278 279 intel_crtc_update_dpms(crtc); 280 } 281 282 intel_modeset_check_state(connector->dev); 283 } 284 285 static enum drm_mode_status 286 intel_crt_mode_valid(struct drm_connector *connector, 287 struct drm_display_mode *mode) 288 { 289 struct drm_device *dev = connector->dev; 290 291 int max_clock = 0; 292 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 293 return MODE_NO_DBLESCAN; 294 295 if (mode->clock < 25000) 296 return MODE_CLOCK_LOW; 297 298 if (IS_GEN2(dev)) 299 max_clock = 350000; 300 else 301 max_clock = 400000; 302 if (mode->clock > max_clock) 303 return MODE_CLOCK_HIGH; 304 305 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 306 if (HAS_PCH_LPT(dev) && 307 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 308 return MODE_CLOCK_HIGH; 309 310 return MODE_OK; 311 } 312 313 static bool intel_crt_compute_config(struct intel_encoder *encoder, 314 struct intel_crtc_state *pipe_config) 315 { 316 struct drm_device *dev = encoder->base.dev; 317 318 if (HAS_PCH_SPLIT(dev)) 319 pipe_config->has_pch_encoder = true; 320 321 /* LPT FDI RX only supports 8bpc. */ 322 if (HAS_PCH_LPT(dev)) 323 pipe_config->pipe_bpp = 24; 324 325 /* FDI must always be 2.7 GHz */ 326 if (HAS_DDI(dev)) { 327 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; 328 pipe_config->port_clock = 135000 * 2; 329 } 330 331 return true; 332 } 333 334 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 335 { 336 struct drm_device *dev = connector->dev; 337 struct intel_crt *crt = intel_attached_crt(connector); 338 struct drm_i915_private *dev_priv = dev->dev_private; 339 u32 adpa; 340 bool ret; 341 342 /* The first time through, trigger an explicit detection cycle */ 343 if (crt->force_hotplug_required) { 344 bool turn_off_dac = HAS_PCH_SPLIT(dev); 345 u32 save_adpa; 346 347 crt->force_hotplug_required = 0; 348 349 save_adpa = adpa = I915_READ(crt->adpa_reg); 350 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 351 352 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 353 if (turn_off_dac) 354 adpa &= ~ADPA_DAC_ENABLE; 355 356 I915_WRITE(crt->adpa_reg, adpa); 357 358 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 359 1000)) 360 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 361 362 if (turn_off_dac) { 363 I915_WRITE(crt->adpa_reg, save_adpa); 364 POSTING_READ(crt->adpa_reg); 365 } 366 } 367 368 /* Check the status to see if both blue and green are on now */ 369 adpa = I915_READ(crt->adpa_reg); 370 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 371 ret = true; 372 else 373 ret = false; 374 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 375 376 return ret; 377 } 378 379 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 380 { 381 struct drm_device *dev = connector->dev; 382 struct intel_crt *crt = intel_attached_crt(connector); 383 struct drm_i915_private *dev_priv = dev->dev_private; 384 u32 adpa; 385 bool ret; 386 u32 save_adpa; 387 388 save_adpa = adpa = I915_READ(crt->adpa_reg); 389 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 390 391 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 392 393 I915_WRITE(crt->adpa_reg, adpa); 394 395 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 396 1000)) { 397 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 398 I915_WRITE(crt->adpa_reg, save_adpa); 399 } 400 401 /* Check the status to see if both blue and green are on now */ 402 adpa = I915_READ(crt->adpa_reg); 403 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 404 ret = true; 405 else 406 ret = false; 407 408 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 409 410 return ret; 411 } 412 413 /** 414 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 415 * 416 * Not for i915G/i915GM 417 * 418 * \return true if CRT is connected. 419 * \return false if CRT is disconnected. 420 */ 421 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 422 { 423 struct drm_device *dev = connector->dev; 424 struct drm_i915_private *dev_priv = dev->dev_private; 425 u32 hotplug_en, orig, stat; 426 bool ret = false; 427 int i, tries = 0; 428 429 if (HAS_PCH_SPLIT(dev)) 430 return intel_ironlake_crt_detect_hotplug(connector); 431 432 if (IS_VALLEYVIEW(dev)) 433 return valleyview_crt_detect_hotplug(connector); 434 435 /* 436 * On 4 series desktop, CRT detect sequence need to be done twice 437 * to get a reliable result. 438 */ 439 440 if (IS_G4X(dev) && !IS_GM45(dev)) 441 tries = 2; 442 else 443 tries = 1; 444 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); 445 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 446 447 for (i = 0; i < tries ; i++) { 448 /* turn on the FORCE_DETECT */ 449 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 450 /* wait for FORCE_DETECT to go off */ 451 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 452 CRT_HOTPLUG_FORCE_DETECT) == 0, 453 1000)) 454 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 455 } 456 457 stat = I915_READ(PORT_HOTPLUG_STAT); 458 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 459 ret = true; 460 461 /* clear the interrupt we just generated, if any */ 462 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 463 464 /* and put the bits back */ 465 I915_WRITE(PORT_HOTPLUG_EN, orig); 466 467 return ret; 468 } 469 470 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 471 struct i2c_adapter *i2c) 472 { 473 struct edid *edid; 474 475 edid = drm_get_edid(connector, i2c); 476 477 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 478 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 479 intel_gmbus_force_bit(i2c, true); 480 edid = drm_get_edid(connector, i2c); 481 intel_gmbus_force_bit(i2c, false); 482 } 483 484 return edid; 485 } 486 487 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 488 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 489 struct i2c_adapter *adapter) 490 { 491 struct edid *edid; 492 int ret; 493 494 edid = intel_crt_get_edid(connector, adapter); 495 if (!edid) 496 return 0; 497 498 ret = intel_connector_update_modes(connector, edid); 499 kfree(edid); 500 501 return ret; 502 } 503 504 static bool intel_crt_detect_ddc(struct drm_connector *connector) 505 { 506 struct intel_crt *crt = intel_attached_crt(connector); 507 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 508 struct edid *edid; 509 struct i2c_adapter *i2c; 510 511 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 512 513 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 514 edid = intel_crt_get_edid(connector, i2c); 515 516 if (edid) { 517 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 518 519 /* 520 * This may be a DVI-I connector with a shared DDC 521 * link between analog and digital outputs, so we 522 * have to check the EDID input spec of the attached device. 523 */ 524 if (!is_digital) { 525 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 526 return true; 527 } 528 529 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 530 } else { 531 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 532 } 533 534 kfree(edid); 535 536 return false; 537 } 538 539 static enum drm_connector_status 540 intel_crt_load_detect(struct intel_crt *crt) 541 { 542 struct drm_device *dev = crt->base.base.dev; 543 struct drm_i915_private *dev_priv = dev->dev_private; 544 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; 545 uint32_t save_bclrpat; 546 uint32_t save_vtotal; 547 uint32_t vtotal, vactive; 548 uint32_t vsample; 549 uint32_t vblank, vblank_start, vblank_end; 550 uint32_t dsl; 551 uint32_t bclrpat_reg; 552 uint32_t vtotal_reg; 553 uint32_t vblank_reg; 554 uint32_t vsync_reg; 555 uint32_t pipeconf_reg; 556 uint32_t pipe_dsl_reg; 557 uint8_t st00; 558 enum drm_connector_status status; 559 560 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 561 562 bclrpat_reg = BCLRPAT(pipe); 563 vtotal_reg = VTOTAL(pipe); 564 vblank_reg = VBLANK(pipe); 565 vsync_reg = VSYNC(pipe); 566 pipeconf_reg = PIPECONF(pipe); 567 pipe_dsl_reg = PIPEDSL(pipe); 568 569 save_bclrpat = I915_READ(bclrpat_reg); 570 save_vtotal = I915_READ(vtotal_reg); 571 vblank = I915_READ(vblank_reg); 572 573 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 574 vactive = (save_vtotal & 0x7ff) + 1; 575 576 vblank_start = (vblank & 0xfff) + 1; 577 vblank_end = ((vblank >> 16) & 0xfff) + 1; 578 579 /* Set the border color to purple. */ 580 I915_WRITE(bclrpat_reg, 0x500050); 581 582 if (!IS_GEN2(dev)) { 583 uint32_t pipeconf = I915_READ(pipeconf_reg); 584 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 585 POSTING_READ(pipeconf_reg); 586 /* Wait for next Vblank to substitue 587 * border color for Color info */ 588 intel_wait_for_vblank(dev, pipe); 589 st00 = I915_READ8(VGA_MSR_WRITE); 590 status = ((st00 & (1 << 4)) != 0) ? 591 connector_status_connected : 592 connector_status_disconnected; 593 594 I915_WRITE(pipeconf_reg, pipeconf); 595 } else { 596 bool restore_vblank = false; 597 int count, detect; 598 599 /* 600 * If there isn't any border, add some. 601 * Yes, this will flicker 602 */ 603 if (vblank_start <= vactive && vblank_end >= vtotal) { 604 uint32_t vsync = I915_READ(vsync_reg); 605 uint32_t vsync_start = (vsync & 0xffff) + 1; 606 607 vblank_start = vsync_start; 608 I915_WRITE(vblank_reg, 609 (vblank_start - 1) | 610 ((vblank_end - 1) << 16)); 611 restore_vblank = true; 612 } 613 /* sample in the vertical border, selecting the larger one */ 614 if (vblank_start - vactive >= vtotal - vblank_end) 615 vsample = (vblank_start + vactive) >> 1; 616 else 617 vsample = (vtotal + vblank_end) >> 1; 618 619 /* 620 * Wait for the border to be displayed 621 */ 622 while (I915_READ(pipe_dsl_reg) >= vactive) 623 ; 624 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 625 ; 626 /* 627 * Watch ST00 for an entire scanline 628 */ 629 detect = 0; 630 count = 0; 631 do { 632 count++; 633 /* Read the ST00 VGA status register */ 634 st00 = I915_READ8(VGA_MSR_WRITE); 635 if (st00 & (1 << 4)) 636 detect++; 637 } while ((I915_READ(pipe_dsl_reg) == dsl)); 638 639 /* restore vblank if necessary */ 640 if (restore_vblank) 641 I915_WRITE(vblank_reg, vblank); 642 /* 643 * If more than 3/4 of the scanline detected a monitor, 644 * then it is assumed to be present. This works even on i830, 645 * where there isn't any way to force the border color across 646 * the screen 647 */ 648 status = detect * 4 > count * 3 ? 649 connector_status_connected : 650 connector_status_disconnected; 651 } 652 653 /* Restore previous settings */ 654 I915_WRITE(bclrpat_reg, save_bclrpat); 655 656 return status; 657 } 658 659 static enum drm_connector_status 660 intel_crt_detect(struct drm_connector *connector, bool force) 661 { 662 struct drm_device *dev = connector->dev; 663 struct drm_i915_private *dev_priv = dev->dev_private; 664 struct intel_crt *crt = intel_attached_crt(connector); 665 struct intel_encoder *intel_encoder = &crt->base; 666 enum intel_display_power_domain power_domain; 667 enum drm_connector_status status; 668 struct intel_load_detect_pipe tmp; 669 struct drm_modeset_acquire_ctx ctx; 670 671 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 672 connector->base.id, connector->name, 673 force); 674 675 power_domain = intel_display_port_power_domain(intel_encoder); 676 intel_display_power_get(dev_priv, power_domain); 677 678 if (I915_HAS_HOTPLUG(dev)) { 679 /* We can not rely on the HPD pin always being correctly wired 680 * up, for example many KVM do not pass it through, and so 681 * only trust an assertion that the monitor is connected. 682 */ 683 if (intel_crt_detect_hotplug(connector)) { 684 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 685 status = connector_status_connected; 686 goto out; 687 } else 688 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 689 } 690 691 if (intel_crt_detect_ddc(connector)) { 692 status = connector_status_connected; 693 goto out; 694 } 695 696 /* Load detection is broken on HPD capable machines. Whoever wants a 697 * broken monitor (without edid) to work behind a broken kvm (that fails 698 * to have the right resistors for HP detection) needs to fix this up. 699 * For now just bail out. */ 700 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { 701 status = connector_status_disconnected; 702 goto out; 703 } 704 705 if (!force) { 706 status = connector->status; 707 goto out; 708 } 709 710 drm_modeset_acquire_init(&ctx, 0); 711 712 /* for pre-945g platforms use load detect */ 713 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 714 if (intel_crt_detect_ddc(connector)) 715 status = connector_status_connected; 716 else if (INTEL_INFO(dev)->gen < 4) 717 status = intel_crt_load_detect(crt); 718 else 719 status = connector_status_unknown; 720 intel_release_load_detect_pipe(connector, &tmp, &ctx); 721 } else 722 status = connector_status_unknown; 723 724 drm_modeset_drop_locks(&ctx); 725 drm_modeset_acquire_fini(&ctx); 726 727 out: 728 intel_display_power_put(dev_priv, power_domain); 729 return status; 730 } 731 732 static void intel_crt_destroy(struct drm_connector *connector) 733 { 734 drm_connector_cleanup(connector); 735 kfree(connector); 736 } 737 738 static int intel_crt_get_modes(struct drm_connector *connector) 739 { 740 struct drm_device *dev = connector->dev; 741 struct drm_i915_private *dev_priv = dev->dev_private; 742 struct intel_crt *crt = intel_attached_crt(connector); 743 struct intel_encoder *intel_encoder = &crt->base; 744 enum intel_display_power_domain power_domain; 745 int ret; 746 struct i2c_adapter *i2c; 747 748 power_domain = intel_display_port_power_domain(intel_encoder); 749 intel_display_power_get(dev_priv, power_domain); 750 751 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 752 ret = intel_crt_ddc_get_modes(connector, i2c); 753 if (ret || !IS_G4X(dev)) 754 goto out; 755 756 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 757 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 758 ret = intel_crt_ddc_get_modes(connector, i2c); 759 760 out: 761 intel_display_power_put(dev_priv, power_domain); 762 763 return ret; 764 } 765 766 static int intel_crt_set_property(struct drm_connector *connector, 767 struct drm_property *property, 768 uint64_t value) 769 { 770 return 0; 771 } 772 773 static void intel_crt_reset(struct drm_connector *connector) 774 { 775 struct drm_device *dev = connector->dev; 776 struct drm_i915_private *dev_priv = dev->dev_private; 777 struct intel_crt *crt = intel_attached_crt(connector); 778 779 if (INTEL_INFO(dev)->gen >= 5) { 780 u32 adpa; 781 782 adpa = I915_READ(crt->adpa_reg); 783 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 784 adpa |= ADPA_HOTPLUG_BITS; 785 I915_WRITE(crt->adpa_reg, adpa); 786 POSTING_READ(crt->adpa_reg); 787 788 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 789 crt->force_hotplug_required = 1; 790 } 791 792 } 793 794 /* 795 * Routines for controlling stuff on the analog port 796 */ 797 798 static const struct drm_connector_funcs intel_crt_connector_funcs = { 799 .reset = intel_crt_reset, 800 .dpms = intel_crt_dpms, 801 .detect = intel_crt_detect, 802 .fill_modes = drm_helper_probe_single_connector_modes, 803 .destroy = intel_crt_destroy, 804 .set_property = intel_crt_set_property, 805 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 806 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 807 .atomic_get_property = intel_connector_atomic_get_property, 808 }; 809 810 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 811 .mode_valid = intel_crt_mode_valid, 812 .get_modes = intel_crt_get_modes, 813 .best_encoder = intel_best_encoder, 814 }; 815 816 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 817 .destroy = intel_encoder_destroy, 818 }; 819 820 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 821 { 822 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 823 return 1; 824 } 825 826 static const struct dmi_system_id intel_no_crt[] = { 827 { 828 .callback = intel_no_crt_dmi_callback, 829 .ident = "ACER ZGB", 830 .matches = { 831 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 832 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 833 }, 834 }, 835 { 836 .callback = intel_no_crt_dmi_callback, 837 .ident = "DELL XPS 8700", 838 .matches = { 839 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 840 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 841 }, 842 }, 843 { } 844 }; 845 846 void intel_crt_init(struct drm_device *dev) 847 { 848 struct drm_connector *connector; 849 struct intel_crt *crt; 850 struct intel_connector *intel_connector; 851 struct drm_i915_private *dev_priv = dev->dev_private; 852 853 /* Skip machines without VGA that falsely report hotplug events */ 854 if (dmi_check_system(intel_no_crt)) 855 return; 856 857 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 858 if (!crt) 859 return; 860 861 intel_connector = intel_connector_alloc(); 862 if (!intel_connector) { 863 kfree(crt); 864 return; 865 } 866 867 connector = &intel_connector->base; 868 crt->connector = intel_connector; 869 drm_connector_init(dev, &intel_connector->base, 870 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 871 872 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 873 DRM_MODE_ENCODER_DAC); 874 875 intel_connector_attach_encoder(intel_connector, &crt->base); 876 877 crt->base.type = INTEL_OUTPUT_ANALOG; 878 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 879 if (IS_I830(dev)) 880 crt->base.crtc_mask = (1 << 0); 881 else 882 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 883 884 if (IS_GEN2(dev)) 885 connector->interlace_allowed = 0; 886 else 887 connector->interlace_allowed = 1; 888 connector->doublescan_allowed = 0; 889 890 if (HAS_PCH_SPLIT(dev)) 891 crt->adpa_reg = PCH_ADPA; 892 else if (IS_VALLEYVIEW(dev)) 893 crt->adpa_reg = VLV_ADPA; 894 else 895 crt->adpa_reg = ADPA; 896 897 crt->base.compute_config = intel_crt_compute_config; 898 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) { 899 crt->base.disable = pch_disable_crt; 900 crt->base.post_disable = pch_post_disable_crt; 901 } else { 902 crt->base.disable = intel_disable_crt; 903 } 904 crt->base.enable = intel_enable_crt; 905 if (I915_HAS_HOTPLUG(dev)) 906 crt->base.hpd_pin = HPD_CRT; 907 if (HAS_DDI(dev)) { 908 crt->base.get_config = hsw_crt_get_config; 909 crt->base.get_hw_state = intel_ddi_get_hw_state; 910 crt->base.pre_enable = hsw_crt_pre_enable; 911 crt->base.post_disable = hsw_crt_post_disable; 912 } else { 913 crt->base.get_config = intel_crt_get_config; 914 crt->base.get_hw_state = intel_crt_get_hw_state; 915 } 916 intel_connector->get_hw_state = intel_connector_get_hw_state; 917 intel_connector->unregister = intel_connector_unregister; 918 919 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 920 921 drm_connector_register(connector); 922 923 if (!I915_HAS_HOTPLUG(dev)) 924 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 925 926 /* 927 * Configure the automatic hotplug detection stuff 928 */ 929 crt->force_hotplug_required = 0; 930 931 /* 932 * TODO: find a proper way to discover whether we need to set the the 933 * polarity and link reversal bits or not, instead of relying on the 934 * BIOS. 935 */ 936 if (HAS_PCH_LPT(dev)) { 937 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 938 FDI_RX_LINK_REVERSAL_OVERRIDE; 939 940 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; 941 } 942 943 intel_crt_reset(connector); 944 } 945