1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 38 /* Here's the desired hotplug mode */ 39 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 40 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 41 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 42 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 43 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 44 ADPA_CRT_HOTPLUG_ENABLE) 45 46 struct intel_crt { 47 struct intel_encoder base; 48 /* DPMS state is stored in the connector, which we need in the 49 * encoder's enable/disable callbacks */ 50 struct intel_connector *connector; 51 bool force_hotplug_required; 52 i915_reg_t adpa_reg; 53 }; 54 55 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 56 { 57 return container_of(encoder, struct intel_crt, base); 58 } 59 60 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 61 { 62 return intel_encoder_to_crt(intel_attached_encoder(connector)); 63 } 64 65 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 66 enum i915_pipe *pipe) 67 { 68 struct drm_device *dev = encoder->base.dev; 69 struct drm_i915_private *dev_priv = dev->dev_private; 70 struct intel_crt *crt = intel_encoder_to_crt(encoder); 71 enum intel_display_power_domain power_domain; 72 u32 tmp; 73 bool ret; 74 75 power_domain = intel_display_port_power_domain(encoder); 76 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 77 return false; 78 79 ret = false; 80 81 tmp = I915_READ(crt->adpa_reg); 82 83 if (!(tmp & ADPA_DAC_ENABLE)) 84 goto out; 85 86 if (HAS_PCH_CPT(dev)) 87 *pipe = PORT_TO_PIPE_CPT(tmp); 88 else 89 *pipe = PORT_TO_PIPE(tmp); 90 91 ret = true; 92 out: 93 intel_display_power_put(dev_priv, power_domain); 94 95 return ret; 96 } 97 98 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 99 { 100 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 101 struct intel_crt *crt = intel_encoder_to_crt(encoder); 102 u32 tmp, flags = 0; 103 104 tmp = I915_READ(crt->adpa_reg); 105 106 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 107 flags |= DRM_MODE_FLAG_PHSYNC; 108 else 109 flags |= DRM_MODE_FLAG_NHSYNC; 110 111 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 112 flags |= DRM_MODE_FLAG_PVSYNC; 113 else 114 flags |= DRM_MODE_FLAG_NVSYNC; 115 116 return flags; 117 } 118 119 static void intel_crt_get_config(struct intel_encoder *encoder, 120 struct intel_crtc_state *pipe_config) 121 { 122 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 123 124 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 125 } 126 127 static void hsw_crt_get_config(struct intel_encoder *encoder, 128 struct intel_crtc_state *pipe_config) 129 { 130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 131 132 intel_ddi_get_config(encoder, pipe_config); 133 134 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 135 DRM_MODE_FLAG_NHSYNC | 136 DRM_MODE_FLAG_PVSYNC | 137 DRM_MODE_FLAG_NVSYNC); 138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 139 140 pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 141 } 142 143 /* Note: The caller is required to filter out dpms modes not supported by the 144 * platform. */ 145 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 146 { 147 struct drm_device *dev = encoder->base.dev; 148 struct drm_i915_private *dev_priv = dev->dev_private; 149 struct intel_crt *crt = intel_encoder_to_crt(encoder); 150 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 151 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 152 u32 adpa; 153 154 if (INTEL_INFO(dev)->gen >= 5) 155 adpa = ADPA_HOTPLUG_BITS; 156 else 157 adpa = 0; 158 159 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 160 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 161 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 162 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 163 164 /* For CPT allow 3 pipe config, for others just use A or B */ 165 if (HAS_PCH_LPT(dev)) 166 ; /* Those bits don't exist here */ 167 else if (HAS_PCH_CPT(dev)) 168 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 169 else if (crtc->pipe == 0) 170 adpa |= ADPA_PIPE_A_SELECT; 171 else 172 adpa |= ADPA_PIPE_B_SELECT; 173 174 if (!HAS_PCH_SPLIT(dev)) 175 I915_WRITE(BCLRPAT(crtc->pipe), 0); 176 177 switch (mode) { 178 case DRM_MODE_DPMS_ON: 179 adpa |= ADPA_DAC_ENABLE; 180 break; 181 case DRM_MODE_DPMS_STANDBY: 182 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 183 break; 184 case DRM_MODE_DPMS_SUSPEND: 185 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 186 break; 187 case DRM_MODE_DPMS_OFF: 188 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 189 break; 190 } 191 192 I915_WRITE(crt->adpa_reg, adpa); 193 } 194 195 static void intel_disable_crt(struct intel_encoder *encoder) 196 { 197 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 198 } 199 200 static void pch_disable_crt(struct intel_encoder *encoder) 201 { 202 } 203 204 static void pch_post_disable_crt(struct intel_encoder *encoder) 205 { 206 intel_disable_crt(encoder); 207 } 208 209 static void intel_enable_crt(struct intel_encoder *encoder) 210 { 211 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON); 212 } 213 214 static enum drm_mode_status 215 intel_crt_mode_valid(struct drm_connector *connector, 216 struct drm_display_mode *mode) 217 { 218 struct drm_device *dev = connector->dev; 219 int max_dotclk = to_i915(dev)->max_dotclk_freq; 220 int max_clock; 221 222 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 223 return MODE_NO_DBLESCAN; 224 225 if (mode->clock < 25000) 226 return MODE_CLOCK_LOW; 227 228 if (HAS_PCH_LPT(dev)) 229 max_clock = 180000; 230 else if (IS_VALLEYVIEW(dev)) 231 /* 232 * 270 MHz due to current DPLL limits, 233 * DAC limit supposedly 355 MHz. 234 */ 235 max_clock = 270000; 236 else if (IS_GEN3(dev) || IS_GEN4(dev)) 237 max_clock = 400000; 238 else 239 max_clock = 350000; 240 if (mode->clock > max_clock) 241 return MODE_CLOCK_HIGH; 242 243 if (mode->clock > max_dotclk) 244 return MODE_CLOCK_HIGH; 245 246 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 247 if (HAS_PCH_LPT(dev) && 248 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 249 return MODE_CLOCK_HIGH; 250 251 return MODE_OK; 252 } 253 254 static bool intel_crt_compute_config(struct intel_encoder *encoder, 255 struct intel_crtc_state *pipe_config) 256 { 257 struct drm_device *dev = encoder->base.dev; 258 259 if (HAS_PCH_SPLIT(dev)) 260 pipe_config->has_pch_encoder = true; 261 262 /* LPT FDI RX only supports 8bpc. */ 263 if (HAS_PCH_LPT(dev)) { 264 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 265 DRM_DEBUG_KMS("LPT only supports 24bpp\n"); 266 return false; 267 } 268 269 pipe_config->pipe_bpp = 24; 270 } 271 272 /* FDI must always be 2.7 GHz */ 273 if (HAS_DDI(dev)) 274 pipe_config->port_clock = 135000 * 2; 275 276 return true; 277 } 278 279 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 280 { 281 struct drm_device *dev = connector->dev; 282 struct intel_crt *crt = intel_attached_crt(connector); 283 struct drm_i915_private *dev_priv = dev->dev_private; 284 u32 adpa; 285 bool ret; 286 287 /* The first time through, trigger an explicit detection cycle */ 288 if (crt->force_hotplug_required) { 289 bool turn_off_dac = HAS_PCH_SPLIT(dev); 290 u32 save_adpa; 291 292 crt->force_hotplug_required = 0; 293 294 save_adpa = adpa = I915_READ(crt->adpa_reg); 295 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 296 297 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 298 if (turn_off_dac) 299 adpa &= ~ADPA_DAC_ENABLE; 300 301 I915_WRITE(crt->adpa_reg, adpa); 302 303 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 304 1000)) 305 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 306 307 if (turn_off_dac) { 308 I915_WRITE(crt->adpa_reg, save_adpa); 309 POSTING_READ(crt->adpa_reg); 310 } 311 } 312 313 /* Check the status to see if both blue and green are on now */ 314 adpa = I915_READ(crt->adpa_reg); 315 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 316 ret = true; 317 else 318 ret = false; 319 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 320 321 return ret; 322 } 323 324 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 325 { 326 struct drm_device *dev = connector->dev; 327 struct intel_crt *crt = intel_attached_crt(connector); 328 struct drm_i915_private *dev_priv = dev->dev_private; 329 bool reenable_hpd; 330 u32 adpa; 331 bool ret; 332 u32 save_adpa; 333 334 /* 335 * Doing a force trigger causes a hpd interrupt to get sent, which can 336 * get us stuck in a loop if we're polling: 337 * - We enable power wells and reset the ADPA 338 * - output_poll_exec does force probe on VGA, triggering a hpd 339 * - HPD handler waits for poll to unlock dev->mode_config.mutex 340 * - output_poll_exec shuts off the ADPA, unlocks 341 * dev->mode_config.mutex 342 * - HPD handler runs, resets ADPA and brings us back to the start 343 * 344 * Just disable HPD interrupts here to prevent this 345 */ 346 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 347 348 save_adpa = adpa = I915_READ(crt->adpa_reg); 349 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 350 351 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 352 353 I915_WRITE(crt->adpa_reg, adpa); 354 355 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 356 1000)) { 357 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 358 I915_WRITE(crt->adpa_reg, save_adpa); 359 } 360 361 /* Check the status to see if both blue and green are on now */ 362 adpa = I915_READ(crt->adpa_reg); 363 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 364 ret = true; 365 else 366 ret = false; 367 368 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 369 370 if (reenable_hpd) 371 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 372 373 return ret; 374 } 375 376 /** 377 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 378 * 379 * Not for i915G/i915GM 380 * 381 * \return true if CRT is connected. 382 * \return false if CRT is disconnected. 383 */ 384 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 385 { 386 struct drm_device *dev = connector->dev; 387 struct drm_i915_private *dev_priv = dev->dev_private; 388 u32 stat; 389 bool ret = false; 390 int i, tries = 0; 391 392 if (HAS_PCH_SPLIT(dev)) 393 return intel_ironlake_crt_detect_hotplug(connector); 394 395 if (IS_VALLEYVIEW(dev)) 396 return valleyview_crt_detect_hotplug(connector); 397 398 /* 399 * On 4 series desktop, CRT detect sequence need to be done twice 400 * to get a reliable result. 401 */ 402 403 if (IS_G4X(dev) && !IS_GM45(dev)) 404 tries = 2; 405 else 406 tries = 1; 407 408 for (i = 0; i < tries ; i++) { 409 /* turn on the FORCE_DETECT */ 410 i915_hotplug_interrupt_update(dev_priv, 411 CRT_HOTPLUG_FORCE_DETECT, 412 CRT_HOTPLUG_FORCE_DETECT); 413 /* wait for FORCE_DETECT to go off */ 414 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 415 CRT_HOTPLUG_FORCE_DETECT) == 0, 416 1000)) 417 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 418 } 419 420 stat = I915_READ(PORT_HOTPLUG_STAT); 421 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 422 ret = true; 423 424 /* clear the interrupt we just generated, if any */ 425 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 426 427 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 428 429 return ret; 430 } 431 432 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 433 struct i2c_adapter *i2c) 434 { 435 struct edid *edid; 436 437 edid = drm_get_edid(connector, i2c); 438 439 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 440 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 441 intel_gmbus_force_bit(i2c, true); 442 edid = drm_get_edid(connector, i2c); 443 intel_gmbus_force_bit(i2c, false); 444 } 445 446 return edid; 447 } 448 449 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 450 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 451 struct i2c_adapter *adapter) 452 { 453 struct edid *edid; 454 int ret; 455 456 edid = intel_crt_get_edid(connector, adapter); 457 if (!edid) 458 return 0; 459 460 ret = intel_connector_update_modes(connector, edid); 461 kfree(edid); 462 463 return ret; 464 } 465 466 static bool intel_crt_detect_ddc(struct drm_connector *connector) 467 { 468 struct intel_crt *crt = intel_attached_crt(connector); 469 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 470 struct edid *edid; 471 struct i2c_adapter *i2c; 472 473 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 474 475 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 476 edid = intel_crt_get_edid(connector, i2c); 477 478 if (edid) { 479 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 480 481 /* 482 * This may be a DVI-I connector with a shared DDC 483 * link between analog and digital outputs, so we 484 * have to check the EDID input spec of the attached device. 485 */ 486 if (!is_digital) { 487 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 488 return true; 489 } 490 491 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 492 } else { 493 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 494 } 495 496 kfree(edid); 497 498 return false; 499 } 500 501 static enum drm_connector_status 502 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) 503 { 504 struct drm_device *dev = crt->base.base.dev; 505 struct drm_i915_private *dev_priv = dev->dev_private; 506 uint32_t save_bclrpat; 507 uint32_t save_vtotal; 508 uint32_t vtotal, vactive; 509 uint32_t vsample; 510 uint32_t vblank, vblank_start, vblank_end; 511 uint32_t dsl; 512 i915_reg_t bclrpat_reg, vtotal_reg, 513 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 514 uint8_t st00; 515 enum drm_connector_status status; 516 517 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 518 519 bclrpat_reg = BCLRPAT(pipe); 520 vtotal_reg = VTOTAL(pipe); 521 vblank_reg = VBLANK(pipe); 522 vsync_reg = VSYNC(pipe); 523 pipeconf_reg = PIPECONF(pipe); 524 pipe_dsl_reg = PIPEDSL(pipe); 525 526 save_bclrpat = I915_READ(bclrpat_reg); 527 save_vtotal = I915_READ(vtotal_reg); 528 vblank = I915_READ(vblank_reg); 529 530 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 531 vactive = (save_vtotal & 0x7ff) + 1; 532 533 vblank_start = (vblank & 0xfff) + 1; 534 vblank_end = ((vblank >> 16) & 0xfff) + 1; 535 536 /* Set the border color to purple. */ 537 I915_WRITE(bclrpat_reg, 0x500050); 538 539 if (!IS_GEN2(dev)) { 540 uint32_t pipeconf = I915_READ(pipeconf_reg); 541 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 542 POSTING_READ(pipeconf_reg); 543 /* Wait for next Vblank to substitue 544 * border color for Color info */ 545 intel_wait_for_vblank(dev, pipe); 546 st00 = I915_READ8(_VGA_MSR_WRITE); 547 status = ((st00 & (1 << 4)) != 0) ? 548 connector_status_connected : 549 connector_status_disconnected; 550 551 I915_WRITE(pipeconf_reg, pipeconf); 552 } else { 553 bool restore_vblank = false; 554 int count, detect; 555 556 /* 557 * If there isn't any border, add some. 558 * Yes, this will flicker 559 */ 560 if (vblank_start <= vactive && vblank_end >= vtotal) { 561 uint32_t vsync = I915_READ(vsync_reg); 562 uint32_t vsync_start = (vsync & 0xffff) + 1; 563 564 vblank_start = vsync_start; 565 I915_WRITE(vblank_reg, 566 (vblank_start - 1) | 567 ((vblank_end - 1) << 16)); 568 restore_vblank = true; 569 } 570 /* sample in the vertical border, selecting the larger one */ 571 if (vblank_start - vactive >= vtotal - vblank_end) 572 vsample = (vblank_start + vactive) >> 1; 573 else 574 vsample = (vtotal + vblank_end) >> 1; 575 576 /* 577 * Wait for the border to be displayed 578 */ 579 while (I915_READ(pipe_dsl_reg) >= vactive) 580 ; 581 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 582 ; 583 /* 584 * Watch ST00 for an entire scanline 585 */ 586 detect = 0; 587 count = 0; 588 do { 589 count++; 590 /* Read the ST00 VGA status register */ 591 st00 = I915_READ8(_VGA_MSR_WRITE); 592 if (st00 & (1 << 4)) 593 detect++; 594 } while ((I915_READ(pipe_dsl_reg) == dsl)); 595 596 /* restore vblank if necessary */ 597 if (restore_vblank) 598 I915_WRITE(vblank_reg, vblank); 599 /* 600 * If more than 3/4 of the scanline detected a monitor, 601 * then it is assumed to be present. This works even on i830, 602 * where there isn't any way to force the border color across 603 * the screen 604 */ 605 status = detect * 4 > count * 3 ? 606 connector_status_connected : 607 connector_status_disconnected; 608 } 609 610 /* Restore previous settings */ 611 I915_WRITE(bclrpat_reg, save_bclrpat); 612 613 return status; 614 } 615 616 static enum drm_connector_status 617 intel_crt_detect(struct drm_connector *connector, bool force) 618 { 619 struct drm_device *dev = connector->dev; 620 struct drm_i915_private *dev_priv = dev->dev_private; 621 struct intel_crt *crt = intel_attached_crt(connector); 622 struct intel_encoder *intel_encoder = &crt->base; 623 enum intel_display_power_domain power_domain; 624 enum drm_connector_status status; 625 struct intel_load_detect_pipe tmp; 626 struct drm_modeset_acquire_ctx ctx; 627 628 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 629 connector->base.id, connector->name, 630 force); 631 632 power_domain = intel_display_port_power_domain(intel_encoder); 633 intel_display_power_get(dev_priv, power_domain); 634 635 if (I915_HAS_HOTPLUG(dev)) { 636 /* We can not rely on the HPD pin always being correctly wired 637 * up, for example many KVM do not pass it through, and so 638 * only trust an assertion that the monitor is connected. 639 */ 640 if (intel_crt_detect_hotplug(connector)) { 641 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 642 status = connector_status_connected; 643 goto out; 644 } else 645 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 646 } 647 648 if (intel_crt_detect_ddc(connector)) { 649 status = connector_status_connected; 650 goto out; 651 } 652 653 /* Load detection is broken on HPD capable machines. Whoever wants a 654 * broken monitor (without edid) to work behind a broken kvm (that fails 655 * to have the right resistors for HP detection) needs to fix this up. 656 * For now just bail out. */ 657 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { 658 status = connector_status_disconnected; 659 goto out; 660 } 661 662 if (!force) { 663 status = connector->status; 664 goto out; 665 } 666 667 drm_modeset_acquire_init(&ctx, 0); 668 669 /* for pre-945g platforms use load detect */ 670 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 671 if (intel_crt_detect_ddc(connector)) 672 status = connector_status_connected; 673 else if (INTEL_INFO(dev)->gen < 4) 674 status = intel_crt_load_detect(crt, 675 to_intel_crtc(connector->state->crtc)->pipe); 676 else if (i915.load_detect_test) 677 status = connector_status_disconnected; 678 else 679 status = connector_status_unknown; 680 intel_release_load_detect_pipe(connector, &tmp, &ctx); 681 } else 682 status = connector_status_unknown; 683 684 drm_modeset_drop_locks(&ctx); 685 drm_modeset_acquire_fini(&ctx); 686 687 out: 688 intel_display_power_put(dev_priv, power_domain); 689 return status; 690 } 691 692 static void intel_crt_destroy(struct drm_connector *connector) 693 { 694 drm_connector_cleanup(connector); 695 kfree(connector); 696 } 697 698 static int intel_crt_get_modes(struct drm_connector *connector) 699 { 700 struct drm_device *dev = connector->dev; 701 struct drm_i915_private *dev_priv = dev->dev_private; 702 struct intel_crt *crt = intel_attached_crt(connector); 703 struct intel_encoder *intel_encoder = &crt->base; 704 enum intel_display_power_domain power_domain; 705 int ret; 706 struct i2c_adapter *i2c; 707 708 power_domain = intel_display_port_power_domain(intel_encoder); 709 intel_display_power_get(dev_priv, power_domain); 710 711 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 712 ret = intel_crt_ddc_get_modes(connector, i2c); 713 if (ret || !IS_G4X(dev)) 714 goto out; 715 716 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 717 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 718 ret = intel_crt_ddc_get_modes(connector, i2c); 719 720 out: 721 intel_display_power_put(dev_priv, power_domain); 722 723 return ret; 724 } 725 726 static int intel_crt_set_property(struct drm_connector *connector, 727 struct drm_property *property, 728 uint64_t value) 729 { 730 return 0; 731 } 732 733 void intel_crt_reset(struct drm_encoder *encoder) 734 { 735 struct drm_device *dev = encoder->dev; 736 struct drm_i915_private *dev_priv = dev->dev_private; 737 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 738 739 if (INTEL_INFO(dev)->gen >= 5) { 740 u32 adpa; 741 742 adpa = I915_READ(crt->adpa_reg); 743 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 744 adpa |= ADPA_HOTPLUG_BITS; 745 I915_WRITE(crt->adpa_reg, adpa); 746 POSTING_READ(crt->adpa_reg); 747 748 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 749 crt->force_hotplug_required = 1; 750 } 751 752 } 753 754 /* 755 * Routines for controlling stuff on the analog port 756 */ 757 758 static const struct drm_connector_funcs intel_crt_connector_funcs = { 759 .dpms = drm_atomic_helper_connector_dpms, 760 .detect = intel_crt_detect, 761 .fill_modes = drm_helper_probe_single_connector_modes, 762 .destroy = intel_crt_destroy, 763 .set_property = intel_crt_set_property, 764 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 765 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 766 .atomic_get_property = intel_connector_atomic_get_property, 767 }; 768 769 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 770 .mode_valid = intel_crt_mode_valid, 771 .get_modes = intel_crt_get_modes, 772 .best_encoder = intel_best_encoder, 773 }; 774 775 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 776 .reset = intel_crt_reset, 777 .destroy = intel_encoder_destroy, 778 }; 779 780 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 781 { 782 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 783 return 1; 784 } 785 786 static const struct dmi_system_id intel_no_crt[] = { 787 { 788 .callback = intel_no_crt_dmi_callback, 789 .ident = "ACER ZGB", 790 .matches = { 791 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 792 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 793 }, 794 }, 795 { 796 .callback = intel_no_crt_dmi_callback, 797 .ident = "DELL XPS 8700", 798 .matches = { 799 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 800 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 801 }, 802 }, 803 { } 804 }; 805 806 void intel_crt_init(struct drm_device *dev) 807 { 808 struct drm_connector *connector; 809 struct intel_crt *crt; 810 struct intel_connector *intel_connector; 811 struct drm_i915_private *dev_priv = dev->dev_private; 812 i915_reg_t adpa_reg; 813 u32 adpa; 814 815 /* Skip machines without VGA that falsely report hotplug events */ 816 if (dmi_check_system(intel_no_crt)) 817 return; 818 819 if (HAS_PCH_SPLIT(dev)) 820 adpa_reg = PCH_ADPA; 821 else if (IS_VALLEYVIEW(dev)) 822 adpa_reg = VLV_ADPA; 823 else 824 adpa_reg = ADPA; 825 826 adpa = I915_READ(adpa_reg); 827 if ((adpa & ADPA_DAC_ENABLE) == 0) { 828 /* 829 * On some machines (some IVB at least) CRT can be 830 * fused off, but there's no known fuse bit to 831 * indicate that. On these machine the ADPA register 832 * works normally, except the DAC enable bit won't 833 * take. So the only way to tell is attempt to enable 834 * it and see what happens. 835 */ 836 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | 837 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 838 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) 839 return; 840 I915_WRITE(adpa_reg, adpa); 841 } 842 843 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 844 if (!crt) 845 return; 846 847 intel_connector = intel_connector_alloc(); 848 if (!intel_connector) { 849 kfree(crt); 850 return; 851 } 852 853 connector = &intel_connector->base; 854 crt->connector = intel_connector; 855 drm_connector_init(dev, &intel_connector->base, 856 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 857 858 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 859 DRM_MODE_ENCODER_DAC, NULL); 860 861 intel_connector_attach_encoder(intel_connector, &crt->base); 862 863 crt->base.type = INTEL_OUTPUT_ANALOG; 864 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 865 if (IS_I830(dev)) 866 crt->base.crtc_mask = (1 << 0); 867 else 868 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 869 870 if (IS_GEN2(dev)) 871 connector->interlace_allowed = 0; 872 else 873 connector->interlace_allowed = 1; 874 connector->doublescan_allowed = 0; 875 876 crt->adpa_reg = adpa_reg; 877 878 crt->base.compute_config = intel_crt_compute_config; 879 if (HAS_PCH_SPLIT(dev)) { 880 crt->base.disable = pch_disable_crt; 881 crt->base.post_disable = pch_post_disable_crt; 882 } else { 883 crt->base.disable = intel_disable_crt; 884 } 885 crt->base.enable = intel_enable_crt; 886 if (I915_HAS_HOTPLUG(dev)) 887 crt->base.hpd_pin = HPD_CRT; 888 if (HAS_DDI(dev)) { 889 crt->base.get_config = hsw_crt_get_config; 890 crt->base.get_hw_state = intel_ddi_get_hw_state; 891 } else { 892 crt->base.get_config = intel_crt_get_config; 893 crt->base.get_hw_state = intel_crt_get_hw_state; 894 } 895 intel_connector->get_hw_state = intel_connector_get_hw_state; 896 intel_connector->unregister = intel_connector_unregister; 897 898 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 899 900 drm_connector_register(connector); 901 902 if (!I915_HAS_HOTPLUG(dev)) 903 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 904 905 /* 906 * Configure the automatic hotplug detection stuff 907 */ 908 crt->force_hotplug_required = 0; 909 910 /* 911 * TODO: find a proper way to discover whether we need to set the the 912 * polarity and link reversal bits or not, instead of relying on the 913 * BIOS. 914 */ 915 if (HAS_PCH_LPT(dev)) { 916 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 917 FDI_RX_LINK_REVERSAL_OVERRIDE; 918 919 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; 920 } 921 922 intel_crt_reset(&crt->base.base); 923 } 924