1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 38 /* Here's the desired hotplug mode */ 39 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 40 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 41 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 42 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 43 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 44 ADPA_CRT_HOTPLUG_ENABLE) 45 46 struct intel_crt { 47 struct intel_encoder base; 48 /* DPMS state is stored in the connector, which we need in the 49 * encoder's enable/disable callbacks */ 50 struct intel_connector *connector; 51 bool force_hotplug_required; 52 u32 adpa_reg; 53 }; 54 55 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 56 { 57 return container_of(encoder, struct intel_crt, base); 58 } 59 60 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 61 { 62 return intel_encoder_to_crt(intel_attached_encoder(connector)); 63 } 64 65 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 66 enum i915_pipe *pipe) 67 { 68 struct drm_device *dev = encoder->base.dev; 69 struct drm_i915_private *dev_priv = dev->dev_private; 70 struct intel_crt *crt = intel_encoder_to_crt(encoder); 71 enum intel_display_power_domain power_domain; 72 u32 tmp; 73 74 power_domain = intel_display_port_power_domain(encoder); 75 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 76 return false; 77 78 tmp = I915_READ(crt->adpa_reg); 79 80 if (!(tmp & ADPA_DAC_ENABLE)) 81 return false; 82 83 if (HAS_PCH_CPT(dev)) 84 *pipe = PORT_TO_PIPE_CPT(tmp); 85 else 86 *pipe = PORT_TO_PIPE(tmp); 87 88 return true; 89 } 90 91 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 92 { 93 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 94 struct intel_crt *crt = intel_encoder_to_crt(encoder); 95 u32 tmp, flags = 0; 96 97 tmp = I915_READ(crt->adpa_reg); 98 99 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 100 flags |= DRM_MODE_FLAG_PHSYNC; 101 else 102 flags |= DRM_MODE_FLAG_NHSYNC; 103 104 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 105 flags |= DRM_MODE_FLAG_PVSYNC; 106 else 107 flags |= DRM_MODE_FLAG_NVSYNC; 108 109 return flags; 110 } 111 112 static void intel_crt_get_config(struct intel_encoder *encoder, 113 struct intel_crtc_state *pipe_config) 114 { 115 struct drm_device *dev = encoder->base.dev; 116 int dotclock; 117 118 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 119 120 dotclock = pipe_config->port_clock; 121 122 if (HAS_PCH_SPLIT(dev)) 123 ironlake_check_encoder_dotclock(pipe_config, dotclock); 124 125 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 126 } 127 128 static void hsw_crt_get_config(struct intel_encoder *encoder, 129 struct intel_crtc_state *pipe_config) 130 { 131 intel_ddi_get_config(encoder, pipe_config); 132 133 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 134 DRM_MODE_FLAG_NHSYNC | 135 DRM_MODE_FLAG_PVSYNC | 136 DRM_MODE_FLAG_NVSYNC); 137 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 138 } 139 140 static void hsw_crt_pre_enable(struct intel_encoder *encoder) 141 { 142 struct drm_device *dev = encoder->base.dev; 143 struct drm_i915_private *dev_priv = dev->dev_private; 144 145 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); 146 I915_WRITE(SPLL_CTL, 147 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); 148 POSTING_READ(SPLL_CTL); 149 udelay(20); 150 } 151 152 /* Note: The caller is required to filter out dpms modes not supported by the 153 * platform. */ 154 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 155 { 156 struct drm_device *dev = encoder->base.dev; 157 struct drm_i915_private *dev_priv = dev->dev_private; 158 struct intel_crt *crt = intel_encoder_to_crt(encoder); 159 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 160 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 161 u32 adpa; 162 163 if (INTEL_INFO(dev)->gen >= 5) 164 adpa = ADPA_HOTPLUG_BITS; 165 else 166 adpa = 0; 167 168 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 169 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 170 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 171 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 172 173 /* For CPT allow 3 pipe config, for others just use A or B */ 174 if (HAS_PCH_LPT(dev)) 175 ; /* Those bits don't exist here */ 176 else if (HAS_PCH_CPT(dev)) 177 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 178 else if (crtc->pipe == 0) 179 adpa |= ADPA_PIPE_A_SELECT; 180 else 181 adpa |= ADPA_PIPE_B_SELECT; 182 183 if (!HAS_PCH_SPLIT(dev)) 184 I915_WRITE(BCLRPAT(crtc->pipe), 0); 185 186 switch (mode) { 187 case DRM_MODE_DPMS_ON: 188 adpa |= ADPA_DAC_ENABLE; 189 break; 190 case DRM_MODE_DPMS_STANDBY: 191 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 192 break; 193 case DRM_MODE_DPMS_SUSPEND: 194 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 195 break; 196 case DRM_MODE_DPMS_OFF: 197 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 198 break; 199 } 200 201 I915_WRITE(crt->adpa_reg, adpa); 202 } 203 204 static void intel_disable_crt(struct intel_encoder *encoder) 205 { 206 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 207 } 208 209 static void pch_disable_crt(struct intel_encoder *encoder) 210 { 211 } 212 213 static void pch_post_disable_crt(struct intel_encoder *encoder) 214 { 215 intel_disable_crt(encoder); 216 } 217 218 static void hsw_crt_post_disable(struct intel_encoder *encoder) 219 { 220 struct drm_device *dev = encoder->base.dev; 221 struct drm_i915_private *dev_priv = dev->dev_private; 222 uint32_t val; 223 224 DRM_DEBUG_KMS("Disabling SPLL\n"); 225 val = I915_READ(SPLL_CTL); 226 WARN_ON(!(val & SPLL_PLL_ENABLE)); 227 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 228 POSTING_READ(SPLL_CTL); 229 } 230 231 static void intel_enable_crt(struct intel_encoder *encoder) 232 { 233 struct intel_crt *crt = intel_encoder_to_crt(encoder); 234 235 intel_crt_set_dpms(encoder, crt->connector->base.dpms); 236 } 237 238 static enum drm_mode_status 239 intel_crt_mode_valid(struct drm_connector *connector, 240 struct drm_display_mode *mode) 241 { 242 struct drm_device *dev = connector->dev; 243 244 int max_clock = 0; 245 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 246 return MODE_NO_DBLESCAN; 247 248 if (mode->clock < 25000) 249 return MODE_CLOCK_LOW; 250 251 if (IS_GEN2(dev)) 252 max_clock = 350000; 253 else 254 max_clock = 400000; 255 if (mode->clock > max_clock) 256 return MODE_CLOCK_HIGH; 257 258 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 259 if (HAS_PCH_LPT(dev) && 260 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 261 return MODE_CLOCK_HIGH; 262 263 return MODE_OK; 264 } 265 266 static bool intel_crt_compute_config(struct intel_encoder *encoder, 267 struct intel_crtc_state *pipe_config) 268 { 269 struct drm_device *dev = encoder->base.dev; 270 271 if (HAS_PCH_SPLIT(dev)) 272 pipe_config->has_pch_encoder = true; 273 274 /* LPT FDI RX only supports 8bpc. */ 275 if (HAS_PCH_LPT(dev)) 276 pipe_config->pipe_bpp = 24; 277 278 /* FDI must always be 2.7 GHz */ 279 if (HAS_DDI(dev)) { 280 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; 281 pipe_config->port_clock = 135000 * 2; 282 } 283 284 return true; 285 } 286 287 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 288 { 289 struct drm_device *dev = connector->dev; 290 struct intel_crt *crt = intel_attached_crt(connector); 291 struct drm_i915_private *dev_priv = dev->dev_private; 292 u32 adpa; 293 bool ret; 294 295 /* The first time through, trigger an explicit detection cycle */ 296 if (crt->force_hotplug_required) { 297 bool turn_off_dac = HAS_PCH_SPLIT(dev); 298 u32 save_adpa; 299 300 crt->force_hotplug_required = 0; 301 302 save_adpa = adpa = I915_READ(crt->adpa_reg); 303 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 304 305 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 306 if (turn_off_dac) 307 adpa &= ~ADPA_DAC_ENABLE; 308 309 I915_WRITE(crt->adpa_reg, adpa); 310 311 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 312 1000)) 313 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 314 315 if (turn_off_dac) { 316 I915_WRITE(crt->adpa_reg, save_adpa); 317 POSTING_READ(crt->adpa_reg); 318 } 319 } 320 321 /* Check the status to see if both blue and green are on now */ 322 adpa = I915_READ(crt->adpa_reg); 323 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 324 ret = true; 325 else 326 ret = false; 327 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 328 329 return ret; 330 } 331 332 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 333 { 334 struct drm_device *dev = connector->dev; 335 struct intel_crt *crt = intel_attached_crt(connector); 336 struct drm_i915_private *dev_priv = dev->dev_private; 337 u32 adpa; 338 bool ret; 339 u32 save_adpa; 340 341 save_adpa = adpa = I915_READ(crt->adpa_reg); 342 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 343 344 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 345 346 I915_WRITE(crt->adpa_reg, adpa); 347 348 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 349 1000)) { 350 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 351 I915_WRITE(crt->adpa_reg, save_adpa); 352 } 353 354 /* Check the status to see if both blue and green are on now */ 355 adpa = I915_READ(crt->adpa_reg); 356 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 357 ret = true; 358 else 359 ret = false; 360 361 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 362 363 return ret; 364 } 365 366 /** 367 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 368 * 369 * Not for i915G/i915GM 370 * 371 * \return true if CRT is connected. 372 * \return false if CRT is disconnected. 373 */ 374 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 375 { 376 struct drm_device *dev = connector->dev; 377 struct drm_i915_private *dev_priv = dev->dev_private; 378 u32 hotplug_en, orig, stat; 379 bool ret = false; 380 int i, tries = 0; 381 382 if (HAS_PCH_SPLIT(dev)) 383 return intel_ironlake_crt_detect_hotplug(connector); 384 385 if (IS_VALLEYVIEW(dev)) 386 return valleyview_crt_detect_hotplug(connector); 387 388 /* 389 * On 4 series desktop, CRT detect sequence need to be done twice 390 * to get a reliable result. 391 */ 392 393 if (IS_G4X(dev) && !IS_GM45(dev)) 394 tries = 2; 395 else 396 tries = 1; 397 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); 398 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 399 400 for (i = 0; i < tries ; i++) { 401 /* turn on the FORCE_DETECT */ 402 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 403 /* wait for FORCE_DETECT to go off */ 404 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 405 CRT_HOTPLUG_FORCE_DETECT) == 0, 406 1000)) 407 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 408 } 409 410 stat = I915_READ(PORT_HOTPLUG_STAT); 411 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 412 ret = true; 413 414 /* clear the interrupt we just generated, if any */ 415 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 416 417 /* and put the bits back */ 418 I915_WRITE(PORT_HOTPLUG_EN, orig); 419 420 return ret; 421 } 422 423 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 424 struct i2c_adapter *i2c) 425 { 426 struct edid *edid; 427 428 edid = drm_get_edid(connector, i2c); 429 430 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 431 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 432 intel_gmbus_force_bit(i2c, true); 433 edid = drm_get_edid(connector, i2c); 434 intel_gmbus_force_bit(i2c, false); 435 } 436 437 return edid; 438 } 439 440 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 441 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 442 struct i2c_adapter *adapter) 443 { 444 struct edid *edid; 445 int ret; 446 447 edid = intel_crt_get_edid(connector, adapter); 448 if (!edid) 449 return 0; 450 451 ret = intel_connector_update_modes(connector, edid); 452 kfree(edid); 453 454 return ret; 455 } 456 457 static bool intel_crt_detect_ddc(struct drm_connector *connector) 458 { 459 struct intel_crt *crt = intel_attached_crt(connector); 460 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 461 struct edid *edid; 462 struct i2c_adapter *i2c; 463 464 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 465 466 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 467 edid = intel_crt_get_edid(connector, i2c); 468 469 if (edid) { 470 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 471 472 /* 473 * This may be a DVI-I connector with a shared DDC 474 * link between analog and digital outputs, so we 475 * have to check the EDID input spec of the attached device. 476 */ 477 if (!is_digital) { 478 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 479 return true; 480 } 481 482 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 483 } else { 484 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 485 } 486 487 kfree(edid); 488 489 return false; 490 } 491 492 static enum drm_connector_status 493 intel_crt_load_detect(struct intel_crt *crt) 494 { 495 struct drm_device *dev = crt->base.base.dev; 496 struct drm_i915_private *dev_priv = dev->dev_private; 497 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; 498 uint32_t save_bclrpat; 499 uint32_t save_vtotal; 500 uint32_t vtotal, vactive; 501 uint32_t vsample; 502 uint32_t vblank, vblank_start, vblank_end; 503 uint32_t dsl; 504 uint32_t bclrpat_reg; 505 uint32_t vtotal_reg; 506 uint32_t vblank_reg; 507 uint32_t vsync_reg; 508 uint32_t pipeconf_reg; 509 uint32_t pipe_dsl_reg; 510 uint8_t st00; 511 enum drm_connector_status status; 512 513 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 514 515 bclrpat_reg = BCLRPAT(pipe); 516 vtotal_reg = VTOTAL(pipe); 517 vblank_reg = VBLANK(pipe); 518 vsync_reg = VSYNC(pipe); 519 pipeconf_reg = PIPECONF(pipe); 520 pipe_dsl_reg = PIPEDSL(pipe); 521 522 save_bclrpat = I915_READ(bclrpat_reg); 523 save_vtotal = I915_READ(vtotal_reg); 524 vblank = I915_READ(vblank_reg); 525 526 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 527 vactive = (save_vtotal & 0x7ff) + 1; 528 529 vblank_start = (vblank & 0xfff) + 1; 530 vblank_end = ((vblank >> 16) & 0xfff) + 1; 531 532 /* Set the border color to purple. */ 533 I915_WRITE(bclrpat_reg, 0x500050); 534 535 if (!IS_GEN2(dev)) { 536 uint32_t pipeconf = I915_READ(pipeconf_reg); 537 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 538 POSTING_READ(pipeconf_reg); 539 /* Wait for next Vblank to substitue 540 * border color for Color info */ 541 intel_wait_for_vblank(dev, pipe); 542 st00 = I915_READ8(VGA_MSR_WRITE); 543 status = ((st00 & (1 << 4)) != 0) ? 544 connector_status_connected : 545 connector_status_disconnected; 546 547 I915_WRITE(pipeconf_reg, pipeconf); 548 } else { 549 bool restore_vblank = false; 550 int count, detect; 551 552 /* 553 * If there isn't any border, add some. 554 * Yes, this will flicker 555 */ 556 if (vblank_start <= vactive && vblank_end >= vtotal) { 557 uint32_t vsync = I915_READ(vsync_reg); 558 uint32_t vsync_start = (vsync & 0xffff) + 1; 559 560 vblank_start = vsync_start; 561 I915_WRITE(vblank_reg, 562 (vblank_start - 1) | 563 ((vblank_end - 1) << 16)); 564 restore_vblank = true; 565 } 566 /* sample in the vertical border, selecting the larger one */ 567 if (vblank_start - vactive >= vtotal - vblank_end) 568 vsample = (vblank_start + vactive) >> 1; 569 else 570 vsample = (vtotal + vblank_end) >> 1; 571 572 /* 573 * Wait for the border to be displayed 574 */ 575 while (I915_READ(pipe_dsl_reg) >= vactive) 576 ; 577 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 578 ; 579 /* 580 * Watch ST00 for an entire scanline 581 */ 582 detect = 0; 583 count = 0; 584 do { 585 count++; 586 /* Read the ST00 VGA status register */ 587 st00 = I915_READ8(VGA_MSR_WRITE); 588 if (st00 & (1 << 4)) 589 detect++; 590 } while ((I915_READ(pipe_dsl_reg) == dsl)); 591 592 /* restore vblank if necessary */ 593 if (restore_vblank) 594 I915_WRITE(vblank_reg, vblank); 595 /* 596 * If more than 3/4 of the scanline detected a monitor, 597 * then it is assumed to be present. This works even on i830, 598 * where there isn't any way to force the border color across 599 * the screen 600 */ 601 status = detect * 4 > count * 3 ? 602 connector_status_connected : 603 connector_status_disconnected; 604 } 605 606 /* Restore previous settings */ 607 I915_WRITE(bclrpat_reg, save_bclrpat); 608 609 return status; 610 } 611 612 static enum drm_connector_status 613 intel_crt_detect(struct drm_connector *connector, bool force) 614 { 615 struct drm_device *dev = connector->dev; 616 struct drm_i915_private *dev_priv = dev->dev_private; 617 struct intel_crt *crt = intel_attached_crt(connector); 618 struct intel_encoder *intel_encoder = &crt->base; 619 enum intel_display_power_domain power_domain; 620 enum drm_connector_status status; 621 struct intel_load_detect_pipe tmp; 622 struct drm_modeset_acquire_ctx ctx; 623 624 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 625 connector->base.id, connector->name, 626 force); 627 628 power_domain = intel_display_port_power_domain(intel_encoder); 629 intel_display_power_get(dev_priv, power_domain); 630 631 if (I915_HAS_HOTPLUG(dev)) { 632 /* We can not rely on the HPD pin always being correctly wired 633 * up, for example many KVM do not pass it through, and so 634 * only trust an assertion that the monitor is connected. 635 */ 636 if (intel_crt_detect_hotplug(connector)) { 637 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 638 status = connector_status_connected; 639 goto out; 640 } else 641 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 642 } 643 644 if (intel_crt_detect_ddc(connector)) { 645 status = connector_status_connected; 646 goto out; 647 } 648 649 /* Load detection is broken on HPD capable machines. Whoever wants a 650 * broken monitor (without edid) to work behind a broken kvm (that fails 651 * to have the right resistors for HP detection) needs to fix this up. 652 * For now just bail out. */ 653 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { 654 status = connector_status_disconnected; 655 goto out; 656 } 657 658 if (!force) { 659 status = connector->status; 660 goto out; 661 } 662 663 drm_modeset_acquire_init(&ctx, 0); 664 665 /* for pre-945g platforms use load detect */ 666 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 667 if (intel_crt_detect_ddc(connector)) 668 status = connector_status_connected; 669 else if (INTEL_INFO(dev)->gen < 4) 670 status = intel_crt_load_detect(crt); 671 else 672 status = connector_status_unknown; 673 intel_release_load_detect_pipe(connector, &tmp, &ctx); 674 } else 675 status = connector_status_unknown; 676 677 drm_modeset_drop_locks(&ctx); 678 drm_modeset_acquire_fini(&ctx); 679 680 out: 681 intel_display_power_put(dev_priv, power_domain); 682 return status; 683 } 684 685 static void intel_crt_destroy(struct drm_connector *connector) 686 { 687 drm_connector_cleanup(connector); 688 kfree(connector); 689 } 690 691 static int intel_crt_get_modes(struct drm_connector *connector) 692 { 693 struct drm_device *dev = connector->dev; 694 struct drm_i915_private *dev_priv = dev->dev_private; 695 struct intel_crt *crt = intel_attached_crt(connector); 696 struct intel_encoder *intel_encoder = &crt->base; 697 enum intel_display_power_domain power_domain; 698 int ret; 699 struct i2c_adapter *i2c; 700 701 power_domain = intel_display_port_power_domain(intel_encoder); 702 intel_display_power_get(dev_priv, power_domain); 703 704 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 705 ret = intel_crt_ddc_get_modes(connector, i2c); 706 if (ret || !IS_G4X(dev)) 707 goto out; 708 709 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 710 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 711 ret = intel_crt_ddc_get_modes(connector, i2c); 712 713 out: 714 intel_display_power_put(dev_priv, power_domain); 715 716 return ret; 717 } 718 719 static int intel_crt_set_property(struct drm_connector *connector, 720 struct drm_property *property, 721 uint64_t value) 722 { 723 return 0; 724 } 725 726 static void intel_crt_reset(struct drm_connector *connector) 727 { 728 struct drm_device *dev = connector->dev; 729 struct drm_i915_private *dev_priv = dev->dev_private; 730 struct intel_crt *crt = intel_attached_crt(connector); 731 732 if (INTEL_INFO(dev)->gen >= 5) { 733 u32 adpa; 734 735 adpa = I915_READ(crt->adpa_reg); 736 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 737 adpa |= ADPA_HOTPLUG_BITS; 738 I915_WRITE(crt->adpa_reg, adpa); 739 POSTING_READ(crt->adpa_reg); 740 741 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 742 crt->force_hotplug_required = 1; 743 } 744 745 } 746 747 /* 748 * Routines for controlling stuff on the analog port 749 */ 750 751 static const struct drm_connector_funcs intel_crt_connector_funcs = { 752 .reset = intel_crt_reset, 753 .dpms = drm_atomic_helper_connector_dpms, 754 .detect = intel_crt_detect, 755 .fill_modes = drm_helper_probe_single_connector_modes, 756 .destroy = intel_crt_destroy, 757 .set_property = intel_crt_set_property, 758 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 759 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 760 .atomic_get_property = intel_connector_atomic_get_property, 761 }; 762 763 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 764 .mode_valid = intel_crt_mode_valid, 765 .get_modes = intel_crt_get_modes, 766 .best_encoder = intel_best_encoder, 767 }; 768 769 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 770 .destroy = intel_encoder_destroy, 771 }; 772 773 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 774 { 775 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 776 return 1; 777 } 778 779 static const struct dmi_system_id intel_no_crt[] = { 780 { 781 .callback = intel_no_crt_dmi_callback, 782 .ident = "ACER ZGB", 783 .matches = { 784 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 785 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 786 }, 787 }, 788 { 789 .callback = intel_no_crt_dmi_callback, 790 .ident = "DELL XPS 8700", 791 .matches = { 792 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 793 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 794 }, 795 }, 796 { } 797 }; 798 799 void intel_crt_init(struct drm_device *dev) 800 { 801 struct drm_connector *connector; 802 struct intel_crt *crt; 803 struct intel_connector *intel_connector; 804 struct drm_i915_private *dev_priv = dev->dev_private; 805 806 /* Skip machines without VGA that falsely report hotplug events */ 807 if (dmi_check_system(intel_no_crt)) 808 return; 809 810 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 811 if (!crt) 812 return; 813 814 intel_connector = intel_connector_alloc(); 815 if (!intel_connector) { 816 kfree(crt); 817 return; 818 } 819 820 connector = &intel_connector->base; 821 crt->connector = intel_connector; 822 drm_connector_init(dev, &intel_connector->base, 823 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 824 825 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 826 DRM_MODE_ENCODER_DAC); 827 828 intel_connector_attach_encoder(intel_connector, &crt->base); 829 830 crt->base.type = INTEL_OUTPUT_ANALOG; 831 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 832 if (IS_I830(dev)) 833 crt->base.crtc_mask = (1 << 0); 834 else 835 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 836 837 if (IS_GEN2(dev)) 838 connector->interlace_allowed = 0; 839 else 840 connector->interlace_allowed = 1; 841 connector->doublescan_allowed = 0; 842 843 if (HAS_PCH_SPLIT(dev)) 844 crt->adpa_reg = PCH_ADPA; 845 else if (IS_VALLEYVIEW(dev)) 846 crt->adpa_reg = VLV_ADPA; 847 else 848 crt->adpa_reg = ADPA; 849 850 crt->base.compute_config = intel_crt_compute_config; 851 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) { 852 crt->base.disable = pch_disable_crt; 853 crt->base.post_disable = pch_post_disable_crt; 854 } else { 855 crt->base.disable = intel_disable_crt; 856 } 857 crt->base.enable = intel_enable_crt; 858 if (I915_HAS_HOTPLUG(dev)) 859 crt->base.hpd_pin = HPD_CRT; 860 if (HAS_DDI(dev)) { 861 crt->base.get_config = hsw_crt_get_config; 862 crt->base.get_hw_state = intel_ddi_get_hw_state; 863 crt->base.pre_enable = hsw_crt_pre_enable; 864 crt->base.post_disable = hsw_crt_post_disable; 865 } else { 866 crt->base.get_config = intel_crt_get_config; 867 crt->base.get_hw_state = intel_crt_get_hw_state; 868 } 869 intel_connector->get_hw_state = intel_connector_get_hw_state; 870 intel_connector->unregister = intel_connector_unregister; 871 872 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 873 874 drm_connector_register(connector); 875 876 if (!I915_HAS_HOTPLUG(dev)) 877 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 878 879 /* 880 * Configure the automatic hotplug detection stuff 881 */ 882 crt->force_hotplug_required = 0; 883 884 /* 885 * TODO: find a proper way to discover whether we need to set the the 886 * polarity and link reversal bits or not, instead of relying on the 887 * BIOS. 888 */ 889 if (HAS_PCH_LPT(dev)) { 890 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 891 FDI_RX_LINK_REVERSAL_OVERRIDE; 892 893 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; 894 } 895 896 intel_crt_reset(connector); 897 } 898