1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #include <linux/firmware.h> 25 #include "i915_drv.h" 26 #include "i915_reg.h" 27 #include "intel_drv.h" 28 29 /** 30 * DOC: csr support for dmc 31 * 32 * Display Context Save and Restore (CSR) firmware support added from gen9 33 * onwards to drive newly added DMC (Display microcontroller) in display 34 * engine to save and restore the state of display engine when it enter into 35 * low-power state and comes back to normal. 36 * 37 * Firmware loading status will be one of the below states: FW_UNINITIALIZED, 38 * FW_LOADED, FW_FAILED. 39 * 40 * Once the firmware is written into the registers status will be moved from 41 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will 42 * be moved to FW_FAILED. 43 */ 44 45 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin" 46 47 MODULE_FIRMWARE(I915_CSR_SKL); 48 49 /* 50 * SKL CSR registers for DC5 and DC6 51 */ 52 #define CSR_PROGRAM_BASE 0x80000 53 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 54 #define CSR_HTP_ADDR_SKL 0x00500034 55 #define CSR_SSP_BASE 0x8F074 56 #define CSR_HTP_SKL 0x8F004 57 #define CSR_LAST_WRITE 0x8F034 58 #define CSR_LAST_WRITE_VALUE 0xc003b400 59 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 60 #define CSR_MAX_FW_SIZE 0x2FFF 61 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF 62 #define CSR_MMIO_START_RANGE 0x80000 63 #define CSR_MMIO_END_RANGE 0x8FFFF 64 65 struct intel_css_header { 66 /* 0x09 for DMC */ 67 uint32_t module_type; 68 69 /* Includes the DMC specific header in dwords */ 70 uint32_t header_len; 71 72 /* always value would be 0x10000 */ 73 uint32_t header_ver; 74 75 /* Not used */ 76 uint32_t module_id; 77 78 /* Not used */ 79 uint32_t module_vendor; 80 81 /* in YYYYMMDD format */ 82 uint32_t date; 83 84 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 85 uint32_t size; 86 87 /* Not used */ 88 uint32_t key_size; 89 90 /* Not used */ 91 uint32_t modulus_size; 92 93 /* Not used */ 94 uint32_t exponent_size; 95 96 /* Not used */ 97 uint32_t reserved1[12]; 98 99 /* Major Minor */ 100 uint32_t version; 101 102 /* Not used */ 103 uint32_t reserved2[8]; 104 105 /* Not used */ 106 uint32_t kernel_header_info; 107 } __packed; 108 109 struct intel_fw_info { 110 uint16_t reserved1; 111 112 /* Stepping (A, B, C, ..., *). * is a wildcard */ 113 char stepping; 114 115 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 116 char substepping; 117 118 uint32_t offset; 119 uint32_t reserved2; 120 } __packed; 121 122 struct intel_package_header { 123 /* DMC container header length in dwords */ 124 unsigned char header_len; 125 126 /* always value would be 0x01 */ 127 unsigned char header_ver; 128 129 unsigned char reserved[10]; 130 131 /* Number of valid entries in the FWInfo array below */ 132 uint32_t num_entries; 133 134 struct intel_fw_info fw_info[20]; 135 } __packed; 136 137 struct intel_dmc_header { 138 /* always value would be 0x40403E3E */ 139 uint32_t signature; 140 141 /* DMC binary header length */ 142 unsigned char header_len; 143 144 /* 0x01 */ 145 unsigned char header_ver; 146 147 /* Reserved */ 148 uint16_t dmcc_ver; 149 150 /* Major, Minor */ 151 uint32_t project; 152 153 /* Firmware program size (excluding header) in dwords */ 154 uint32_t fw_size; 155 156 /* Major Minor version */ 157 uint32_t fw_version; 158 159 /* Number of valid MMIO cycles present. */ 160 uint32_t mmio_count; 161 162 /* MMIO address */ 163 uint32_t mmioaddr[8]; 164 165 /* MMIO data */ 166 uint32_t mmiodata[8]; 167 168 /* FW filename */ 169 unsigned char dfile[32]; 170 171 uint32_t reserved1[2]; 172 } __packed; 173 174 struct stepping_info { 175 char stepping; 176 char substepping; 177 }; 178 179 static const struct stepping_info skl_stepping_info[] = { 180 {'A', '0'}, {'B', '0'}, {'C', '0'}, 181 {'D', '0'}, {'E', '0'}, {'F', '0'}, 182 {'G', '0'}, {'H', '0'}, {'I', '0'} 183 }; 184 185 #if 0 186 static char intel_get_stepping(struct drm_device *dev) 187 { 188 if (IS_SKYLAKE(dev) && (dev->pdev->revision < 189 ARRAY_SIZE(skl_stepping_info))) 190 return skl_stepping_info[dev->pdev->revision].stepping; 191 else 192 return -ENODATA; 193 } 194 195 static char intel_get_substepping(struct drm_device *dev) 196 { 197 if (IS_SKYLAKE(dev) && (dev->pdev->revision < 198 ARRAY_SIZE(skl_stepping_info))) 199 return skl_stepping_info[dev->pdev->revision].substepping; 200 else 201 return -ENODATA; 202 } 203 #endif 204 205 /** 206 * intel_csr_load_status_get() - to get firmware loading status. 207 * @dev_priv: i915 device. 208 * 209 * This function helps to get the firmware loading status. 210 * 211 * Return: Firmware loading status. 212 */ 213 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv) 214 { 215 enum csr_state state; 216 217 mutex_lock(&dev_priv->csr_lock); 218 state = dev_priv->csr.state; 219 mutex_unlock(&dev_priv->csr_lock); 220 221 return state; 222 } 223 224 /** 225 * intel_csr_load_status_set() - help to set firmware loading status. 226 * @dev_priv: i915 device. 227 * @state: enumeration of firmware loading status. 228 * 229 * Set the firmware loading status. 230 */ 231 void intel_csr_load_status_set(struct drm_i915_private *dev_priv, 232 enum csr_state state) 233 { 234 mutex_lock(&dev_priv->csr_lock); 235 dev_priv->csr.state = state; 236 mutex_unlock(&dev_priv->csr_lock); 237 } 238 239 /** 240 * intel_csr_load_program() - write the firmware from memory to register. 241 * @dev: drm device. 242 * 243 * CSR firmware is read from a .bin file and kept in internal memory one time. 244 * Everytime display comes back from low power state this function is called to 245 * copy the firmware from internal memory to registers. 246 */ 247 void intel_csr_load_program(struct drm_device *dev) 248 { 249 struct drm_i915_private *dev_priv = dev->dev_private; 250 __be32 *payload = dev_priv->csr.dmc_payload; 251 uint32_t i, fw_size; 252 253 if (!IS_GEN9(dev)) { 254 DRM_ERROR("No CSR support available for this platform\n"); 255 return; 256 } 257 258 mutex_lock(&dev_priv->csr_lock); 259 fw_size = dev_priv->csr.dmc_fw_size; 260 for (i = 0; i < fw_size; i++) 261 I915_WRITE(CSR_PROGRAM_BASE + i * 4, 262 (u32 __force)payload[i]); 263 264 for (i = 0; i < dev_priv->csr.mmio_count; i++) { 265 I915_WRITE(dev_priv->csr.mmioaddr[i], 266 dev_priv->csr.mmiodata[i]); 267 } 268 269 dev_priv->csr.state = FW_LOADED; 270 mutex_unlock(&dev_priv->csr_lock); 271 } 272 273 #if 0 274 static void finish_csr_load(const struct firmware *fw, void *context) 275 { 276 struct drm_i915_private *dev_priv = context; 277 struct drm_device *dev = dev_priv->dev; 278 struct intel_css_header *css_header; 279 struct intel_package_header *package_header; 280 struct intel_dmc_header *dmc_header; 281 struct intel_csr *csr = &dev_priv->csr; 282 char stepping = intel_get_stepping(dev); 283 char substepping = intel_get_substepping(dev); 284 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; 285 uint32_t i; 286 __be32 *dmc_payload; 287 bool fw_loaded = false; 288 289 if (!fw) { 290 i915_firmware_load_error_print(csr->fw_path, 0); 291 goto out; 292 } 293 294 if ((stepping == -ENODATA) || (substepping == -ENODATA)) { 295 DRM_ERROR("Unknown stepping info, firmware loading failed\n"); 296 goto out; 297 } 298 299 /* Extract CSS Header information*/ 300 css_header = (struct intel_css_header *)fw->data; 301 if (sizeof(struct intel_css_header) != 302 (css_header->header_len * 4)) { 303 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", 304 (css_header->header_len * 4)); 305 goto out; 306 } 307 readcount += sizeof(struct intel_css_header); 308 309 /* Extract Package Header information*/ 310 package_header = (struct intel_package_header *) 311 &fw->data[readcount]; 312 if (sizeof(struct intel_package_header) != 313 (package_header->header_len * 4)) { 314 DRM_ERROR("Firmware has wrong package header length %u bytes\n", 315 (package_header->header_len * 4)); 316 goto out; 317 } 318 readcount += sizeof(struct intel_package_header); 319 320 /* Search for dmc_offset to find firware binary. */ 321 for (i = 0; i < package_header->num_entries; i++) { 322 if (package_header->fw_info[i].substepping == '*' && 323 stepping == package_header->fw_info[i].stepping) { 324 dmc_offset = package_header->fw_info[i].offset; 325 break; 326 } else if (stepping == package_header->fw_info[i].stepping && 327 substepping == package_header->fw_info[i].substepping) { 328 dmc_offset = package_header->fw_info[i].offset; 329 break; 330 } else if (package_header->fw_info[i].stepping == '*' && 331 package_header->fw_info[i].substepping == '*') 332 dmc_offset = package_header->fw_info[i].offset; 333 } 334 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { 335 DRM_ERROR("Firmware not supported for %c stepping\n", stepping); 336 goto out; 337 } 338 readcount += dmc_offset; 339 340 /* Extract dmc_header information. */ 341 dmc_header = (struct intel_dmc_header *)&fw->data[readcount]; 342 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { 343 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", 344 (dmc_header->header_len)); 345 goto out; 346 } 347 readcount += sizeof(struct intel_dmc_header); 348 349 /* Cache the dmc header info. */ 350 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { 351 DRM_ERROR("Firmware has wrong mmio count %u\n", 352 dmc_header->mmio_count); 353 goto out; 354 } 355 csr->mmio_count = dmc_header->mmio_count; 356 for (i = 0; i < dmc_header->mmio_count; i++) { 357 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE && 358 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { 359 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", 360 dmc_header->mmioaddr[i]); 361 goto out; 362 } 363 csr->mmioaddr[i] = dmc_header->mmioaddr[i]; 364 csr->mmiodata[i] = dmc_header->mmiodata[i]; 365 } 366 367 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 368 nbytes = dmc_header->fw_size * 4; 369 if (nbytes > CSR_MAX_FW_SIZE) { 370 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); 371 goto out; 372 } 373 csr->dmc_fw_size = dmc_header->fw_size; 374 375 csr->dmc_payload = kmalloc(nbytes, M_DRM, M_WAITOK); 376 if (!csr->dmc_payload) { 377 DRM_ERROR("Memory allocation failed for dmc payload\n"); 378 goto out; 379 } 380 381 dmc_payload = csr->dmc_payload; 382 for (i = 0; i < dmc_header->fw_size; i++) { 383 uint32_t *tmp = (u32 *)&fw->data[readcount + i * 4]; 384 /* 385 * The firmware payload is an array of 32 bit words stored in 386 * little-endian format in the firmware image and programmed 387 * as 32 bit big-endian format to memory. 388 */ 389 dmc_payload[i] = cpu_to_be32(*tmp); 390 } 391 392 /* load csr program during system boot, as needed for DC states */ 393 intel_csr_load_program(dev); 394 fw_loaded = true; 395 396 out: 397 if (fw_loaded) 398 intel_runtime_pm_put(dev_priv); 399 else 400 intel_csr_load_status_set(dev_priv, FW_FAILED); 401 402 release_firmware(fw); 403 } 404 #endif 405 406 /** 407 * intel_csr_ucode_init() - initialize the firmware loading. 408 * @dev: drm device. 409 * 410 * This function is called at the time of loading the display driver to read 411 * firmware from a .bin file and copied into a internal memory. 412 */ 413 void intel_csr_ucode_init(struct drm_device *dev) 414 { 415 #if 0 416 struct drm_i915_private *dev_priv = dev->dev_private; 417 struct intel_csr *csr = &dev_priv->csr; 418 int ret; 419 420 if (!HAS_CSR(dev)) 421 return; 422 423 if (IS_SKYLAKE(dev)) 424 csr->fw_path = I915_CSR_SKL; 425 else { 426 DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); 427 intel_csr_load_status_set(dev_priv, FW_FAILED); 428 return; 429 } 430 431 /* 432 * Obtain a runtime pm reference, until CSR is loaded, 433 * to avoid entering runtime-suspend. 434 */ 435 intel_runtime_pm_get(dev_priv); 436 437 /* CSR supported for platform, load firmware */ 438 ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path, 439 &dev_priv->dev->pdev->dev, 440 GFP_KERNEL, dev_priv, 441 finish_csr_load); 442 if (ret) { 443 i915_firmware_load_error_print(csr->fw_path, ret); 444 intel_csr_load_status_set(dev_priv, FW_FAILED); 445 } 446 #endif 447 } 448 449 /** 450 * intel_csr_ucode_fini() - unload the CSR firmware. 451 * @dev: drm device. 452 * 453 * Firmmware unloading includes freeing the internal momory and reset the 454 * firmware loading status. 455 */ 456 void intel_csr_ucode_fini(struct drm_device *dev) 457 { 458 #if 0 459 struct drm_i915_private *dev_priv = dev->dev_private; 460 461 if (!HAS_CSR(dev)) 462 return; 463 464 intel_csr_load_status_set(dev_priv, FW_FAILED); 465 kfree(dev_priv->csr.dmc_payload); 466 #endif 467 } 468 469 void assert_csr_loaded(struct drm_i915_private *dev_priv) 470 { 471 WARN((intel_csr_load_status_get(dev_priv) != FW_LOADED), "CSR is not loaded.\n"); 472 WARN(!I915_READ(CSR_PROGRAM_BASE), 473 "CSR program storage start is NULL\n"); 474 WARN(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 475 WARN(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 476 } 477