1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <asm/int-ll64.h> 31 32 struct ddi_buf_trans { 33 u32 trans1; /* balance leg enable, de-emph level */ 34 u32 trans2; /* vref sel, vswing */ 35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 36 }; 37 38 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 39 * them for both DP and FDI transports, allowing those ports to 40 * automatically adapt to HDMI connections as well 41 */ 42 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 43 { 0x00FFFFFF, 0x0006000E, 0x0 }, 44 { 0x00D75FFF, 0x0005000A, 0x0 }, 45 { 0x00C30FFF, 0x00040006, 0x0 }, 46 { 0x80AAAFFF, 0x000B0000, 0x0 }, 47 { 0x00FFFFFF, 0x0005000A, 0x0 }, 48 { 0x00D75FFF, 0x000C0004, 0x0 }, 49 { 0x80C30FFF, 0x000B0000, 0x0 }, 50 { 0x00FFFFFF, 0x00040006, 0x0 }, 51 { 0x80D75FFF, 0x000B0000, 0x0 }, 52 }; 53 54 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 55 { 0x00FFFFFF, 0x0007000E, 0x0 }, 56 { 0x00D75FFF, 0x000F000A, 0x0 }, 57 { 0x00C30FFF, 0x00060006, 0x0 }, 58 { 0x00AAAFFF, 0x001E0000, 0x0 }, 59 { 0x00FFFFFF, 0x000F000A, 0x0 }, 60 { 0x00D75FFF, 0x00160004, 0x0 }, 61 { 0x00C30FFF, 0x001E0000, 0x0 }, 62 { 0x00FFFFFF, 0x00060006, 0x0 }, 63 { 0x00D75FFF, 0x001E0000, 0x0 }, 64 }; 65 66 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 67 /* Idx NT mV d T mV d db */ 68 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 69 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 70 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 71 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 72 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 73 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 74 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 75 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 76 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 77 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 78 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 79 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 80 }; 81 82 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 83 { 0x00FFFFFF, 0x00000012, 0x0 }, 84 { 0x00EBAFFF, 0x00020011, 0x0 }, 85 { 0x00C71FFF, 0x0006000F, 0x0 }, 86 { 0x00AAAFFF, 0x000E000A, 0x0 }, 87 { 0x00FFFFFF, 0x00020011, 0x0 }, 88 { 0x00DB6FFF, 0x0005000F, 0x0 }, 89 { 0x00BEEFFF, 0x000A000C, 0x0 }, 90 { 0x00FFFFFF, 0x0005000F, 0x0 }, 91 { 0x00DB6FFF, 0x000A000C, 0x0 }, 92 }; 93 94 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 95 { 0x00FFFFFF, 0x0007000E, 0x0 }, 96 { 0x00D75FFF, 0x000E000A, 0x0 }, 97 { 0x00BEFFFF, 0x00140006, 0x0 }, 98 { 0x80B2CFFF, 0x001B0002, 0x0 }, 99 { 0x00FFFFFF, 0x000E000A, 0x0 }, 100 { 0x00DB6FFF, 0x00160005, 0x0 }, 101 { 0x80C71FFF, 0x001A0002, 0x0 }, 102 { 0x00F7DFFF, 0x00180004, 0x0 }, 103 { 0x80D75FFF, 0x001B0002, 0x0 }, 104 }; 105 106 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 107 { 0x00FFFFFF, 0x0001000E, 0x0 }, 108 { 0x00D75FFF, 0x0004000A, 0x0 }, 109 { 0x00C30FFF, 0x00070006, 0x0 }, 110 { 0x00AAAFFF, 0x000C0000, 0x0 }, 111 { 0x00FFFFFF, 0x0004000A, 0x0 }, 112 { 0x00D75FFF, 0x00090004, 0x0 }, 113 { 0x00C30FFF, 0x000C0000, 0x0 }, 114 { 0x00FFFFFF, 0x00070006, 0x0 }, 115 { 0x00D75FFF, 0x000C0000, 0x0 }, 116 }; 117 118 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 119 /* Idx NT mV d T mV df db */ 120 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 121 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 122 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 123 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 124 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 125 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 126 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 127 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 128 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 129 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 130 }; 131 132 /* Skylake H and S */ 133 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 134 { 0x00002016, 0x000000A0, 0x0 }, 135 { 0x00005012, 0x0000009B, 0x0 }, 136 { 0x00007011, 0x00000088, 0x0 }, 137 { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ 138 { 0x00002016, 0x0000009B, 0x0 }, 139 { 0x00005012, 0x00000088, 0x0 }, 140 { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ 141 { 0x00002016, 0x000000DF, 0x0 }, 142 { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ 143 }; 144 145 /* Skylake U */ 146 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 147 { 0x0000201B, 0x000000A2, 0x0 }, 148 { 0x00005012, 0x00000088, 0x0 }, 149 { 0x00007011, 0x00000087, 0x0 }, 150 { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ 151 { 0x0000201B, 0x0000009D, 0x0 }, 152 { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ 153 { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ 154 { 0x00002016, 0x00000088, 0x0 }, 155 { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */ 156 }; 157 158 /* Skylake Y */ 159 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 160 { 0x00000018, 0x000000A2, 0x0 }, 161 { 0x00005012, 0x00000088, 0x0 }, 162 { 0x00007011, 0x00000087, 0x0 }, 163 { 0x80009010, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ 164 { 0x00000018, 0x0000009D, 0x0 }, 165 { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ 166 { 0x80007011, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ 167 { 0x00000018, 0x00000088, 0x0 }, 168 { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */ 169 }; 170 171 /* 172 * Skylake H and S 173 * eDP 1.4 low vswing translation parameters 174 */ 175 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 176 { 0x00000018, 0x000000A8, 0x0 }, 177 { 0x00004013, 0x000000A9, 0x0 }, 178 { 0x00007011, 0x000000A2, 0x0 }, 179 { 0x00009010, 0x0000009C, 0x0 }, 180 { 0x00000018, 0x000000A9, 0x0 }, 181 { 0x00006013, 0x000000A2, 0x0 }, 182 { 0x00007011, 0x000000A6, 0x0 }, 183 { 0x00000018, 0x000000AB, 0x0 }, 184 { 0x00007013, 0x0000009F, 0x0 }, 185 { 0x00000018, 0x000000DF, 0x0 }, 186 }; 187 188 /* 189 * Skylake U 190 * eDP 1.4 low vswing translation parameters 191 */ 192 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 193 { 0x00000018, 0x000000A8, 0x0 }, 194 { 0x00004013, 0x000000A9, 0x0 }, 195 { 0x00007011, 0x000000A2, 0x0 }, 196 { 0x00009010, 0x0000009C, 0x0 }, 197 { 0x00000018, 0x000000A9, 0x0 }, 198 { 0x00006013, 0x000000A2, 0x0 }, 199 { 0x00007011, 0x000000A6, 0x0 }, 200 { 0x00002016, 0x000000AB, 0x0 }, 201 { 0x00005013, 0x0000009F, 0x0 }, 202 { 0x00000018, 0x000000DF, 0x0 }, 203 }; 204 205 /* 206 * Skylake Y 207 * eDP 1.4 low vswing translation parameters 208 */ 209 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 210 { 0x00000018, 0x000000A8, 0x0 }, 211 { 0x00004013, 0x000000AB, 0x0 }, 212 { 0x00007011, 0x000000A4, 0x0 }, 213 { 0x00009010, 0x000000DF, 0x0 }, 214 { 0x00000018, 0x000000AA, 0x0 }, 215 { 0x00006013, 0x000000A4, 0x0 }, 216 { 0x00007011, 0x0000009D, 0x0 }, 217 { 0x00000018, 0x000000A0, 0x0 }, 218 { 0x00006012, 0x000000DF, 0x0 }, 219 { 0x00000018, 0x0000008A, 0x0 }, 220 }; 221 222 /* Skylake U, H and S */ 223 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 224 { 0x00000018, 0x000000AC, 0x0 }, 225 { 0x00005012, 0x0000009D, 0x0 }, 226 { 0x00007011, 0x00000088, 0x0 }, 227 { 0x00000018, 0x000000A1, 0x0 }, 228 { 0x00000018, 0x00000098, 0x0 }, 229 { 0x00004013, 0x00000088, 0x0 }, 230 { 0x00006012, 0x00000087, 0x0 }, 231 { 0x00000018, 0x000000DF, 0x0 }, 232 { 0x00003015, 0x00000087, 0x0 }, /* Default */ 233 { 0x00003015, 0x000000C7, 0x0 }, 234 { 0x00000018, 0x000000C7, 0x0 }, 235 }; 236 237 /* Skylake Y */ 238 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 239 { 0x00000018, 0x000000A1, 0x0 }, 240 { 0x00005012, 0x000000DF, 0x0 }, 241 { 0x00007011, 0x00000084, 0x0 }, 242 { 0x00000018, 0x000000A4, 0x0 }, 243 { 0x00000018, 0x0000009D, 0x0 }, 244 { 0x00004013, 0x00000080, 0x0 }, 245 { 0x00006013, 0x000000C7, 0x0 }, 246 { 0x00000018, 0x0000008A, 0x0 }, 247 { 0x00003015, 0x000000C7, 0x0 }, /* Default */ 248 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */ 249 { 0x00000018, 0x000000C7, 0x0 }, 250 }; 251 252 struct bxt_ddi_buf_trans { 253 u32 margin; /* swing value */ 254 u32 scale; /* scale value */ 255 u32 enable; /* scale enable */ 256 u32 deemphasis; 257 bool default_index; /* true if the entry represents default value */ 258 }; 259 260 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 261 /* Idx NT mV diff db */ 262 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ 263 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 264 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ 265 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 266 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 267 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 268 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ 269 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 270 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 271 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ 272 }; 273 274 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 275 /* Idx NT mV diff db */ 276 { 26, 0, 0, 128, false }, /* 0: 200 0 */ 277 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ 278 { 48, 0, 0, 96, false }, /* 2: 200 4 */ 279 { 54, 0, 0, 69, false }, /* 3: 200 6 */ 280 { 32, 0, 0, 128, false }, /* 4: 250 0 */ 281 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ 282 { 54, 0, 0, 85, false }, /* 6: 250 4 */ 283 { 43, 0, 0, 128, false }, /* 7: 300 0 */ 284 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ 285 { 48, 0, 0, 128, false }, /* 9: 300 0 */ 286 }; 287 288 /* BSpec has 2 recommended values - entries 0 and 8. 289 * Using the entry with higher vswing. 290 */ 291 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 292 /* Idx NT mV diff db */ 293 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ 294 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 295 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ 296 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 297 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 298 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 299 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ 300 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 301 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 302 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ 303 }; 304 305 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, 306 enum port port, int type); 307 308 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, 309 struct intel_digital_port **dig_port, 310 enum port *port) 311 { 312 struct drm_encoder *encoder = &intel_encoder->base; 313 314 *dig_port = 0; /* silence gcc warnings */ 315 *port = 0; /* silence gcc warnings */ 316 317 switch (intel_encoder->type) { 318 case INTEL_OUTPUT_DP_MST: 319 *dig_port = enc_to_mst(encoder)->primary; 320 *port = (*dig_port)->port; 321 break; 322 case INTEL_OUTPUT_DISPLAYPORT: 323 case INTEL_OUTPUT_EDP: 324 case INTEL_OUTPUT_HDMI: 325 case INTEL_OUTPUT_UNKNOWN: 326 *dig_port = enc_to_dig_port(encoder); 327 *port = (*dig_port)->port; 328 break; 329 case INTEL_OUTPUT_ANALOG: 330 *dig_port = NULL; 331 *port = PORT_E; 332 break; 333 default: 334 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type); 335 break; 336 } 337 } 338 339 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 340 { 341 struct intel_digital_port *dig_port; 342 enum port port; 343 344 ddi_get_encoder_port(intel_encoder, &dig_port, &port); 345 346 return port; 347 } 348 349 static bool 350 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) 351 { 352 return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg); 353 } 354 355 static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev, 356 int *n_entries) 357 { 358 const struct ddi_buf_trans *ddi_translations; 359 360 if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { 361 ddi_translations = skl_y_ddi_translations_dp; 362 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 363 } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { 364 ddi_translations = skl_u_ddi_translations_dp; 365 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 366 } else { 367 ddi_translations = skl_ddi_translations_dp; 368 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 369 } 370 371 return ddi_translations; 372 } 373 374 static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, 375 int *n_entries) 376 { 377 struct drm_i915_private *dev_priv = dev->dev_private; 378 const struct ddi_buf_trans *ddi_translations; 379 380 if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { 381 if (dev_priv->edp_low_vswing) { 382 ddi_translations = skl_y_ddi_translations_edp; 383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 384 } else { 385 ddi_translations = skl_y_ddi_translations_dp; 386 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 387 } 388 } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) { 389 if (dev_priv->edp_low_vswing) { 390 ddi_translations = skl_u_ddi_translations_edp; 391 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 392 } else { 393 ddi_translations = skl_u_ddi_translations_dp; 394 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 395 } 396 } else { 397 if (dev_priv->edp_low_vswing) { 398 ddi_translations = skl_ddi_translations_edp; 399 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 400 } else { 401 ddi_translations = skl_ddi_translations_dp; 402 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 403 } 404 } 405 406 return ddi_translations; 407 } 408 409 static const struct ddi_buf_trans * 410 skl_get_buf_trans_hdmi(struct drm_device *dev, 411 int *n_entries) 412 { 413 const struct ddi_buf_trans *ddi_translations; 414 415 if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) { 416 ddi_translations = skl_y_ddi_translations_hdmi; 417 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 418 } else { 419 ddi_translations = skl_ddi_translations_hdmi; 420 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 421 } 422 423 return ddi_translations; 424 } 425 426 /* 427 * Starting with Haswell, DDI port buffers must be programmed with correct 428 * values in advance. The buffer values are different for FDI and DP modes, 429 * but the HDMI/DVI fields are shared among those. So we program the DDI 430 * in either FDI or DP modes only, as HDMI connections will work with both 431 * of those 432 */ 433 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, 434 bool supports_hdmi) 435 { 436 struct drm_i915_private *dev_priv = dev->dev_private; 437 u32 iboost_bit = 0; 438 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, 439 size; 440 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 441 const struct ddi_buf_trans *ddi_translations_fdi; 442 const struct ddi_buf_trans *ddi_translations_dp; 443 const struct ddi_buf_trans *ddi_translations_edp; 444 const struct ddi_buf_trans *ddi_translations_hdmi; 445 const struct ddi_buf_trans *ddi_translations; 446 447 if (IS_BROXTON(dev)) { 448 if (!supports_hdmi) 449 return; 450 451 /* Vswing programming for HDMI */ 452 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 453 INTEL_OUTPUT_HDMI); 454 return; 455 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 456 ddi_translations_fdi = NULL; 457 ddi_translations_dp = 458 skl_get_buf_trans_dp(dev, &n_dp_entries); 459 ddi_translations_edp = 460 skl_get_buf_trans_edp(dev, &n_edp_entries); 461 ddi_translations_hdmi = 462 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries); 463 hdmi_default_entry = 8; 464 /* If we're boosting the current, set bit 31 of trans1 */ 465 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || 466 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 467 iboost_bit = 1<<31; 468 } else if (IS_BROADWELL(dev)) { 469 ddi_translations_fdi = bdw_ddi_translations_fdi; 470 ddi_translations_dp = bdw_ddi_translations_dp; 471 ddi_translations_edp = bdw_ddi_translations_edp; 472 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 473 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 474 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 475 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 476 hdmi_default_entry = 7; 477 } else if (IS_HASWELL(dev)) { 478 ddi_translations_fdi = hsw_ddi_translations_fdi; 479 ddi_translations_dp = hsw_ddi_translations_dp; 480 ddi_translations_edp = hsw_ddi_translations_dp; 481 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 482 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 483 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 484 hdmi_default_entry = 6; 485 } else { 486 WARN(1, "ddi translation table missing\n"); 487 ddi_translations_edp = bdw_ddi_translations_dp; 488 ddi_translations_fdi = bdw_ddi_translations_fdi; 489 ddi_translations_dp = bdw_ddi_translations_dp; 490 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 491 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 492 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 493 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 494 hdmi_default_entry = 7; 495 } 496 497 switch (port) { 498 case PORT_A: 499 ddi_translations = ddi_translations_edp; 500 size = n_edp_entries; 501 break; 502 case PORT_B: 503 case PORT_C: 504 ddi_translations = ddi_translations_dp; 505 size = n_dp_entries; 506 break; 507 case PORT_D: 508 if (intel_dp_is_edp(dev, PORT_D)) { 509 ddi_translations = ddi_translations_edp; 510 size = n_edp_entries; 511 } else { 512 ddi_translations = ddi_translations_dp; 513 size = n_dp_entries; 514 } 515 break; 516 case PORT_E: 517 if (ddi_translations_fdi) 518 ddi_translations = ddi_translations_fdi; 519 else 520 ddi_translations = ddi_translations_dp; 521 size = n_dp_entries; 522 break; 523 default: 524 BUG(); 525 } 526 527 for (i = 0; i < size; i++) { 528 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 529 ddi_translations[i].trans1 | iboost_bit); 530 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 531 ddi_translations[i].trans2); 532 } 533 534 if (!supports_hdmi) 535 return; 536 537 /* Choose a good default if VBT is badly populated */ 538 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 539 hdmi_level >= n_hdmi_entries) 540 hdmi_level = hdmi_default_entry; 541 542 /* Entry 9 is for HDMI: */ 543 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 544 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); 545 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 546 ddi_translations_hdmi[hdmi_level].trans2); 547 } 548 549 /* Program DDI buffers translations for DP. By default, program ports A-D in DP 550 * mode and port E for FDI. 551 */ 552 void intel_prepare_ddi(struct drm_device *dev) 553 { 554 struct intel_encoder *intel_encoder; 555 bool visited[I915_MAX_PORTS] = { 0, }; 556 557 if (!HAS_DDI(dev)) 558 return; 559 560 for_each_intel_encoder(dev, intel_encoder) { 561 struct intel_digital_port *intel_dig_port; 562 enum port port; 563 bool supports_hdmi; 564 565 if (intel_encoder->type == INTEL_OUTPUT_DSI) 566 continue; 567 568 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port); 569 if (visited[port]) 570 continue; 571 572 supports_hdmi = intel_dig_port && 573 intel_dig_port_supports_hdmi(intel_dig_port); 574 575 intel_prepare_ddi_buffers(dev, port, supports_hdmi); 576 visited[port] = true; 577 } 578 } 579 580 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 581 enum port port) 582 { 583 i915_reg_t reg = DDI_BUF_CTL(port); 584 int i; 585 586 for (i = 0; i < 16; i++) { 587 udelay(1); 588 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 589 return; 590 } 591 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 592 } 593 594 /* Starting with Haswell, different DDI ports can work in FDI mode for 595 * connection to the PCH-located connectors. For this, it is necessary to train 596 * both the DDI port and PCH receiver for the desired DDI buffer settings. 597 * 598 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 599 * please note that when FDI mode is active on DDI E, it shares 2 lines with 600 * DDI A (which is used for eDP) 601 */ 602 603 void hsw_fdi_link_train(struct drm_crtc *crtc) 604 { 605 struct drm_device *dev = crtc->dev; 606 struct drm_i915_private *dev_priv = dev->dev_private; 607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 608 u32 temp, i, rx_ctl_val; 609 610 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 611 * mode set "sequence for CRT port" document: 612 * - TP1 to TP2 time with the default value 613 * - FDI delay to 90h 614 * 615 * WaFDIAutoLinkSetTimingOverrride:hsw 616 */ 617 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 618 FDI_RX_PWRDN_LANE0_VAL(2) | 619 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 620 621 /* Enable the PCH Receiver FDI PLL */ 622 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 623 FDI_RX_PLL_ENABLE | 624 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 625 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 626 POSTING_READ(FDI_RX_CTL(PIPE_A)); 627 udelay(220); 628 629 /* Switch from Rawclk to PCDclk */ 630 rx_ctl_val |= FDI_PCDCLK; 631 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 632 633 /* Configure Port Clock Select */ 634 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); 635 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); 636 637 /* Start the training iterating through available voltages and emphasis, 638 * testing each value twice. */ 639 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 640 /* Configure DP_TP_CTL with auto-training */ 641 I915_WRITE(DP_TP_CTL(PORT_E), 642 DP_TP_CTL_FDI_AUTOTRAIN | 643 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 644 DP_TP_CTL_LINK_TRAIN_PAT1 | 645 DP_TP_CTL_ENABLE); 646 647 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 648 * DDI E does not support port reversal, the functionality is 649 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 650 * port reversal bit */ 651 I915_WRITE(DDI_BUF_CTL(PORT_E), 652 DDI_BUF_CTL_ENABLE | 653 ((intel_crtc->config->fdi_lanes - 1) << 1) | 654 DDI_BUF_TRANS_SELECT(i / 2)); 655 POSTING_READ(DDI_BUF_CTL(PORT_E)); 656 657 udelay(600); 658 659 /* Program PCH FDI Receiver TU */ 660 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 661 662 /* Enable PCH FDI Receiver with auto-training */ 663 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 664 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 665 POSTING_READ(FDI_RX_CTL(PIPE_A)); 666 667 /* Wait for FDI receiver lane calibration */ 668 udelay(30); 669 670 /* Unset FDI_RX_MISC pwrdn lanes */ 671 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 672 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 673 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 674 POSTING_READ(FDI_RX_MISC(PIPE_A)); 675 676 /* Wait for FDI auto training time */ 677 udelay(5); 678 679 temp = I915_READ(DP_TP_STATUS(PORT_E)); 680 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 681 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 682 break; 683 } 684 685 /* 686 * Leave things enabled even if we failed to train FDI. 687 * Results in less fireworks from the state checker. 688 */ 689 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 690 DRM_ERROR("FDI link training failed!\n"); 691 break; 692 } 693 694 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 695 temp &= ~DDI_BUF_CTL_ENABLE; 696 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 697 POSTING_READ(DDI_BUF_CTL(PORT_E)); 698 699 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 700 temp = I915_READ(DP_TP_CTL(PORT_E)); 701 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 702 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 703 I915_WRITE(DP_TP_CTL(PORT_E), temp); 704 POSTING_READ(DP_TP_CTL(PORT_E)); 705 706 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 707 708 rx_ctl_val &= ~FDI_RX_ENABLE; 709 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 710 POSTING_READ(FDI_RX_CTL(PIPE_A)); 711 712 /* Reset FDI_RX_MISC pwrdn lanes */ 713 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 714 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 715 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 716 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 717 POSTING_READ(FDI_RX_MISC(PIPE_A)); 718 } 719 720 /* Enable normal pixel sending for FDI */ 721 I915_WRITE(DP_TP_CTL(PORT_E), 722 DP_TP_CTL_FDI_AUTOTRAIN | 723 DP_TP_CTL_LINK_TRAIN_NORMAL | 724 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 725 DP_TP_CTL_ENABLE); 726 } 727 728 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 729 { 730 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 731 struct intel_digital_port *intel_dig_port = 732 enc_to_dig_port(&encoder->base); 733 734 intel_dp->DP = intel_dig_port->saved_port_bits | 735 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 736 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 737 } 738 739 static struct intel_encoder * 740 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 741 { 742 struct drm_device *dev = crtc->dev; 743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 744 struct intel_encoder *intel_encoder, *ret = NULL; 745 int num_encoders = 0; 746 747 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 748 ret = intel_encoder; 749 num_encoders++; 750 } 751 752 if (num_encoders != 1) 753 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 754 pipe_name(intel_crtc->pipe)); 755 756 BUG_ON(ret == NULL); 757 return ret; 758 } 759 760 struct intel_encoder * 761 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 762 { 763 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 764 struct intel_encoder *ret = NULL; 765 struct drm_atomic_state *state; 766 struct drm_connector *connector; 767 struct drm_connector_state *connector_state; 768 int num_encoders = 0; 769 int i; 770 771 state = crtc_state->base.state; 772 773 for_each_connector_in_state(state, connector, connector_state, i) { 774 if (connector_state->crtc != crtc_state->base.crtc) 775 continue; 776 777 ret = to_intel_encoder(connector_state->best_encoder); 778 num_encoders++; 779 } 780 781 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 782 pipe_name(crtc->pipe)); 783 784 BUG_ON(ret == NULL); 785 return ret; 786 } 787 788 #define LC_FREQ 2700 789 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 790 791 #define P_MIN 2 792 #define P_MAX 64 793 #define P_INC 2 794 795 /* Constraints for PLL good behavior */ 796 #define REF_MIN 48 797 #define REF_MAX 400 798 #define VCO_MIN 2400 799 #define VCO_MAX 4800 800 801 #define abs_diff(a, b) ({ \ 802 typeof(a) __a = (a); \ 803 typeof(b) __b = (b); \ 804 (void) (&__a == &__b); \ 805 __a > __b ? (__a - __b) : (__b - __a); }) 806 807 struct hsw_wrpll_rnp { 808 unsigned p, n2, r2; 809 }; 810 811 static unsigned hsw_wrpll_get_budget_for_freq(int clock) 812 { 813 unsigned budget; 814 815 switch (clock) { 816 case 25175000: 817 case 25200000: 818 case 27000000: 819 case 27027000: 820 case 37762500: 821 case 37800000: 822 case 40500000: 823 case 40541000: 824 case 54000000: 825 case 54054000: 826 case 59341000: 827 case 59400000: 828 case 72000000: 829 case 74176000: 830 case 74250000: 831 case 81000000: 832 case 81081000: 833 case 89012000: 834 case 89100000: 835 case 108000000: 836 case 108108000: 837 case 111264000: 838 case 111375000: 839 case 148352000: 840 case 148500000: 841 case 162000000: 842 case 162162000: 843 case 222525000: 844 case 222750000: 845 case 296703000: 846 case 297000000: 847 budget = 0; 848 break; 849 case 233500000: 850 case 245250000: 851 case 247750000: 852 case 253250000: 853 case 298000000: 854 budget = 1500; 855 break; 856 case 169128000: 857 case 169500000: 858 case 179500000: 859 case 202000000: 860 budget = 2000; 861 break; 862 case 256250000: 863 case 262500000: 864 case 270000000: 865 case 272500000: 866 case 273750000: 867 case 280750000: 868 case 281250000: 869 case 286000000: 870 case 291750000: 871 budget = 4000; 872 break; 873 case 267250000: 874 case 268500000: 875 budget = 5000; 876 break; 877 default: 878 budget = 1000; 879 break; 880 } 881 882 return budget; 883 } 884 885 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, 886 unsigned r2, unsigned n2, unsigned p, 887 struct hsw_wrpll_rnp *best) 888 { 889 uint64_t a, b, c, d, diff, diff_best; 890 891 /* No best (r,n,p) yet */ 892 if (best->p == 0) { 893 best->p = p; 894 best->n2 = n2; 895 best->r2 = r2; 896 return; 897 } 898 899 /* 900 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 901 * freq2k. 902 * 903 * delta = 1e6 * 904 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 905 * freq2k; 906 * 907 * and we would like delta <= budget. 908 * 909 * If the discrepancy is above the PPM-based budget, always prefer to 910 * improve upon the previous solution. However, if you're within the 911 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 912 */ 913 a = freq2k * budget * p * r2; 914 b = freq2k * budget * best->p * best->r2; 915 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); 916 diff_best = abs_diff(freq2k * best->p * best->r2, 917 LC_FREQ_2K * best->n2); 918 c = 1000000 * diff; 919 d = 1000000 * diff_best; 920 921 if (a < c && b < d) { 922 /* If both are above the budget, pick the closer */ 923 if (best->p * best->r2 * diff < p * r2 * diff_best) { 924 best->p = p; 925 best->n2 = n2; 926 best->r2 = r2; 927 } 928 } else if (a >= c && b < d) { 929 /* If A is below the threshold but B is above it? Update. */ 930 best->p = p; 931 best->n2 = n2; 932 best->r2 = r2; 933 } else if (a >= c && b >= d) { 934 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 935 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 936 best->p = p; 937 best->n2 = n2; 938 best->r2 = r2; 939 } 940 } 941 /* Otherwise a < c && b >= d, do nothing */ 942 } 943 944 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 945 i915_reg_t reg) 946 { 947 int refclk = LC_FREQ; 948 int n, p, r; 949 u32 wrpll; 950 951 wrpll = I915_READ(reg); 952 switch (wrpll & WRPLL_PLL_REF_MASK) { 953 case WRPLL_PLL_SSC: 954 case WRPLL_PLL_NON_SSC: 955 /* 956 * We could calculate spread here, but our checking 957 * code only cares about 5% accuracy, and spread is a max of 958 * 0.5% downspread. 959 */ 960 refclk = 135; 961 break; 962 case WRPLL_PLL_LCPLL: 963 refclk = LC_FREQ; 964 break; 965 default: 966 WARN(1, "bad wrpll refclk\n"); 967 return 0; 968 } 969 970 r = wrpll & WRPLL_DIVIDER_REF_MASK; 971 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 972 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 973 974 /* Convert to KHz, p & r have a fixed point portion */ 975 return (refclk * n * 100) / (p * r); 976 } 977 978 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 979 uint32_t dpll) 980 { 981 i915_reg_t cfgcr1_reg, cfgcr2_reg; 982 uint32_t cfgcr1_val, cfgcr2_val; 983 uint32_t p0, p1, p2, dco_freq; 984 985 cfgcr1_reg = DPLL_CFGCR1(dpll); 986 cfgcr2_reg = DPLL_CFGCR2(dpll); 987 988 cfgcr1_val = I915_READ(cfgcr1_reg); 989 cfgcr2_val = I915_READ(cfgcr2_reg); 990 991 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 992 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 993 994 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 995 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 996 else 997 p1 = 1; 998 999 1000 switch (p0) { 1001 case DPLL_CFGCR2_PDIV_1: 1002 p0 = 1; 1003 break; 1004 case DPLL_CFGCR2_PDIV_2: 1005 p0 = 2; 1006 break; 1007 case DPLL_CFGCR2_PDIV_3: 1008 p0 = 3; 1009 break; 1010 case DPLL_CFGCR2_PDIV_7: 1011 p0 = 7; 1012 break; 1013 } 1014 1015 switch (p2) { 1016 case DPLL_CFGCR2_KDIV_5: 1017 p2 = 5; 1018 break; 1019 case DPLL_CFGCR2_KDIV_2: 1020 p2 = 2; 1021 break; 1022 case DPLL_CFGCR2_KDIV_3: 1023 p2 = 3; 1024 break; 1025 case DPLL_CFGCR2_KDIV_1: 1026 p2 = 1; 1027 break; 1028 } 1029 1030 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 1031 1032 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 1033 1000) / 0x8000; 1034 1035 return dco_freq / (p0 * p1 * p2 * 5); 1036 } 1037 1038 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1039 { 1040 int dotclock; 1041 1042 if (pipe_config->has_pch_encoder) 1043 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1044 &pipe_config->fdi_m_n); 1045 else if (pipe_config->has_dp_encoder) 1046 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1047 &pipe_config->dp_m_n); 1048 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) 1049 dotclock = pipe_config->port_clock * 2 / 3; 1050 else 1051 dotclock = pipe_config->port_clock; 1052 1053 if (pipe_config->pixel_multiplier) 1054 dotclock /= pipe_config->pixel_multiplier; 1055 1056 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1057 } 1058 1059 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1060 struct intel_crtc_state *pipe_config) 1061 { 1062 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1063 int link_clock = 0; 1064 uint32_t dpll_ctl1, dpll; 1065 1066 dpll = pipe_config->ddi_pll_sel; 1067 1068 dpll_ctl1 = I915_READ(DPLL_CTRL1); 1069 1070 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 1071 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 1072 } else { 1073 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); 1074 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); 1075 1076 switch (link_clock) { 1077 case DPLL_CTRL1_LINK_RATE_810: 1078 link_clock = 81000; 1079 break; 1080 case DPLL_CTRL1_LINK_RATE_1080: 1081 link_clock = 108000; 1082 break; 1083 case DPLL_CTRL1_LINK_RATE_1350: 1084 link_clock = 135000; 1085 break; 1086 case DPLL_CTRL1_LINK_RATE_1620: 1087 link_clock = 162000; 1088 break; 1089 case DPLL_CTRL1_LINK_RATE_2160: 1090 link_clock = 216000; 1091 break; 1092 case DPLL_CTRL1_LINK_RATE_2700: 1093 link_clock = 270000; 1094 break; 1095 default: 1096 WARN(1, "Unsupported link rate\n"); 1097 break; 1098 } 1099 link_clock *= 2; 1100 } 1101 1102 pipe_config->port_clock = link_clock; 1103 1104 ddi_dotclock_get(pipe_config); 1105 } 1106 1107 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1108 struct intel_crtc_state *pipe_config) 1109 { 1110 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1111 int link_clock = 0; 1112 u32 val, pll; 1113 1114 val = pipe_config->ddi_pll_sel; 1115 switch (val & PORT_CLK_SEL_MASK) { 1116 case PORT_CLK_SEL_LCPLL_810: 1117 link_clock = 81000; 1118 break; 1119 case PORT_CLK_SEL_LCPLL_1350: 1120 link_clock = 135000; 1121 break; 1122 case PORT_CLK_SEL_LCPLL_2700: 1123 link_clock = 270000; 1124 break; 1125 case PORT_CLK_SEL_WRPLL1: 1126 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); 1127 break; 1128 case PORT_CLK_SEL_WRPLL2: 1129 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); 1130 break; 1131 case PORT_CLK_SEL_SPLL: 1132 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 1133 if (pll == SPLL_PLL_FREQ_810MHz) 1134 link_clock = 81000; 1135 else if (pll == SPLL_PLL_FREQ_1350MHz) 1136 link_clock = 135000; 1137 else if (pll == SPLL_PLL_FREQ_2700MHz) 1138 link_clock = 270000; 1139 else { 1140 WARN(1, "bad spll freq\n"); 1141 return; 1142 } 1143 break; 1144 default: 1145 WARN(1, "bad port clock sel\n"); 1146 return; 1147 } 1148 1149 pipe_config->port_clock = link_clock * 2; 1150 1151 ddi_dotclock_get(pipe_config); 1152 } 1153 1154 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, 1155 enum intel_dpll_id dpll) 1156 { 1157 struct intel_shared_dpll *pll; 1158 struct intel_dpll_hw_state *state; 1159 intel_clock_t clock; 1160 1161 /* For DDI ports we always use a shared PLL. */ 1162 if (WARN_ON(dpll == DPLL_ID_PRIVATE)) 1163 return 0; 1164 1165 pll = &dev_priv->shared_dplls[dpll]; 1166 state = &pll->config.hw_state; 1167 1168 clock.m1 = 2; 1169 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; 1170 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1171 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; 1172 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1173 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1174 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1175 1176 return chv_calc_dpll_params(100000, &clock); 1177 } 1178 1179 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1180 struct intel_crtc_state *pipe_config) 1181 { 1182 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1183 enum port port = intel_ddi_get_encoder_port(encoder); 1184 uint32_t dpll = port; 1185 1186 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); 1187 1188 ddi_dotclock_get(pipe_config); 1189 } 1190 1191 void intel_ddi_clock_get(struct intel_encoder *encoder, 1192 struct intel_crtc_state *pipe_config) 1193 { 1194 struct drm_device *dev = encoder->base.dev; 1195 1196 if (INTEL_INFO(dev)->gen <= 8) 1197 hsw_ddi_clock_get(encoder, pipe_config); 1198 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 1199 skl_ddi_clock_get(encoder, pipe_config); 1200 else if (IS_BROXTON(dev)) 1201 bxt_ddi_clock_get(encoder, pipe_config); 1202 } 1203 1204 static void 1205 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 1206 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 1207 { 1208 uint64_t freq2k; 1209 unsigned p, n2, r2; 1210 struct hsw_wrpll_rnp best = { 0, 0, 0 }; 1211 unsigned budget; 1212 1213 freq2k = clock / 100; 1214 1215 budget = hsw_wrpll_get_budget_for_freq(clock); 1216 1217 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 1218 * and directly pass the LC PLL to it. */ 1219 if (freq2k == 5400000) { 1220 *n2_out = 2; 1221 *p_out = 1; 1222 *r2_out = 2; 1223 return; 1224 } 1225 1226 /* 1227 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 1228 * the WR PLL. 1229 * 1230 * We want R so that REF_MIN <= Ref <= REF_MAX. 1231 * Injecting R2 = 2 * R gives: 1232 * REF_MAX * r2 > LC_FREQ * 2 and 1233 * REF_MIN * r2 < LC_FREQ * 2 1234 * 1235 * Which means the desired boundaries for r2 are: 1236 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 1237 * 1238 */ 1239 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 1240 r2 <= LC_FREQ * 2 / REF_MIN; 1241 r2++) { 1242 1243 /* 1244 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 1245 * 1246 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 1247 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 1248 * VCO_MAX * r2 > n2 * LC_FREQ and 1249 * VCO_MIN * r2 < n2 * LC_FREQ) 1250 * 1251 * Which means the desired boundaries for n2 are: 1252 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 1253 */ 1254 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 1255 n2 <= VCO_MAX * r2 / LC_FREQ; 1256 n2++) { 1257 1258 for (p = P_MIN; p <= P_MAX; p += P_INC) 1259 hsw_wrpll_update_rnp(freq2k, budget, 1260 r2, n2, p, &best); 1261 } 1262 } 1263 1264 *n2_out = best.n2; 1265 *p_out = best.p; 1266 *r2_out = best.r2; 1267 } 1268 1269 static bool 1270 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 1271 struct intel_crtc_state *crtc_state, 1272 struct intel_encoder *intel_encoder) 1273 { 1274 int clock = crtc_state->port_clock; 1275 1276 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1277 struct intel_shared_dpll *pll; 1278 uint32_t val; 1279 unsigned p, n2, r2; 1280 1281 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 1282 1283 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 1284 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 1285 WRPLL_DIVIDER_POST(p); 1286 1287 memset(&crtc_state->dpll_hw_state, 0, 1288 sizeof(crtc_state->dpll_hw_state)); 1289 1290 crtc_state->dpll_hw_state.wrpll = val; 1291 1292 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1293 if (pll == NULL) { 1294 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1295 pipe_name(intel_crtc->pipe)); 1296 return false; 1297 } 1298 1299 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 1300 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { 1301 struct drm_atomic_state *state = crtc_state->base.state; 1302 struct intel_shared_dpll_config *spll = 1303 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL]; 1304 1305 if (spll->crtc_mask && 1306 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) 1307 return false; 1308 1309 crtc_state->shared_dpll = DPLL_ID_SPLL; 1310 spll->hw_state.spll = crtc_state->dpll_hw_state.spll; 1311 spll->crtc_mask |= 1 << intel_crtc->pipe; 1312 } 1313 1314 return true; 1315 } 1316 1317 struct skl_wrpll_context { 1318 uint64_t min_deviation; /* current minimal deviation */ 1319 uint64_t central_freq; /* chosen central freq */ 1320 uint64_t dco_freq; /* chosen dco freq */ 1321 unsigned int p; /* chosen divider */ 1322 }; 1323 1324 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) 1325 { 1326 memset(ctx, 0, sizeof(*ctx)); 1327 1328 ctx->min_deviation = U64_MAX; 1329 } 1330 1331 /* DCO freq must be within +1%/-6% of the DCO central freq */ 1332 #define SKL_DCO_MAX_PDEVIATION 100 1333 #define SKL_DCO_MAX_NDEVIATION 600 1334 1335 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, 1336 uint64_t central_freq, 1337 uint64_t dco_freq, 1338 unsigned int divider) 1339 { 1340 uint64_t deviation; 1341 1342 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), 1343 central_freq); 1344 1345 /* positive deviation */ 1346 if (dco_freq >= central_freq) { 1347 if (deviation < SKL_DCO_MAX_PDEVIATION && 1348 deviation < ctx->min_deviation) { 1349 ctx->min_deviation = deviation; 1350 ctx->central_freq = central_freq; 1351 ctx->dco_freq = dco_freq; 1352 ctx->p = divider; 1353 } 1354 /* negative deviation */ 1355 } else if (deviation < SKL_DCO_MAX_NDEVIATION && 1356 deviation < ctx->min_deviation) { 1357 ctx->min_deviation = deviation; 1358 ctx->central_freq = central_freq; 1359 ctx->dco_freq = dco_freq; 1360 ctx->p = divider; 1361 } 1362 } 1363 1364 static void skl_wrpll_get_multipliers(unsigned int p, 1365 unsigned int *p0 /* out */, 1366 unsigned int *p1 /* out */, 1367 unsigned int *p2 /* out */) 1368 { 1369 /* even dividers */ 1370 if (p % 2 == 0) { 1371 unsigned int half = p / 2; 1372 1373 if (half == 1 || half == 2 || half == 3 || half == 5) { 1374 *p0 = 2; 1375 *p1 = 1; 1376 *p2 = half; 1377 } else if (half % 2 == 0) { 1378 *p0 = 2; 1379 *p1 = half / 2; 1380 *p2 = 2; 1381 } else if (half % 3 == 0) { 1382 *p0 = 3; 1383 *p1 = half / 3; 1384 *p2 = 2; 1385 } else if (half % 7 == 0) { 1386 *p0 = 7; 1387 *p1 = half / 7; 1388 *p2 = 2; 1389 } 1390 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ 1391 *p0 = 3; 1392 *p1 = 1; 1393 *p2 = p / 3; 1394 } else if (p == 5 || p == 7) { 1395 *p0 = p; 1396 *p1 = 1; 1397 *p2 = 1; 1398 } else if (p == 15) { 1399 *p0 = 3; 1400 *p1 = 1; 1401 *p2 = 5; 1402 } else if (p == 21) { 1403 *p0 = 7; 1404 *p1 = 1; 1405 *p2 = 3; 1406 } else if (p == 35) { 1407 *p0 = 7; 1408 *p1 = 1; 1409 *p2 = 5; 1410 } 1411 } 1412 1413 struct skl_wrpll_params { 1414 uint32_t dco_fraction; 1415 uint32_t dco_integer; 1416 uint32_t qdiv_ratio; 1417 uint32_t qdiv_mode; 1418 uint32_t kdiv; 1419 uint32_t pdiv; 1420 uint32_t central_freq; 1421 }; 1422 1423 static void skl_wrpll_params_populate(struct skl_wrpll_params *params, 1424 uint64_t afe_clock, 1425 uint64_t central_freq, 1426 uint32_t p0, uint32_t p1, uint32_t p2) 1427 { 1428 uint64_t dco_freq; 1429 1430 switch (central_freq) { 1431 case 9600000000ULL: 1432 params->central_freq = 0; 1433 break; 1434 case 9000000000ULL: 1435 params->central_freq = 1; 1436 break; 1437 case 8400000000ULL: 1438 params->central_freq = 3; 1439 } 1440 1441 switch (p0) { 1442 case 1: 1443 params->pdiv = 0; 1444 break; 1445 case 2: 1446 params->pdiv = 1; 1447 break; 1448 case 3: 1449 params->pdiv = 2; 1450 break; 1451 case 7: 1452 params->pdiv = 4; 1453 break; 1454 default: 1455 WARN(1, "Incorrect PDiv\n"); 1456 } 1457 1458 switch (p2) { 1459 case 5: 1460 params->kdiv = 0; 1461 break; 1462 case 2: 1463 params->kdiv = 1; 1464 break; 1465 case 3: 1466 params->kdiv = 2; 1467 break; 1468 case 1: 1469 params->kdiv = 3; 1470 break; 1471 default: 1472 WARN(1, "Incorrect KDiv\n"); 1473 } 1474 1475 params->qdiv_ratio = p1; 1476 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; 1477 1478 dco_freq = p0 * p1 * p2 * afe_clock; 1479 1480 /* 1481 * Intermediate values are in Hz. 1482 * Divide by MHz to match bsepc 1483 */ 1484 params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); 1485 params->dco_fraction = 1486 div_u64((div_u64(dco_freq, 24) - 1487 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); 1488 } 1489 1490 static bool 1491 skl_ddi_calculate_wrpll(int clock /* in Hz */, 1492 struct skl_wrpll_params *wrpll_params) 1493 { 1494 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 1495 uint64_t dco_central_freq[3] = {8400000000ULL, 1496 9000000000ULL, 1497 9600000000ULL}; 1498 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, 1499 24, 28, 30, 32, 36, 40, 42, 44, 1500 48, 52, 54, 56, 60, 64, 66, 68, 1501 70, 72, 76, 78, 80, 84, 88, 90, 1502 92, 96, 98 }; 1503 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; 1504 static const struct { 1505 const int *list; 1506 int n_dividers; 1507 } dividers[] = { 1508 { even_dividers, ARRAY_SIZE(even_dividers) }, 1509 { odd_dividers, ARRAY_SIZE(odd_dividers) }, 1510 }; 1511 struct skl_wrpll_context ctx; 1512 unsigned int dco, d, i; 1513 unsigned int p0, p1, p2; 1514 1515 skl_wrpll_context_init(&ctx); 1516 1517 for (d = 0; d < ARRAY_SIZE(dividers); d++) { 1518 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { 1519 for (i = 0; i < dividers[d].n_dividers; i++) { 1520 unsigned int p = dividers[d].list[i]; 1521 uint64_t dco_freq = p * afe_clock; 1522 1523 skl_wrpll_try_divider(&ctx, 1524 dco_central_freq[dco], 1525 dco_freq, 1526 p); 1527 /* 1528 * Skip the remaining dividers if we're sure to 1529 * have found the definitive divider, we can't 1530 * improve a 0 deviation. 1531 */ 1532 if (ctx.min_deviation == 0) 1533 goto skip_remaining_dividers; 1534 } 1535 } 1536 1537 skip_remaining_dividers: 1538 /* 1539 * If a solution is found with an even divider, prefer 1540 * this one. 1541 */ 1542 if (d == 0 && ctx.p) 1543 break; 1544 } 1545 1546 if (!ctx.p) { 1547 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); 1548 return false; 1549 } 1550 1551 /* 1552 * gcc incorrectly analyses that these can be used without being 1553 * initialized. To be fair, it's hard to guess. 1554 */ 1555 p0 = p1 = p2 = 0; 1556 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); 1557 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, 1558 p0, p1, p2); 1559 1560 return true; 1561 } 1562 1563 static bool 1564 skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1565 struct intel_crtc_state *crtc_state, 1566 struct intel_encoder *intel_encoder) 1567 { 1568 struct intel_shared_dpll *pll; 1569 uint32_t ctrl1, cfgcr1, cfgcr2; 1570 int clock = crtc_state->port_clock; 1571 1572 /* 1573 * See comment in intel_dpll_hw_state to understand why we always use 0 1574 * as the DPLL id in this function. 1575 */ 1576 1577 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1578 1579 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1580 struct skl_wrpll_params wrpll_params = { 0, }; 1581 1582 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1583 1584 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) 1585 return false; 1586 1587 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1588 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1589 wrpll_params.dco_integer; 1590 1591 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1592 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1593 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1594 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1595 wrpll_params.central_freq; 1596 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1597 intel_encoder->type == INTEL_OUTPUT_DP_MST) { 1598 switch (crtc_state->port_clock / 2) { 1599 case 81000: 1600 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); 1601 break; 1602 case 135000: 1603 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); 1604 break; 1605 case 270000: 1606 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); 1607 break; 1608 } 1609 1610 cfgcr1 = cfgcr2 = 0; 1611 } else /* eDP */ 1612 return true; 1613 1614 memset(&crtc_state->dpll_hw_state, 0, 1615 sizeof(crtc_state->dpll_hw_state)); 1616 1617 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1618 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1619 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1620 1621 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1622 if (pll == NULL) { 1623 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1624 pipe_name(intel_crtc->pipe)); 1625 return false; 1626 } 1627 1628 /* shared DPLL id 0 is DPLL 1 */ 1629 crtc_state->ddi_pll_sel = pll->id + 1; 1630 1631 return true; 1632 } 1633 1634 /* bxt clock parameters */ 1635 struct bxt_clk_div { 1636 int clock; 1637 uint32_t p1; 1638 uint32_t p2; 1639 uint32_t m2_int; 1640 uint32_t m2_frac; 1641 bool m2_frac_en; 1642 uint32_t n; 1643 }; 1644 1645 /* pre-calculated values for DP linkrates */ 1646 static const struct bxt_clk_div bxt_dp_clk_val[] = { 1647 {162000, 4, 2, 32, 1677722, 1, 1}, 1648 {270000, 4, 1, 27, 0, 0, 1}, 1649 {540000, 2, 1, 27, 0, 0, 1}, 1650 {216000, 3, 2, 32, 1677722, 1, 1}, 1651 {243000, 4, 1, 24, 1258291, 1, 1}, 1652 {324000, 4, 1, 32, 1677722, 1, 1}, 1653 {432000, 3, 1, 32, 1677722, 1, 1} 1654 }; 1655 1656 static bool 1657 bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 1658 struct intel_crtc_state *crtc_state, 1659 struct intel_encoder *intel_encoder) 1660 { 1661 struct intel_shared_dpll *pll; 1662 struct bxt_clk_div clk_div = {0}; 1663 int vco = 0; 1664 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; 1665 uint32_t lanestagger; 1666 int clock = crtc_state->port_clock; 1667 1668 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1669 intel_clock_t best_clock; 1670 1671 /* Calculate HDMI div */ 1672 /* 1673 * FIXME: tie the following calculation into 1674 * i9xx_crtc_compute_clock 1675 */ 1676 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { 1677 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", 1678 clock, pipe_name(intel_crtc->pipe)); 1679 return false; 1680 } 1681 1682 clk_div.p1 = best_clock.p1; 1683 clk_div.p2 = best_clock.p2; 1684 WARN_ON(best_clock.m1 != 2); 1685 clk_div.n = best_clock.n; 1686 clk_div.m2_int = best_clock.m2 >> 22; 1687 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); 1688 clk_div.m2_frac_en = clk_div.m2_frac != 0; 1689 1690 vco = best_clock.vco; 1691 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1692 intel_encoder->type == INTEL_OUTPUT_EDP) { 1693 int i; 1694 1695 clk_div = bxt_dp_clk_val[0]; 1696 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { 1697 if (bxt_dp_clk_val[i].clock == clock) { 1698 clk_div = bxt_dp_clk_val[i]; 1699 break; 1700 } 1701 } 1702 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; 1703 } 1704 1705 if (vco >= 6200000 && vco <= 6700000) { 1706 prop_coef = 4; 1707 int_coef = 9; 1708 gain_ctl = 3; 1709 targ_cnt = 8; 1710 } else if ((vco > 5400000 && vco < 6200000) || 1711 (vco >= 4800000 && vco < 5400000)) { 1712 prop_coef = 5; 1713 int_coef = 11; 1714 gain_ctl = 3; 1715 targ_cnt = 9; 1716 } else if (vco == 5400000) { 1717 prop_coef = 3; 1718 int_coef = 8; 1719 gain_ctl = 1; 1720 targ_cnt = 9; 1721 } else { 1722 DRM_ERROR("Invalid VCO\n"); 1723 return false; 1724 } 1725 1726 memset(&crtc_state->dpll_hw_state, 0, 1727 sizeof(crtc_state->dpll_hw_state)); 1728 1729 if (clock > 270000) 1730 lanestagger = 0x18; 1731 else if (clock > 135000) 1732 lanestagger = 0x0d; 1733 else if (clock > 67000) 1734 lanestagger = 0x07; 1735 else if (clock > 33000) 1736 lanestagger = 0x04; 1737 else 1738 lanestagger = 0x02; 1739 1740 crtc_state->dpll_hw_state.ebb0 = 1741 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); 1742 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; 1743 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); 1744 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; 1745 1746 if (clk_div.m2_frac_en) 1747 crtc_state->dpll_hw_state.pll3 = 1748 PORT_PLL_M2_FRAC_ENABLE; 1749 1750 crtc_state->dpll_hw_state.pll6 = 1751 prop_coef | PORT_PLL_INT_COEFF(int_coef); 1752 crtc_state->dpll_hw_state.pll6 |= 1753 PORT_PLL_GAIN_CTL(gain_ctl); 1754 1755 crtc_state->dpll_hw_state.pll8 = targ_cnt; 1756 1757 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; 1758 1759 crtc_state->dpll_hw_state.pll10 = 1760 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) 1761 | PORT_PLL_DCO_AMP_OVR_EN_H; 1762 1763 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; 1764 1765 crtc_state->dpll_hw_state.pcsdw12 = 1766 LANESTAGGER_STRAP_OVRD | lanestagger; 1767 1768 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1769 if (pll == NULL) { 1770 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1771 pipe_name(intel_crtc->pipe)); 1772 return false; 1773 } 1774 1775 /* shared DPLL id 0 is DPLL A */ 1776 crtc_state->ddi_pll_sel = pll->id; 1777 1778 return true; 1779 } 1780 1781 /* 1782 * Tries to find a *shared* PLL for the CRTC and store it in 1783 * intel_crtc->ddi_pll_sel. 1784 * 1785 * For private DPLLs, compute_config() should do the selection for us. This 1786 * function should be folded into compute_config() eventually. 1787 */ 1788 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, 1789 struct intel_crtc_state *crtc_state) 1790 { 1791 struct drm_device *dev = intel_crtc->base.dev; 1792 struct intel_encoder *intel_encoder = 1793 intel_ddi_get_crtc_new_encoder(crtc_state); 1794 1795 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 1796 return skl_ddi_pll_select(intel_crtc, crtc_state, 1797 intel_encoder); 1798 else if (IS_BROXTON(dev)) 1799 return bxt_ddi_pll_select(intel_crtc, crtc_state, 1800 intel_encoder); 1801 else 1802 return hsw_ddi_pll_select(intel_crtc, crtc_state, 1803 intel_encoder); 1804 } 1805 1806 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1807 { 1808 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1810 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1811 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1812 int type = intel_encoder->type; 1813 uint32_t temp; 1814 1815 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1816 temp = TRANS_MSA_SYNC_CLK; 1817 switch (intel_crtc->config->pipe_bpp) { 1818 case 18: 1819 temp |= TRANS_MSA_6_BPC; 1820 break; 1821 case 24: 1822 temp |= TRANS_MSA_8_BPC; 1823 break; 1824 case 30: 1825 temp |= TRANS_MSA_10_BPC; 1826 break; 1827 case 36: 1828 temp |= TRANS_MSA_12_BPC; 1829 break; 1830 default: 1831 BUG(); 1832 } 1833 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1834 } 1835 } 1836 1837 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) 1838 { 1839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1840 struct drm_device *dev = crtc->dev; 1841 struct drm_i915_private *dev_priv = dev->dev_private; 1842 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1843 uint32_t temp; 1844 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1845 if (state == true) 1846 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1847 else 1848 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1849 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1850 } 1851 1852 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 1853 { 1854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1855 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1856 struct drm_encoder *encoder = &intel_encoder->base; 1857 struct drm_device *dev = crtc->dev; 1858 struct drm_i915_private *dev_priv = dev->dev_private; 1859 enum i915_pipe pipe = intel_crtc->pipe; 1860 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1861 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1862 int type = intel_encoder->type; 1863 uint32_t temp; 1864 1865 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1866 temp = TRANS_DDI_FUNC_ENABLE; 1867 temp |= TRANS_DDI_SELECT_PORT(port); 1868 1869 switch (intel_crtc->config->pipe_bpp) { 1870 case 18: 1871 temp |= TRANS_DDI_BPC_6; 1872 break; 1873 case 24: 1874 temp |= TRANS_DDI_BPC_8; 1875 break; 1876 case 30: 1877 temp |= TRANS_DDI_BPC_10; 1878 break; 1879 case 36: 1880 temp |= TRANS_DDI_BPC_12; 1881 break; 1882 default: 1883 BUG(); 1884 } 1885 1886 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1887 temp |= TRANS_DDI_PVSYNC; 1888 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1889 temp |= TRANS_DDI_PHSYNC; 1890 1891 if (cpu_transcoder == TRANSCODER_EDP) { 1892 switch (pipe) { 1893 case PIPE_A: 1894 /* On Haswell, can only use the always-on power well for 1895 * eDP when not using the panel fitter, and when not 1896 * using motion blur mitigation (which we don't 1897 * support). */ 1898 if (IS_HASWELL(dev) && 1899 (intel_crtc->config->pch_pfit.enabled || 1900 intel_crtc->config->pch_pfit.force_thru)) 1901 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1902 else 1903 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1904 break; 1905 case PIPE_B: 1906 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1907 break; 1908 case PIPE_C: 1909 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1910 break; 1911 default: 1912 BUG(); 1913 break; 1914 } 1915 } 1916 1917 if (type == INTEL_OUTPUT_HDMI) { 1918 if (intel_crtc->config->has_hdmi_sink) 1919 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1920 else 1921 temp |= TRANS_DDI_MODE_SELECT_DVI; 1922 1923 } else if (type == INTEL_OUTPUT_ANALOG) { 1924 temp |= TRANS_DDI_MODE_SELECT_FDI; 1925 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; 1926 1927 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1928 type == INTEL_OUTPUT_EDP) { 1929 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1930 1931 if (intel_dp->is_mst) { 1932 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1933 } else 1934 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1935 1936 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1937 } else if (type == INTEL_OUTPUT_DP_MST) { 1938 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; 1939 1940 if (intel_dp->is_mst) { 1941 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1942 } else 1943 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1944 1945 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1946 } else { 1947 WARN(1, "Invalid encoder type %d for pipe %c\n", 1948 intel_encoder->type, pipe_name(pipe)); 1949 } 1950 1951 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1952 } 1953 1954 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1955 enum transcoder cpu_transcoder) 1956 { 1957 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1958 uint32_t val = I915_READ(reg); 1959 1960 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1961 val |= TRANS_DDI_PORT_NONE; 1962 I915_WRITE(reg, val); 1963 } 1964 1965 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1966 { 1967 struct drm_device *dev = intel_connector->base.dev; 1968 struct drm_i915_private *dev_priv = dev->dev_private; 1969 struct intel_encoder *intel_encoder = intel_connector->encoder; 1970 int type = intel_connector->base.connector_type; 1971 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1972 enum i915_pipe pipe = 0; 1973 enum transcoder cpu_transcoder; 1974 enum intel_display_power_domain power_domain; 1975 uint32_t tmp; 1976 bool ret; 1977 1978 power_domain = intel_display_port_power_domain(intel_encoder); 1979 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 1980 return false; 1981 1982 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { 1983 ret = false; 1984 goto out; 1985 } 1986 1987 if (port == PORT_A) 1988 cpu_transcoder = TRANSCODER_EDP; 1989 else 1990 cpu_transcoder = (enum transcoder) pipe; 1991 1992 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1993 1994 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1995 case TRANS_DDI_MODE_SELECT_HDMI: 1996 case TRANS_DDI_MODE_SELECT_DVI: 1997 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1998 break; 1999 2000 case TRANS_DDI_MODE_SELECT_DP_SST: 2001 ret = type == DRM_MODE_CONNECTOR_eDP || 2002 type == DRM_MODE_CONNECTOR_DisplayPort; 2003 break; 2004 2005 case TRANS_DDI_MODE_SELECT_DP_MST: 2006 /* if the transcoder is in MST state then 2007 * connector isn't connected */ 2008 ret = false; 2009 break; 2010 2011 case TRANS_DDI_MODE_SELECT_FDI: 2012 ret = type == DRM_MODE_CONNECTOR_VGA; 2013 break; 2014 2015 default: 2016 ret = false; 2017 break; 2018 } 2019 2020 out: 2021 intel_display_power_put(dev_priv, power_domain); 2022 2023 return ret; 2024 } 2025 2026 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2027 enum i915_pipe *pipe) 2028 { 2029 struct drm_device *dev = encoder->base.dev; 2030 struct drm_i915_private *dev_priv = dev->dev_private; 2031 enum port port = intel_ddi_get_encoder_port(encoder); 2032 enum intel_display_power_domain power_domain; 2033 u32 tmp; 2034 int i; 2035 bool ret; 2036 2037 power_domain = intel_display_port_power_domain(encoder); 2038 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 2039 return false; 2040 2041 ret = false; 2042 2043 tmp = I915_READ(DDI_BUF_CTL(port)); 2044 2045 if (!(tmp & DDI_BUF_CTL_ENABLE)) 2046 goto out; 2047 2048 if (port == PORT_A) { 2049 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2050 2051 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2052 case TRANS_DDI_EDP_INPUT_A_ON: 2053 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2054 *pipe = PIPE_A; 2055 break; 2056 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2057 *pipe = PIPE_B; 2058 break; 2059 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2060 *pipe = PIPE_C; 2061 break; 2062 } 2063 2064 ret = true; 2065 2066 goto out; 2067 } 2068 2069 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 2070 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 2071 2072 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { 2073 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2074 TRANS_DDI_MODE_SELECT_DP_MST) 2075 goto out; 2076 2077 *pipe = i; 2078 ret = true; 2079 2080 goto out; 2081 } 2082 } 2083 2084 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 2085 2086 out: 2087 intel_display_power_put(dev_priv, power_domain); 2088 2089 return ret; 2090 } 2091 2092 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 2093 { 2094 struct drm_crtc *crtc = &intel_crtc->base; 2095 struct drm_device *dev = crtc->dev; 2096 struct drm_i915_private *dev_priv = dev->dev_private; 2097 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2098 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2099 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2100 2101 if (cpu_transcoder != TRANSCODER_EDP) 2102 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2103 TRANS_CLK_SEL_PORT(port)); 2104 } 2105 2106 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 2107 { 2108 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 2109 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2110 2111 if (cpu_transcoder != TRANSCODER_EDP) 2112 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2113 TRANS_CLK_SEL_DISABLED); 2114 } 2115 2116 static void skl_ddi_set_iboost(struct drm_device *dev, u32 level, 2117 enum port port, int type) 2118 { 2119 struct drm_i915_private *dev_priv = dev->dev_private; 2120 const struct ddi_buf_trans *ddi_translations; 2121 uint8_t iboost; 2122 uint8_t dp_iboost, hdmi_iboost; 2123 int n_entries; 2124 u32 reg; 2125 2126 /* VBT may override standard boost values */ 2127 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 2128 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 2129 2130 if (type == INTEL_OUTPUT_DISPLAYPORT) { 2131 if (dp_iboost) { 2132 iboost = dp_iboost; 2133 } else { 2134 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries); 2135 iboost = ddi_translations[level].i_boost; 2136 } 2137 } else if (type == INTEL_OUTPUT_EDP) { 2138 if (dp_iboost) { 2139 iboost = dp_iboost; 2140 } else { 2141 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries); 2142 iboost = ddi_translations[level].i_boost; 2143 } 2144 } else if (type == INTEL_OUTPUT_HDMI) { 2145 if (hdmi_iboost) { 2146 iboost = hdmi_iboost; 2147 } else { 2148 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries); 2149 iboost = ddi_translations[level].i_boost; 2150 } 2151 } else { 2152 return; 2153 } 2154 2155 /* Make sure that the requested I_boost is valid */ 2156 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2157 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2158 return; 2159 } 2160 2161 reg = I915_READ(DISPIO_CR_TX_BMU_CR0); 2162 reg &= ~BALANCE_LEG_MASK(port); 2163 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port)); 2164 2165 if (iboost) 2166 reg |= iboost << BALANCE_LEG_SHIFT(port); 2167 else 2168 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); 2169 2170 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); 2171 } 2172 2173 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, 2174 enum port port, int type) 2175 { 2176 struct drm_i915_private *dev_priv = dev->dev_private; 2177 const struct bxt_ddi_buf_trans *ddi_translations; 2178 u32 n_entries, i; 2179 uint32_t val; 2180 2181 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) { 2182 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 2183 ddi_translations = bxt_ddi_translations_edp; 2184 } else if (type == INTEL_OUTPUT_DISPLAYPORT 2185 || type == INTEL_OUTPUT_EDP) { 2186 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 2187 ddi_translations = bxt_ddi_translations_dp; 2188 } else if (type == INTEL_OUTPUT_HDMI) { 2189 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 2190 ddi_translations = bxt_ddi_translations_hdmi; 2191 } else { 2192 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", 2193 type); 2194 return; 2195 } 2196 2197 /* Check if default value has to be used */ 2198 if (level >= n_entries || 2199 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { 2200 for (i = 0; i < n_entries; i++) { 2201 if (ddi_translations[i].default_index) { 2202 level = i; 2203 break; 2204 } 2205 } 2206 } 2207 2208 /* 2209 * While we write to the group register to program all lanes at once we 2210 * can read only lane registers and we pick lanes 0/1 for that. 2211 */ 2212 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2213 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 2214 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2215 2216 val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); 2217 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 2218 val |= ddi_translations[level].margin << MARGIN_000_SHIFT | 2219 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; 2220 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); 2221 2222 val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); 2223 val &= ~SCALE_DCOMP_METHOD; 2224 if (ddi_translations[level].enable) 2225 val |= SCALE_DCOMP_METHOD; 2226 2227 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 2228 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); 2229 2230 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); 2231 2232 val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); 2233 val &= ~DE_EMPHASIS; 2234 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; 2235 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); 2236 2237 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2238 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 2239 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2240 } 2241 2242 static uint32_t translate_signal_level(int signal_levels) 2243 { 2244 uint32_t level; 2245 2246 switch (signal_levels) { 2247 default: 2248 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2249 signal_levels); 2250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2251 level = 0; 2252 break; 2253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2254 level = 1; 2255 break; 2256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2257 level = 2; 2258 break; 2259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: 2260 level = 3; 2261 break; 2262 2263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2264 level = 4; 2265 break; 2266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2267 level = 5; 2268 break; 2269 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2270 level = 6; 2271 break; 2272 2273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2274 level = 7; 2275 break; 2276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2277 level = 8; 2278 break; 2279 2280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2281 level = 9; 2282 break; 2283 } 2284 2285 return level; 2286 } 2287 2288 uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 2289 { 2290 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2291 struct drm_device *dev = dport->base.base.dev; 2292 struct intel_encoder *encoder = &dport->base; 2293 uint8_t train_set = intel_dp->train_set[0]; 2294 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2295 DP_TRAIN_PRE_EMPHASIS_MASK); 2296 enum port port = dport->port; 2297 uint32_t level; 2298 2299 level = translate_signal_level(signal_levels); 2300 2301 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 2302 skl_ddi_set_iboost(dev, level, port, encoder->type); 2303 else if (IS_BROXTON(dev)) 2304 bxt_ddi_vswing_sequence(dev, level, port, encoder->type); 2305 2306 return DDI_BUF_TRANS_SELECT(level); 2307 } 2308 2309 void intel_ddi_clk_select(struct intel_encoder *encoder, 2310 const struct intel_crtc_state *pipe_config) 2311 { 2312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2313 enum port port = intel_ddi_get_encoder_port(encoder); 2314 2315 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 2316 uint32_t dpll = pipe_config->ddi_pll_sel; 2317 uint32_t val; 2318 2319 /* 2320 * DPLL0 is used for eDP and is the only "private" DPLL (as 2321 * opposed to shared) on SKL 2322 */ 2323 if (encoder->type == INTEL_OUTPUT_EDP) { 2324 WARN_ON(dpll != SKL_DPLL0); 2325 2326 val = I915_READ(DPLL_CTRL1); 2327 2328 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | 2329 DPLL_CTRL1_SSC(dpll) | 2330 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2331 val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6); 2332 2333 I915_WRITE(DPLL_CTRL1, val); 2334 POSTING_READ(DPLL_CTRL1); 2335 } 2336 2337 /* DDI -> PLL mapping */ 2338 val = I915_READ(DPLL_CTRL2); 2339 2340 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2341 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2342 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | 2343 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2344 2345 I915_WRITE(DPLL_CTRL2, val); 2346 2347 } else if (INTEL_INFO(dev_priv)->gen < 9) { 2348 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE); 2349 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel); 2350 } 2351 } 2352 2353 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 2354 { 2355 struct drm_encoder *encoder = &intel_encoder->base; 2356 struct drm_device *dev = encoder->dev; 2357 struct drm_i915_private *dev_priv = dev->dev_private; 2358 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 2359 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2360 int type = intel_encoder->type; 2361 int hdmi_level; 2362 2363 if (type == INTEL_OUTPUT_EDP) { 2364 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2365 intel_edp_panel_on(intel_dp); 2366 } 2367 2368 intel_ddi_clk_select(intel_encoder, crtc->config); 2369 2370 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2371 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2372 2373 intel_dp_set_link_params(intel_dp, crtc->config); 2374 2375 intel_ddi_init_dp_buf_reg(intel_encoder); 2376 2377 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2378 intel_dp_start_link_train(intel_dp); 2379 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) 2380 intel_dp_stop_link_train(intel_dp); 2381 } else if (type == INTEL_OUTPUT_HDMI) { 2382 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2383 2384 if (IS_BROXTON(dev)) { 2385 hdmi_level = dev_priv->vbt. 2386 ddi_port_info[port].hdmi_level_shift; 2387 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 2388 INTEL_OUTPUT_HDMI); 2389 } 2390 intel_hdmi->set_infoframes(encoder, 2391 crtc->config->has_hdmi_sink, 2392 &crtc->config->base.adjusted_mode); 2393 } 2394 } 2395 2396 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 2397 { 2398 struct drm_encoder *encoder = &intel_encoder->base; 2399 struct drm_device *dev = encoder->dev; 2400 struct drm_i915_private *dev_priv = dev->dev_private; 2401 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2402 int type = intel_encoder->type; 2403 uint32_t val; 2404 bool wait = false; 2405 2406 val = I915_READ(DDI_BUF_CTL(port)); 2407 if (val & DDI_BUF_CTL_ENABLE) { 2408 val &= ~DDI_BUF_CTL_ENABLE; 2409 I915_WRITE(DDI_BUF_CTL(port), val); 2410 wait = true; 2411 } 2412 2413 val = I915_READ(DP_TP_CTL(port)); 2414 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2415 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2416 I915_WRITE(DP_TP_CTL(port), val); 2417 2418 if (wait) 2419 intel_wait_ddi_buf_idle(dev_priv, port); 2420 2421 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2422 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2423 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2424 intel_edp_panel_vdd_on(intel_dp); 2425 intel_edp_panel_off(intel_dp); 2426 } 2427 2428 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 2429 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 2430 DPLL_CTRL2_DDI_CLK_OFF(port))); 2431 else if (INTEL_INFO(dev)->gen < 9) 2432 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2433 } 2434 2435 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 2436 { 2437 struct drm_encoder *encoder = &intel_encoder->base; 2438 struct drm_crtc *crtc = encoder->crtc; 2439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2440 struct drm_device *dev = encoder->dev; 2441 struct drm_i915_private *dev_priv = dev->dev_private; 2442 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2443 int type = intel_encoder->type; 2444 2445 if (type == INTEL_OUTPUT_HDMI) { 2446 struct intel_digital_port *intel_dig_port = 2447 enc_to_dig_port(encoder); 2448 2449 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2450 * are ignored so nothing special needs to be done besides 2451 * enabling the port. 2452 */ 2453 I915_WRITE(DDI_BUF_CTL(port), 2454 intel_dig_port->saved_port_bits | 2455 DDI_BUF_CTL_ENABLE); 2456 } else if (type == INTEL_OUTPUT_EDP) { 2457 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2458 2459 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) 2460 intel_dp_stop_link_train(intel_dp); 2461 2462 intel_edp_backlight_on(intel_dp); 2463 intel_psr_enable(intel_dp); 2464 intel_edp_drrs_enable(intel_dp); 2465 } 2466 2467 if (intel_crtc->config->has_audio) { 2468 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 2469 intel_audio_codec_enable(intel_encoder); 2470 } 2471 } 2472 2473 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 2474 { 2475 struct drm_encoder *encoder = &intel_encoder->base; 2476 struct drm_crtc *crtc = encoder->crtc; 2477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2478 int type = intel_encoder->type; 2479 struct drm_device *dev = encoder->dev; 2480 struct drm_i915_private *dev_priv = dev->dev_private; 2481 2482 if (intel_crtc->config->has_audio) { 2483 intel_audio_codec_disable(intel_encoder); 2484 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 2485 } 2486 2487 if (type == INTEL_OUTPUT_EDP) { 2488 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2489 2490 intel_edp_drrs_disable(intel_dp); 2491 intel_psr_disable(intel_dp); 2492 intel_edp_backlight_off(intel_dp); 2493 } 2494 } 2495 2496 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, 2497 struct intel_shared_dpll *pll) 2498 { 2499 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 2500 POSTING_READ(WRPLL_CTL(pll->id)); 2501 udelay(20); 2502 } 2503 2504 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, 2505 struct intel_shared_dpll *pll) 2506 { 2507 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); 2508 POSTING_READ(SPLL_CTL); 2509 udelay(20); 2510 } 2511 2512 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, 2513 struct intel_shared_dpll *pll) 2514 { 2515 uint32_t val; 2516 2517 val = I915_READ(WRPLL_CTL(pll->id)); 2518 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 2519 POSTING_READ(WRPLL_CTL(pll->id)); 2520 } 2521 2522 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, 2523 struct intel_shared_dpll *pll) 2524 { 2525 uint32_t val; 2526 2527 val = I915_READ(SPLL_CTL); 2528 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 2529 POSTING_READ(SPLL_CTL); 2530 } 2531 2532 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, 2533 struct intel_shared_dpll *pll, 2534 struct intel_dpll_hw_state *hw_state) 2535 { 2536 uint32_t val; 2537 2538 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2539 return false; 2540 2541 val = I915_READ(WRPLL_CTL(pll->id)); 2542 hw_state->wrpll = val; 2543 2544 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 2545 2546 return val & WRPLL_PLL_ENABLE; 2547 } 2548 2549 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, 2550 struct intel_shared_dpll *pll, 2551 struct intel_dpll_hw_state *hw_state) 2552 { 2553 uint32_t val; 2554 2555 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2556 return false; 2557 2558 val = I915_READ(SPLL_CTL); 2559 hw_state->spll = val; 2560 2561 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 2562 2563 return val & SPLL_PLL_ENABLE; 2564 } 2565 2566 2567 static const char * const hsw_ddi_pll_names[] = { 2568 "WRPLL 1", 2569 "WRPLL 2", 2570 "SPLL" 2571 }; 2572 2573 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) 2574 { 2575 int i; 2576 2577 dev_priv->num_shared_dpll = 3; 2578 2579 for (i = 0; i < 2; i++) { 2580 dev_priv->shared_dplls[i].id = i; 2581 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2582 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable; 2583 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable; 2584 dev_priv->shared_dplls[i].get_hw_state = 2585 hsw_ddi_wrpll_get_hw_state; 2586 } 2587 2588 /* SPLL is special, but needs to be initialized anyway.. */ 2589 dev_priv->shared_dplls[i].id = i; 2590 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2591 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable; 2592 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable; 2593 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state; 2594 2595 } 2596 2597 static const char * const skl_ddi_pll_names[] = { 2598 "DPLL 1", 2599 "DPLL 2", 2600 "DPLL 3", 2601 }; 2602 2603 struct skl_dpll_regs { 2604 i915_reg_t ctl, cfgcr1, cfgcr2; 2605 }; 2606 2607 /* this array is indexed by the *shared* pll id */ 2608 static const struct skl_dpll_regs skl_dpll_regs[3] = { 2609 { 2610 /* DPLL 1 */ 2611 .ctl = LCPLL2_CTL, 2612 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), 2613 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), 2614 }, 2615 { 2616 /* DPLL 2 */ 2617 .ctl = WRPLL_CTL(0), 2618 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), 2619 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), 2620 }, 2621 { 2622 /* DPLL 3 */ 2623 .ctl = WRPLL_CTL(1), 2624 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), 2625 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), 2626 }, 2627 }; 2628 2629 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 2630 struct intel_shared_dpll *pll) 2631 { 2632 uint32_t val; 2633 unsigned int dpll; 2634 const struct skl_dpll_regs *regs = skl_dpll_regs; 2635 2636 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2637 dpll = pll->id + 1; 2638 2639 val = I915_READ(DPLL_CTRL1); 2640 2641 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | 2642 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2643 val |= pll->config.hw_state.ctrl1 << (dpll * 6); 2644 2645 I915_WRITE(DPLL_CTRL1, val); 2646 POSTING_READ(DPLL_CTRL1); 2647 2648 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 2649 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 2650 POSTING_READ(regs[pll->id].cfgcr1); 2651 POSTING_READ(regs[pll->id].cfgcr2); 2652 2653 /* the enable bit is always bit 31 */ 2654 I915_WRITE(regs[pll->id].ctl, 2655 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 2656 2657 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) 2658 DRM_ERROR("DPLL %d not locked\n", dpll); 2659 } 2660 2661 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 2662 struct intel_shared_dpll *pll) 2663 { 2664 const struct skl_dpll_regs *regs = skl_dpll_regs; 2665 2666 /* the enable bit is always bit 31 */ 2667 I915_WRITE(regs[pll->id].ctl, 2668 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 2669 POSTING_READ(regs[pll->id].ctl); 2670 } 2671 2672 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2673 struct intel_shared_dpll *pll, 2674 struct intel_dpll_hw_state *hw_state) 2675 { 2676 uint32_t val; 2677 unsigned int dpll; 2678 const struct skl_dpll_regs *regs = skl_dpll_regs; 2679 bool ret; 2680 2681 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2682 return false; 2683 2684 ret = false; 2685 2686 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2687 dpll = pll->id + 1; 2688 2689 val = I915_READ(regs[pll->id].ctl); 2690 if (!(val & LCPLL_PLL_ENABLE)) 2691 goto out; 2692 2693 val = I915_READ(DPLL_CTRL1); 2694 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; 2695 2696 /* avoid reading back stale values if HDMI mode is not enabled */ 2697 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { 2698 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 2699 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 2700 } 2701 ret = true; 2702 2703 out: 2704 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 2705 2706 return ret; 2707 } 2708 2709 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) 2710 { 2711 int i; 2712 2713 dev_priv->num_shared_dpll = 3; 2714 2715 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2716 dev_priv->shared_dplls[i].id = i; 2717 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; 2718 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; 2719 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; 2720 dev_priv->shared_dplls[i].get_hw_state = 2721 skl_ddi_pll_get_hw_state; 2722 } 2723 } 2724 2725 static void broxton_phy_init(struct drm_i915_private *dev_priv, 2726 enum dpio_phy phy) 2727 { 2728 enum port port; 2729 uint32_t val; 2730 2731 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 2732 val |= GT_DISPLAY_POWER_ON(phy); 2733 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 2734 2735 /* Considering 10ms timeout until BSpec is updated */ 2736 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) 2737 DRM_ERROR("timeout during PHY%d power on\n", phy); 2738 2739 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); 2740 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { 2741 int lane; 2742 2743 for (lane = 0; lane < 4; lane++) { 2744 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); 2745 /* 2746 * Note that on CHV this flag is called UPAR, but has 2747 * the same function. 2748 */ 2749 val &= ~LATENCY_OPTIM; 2750 if (lane != 1) 2751 val |= LATENCY_OPTIM; 2752 2753 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); 2754 } 2755 } 2756 2757 /* Program PLL Rcomp code offset */ 2758 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); 2759 val &= ~IREF0RC_OFFSET_MASK; 2760 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 2761 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); 2762 2763 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); 2764 val &= ~IREF1RC_OFFSET_MASK; 2765 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 2766 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); 2767 2768 /* Program power gating */ 2769 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); 2770 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 2771 SUS_CLK_CONFIG; 2772 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); 2773 2774 if (phy == DPIO_PHY0) { 2775 val = I915_READ(BXT_PORT_CL2CM_DW6_BC); 2776 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 2777 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); 2778 } 2779 2780 val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); 2781 val &= ~OCL2_LDOFUSE_PWR_DIS; 2782 /* 2783 * On PHY1 disable power on the second channel, since no port is 2784 * connected there. On PHY0 both channels have a port, so leave it 2785 * enabled. 2786 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should 2787 * power down the second channel on PHY0 as well. 2788 */ 2789 if (phy == DPIO_PHY1) 2790 val |= OCL2_LDOFUSE_PWR_DIS; 2791 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); 2792 2793 if (phy == DPIO_PHY0) { 2794 uint32_t grc_code; 2795 /* 2796 * PHY0 isn't connected to an RCOMP resistor so copy over 2797 * the corresponding calibrated value from PHY1, and disable 2798 * the automatic calibration on PHY0. 2799 */ 2800 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, 2801 10)) 2802 DRM_ERROR("timeout waiting for PHY1 GRC\n"); 2803 2804 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); 2805 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 2806 grc_code = val << GRC_CODE_FAST_SHIFT | 2807 val << GRC_CODE_SLOW_SHIFT | 2808 val; 2809 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); 2810 2811 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); 2812 val |= GRC_DIS | GRC_RDY_OVRD; 2813 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); 2814 } 2815 2816 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2817 val |= COMMON_RESET_DIS; 2818 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2819 } 2820 2821 void broxton_ddi_phy_init(struct drm_device *dev) 2822 { 2823 /* Enable PHY1 first since it provides Rcomp for PHY0 */ 2824 broxton_phy_init(dev->dev_private, DPIO_PHY1); 2825 broxton_phy_init(dev->dev_private, DPIO_PHY0); 2826 } 2827 2828 static void broxton_phy_uninit(struct drm_i915_private *dev_priv, 2829 enum dpio_phy phy) 2830 { 2831 uint32_t val; 2832 2833 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2834 val &= ~COMMON_RESET_DIS; 2835 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2836 } 2837 2838 void broxton_ddi_phy_uninit(struct drm_device *dev) 2839 { 2840 struct drm_i915_private *dev_priv = dev->dev_private; 2841 2842 broxton_phy_uninit(dev_priv, DPIO_PHY1); 2843 broxton_phy_uninit(dev_priv, DPIO_PHY0); 2844 2845 /* FIXME: do this in broxton_phy_uninit per phy */ 2846 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); 2847 } 2848 2849 static const char * const bxt_ddi_pll_names[] = { 2850 "PORT PLL A", 2851 "PORT PLL B", 2852 "PORT PLL C", 2853 }; 2854 2855 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 2856 struct intel_shared_dpll *pll) 2857 { 2858 uint32_t temp; 2859 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2860 2861 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2862 temp &= ~PORT_PLL_REF_SEL; 2863 /* Non-SSC reference */ 2864 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2865 2866 /* Disable 10 bit clock */ 2867 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2868 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2869 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2870 2871 /* Write P1 & P2 */ 2872 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2873 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); 2874 temp |= pll->config.hw_state.ebb0; 2875 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); 2876 2877 /* Write M2 integer */ 2878 temp = I915_READ(BXT_PORT_PLL(port, 0)); 2879 temp &= ~PORT_PLL_M2_MASK; 2880 temp |= pll->config.hw_state.pll0; 2881 I915_WRITE(BXT_PORT_PLL(port, 0), temp); 2882 2883 /* Write N */ 2884 temp = I915_READ(BXT_PORT_PLL(port, 1)); 2885 temp &= ~PORT_PLL_N_MASK; 2886 temp |= pll->config.hw_state.pll1; 2887 I915_WRITE(BXT_PORT_PLL(port, 1), temp); 2888 2889 /* Write M2 fraction */ 2890 temp = I915_READ(BXT_PORT_PLL(port, 2)); 2891 temp &= ~PORT_PLL_M2_FRAC_MASK; 2892 temp |= pll->config.hw_state.pll2; 2893 I915_WRITE(BXT_PORT_PLL(port, 2), temp); 2894 2895 /* Write M2 fraction enable */ 2896 temp = I915_READ(BXT_PORT_PLL(port, 3)); 2897 temp &= ~PORT_PLL_M2_FRAC_ENABLE; 2898 temp |= pll->config.hw_state.pll3; 2899 I915_WRITE(BXT_PORT_PLL(port, 3), temp); 2900 2901 /* Write coeff */ 2902 temp = I915_READ(BXT_PORT_PLL(port, 6)); 2903 temp &= ~PORT_PLL_PROP_COEFF_MASK; 2904 temp &= ~PORT_PLL_INT_COEFF_MASK; 2905 temp &= ~PORT_PLL_GAIN_CTL_MASK; 2906 temp |= pll->config.hw_state.pll6; 2907 I915_WRITE(BXT_PORT_PLL(port, 6), temp); 2908 2909 /* Write calibration val */ 2910 temp = I915_READ(BXT_PORT_PLL(port, 8)); 2911 temp &= ~PORT_PLL_TARGET_CNT_MASK; 2912 temp |= pll->config.hw_state.pll8; 2913 I915_WRITE(BXT_PORT_PLL(port, 8), temp); 2914 2915 temp = I915_READ(BXT_PORT_PLL(port, 9)); 2916 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; 2917 temp |= pll->config.hw_state.pll9; 2918 I915_WRITE(BXT_PORT_PLL(port, 9), temp); 2919 2920 temp = I915_READ(BXT_PORT_PLL(port, 10)); 2921 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; 2922 temp &= ~PORT_PLL_DCO_AMP_MASK; 2923 temp |= pll->config.hw_state.pll10; 2924 I915_WRITE(BXT_PORT_PLL(port, 10), temp); 2925 2926 /* Recalibrate with new settings */ 2927 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2928 temp |= PORT_PLL_RECALIBRATE; 2929 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2930 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2931 temp |= pll->config.hw_state.ebb4; 2932 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2933 2934 /* Enable PLL */ 2935 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2936 temp |= PORT_PLL_ENABLE; 2937 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2938 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2939 2940 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & 2941 PORT_PLL_LOCK), 200)) 2942 DRM_ERROR("PLL %d not locked\n", port); 2943 2944 /* 2945 * While we write to the group register to program all lanes at once we 2946 * can read only lane registers and we pick lanes 0/1 for that. 2947 */ 2948 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2949 temp &= ~LANE_STAGGER_MASK; 2950 temp &= ~LANESTAGGER_STRAP_OVRD; 2951 temp |= pll->config.hw_state.pcsdw12; 2952 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); 2953 } 2954 2955 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, 2956 struct intel_shared_dpll *pll) 2957 { 2958 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2959 uint32_t temp; 2960 2961 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2962 temp &= ~PORT_PLL_ENABLE; 2963 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2964 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2965 } 2966 2967 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2968 struct intel_shared_dpll *pll, 2969 struct intel_dpll_hw_state *hw_state) 2970 { 2971 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2972 uint32_t val; 2973 bool ret; 2974 2975 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2976 return false; 2977 2978 ret = false; 2979 2980 val = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2981 if (!(val & PORT_PLL_ENABLE)) 2982 goto out; 2983 2984 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2985 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; 2986 2987 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2988 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; 2989 2990 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); 2991 hw_state->pll0 &= PORT_PLL_M2_MASK; 2992 2993 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); 2994 hw_state->pll1 &= PORT_PLL_N_MASK; 2995 2996 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); 2997 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; 2998 2999 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); 3000 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; 3001 3002 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); 3003 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | 3004 PORT_PLL_INT_COEFF_MASK | 3005 PORT_PLL_GAIN_CTL_MASK; 3006 3007 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); 3008 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; 3009 3010 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); 3011 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; 3012 3013 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); 3014 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | 3015 PORT_PLL_DCO_AMP_MASK; 3016 3017 /* 3018 * While we write to the group register to program all lanes at once we 3019 * can read only lane registers. We configure all lanes the same way, so 3020 * here just read out lanes 0/1 and output a note if lanes 2/3 differ. 3021 */ 3022 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 3023 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) 3024 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", 3025 hw_state->pcsdw12, 3026 I915_READ(BXT_PORT_PCS_DW12_LN23(port))); 3027 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; 3028 3029 ret = true; 3030 3031 out: 3032 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 3033 3034 return ret; 3035 } 3036 3037 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) 3038 { 3039 int i; 3040 3041 dev_priv->num_shared_dpll = 3; 3042 3043 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 3044 dev_priv->shared_dplls[i].id = i; 3045 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; 3046 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; 3047 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; 3048 dev_priv->shared_dplls[i].get_hw_state = 3049 bxt_ddi_pll_get_hw_state; 3050 } 3051 } 3052 3053 void intel_ddi_pll_init(struct drm_device *dev) 3054 { 3055 struct drm_i915_private *dev_priv = dev->dev_private; 3056 uint32_t val = I915_READ(LCPLL_CTL); 3057 3058 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 3059 skl_shared_dplls_init(dev_priv); 3060 else if (IS_BROXTON(dev)) 3061 bxt_shared_dplls_init(dev_priv); 3062 else 3063 hsw_shared_dplls_init(dev_priv); 3064 3065 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 3066 int cdclk_freq; 3067 3068 cdclk_freq = dev_priv->display.get_display_clock_speed(dev); 3069 dev_priv->skl_boot_cdclk = cdclk_freq; 3070 if (skl_sanitize_cdclk(dev_priv)) 3071 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); 3072 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) 3073 DRM_ERROR("LCPLL1 is disabled\n"); 3074 } else if (IS_BROXTON(dev)) { 3075 broxton_init_cdclk(dev); 3076 broxton_ddi_phy_init(dev); 3077 } else { 3078 /* 3079 * The LCPLL register should be turned on by the BIOS. For now 3080 * let's just check its state and print errors in case 3081 * something is wrong. Don't even try to turn it on. 3082 */ 3083 3084 if (val & LCPLL_CD_SOURCE_FCLK) 3085 DRM_ERROR("CDCLK source is not LCPLL\n"); 3086 3087 if (val & LCPLL_PLL_DISABLE) 3088 DRM_ERROR("LCPLL is disabled\n"); 3089 } 3090 } 3091 3092 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 3093 { 3094 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3095 struct drm_i915_private *dev_priv = 3096 to_i915(intel_dig_port->base.base.dev); 3097 enum port port = intel_dig_port->port; 3098 uint32_t val; 3099 bool wait = false; 3100 3101 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 3102 val = I915_READ(DDI_BUF_CTL(port)); 3103 if (val & DDI_BUF_CTL_ENABLE) { 3104 val &= ~DDI_BUF_CTL_ENABLE; 3105 I915_WRITE(DDI_BUF_CTL(port), val); 3106 wait = true; 3107 } 3108 3109 val = I915_READ(DP_TP_CTL(port)); 3110 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3111 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3112 I915_WRITE(DP_TP_CTL(port), val); 3113 POSTING_READ(DP_TP_CTL(port)); 3114 3115 if (wait) 3116 intel_wait_ddi_buf_idle(dev_priv, port); 3117 } 3118 3119 val = DP_TP_CTL_ENABLE | 3120 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 3121 if (intel_dp->is_mst) 3122 val |= DP_TP_CTL_MODE_MST; 3123 else { 3124 val |= DP_TP_CTL_MODE_SST; 3125 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3126 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3127 } 3128 I915_WRITE(DP_TP_CTL(port), val); 3129 POSTING_READ(DP_TP_CTL(port)); 3130 3131 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3132 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 3133 POSTING_READ(DDI_BUF_CTL(port)); 3134 3135 udelay(600); 3136 } 3137 3138 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 3139 { 3140 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 3141 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 3142 uint32_t val; 3143 3144 intel_ddi_post_disable(intel_encoder); 3145 3146 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3147 val &= ~FDI_RX_ENABLE; 3148 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3149 3150 val = I915_READ(FDI_RX_MISC(PIPE_A)); 3151 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3152 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3153 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 3154 3155 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3156 val &= ~FDI_PCDCLK; 3157 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3158 3159 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3160 val &= ~FDI_RX_PLL_ENABLE; 3161 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3162 } 3163 3164 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3165 struct intel_crtc *intel_crtc) 3166 { 3167 u32 temp; 3168 3169 if (intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 3170 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 3171 3172 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 3173 3174 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 3175 return true; 3176 } 3177 3178 return false; 3179 } 3180 3181 void intel_ddi_get_config(struct intel_encoder *encoder, 3182 struct intel_crtc_state *pipe_config) 3183 { 3184 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 3185 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 3186 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3187 struct intel_hdmi *intel_hdmi; 3188 u32 temp, flags = 0; 3189 3190 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3191 if (temp & TRANS_DDI_PHSYNC) 3192 flags |= DRM_MODE_FLAG_PHSYNC; 3193 else 3194 flags |= DRM_MODE_FLAG_NHSYNC; 3195 if (temp & TRANS_DDI_PVSYNC) 3196 flags |= DRM_MODE_FLAG_PVSYNC; 3197 else 3198 flags |= DRM_MODE_FLAG_NVSYNC; 3199 3200 pipe_config->base.adjusted_mode.flags |= flags; 3201 3202 switch (temp & TRANS_DDI_BPC_MASK) { 3203 case TRANS_DDI_BPC_6: 3204 pipe_config->pipe_bpp = 18; 3205 break; 3206 case TRANS_DDI_BPC_8: 3207 pipe_config->pipe_bpp = 24; 3208 break; 3209 case TRANS_DDI_BPC_10: 3210 pipe_config->pipe_bpp = 30; 3211 break; 3212 case TRANS_DDI_BPC_12: 3213 pipe_config->pipe_bpp = 36; 3214 break; 3215 default: 3216 break; 3217 } 3218 3219 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3220 case TRANS_DDI_MODE_SELECT_HDMI: 3221 pipe_config->has_hdmi_sink = true; 3222 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 3223 3224 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 3225 pipe_config->has_infoframe = true; 3226 break; 3227 case TRANS_DDI_MODE_SELECT_DVI: 3228 case TRANS_DDI_MODE_SELECT_FDI: 3229 break; 3230 case TRANS_DDI_MODE_SELECT_DP_SST: 3231 case TRANS_DDI_MODE_SELECT_DP_MST: 3232 pipe_config->has_dp_encoder = true; 3233 pipe_config->lane_count = 3234 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3235 intel_dp_get_m_n(intel_crtc, pipe_config); 3236 break; 3237 default: 3238 break; 3239 } 3240 3241 pipe_config->has_audio = 3242 intel_ddi_is_audio_enabled(dev_priv, intel_crtc); 3243 3244 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && 3245 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 3246 /* 3247 * This is a big fat ugly hack. 3248 * 3249 * Some machines in UEFI boot mode provide us a VBT that has 18 3250 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3251 * unknown we fail to light up. Yet the same BIOS boots up with 3252 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3253 * max, not what it tells us to use. 3254 * 3255 * Note: This will still be broken if the eDP panel is not lit 3256 * up by the BIOS, and thus we can't get the mode at module 3257 * load. 3258 */ 3259 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3260 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 3261 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 3262 } 3263 3264 intel_ddi_clock_get(encoder, pipe_config); 3265 } 3266 3267 static void intel_ddi_destroy(struct drm_encoder *encoder) 3268 { 3269 /* HDMI has nothing special to destroy, so we can go with this. */ 3270 intel_dp_encoder_destroy(encoder); 3271 } 3272 3273 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 3274 struct intel_crtc_state *pipe_config) 3275 { 3276 int type = encoder->type; 3277 int port = intel_ddi_get_encoder_port(encoder); 3278 3279 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 3280 3281 if (port == PORT_A) 3282 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3283 3284 if (type == INTEL_OUTPUT_HDMI) 3285 return intel_hdmi_compute_config(encoder, pipe_config); 3286 else 3287 return intel_dp_compute_config(encoder, pipe_config); 3288 } 3289 3290 static const struct drm_encoder_funcs intel_ddi_funcs = { 3291 .destroy = intel_ddi_destroy, 3292 }; 3293 3294 static struct intel_connector * 3295 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 3296 { 3297 struct intel_connector *connector; 3298 enum port port = intel_dig_port->port; 3299 3300 connector = intel_connector_alloc(); 3301 if (!connector) 3302 return NULL; 3303 3304 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 3305 if (!intel_dp_init_connector(intel_dig_port, connector)) { 3306 kfree(connector); 3307 return NULL; 3308 } 3309 3310 return connector; 3311 } 3312 3313 static struct intel_connector * 3314 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 3315 { 3316 struct intel_connector *connector; 3317 enum port port = intel_dig_port->port; 3318 3319 connector = intel_connector_alloc(); 3320 if (!connector) 3321 return NULL; 3322 3323 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 3324 intel_hdmi_init_connector(intel_dig_port, connector); 3325 3326 return connector; 3327 } 3328 3329 void intel_ddi_init(struct drm_device *dev, enum port port) 3330 { 3331 struct drm_i915_private *dev_priv = dev->dev_private; 3332 struct intel_digital_port *intel_dig_port; 3333 struct intel_encoder *intel_encoder; 3334 struct drm_encoder *encoder; 3335 bool init_hdmi, init_dp; 3336 3337 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 3338 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 3339 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 3340 if (!init_dp && !init_hdmi) { 3341 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 3342 port_name(port)); 3343 return; 3344 } 3345 3346 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3347 if (!intel_dig_port) 3348 return; 3349 3350 intel_encoder = &intel_dig_port->base; 3351 encoder = &intel_encoder->base; 3352 3353 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 3354 DRM_MODE_ENCODER_TMDS, NULL); 3355 3356 intel_encoder->compute_config = intel_ddi_compute_config; 3357 intel_encoder->enable = intel_enable_ddi; 3358 intel_encoder->pre_enable = intel_ddi_pre_enable; 3359 intel_encoder->disable = intel_disable_ddi; 3360 intel_encoder->post_disable = intel_ddi_post_disable; 3361 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 3362 intel_encoder->get_config = intel_ddi_get_config; 3363 3364 intel_dig_port->port = port; 3365 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 3366 (DDI_BUF_PORT_REVERSAL | 3367 DDI_A_4_LANES); 3368 3369 /* 3370 * Bspec says that DDI_A_4_LANES is the only supported configuration 3371 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP 3372 * wasn't lit up at boot. Force this bit on in our internal 3373 * configuration so that we use the proper lane count for our 3374 * calculations. 3375 */ 3376 if (IS_BROXTON(dev) && port == PORT_A) { 3377 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { 3378 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); 3379 intel_dig_port->saved_port_bits |= DDI_A_4_LANES; 3380 } 3381 } 3382 3383 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 3384 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3385 intel_encoder->cloneable = 0; 3386 3387 if (init_dp) { 3388 if (!intel_ddi_init_dp_connector(intel_dig_port)) 3389 goto err; 3390 3391 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 3392 /* 3393 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 3394 * interrupts to check the external panel connection. 3395 */ 3396 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B) 3397 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; 3398 else 3399 dev_priv->hotplug.irq_port[port] = intel_dig_port; 3400 } 3401 3402 /* In theory we don't need the encoder->type check, but leave it just in 3403 * case we have some really bad VBTs... */ 3404 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 3405 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 3406 goto err; 3407 } 3408 3409 return; 3410 3411 err: 3412 drm_encoder_cleanup(encoder); 3413 kfree(intel_dig_port); 3414 } 3415