1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <asm/int-ll64.h> 31 32 struct ddi_buf_trans { 33 u32 trans1; /* balance leg enable, de-emph level */ 34 u32 trans2; /* vref sel, vswing */ 35 }; 36 37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 38 * them for both DP and FDI transports, allowing those ports to 39 * automatically adapt to HDMI connections as well 40 */ 41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 42 { 0x00FFFFFF, 0x0006000E }, 43 { 0x00D75FFF, 0x0005000A }, 44 { 0x00C30FFF, 0x00040006 }, 45 { 0x80AAAFFF, 0x000B0000 }, 46 { 0x00FFFFFF, 0x0005000A }, 47 { 0x00D75FFF, 0x000C0004 }, 48 { 0x80C30FFF, 0x000B0000 }, 49 { 0x00FFFFFF, 0x00040006 }, 50 { 0x80D75FFF, 0x000B0000 }, 51 }; 52 53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 54 { 0x00FFFFFF, 0x0007000E }, 55 { 0x00D75FFF, 0x000F000A }, 56 { 0x00C30FFF, 0x00060006 }, 57 { 0x00AAAFFF, 0x001E0000 }, 58 { 0x00FFFFFF, 0x000F000A }, 59 { 0x00D75FFF, 0x00160004 }, 60 { 0x00C30FFF, 0x001E0000 }, 61 { 0x00FFFFFF, 0x00060006 }, 62 { 0x00D75FFF, 0x001E0000 }, 63 }; 64 65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 66 /* Idx NT mV d T mV d db */ 67 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */ 68 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */ 69 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */ 70 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */ 71 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */ 72 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */ 73 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */ 74 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */ 75 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */ 76 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */ 77 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */ 78 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */ 79 }; 80 81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 82 { 0x00FFFFFF, 0x00000012 }, 83 { 0x00EBAFFF, 0x00020011 }, 84 { 0x00C71FFF, 0x0006000F }, 85 { 0x00AAAFFF, 0x000E000A }, 86 { 0x00FFFFFF, 0x00020011 }, 87 { 0x00DB6FFF, 0x0005000F }, 88 { 0x00BEEFFF, 0x000A000C }, 89 { 0x00FFFFFF, 0x0005000F }, 90 { 0x00DB6FFF, 0x000A000C }, 91 }; 92 93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 94 { 0x00FFFFFF, 0x0007000E }, 95 { 0x00D75FFF, 0x000E000A }, 96 { 0x00BEFFFF, 0x00140006 }, 97 { 0x80B2CFFF, 0x001B0002 }, 98 { 0x00FFFFFF, 0x000E000A }, 99 { 0x00DB6FFF, 0x00160005 }, 100 { 0x80C71FFF, 0x001A0002 }, 101 { 0x00F7DFFF, 0x00180004 }, 102 { 0x80D75FFF, 0x001B0002 }, 103 }; 104 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 106 { 0x00FFFFFF, 0x0001000E }, 107 { 0x00D75FFF, 0x0004000A }, 108 { 0x00C30FFF, 0x00070006 }, 109 { 0x00AAAFFF, 0x000C0000 }, 110 { 0x00FFFFFF, 0x0004000A }, 111 { 0x00D75FFF, 0x00090004 }, 112 { 0x00C30FFF, 0x000C0000 }, 113 { 0x00FFFFFF, 0x00070006 }, 114 { 0x00D75FFF, 0x000C0000 }, 115 }; 116 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 118 /* Idx NT mV d T mV df db */ 119 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */ 120 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */ 121 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */ 122 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */ 123 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */ 124 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */ 125 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */ 126 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */ 127 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */ 128 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */ 129 }; 130 131 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 132 { 0x00000018, 0x000000a2 }, 133 { 0x00004014, 0x0000009B }, 134 { 0x00006012, 0x00000088 }, 135 { 0x00008010, 0x00000087 }, 136 { 0x00000018, 0x0000009B }, 137 { 0x00004014, 0x00000088 }, 138 { 0x00006012, 0x00000087 }, 139 { 0x00000018, 0x00000088 }, 140 { 0x00004014, 0x00000087 }, 141 }; 142 143 /* eDP 1.4 low vswing translation parameters */ 144 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 145 { 0x00000018, 0x000000a8 }, 146 { 0x00002016, 0x000000ab }, 147 { 0x00006012, 0x000000a2 }, 148 { 0x00008010, 0x00000088 }, 149 { 0x00000018, 0x000000ab }, 150 { 0x00004014, 0x000000a2 }, 151 { 0x00006012, 0x000000a6 }, 152 { 0x00000018, 0x000000a2 }, 153 { 0x00005013, 0x0000009c }, 154 { 0x00000018, 0x00000088 }, 155 }; 156 157 158 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 159 /* Idx NT mV T mV db */ 160 { 0x00004014, 0x00000087 }, /* 0: 800 1000 2 */ 161 }; 162 163 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 164 { 165 struct drm_encoder *encoder = &intel_encoder->base; 166 int type = intel_encoder->type; 167 168 if (type == INTEL_OUTPUT_DP_MST) { 169 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary; 170 return intel_dig_port->port; 171 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || 172 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { 173 struct intel_digital_port *intel_dig_port = 174 enc_to_dig_port(encoder); 175 return intel_dig_port->port; 176 177 } else if (type == INTEL_OUTPUT_ANALOG) { 178 return PORT_E; 179 180 } else { 181 DRM_ERROR("Invalid DDI encoder type %d\n", type); 182 BUG(); 183 } 184 } 185 186 /* 187 * Starting with Haswell, DDI port buffers must be programmed with correct 188 * values in advance. The buffer values are different for FDI and DP modes, 189 * but the HDMI/DVI fields are shared among those. So we program the DDI 190 * in either FDI or DP modes only, as HDMI connections will work with both 191 * of those 192 */ 193 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) 194 { 195 struct drm_i915_private *dev_priv = dev->dev_private; 196 u32 reg; 197 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, 198 size; 199 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 200 const struct ddi_buf_trans *ddi_translations_fdi; 201 const struct ddi_buf_trans *ddi_translations_dp; 202 const struct ddi_buf_trans *ddi_translations_edp; 203 const struct ddi_buf_trans *ddi_translations_hdmi; 204 const struct ddi_buf_trans *ddi_translations; 205 206 if (IS_SKYLAKE(dev)) { 207 ddi_translations_fdi = NULL; 208 ddi_translations_dp = skl_ddi_translations_dp; 209 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp); 210 if (dev_priv->vbt.edp_low_vswing) { 211 ddi_translations_edp = skl_ddi_translations_edp; 212 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp); 213 } else { 214 ddi_translations_edp = skl_ddi_translations_dp; 215 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp); 216 } 217 218 /* 219 * On SKL, the recommendation from the hw team is to always use 220 * a certain type of level shifter (and thus the corresponding 221 * 800mV+2dB entry). Given that's the only validated entry, we 222 * override what is in the VBT, at least until further notice. 223 */ 224 hdmi_level = 0; 225 ddi_translations_hdmi = skl_ddi_translations_hdmi; 226 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 227 hdmi_default_entry = 0; 228 } else if (IS_BROADWELL(dev)) { 229 ddi_translations_fdi = bdw_ddi_translations_fdi; 230 ddi_translations_dp = bdw_ddi_translations_dp; 231 ddi_translations_edp = bdw_ddi_translations_edp; 232 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 233 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 234 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 235 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 236 hdmi_default_entry = 7; 237 } else if (IS_HASWELL(dev)) { 238 ddi_translations_fdi = hsw_ddi_translations_fdi; 239 ddi_translations_dp = hsw_ddi_translations_dp; 240 ddi_translations_edp = hsw_ddi_translations_dp; 241 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 242 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 243 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 244 hdmi_default_entry = 6; 245 } else { 246 WARN(1, "ddi translation table missing\n"); 247 ddi_translations_edp = bdw_ddi_translations_dp; 248 ddi_translations_fdi = bdw_ddi_translations_fdi; 249 ddi_translations_dp = bdw_ddi_translations_dp; 250 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 251 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 252 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 253 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 254 hdmi_default_entry = 7; 255 } 256 257 switch (port) { 258 case PORT_A: 259 ddi_translations = ddi_translations_edp; 260 size = n_edp_entries; 261 break; 262 case PORT_B: 263 case PORT_C: 264 ddi_translations = ddi_translations_dp; 265 size = n_dp_entries; 266 break; 267 case PORT_D: 268 if (intel_dp_is_edp(dev, PORT_D)) { 269 ddi_translations = ddi_translations_edp; 270 size = n_edp_entries; 271 } else { 272 ddi_translations = ddi_translations_dp; 273 size = n_dp_entries; 274 } 275 break; 276 case PORT_E: 277 if (ddi_translations_fdi) 278 ddi_translations = ddi_translations_fdi; 279 else 280 ddi_translations = ddi_translations_dp; 281 size = n_dp_entries; 282 break; 283 default: 284 BUG(); 285 } 286 287 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) { 288 I915_WRITE(reg, ddi_translations[i].trans1); 289 reg += 4; 290 I915_WRITE(reg, ddi_translations[i].trans2); 291 reg += 4; 292 } 293 294 /* Choose a good default if VBT is badly populated */ 295 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 296 hdmi_level >= n_hdmi_entries) 297 hdmi_level = hdmi_default_entry; 298 299 /* Entry 9 is for HDMI: */ 300 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1); 301 reg += 4; 302 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2); 303 reg += 4; 304 } 305 306 /* Program DDI buffers translations for DP. By default, program ports A-D in DP 307 * mode and port E for FDI. 308 */ 309 void intel_prepare_ddi(struct drm_device *dev) 310 { 311 int port; 312 313 if (!HAS_DDI(dev)) 314 return; 315 316 for (port = PORT_A; port <= PORT_E; port++) 317 intel_prepare_ddi_buffers(dev, port); 318 } 319 320 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 321 enum port port) 322 { 323 uint32_t reg = DDI_BUF_CTL(port); 324 int i; 325 326 for (i = 0; i < 8; i++) { 327 udelay(1); 328 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 329 return; 330 } 331 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 332 } 333 334 /* Starting with Haswell, different DDI ports can work in FDI mode for 335 * connection to the PCH-located connectors. For this, it is necessary to train 336 * both the DDI port and PCH receiver for the desired DDI buffer settings. 337 * 338 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 339 * please note that when FDI mode is active on DDI E, it shares 2 lines with 340 * DDI A (which is used for eDP) 341 */ 342 343 void hsw_fdi_link_train(struct drm_crtc *crtc) 344 { 345 struct drm_device *dev = crtc->dev; 346 struct drm_i915_private *dev_priv = dev->dev_private; 347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 348 u32 temp, i, rx_ctl_val; 349 350 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 351 * mode set "sequence for CRT port" document: 352 * - TP1 to TP2 time with the default value 353 * - FDI delay to 90h 354 * 355 * WaFDIAutoLinkSetTimingOverrride:hsw 356 */ 357 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | 358 FDI_RX_PWRDN_LANE0_VAL(2) | 359 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 360 361 /* Enable the PCH Receiver FDI PLL */ 362 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 363 FDI_RX_PLL_ENABLE | 364 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 365 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 366 POSTING_READ(_FDI_RXA_CTL); 367 udelay(220); 368 369 /* Switch from Rawclk to PCDclk */ 370 rx_ctl_val |= FDI_PCDCLK; 371 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 372 373 /* Configure Port Clock Select */ 374 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); 375 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); 376 377 /* Start the training iterating through available voltages and emphasis, 378 * testing each value twice. */ 379 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 380 /* Configure DP_TP_CTL with auto-training */ 381 I915_WRITE(DP_TP_CTL(PORT_E), 382 DP_TP_CTL_FDI_AUTOTRAIN | 383 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 384 DP_TP_CTL_LINK_TRAIN_PAT1 | 385 DP_TP_CTL_ENABLE); 386 387 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 388 * DDI E does not support port reversal, the functionality is 389 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 390 * port reversal bit */ 391 I915_WRITE(DDI_BUF_CTL(PORT_E), 392 DDI_BUF_CTL_ENABLE | 393 ((intel_crtc->config->fdi_lanes - 1) << 1) | 394 DDI_BUF_TRANS_SELECT(i / 2)); 395 POSTING_READ(DDI_BUF_CTL(PORT_E)); 396 397 udelay(600); 398 399 /* Program PCH FDI Receiver TU */ 400 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); 401 402 /* Enable PCH FDI Receiver with auto-training */ 403 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 404 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 405 POSTING_READ(_FDI_RXA_CTL); 406 407 /* Wait for FDI receiver lane calibration */ 408 udelay(30); 409 410 /* Unset FDI_RX_MISC pwrdn lanes */ 411 temp = I915_READ(_FDI_RXA_MISC); 412 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 413 I915_WRITE(_FDI_RXA_MISC, temp); 414 POSTING_READ(_FDI_RXA_MISC); 415 416 /* Wait for FDI auto training time */ 417 udelay(5); 418 419 temp = I915_READ(DP_TP_STATUS(PORT_E)); 420 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 421 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 422 423 /* Enable normal pixel sending for FDI */ 424 I915_WRITE(DP_TP_CTL(PORT_E), 425 DP_TP_CTL_FDI_AUTOTRAIN | 426 DP_TP_CTL_LINK_TRAIN_NORMAL | 427 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 428 DP_TP_CTL_ENABLE); 429 430 return; 431 } 432 433 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 434 temp &= ~DDI_BUF_CTL_ENABLE; 435 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 436 POSTING_READ(DDI_BUF_CTL(PORT_E)); 437 438 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 439 temp = I915_READ(DP_TP_CTL(PORT_E)); 440 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 441 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 442 I915_WRITE(DP_TP_CTL(PORT_E), temp); 443 POSTING_READ(DP_TP_CTL(PORT_E)); 444 445 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 446 447 rx_ctl_val &= ~FDI_RX_ENABLE; 448 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 449 POSTING_READ(_FDI_RXA_CTL); 450 451 /* Reset FDI_RX_MISC pwrdn lanes */ 452 temp = I915_READ(_FDI_RXA_MISC); 453 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 454 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 455 I915_WRITE(_FDI_RXA_MISC, temp); 456 POSTING_READ(_FDI_RXA_MISC); 457 } 458 459 DRM_ERROR("FDI link training failed!\n"); 460 } 461 462 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 463 { 464 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 465 struct intel_digital_port *intel_dig_port = 466 enc_to_dig_port(&encoder->base); 467 468 intel_dp->DP = intel_dig_port->saved_port_bits | 469 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 470 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 471 472 } 473 474 static struct intel_encoder * 475 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 476 { 477 struct drm_device *dev = crtc->dev; 478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 479 struct intel_encoder *intel_encoder, *ret = NULL; 480 int num_encoders = 0; 481 482 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 483 ret = intel_encoder; 484 num_encoders++; 485 } 486 487 if (num_encoders != 1) 488 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 489 pipe_name(intel_crtc->pipe)); 490 491 BUG_ON(ret == NULL); 492 return ret; 493 } 494 495 static struct intel_encoder * 496 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 497 { 498 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 499 struct intel_encoder *ret = NULL; 500 struct drm_atomic_state *state; 501 int num_encoders = 0; 502 int i; 503 504 state = crtc_state->base.state; 505 506 for (i = 0; i < state->num_connector; i++) { 507 if (!state->connectors[i] || 508 state->connector_states[i]->crtc != crtc_state->base.crtc) 509 continue; 510 511 ret = to_intel_encoder(state->connector_states[i]->best_encoder); 512 num_encoders++; 513 } 514 515 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 516 pipe_name(crtc->pipe)); 517 518 BUG_ON(ret == NULL); 519 return ret; 520 } 521 522 #define LC_FREQ 2700 523 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 524 525 #define P_MIN 2 526 #define P_MAX 64 527 #define P_INC 2 528 529 /* Constraints for PLL good behavior */ 530 #define REF_MIN 48 531 #define REF_MAX 400 532 #define VCO_MIN 2400 533 #define VCO_MAX 4800 534 535 #define abs_diff(a, b) ({ \ 536 typeof(a) __a = (a); \ 537 typeof(b) __b = (b); \ 538 (void) (&__a == &__b); \ 539 __a > __b ? (__a - __b) : (__b - __a); }) 540 541 struct wrpll_rnp { 542 unsigned p, n2, r2; 543 }; 544 545 static unsigned wrpll_get_budget_for_freq(int clock) 546 { 547 unsigned budget; 548 549 switch (clock) { 550 case 25175000: 551 case 25200000: 552 case 27000000: 553 case 27027000: 554 case 37762500: 555 case 37800000: 556 case 40500000: 557 case 40541000: 558 case 54000000: 559 case 54054000: 560 case 59341000: 561 case 59400000: 562 case 72000000: 563 case 74176000: 564 case 74250000: 565 case 81000000: 566 case 81081000: 567 case 89012000: 568 case 89100000: 569 case 108000000: 570 case 108108000: 571 case 111264000: 572 case 111375000: 573 case 148352000: 574 case 148500000: 575 case 162000000: 576 case 162162000: 577 case 222525000: 578 case 222750000: 579 case 296703000: 580 case 297000000: 581 budget = 0; 582 break; 583 case 233500000: 584 case 245250000: 585 case 247750000: 586 case 253250000: 587 case 298000000: 588 budget = 1500; 589 break; 590 case 169128000: 591 case 169500000: 592 case 179500000: 593 case 202000000: 594 budget = 2000; 595 break; 596 case 256250000: 597 case 262500000: 598 case 270000000: 599 case 272500000: 600 case 273750000: 601 case 280750000: 602 case 281250000: 603 case 286000000: 604 case 291750000: 605 budget = 4000; 606 break; 607 case 267250000: 608 case 268500000: 609 budget = 5000; 610 break; 611 default: 612 budget = 1000; 613 break; 614 } 615 616 return budget; 617 } 618 619 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, 620 unsigned r2, unsigned n2, unsigned p, 621 struct wrpll_rnp *best) 622 { 623 uint64_t a, b, c, d, diff, diff_best; 624 625 /* No best (r,n,p) yet */ 626 if (best->p == 0) { 627 best->p = p; 628 best->n2 = n2; 629 best->r2 = r2; 630 return; 631 } 632 633 /* 634 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 635 * freq2k. 636 * 637 * delta = 1e6 * 638 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 639 * freq2k; 640 * 641 * and we would like delta <= budget. 642 * 643 * If the discrepancy is above the PPM-based budget, always prefer to 644 * improve upon the previous solution. However, if you're within the 645 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 646 */ 647 a = freq2k * budget * p * r2; 648 b = freq2k * budget * best->p * best->r2; 649 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); 650 diff_best = abs_diff(freq2k * best->p * best->r2, 651 LC_FREQ_2K * best->n2); 652 c = 1000000 * diff; 653 d = 1000000 * diff_best; 654 655 if (a < c && b < d) { 656 /* If both are above the budget, pick the closer */ 657 if (best->p * best->r2 * diff < p * r2 * diff_best) { 658 best->p = p; 659 best->n2 = n2; 660 best->r2 = r2; 661 } 662 } else if (a >= c && b < d) { 663 /* If A is below the threshold but B is above it? Update. */ 664 best->p = p; 665 best->n2 = n2; 666 best->r2 = r2; 667 } else if (a >= c && b >= d) { 668 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 669 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 670 best->p = p; 671 best->n2 = n2; 672 best->r2 = r2; 673 } 674 } 675 /* Otherwise a < c && b >= d, do nothing */ 676 } 677 678 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 679 int reg) 680 { 681 int refclk = LC_FREQ; 682 int n, p, r; 683 u32 wrpll; 684 685 wrpll = I915_READ(reg); 686 switch (wrpll & WRPLL_PLL_REF_MASK) { 687 case WRPLL_PLL_SSC: 688 case WRPLL_PLL_NON_SSC: 689 /* 690 * We could calculate spread here, but our checking 691 * code only cares about 5% accuracy, and spread is a max of 692 * 0.5% downspread. 693 */ 694 refclk = 135; 695 break; 696 case WRPLL_PLL_LCPLL: 697 refclk = LC_FREQ; 698 break; 699 default: 700 WARN(1, "bad wrpll refclk\n"); 701 return 0; 702 } 703 704 r = wrpll & WRPLL_DIVIDER_REF_MASK; 705 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 706 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 707 708 /* Convert to KHz, p & r have a fixed point portion */ 709 return (refclk * n * 100) / (p * r); 710 } 711 712 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 713 uint32_t dpll) 714 { 715 uint32_t cfgcr1_reg, cfgcr2_reg; 716 uint32_t cfgcr1_val, cfgcr2_val; 717 uint32_t p0, p1, p2, dco_freq; 718 719 cfgcr1_reg = GET_CFG_CR1_REG(dpll); 720 cfgcr2_reg = GET_CFG_CR2_REG(dpll); 721 722 cfgcr1_val = I915_READ(cfgcr1_reg); 723 cfgcr2_val = I915_READ(cfgcr2_reg); 724 725 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 726 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 727 728 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 729 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 730 else 731 p1 = 1; 732 733 734 switch (p0) { 735 case DPLL_CFGCR2_PDIV_1: 736 p0 = 1; 737 break; 738 case DPLL_CFGCR2_PDIV_2: 739 p0 = 2; 740 break; 741 case DPLL_CFGCR2_PDIV_3: 742 p0 = 3; 743 break; 744 case DPLL_CFGCR2_PDIV_7: 745 p0 = 7; 746 break; 747 } 748 749 switch (p2) { 750 case DPLL_CFGCR2_KDIV_5: 751 p2 = 5; 752 break; 753 case DPLL_CFGCR2_KDIV_2: 754 p2 = 2; 755 break; 756 case DPLL_CFGCR2_KDIV_3: 757 p2 = 3; 758 break; 759 case DPLL_CFGCR2_KDIV_1: 760 p2 = 1; 761 break; 762 } 763 764 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 765 766 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 767 1000) / 0x8000; 768 769 return dco_freq / (p0 * p1 * p2 * 5); 770 } 771 772 773 static void skl_ddi_clock_get(struct intel_encoder *encoder, 774 struct intel_crtc_state *pipe_config) 775 { 776 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 777 int link_clock = 0; 778 uint32_t dpll_ctl1, dpll; 779 780 dpll = pipe_config->ddi_pll_sel; 781 782 dpll_ctl1 = I915_READ(DPLL_CTRL1); 783 784 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 785 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 786 } else { 787 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll); 788 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll); 789 790 switch (link_clock) { 791 case DPLL_CRTL1_LINK_RATE_810: 792 link_clock = 81000; 793 break; 794 case DPLL_CRTL1_LINK_RATE_1080: 795 link_clock = 108000; 796 break; 797 case DPLL_CRTL1_LINK_RATE_1350: 798 link_clock = 135000; 799 break; 800 case DPLL_CRTL1_LINK_RATE_1620: 801 link_clock = 162000; 802 break; 803 case DPLL_CRTL1_LINK_RATE_2160: 804 link_clock = 216000; 805 break; 806 case DPLL_CRTL1_LINK_RATE_2700: 807 link_clock = 270000; 808 break; 809 default: 810 WARN(1, "Unsupported link rate\n"); 811 break; 812 } 813 link_clock *= 2; 814 } 815 816 pipe_config->port_clock = link_clock; 817 818 if (pipe_config->has_dp_encoder) 819 pipe_config->base.adjusted_mode.crtc_clock = 820 intel_dotclock_calculate(pipe_config->port_clock, 821 &pipe_config->dp_m_n); 822 else 823 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 824 } 825 826 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 827 struct intel_crtc_state *pipe_config) 828 { 829 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 830 int link_clock = 0; 831 u32 val, pll; 832 833 val = pipe_config->ddi_pll_sel; 834 switch (val & PORT_CLK_SEL_MASK) { 835 case PORT_CLK_SEL_LCPLL_810: 836 link_clock = 81000; 837 break; 838 case PORT_CLK_SEL_LCPLL_1350: 839 link_clock = 135000; 840 break; 841 case PORT_CLK_SEL_LCPLL_2700: 842 link_clock = 270000; 843 break; 844 case PORT_CLK_SEL_WRPLL1: 845 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); 846 break; 847 case PORT_CLK_SEL_WRPLL2: 848 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); 849 break; 850 case PORT_CLK_SEL_SPLL: 851 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 852 if (pll == SPLL_PLL_FREQ_810MHz) 853 link_clock = 81000; 854 else if (pll == SPLL_PLL_FREQ_1350MHz) 855 link_clock = 135000; 856 else if (pll == SPLL_PLL_FREQ_2700MHz) 857 link_clock = 270000; 858 else { 859 WARN(1, "bad spll freq\n"); 860 return; 861 } 862 break; 863 default: 864 WARN(1, "bad port clock sel\n"); 865 return; 866 } 867 868 pipe_config->port_clock = link_clock * 2; 869 870 if (pipe_config->has_pch_encoder) 871 pipe_config->base.adjusted_mode.crtc_clock = 872 intel_dotclock_calculate(pipe_config->port_clock, 873 &pipe_config->fdi_m_n); 874 else if (pipe_config->has_dp_encoder) 875 pipe_config->base.adjusted_mode.crtc_clock = 876 intel_dotclock_calculate(pipe_config->port_clock, 877 &pipe_config->dp_m_n); 878 else 879 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 880 } 881 882 void intel_ddi_clock_get(struct intel_encoder *encoder, 883 struct intel_crtc_state *pipe_config) 884 { 885 struct drm_device *dev = encoder->base.dev; 886 887 if (INTEL_INFO(dev)->gen <= 8) 888 hsw_ddi_clock_get(encoder, pipe_config); 889 else 890 skl_ddi_clock_get(encoder, pipe_config); 891 } 892 893 static void 894 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 895 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 896 { 897 uint64_t freq2k; 898 unsigned p, n2, r2; 899 struct wrpll_rnp best = { 0, 0, 0 }; 900 unsigned budget; 901 902 freq2k = clock / 100; 903 904 budget = wrpll_get_budget_for_freq(clock); 905 906 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 907 * and directly pass the LC PLL to it. */ 908 if (freq2k == 5400000) { 909 *n2_out = 2; 910 *p_out = 1; 911 *r2_out = 2; 912 return; 913 } 914 915 /* 916 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 917 * the WR PLL. 918 * 919 * We want R so that REF_MIN <= Ref <= REF_MAX. 920 * Injecting R2 = 2 * R gives: 921 * REF_MAX * r2 > LC_FREQ * 2 and 922 * REF_MIN * r2 < LC_FREQ * 2 923 * 924 * Which means the desired boundaries for r2 are: 925 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 926 * 927 */ 928 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 929 r2 <= LC_FREQ * 2 / REF_MIN; 930 r2++) { 931 932 /* 933 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 934 * 935 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 936 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 937 * VCO_MAX * r2 > n2 * LC_FREQ and 938 * VCO_MIN * r2 < n2 * LC_FREQ) 939 * 940 * Which means the desired boundaries for n2 are: 941 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 942 */ 943 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 944 n2 <= VCO_MAX * r2 / LC_FREQ; 945 n2++) { 946 947 for (p = P_MIN; p <= P_MAX; p += P_INC) 948 wrpll_update_rnp(freq2k, budget, 949 r2, n2, p, &best); 950 } 951 } 952 953 *n2_out = best.n2; 954 *p_out = best.p; 955 *r2_out = best.r2; 956 } 957 958 static bool 959 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 960 struct intel_crtc_state *crtc_state, 961 struct intel_encoder *intel_encoder, 962 int clock) 963 { 964 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 965 struct intel_shared_dpll *pll; 966 uint32_t val; 967 unsigned p, n2, r2; 968 969 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 970 971 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 972 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 973 WRPLL_DIVIDER_POST(p); 974 975 crtc_state->dpll_hw_state.wrpll = val; 976 977 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 978 if (pll == NULL) { 979 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 980 pipe_name(intel_crtc->pipe)); 981 return false; 982 } 983 984 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 985 } 986 987 return true; 988 } 989 990 struct skl_wrpll_params { 991 uint32_t dco_fraction; 992 uint32_t dco_integer; 993 uint32_t qdiv_ratio; 994 uint32_t qdiv_mode; 995 uint32_t kdiv; 996 uint32_t pdiv; 997 uint32_t central_freq; 998 }; 999 1000 static void 1001 skl_ddi_calculate_wrpll(int clock /* in Hz */, 1002 struct skl_wrpll_params *wrpll_params) 1003 { 1004 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 1005 uint64_t dco_central_freq[3] = {8400000000ULL, 1006 9000000000ULL, 1007 9600000000ULL}; 1008 uint32_t min_dco_deviation = 400; 1009 uint32_t min_dco_index = 3; 1010 uint32_t P0[4] = {1, 2, 3, 7}; 1011 uint32_t P2[4] = {1, 2, 3, 5}; 1012 bool found = false; 1013 uint32_t candidate_p = 0; 1014 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0}; 1015 uint32_t candidate_p2[3] = {0}; 1016 uint32_t dco_central_freq_deviation[3]; 1017 uint32_t i, P1, k, dco_count; 1018 bool retry_with_odd = false; 1019 uint64_t dco_freq; 1020 1021 /* Determine P0, P1 or P2 */ 1022 for (dco_count = 0; dco_count < 3; dco_count++) { 1023 found = false; 1024 candidate_p = 1025 div64_u64(dco_central_freq[dco_count], afe_clock); 1026 if (retry_with_odd == false) 1027 candidate_p = (candidate_p % 2 == 0 ? 1028 candidate_p : candidate_p + 1); 1029 1030 for (P1 = 1; P1 < candidate_p; P1++) { 1031 for (i = 0; i < 4; i++) { 1032 if (!(P0[i] != 1 || P1 == 1)) 1033 continue; 1034 1035 for (k = 0; k < 4; k++) { 1036 if (P1 != 1 && P2[k] != 2) 1037 continue; 1038 1039 if (candidate_p == P0[i] * P1 * P2[k]) { 1040 /* Found possible P0, P1, P2 */ 1041 found = true; 1042 candidate_p0[dco_count] = P0[i]; 1043 candidate_p1[dco_count] = P1; 1044 candidate_p2[dco_count] = P2[k]; 1045 goto found; 1046 } 1047 1048 } 1049 } 1050 } 1051 1052 found: 1053 if (found) { 1054 dco_central_freq_deviation[dco_count] = 1055 div64_u64(10000 * 1056 abs_diff((candidate_p * afe_clock), 1057 dco_central_freq[dco_count]), 1058 dco_central_freq[dco_count]); 1059 1060 if (dco_central_freq_deviation[dco_count] < 1061 min_dco_deviation) { 1062 min_dco_deviation = 1063 dco_central_freq_deviation[dco_count]; 1064 min_dco_index = dco_count; 1065 } 1066 } 1067 1068 if (min_dco_index > 2 && dco_count == 2) { 1069 retry_with_odd = true; 1070 dco_count = 0; 1071 } 1072 } 1073 1074 if (min_dco_index > 2) { 1075 WARN(1, "No valid values found for the given pixel clock\n"); 1076 } else { 1077 wrpll_params->central_freq = dco_central_freq[min_dco_index]; 1078 1079 switch (dco_central_freq[min_dco_index]) { 1080 case 9600000000ULL: 1081 wrpll_params->central_freq = 0; 1082 break; 1083 case 9000000000ULL: 1084 wrpll_params->central_freq = 1; 1085 break; 1086 case 8400000000ULL: 1087 wrpll_params->central_freq = 3; 1088 } 1089 1090 switch (candidate_p0[min_dco_index]) { 1091 case 1: 1092 wrpll_params->pdiv = 0; 1093 break; 1094 case 2: 1095 wrpll_params->pdiv = 1; 1096 break; 1097 case 3: 1098 wrpll_params->pdiv = 2; 1099 break; 1100 case 7: 1101 wrpll_params->pdiv = 4; 1102 break; 1103 default: 1104 WARN(1, "Incorrect PDiv\n"); 1105 } 1106 1107 switch (candidate_p2[min_dco_index]) { 1108 case 5: 1109 wrpll_params->kdiv = 0; 1110 break; 1111 case 2: 1112 wrpll_params->kdiv = 1; 1113 break; 1114 case 3: 1115 wrpll_params->kdiv = 2; 1116 break; 1117 case 1: 1118 wrpll_params->kdiv = 3; 1119 break; 1120 default: 1121 WARN(1, "Incorrect KDiv\n"); 1122 } 1123 1124 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index]; 1125 wrpll_params->qdiv_mode = 1126 (wrpll_params->qdiv_ratio == 1) ? 0 : 1; 1127 1128 dco_freq = candidate_p0[min_dco_index] * 1129 candidate_p1[min_dco_index] * 1130 candidate_p2[min_dco_index] * afe_clock; 1131 1132 /* 1133 * Intermediate values are in Hz. 1134 * Divide by MHz to match bsepc 1135 */ 1136 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1))); 1137 wrpll_params->dco_fraction = 1138 div_u64(((div_u64(dco_freq, 24) - 1139 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1)); 1140 1141 } 1142 } 1143 1144 1145 static bool 1146 skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1147 struct intel_crtc_state *crtc_state, 1148 struct intel_encoder *intel_encoder, 1149 int clock) 1150 { 1151 struct intel_shared_dpll *pll; 1152 uint32_t ctrl1, cfgcr1, cfgcr2; 1153 1154 /* 1155 * See comment in intel_dpll_hw_state to understand why we always use 0 1156 * as the DPLL id in this function. 1157 */ 1158 1159 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1160 1161 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1162 struct skl_wrpll_params wrpll_params = { 0, }; 1163 1164 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1165 1166 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params); 1167 1168 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1169 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1170 wrpll_params.dco_integer; 1171 1172 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1173 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1174 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1175 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1176 wrpll_params.central_freq; 1177 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 1178 struct drm_encoder *encoder = &intel_encoder->base; 1179 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1180 1181 switch (intel_dp->link_bw) { 1182 case DP_LINK_BW_1_62: 1183 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0); 1184 break; 1185 case DP_LINK_BW_2_7: 1186 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0); 1187 break; 1188 case DP_LINK_BW_5_4: 1189 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0); 1190 break; 1191 } 1192 1193 cfgcr1 = cfgcr2 = 0; 1194 } else /* eDP */ 1195 return true; 1196 1197 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1198 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1199 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1200 1201 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1202 if (pll == NULL) { 1203 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1204 pipe_name(intel_crtc->pipe)); 1205 return false; 1206 } 1207 1208 /* shared DPLL id 0 is DPLL 1 */ 1209 crtc_state->ddi_pll_sel = pll->id + 1; 1210 1211 return true; 1212 } 1213 1214 /* 1215 * Tries to find a *shared* PLL for the CRTC and store it in 1216 * intel_crtc->ddi_pll_sel. 1217 * 1218 * For private DPLLs, compute_config() should do the selection for us. This 1219 * function should be folded into compute_config() eventually. 1220 */ 1221 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, 1222 struct intel_crtc_state *crtc_state) 1223 { 1224 struct drm_device *dev = intel_crtc->base.dev; 1225 struct intel_encoder *intel_encoder = 1226 intel_ddi_get_crtc_new_encoder(crtc_state); 1227 int clock = crtc_state->port_clock; 1228 1229 if (IS_SKYLAKE(dev)) 1230 return skl_ddi_pll_select(intel_crtc, crtc_state, 1231 intel_encoder, clock); 1232 else 1233 return hsw_ddi_pll_select(intel_crtc, crtc_state, 1234 intel_encoder, clock); 1235 } 1236 1237 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1238 { 1239 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1241 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1242 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1243 int type = intel_encoder->type; 1244 uint32_t temp; 1245 1246 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1247 temp = TRANS_MSA_SYNC_CLK; 1248 switch (intel_crtc->config->pipe_bpp) { 1249 case 18: 1250 temp |= TRANS_MSA_6_BPC; 1251 break; 1252 case 24: 1253 temp |= TRANS_MSA_8_BPC; 1254 break; 1255 case 30: 1256 temp |= TRANS_MSA_10_BPC; 1257 break; 1258 case 36: 1259 temp |= TRANS_MSA_12_BPC; 1260 break; 1261 default: 1262 BUG(); 1263 } 1264 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1265 } 1266 } 1267 1268 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) 1269 { 1270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1271 struct drm_device *dev = crtc->dev; 1272 struct drm_i915_private *dev_priv = dev->dev_private; 1273 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1274 uint32_t temp; 1275 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1276 if (state == true) 1277 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1278 else 1279 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1280 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1281 } 1282 1283 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 1284 { 1285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1286 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1287 struct drm_encoder *encoder = &intel_encoder->base; 1288 struct drm_device *dev = crtc->dev; 1289 struct drm_i915_private *dev_priv = dev->dev_private; 1290 enum i915_pipe pipe = intel_crtc->pipe; 1291 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1292 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1293 int type = intel_encoder->type; 1294 uint32_t temp; 1295 1296 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1297 temp = TRANS_DDI_FUNC_ENABLE; 1298 temp |= TRANS_DDI_SELECT_PORT(port); 1299 1300 switch (intel_crtc->config->pipe_bpp) { 1301 case 18: 1302 temp |= TRANS_DDI_BPC_6; 1303 break; 1304 case 24: 1305 temp |= TRANS_DDI_BPC_8; 1306 break; 1307 case 30: 1308 temp |= TRANS_DDI_BPC_10; 1309 break; 1310 case 36: 1311 temp |= TRANS_DDI_BPC_12; 1312 break; 1313 default: 1314 BUG(); 1315 } 1316 1317 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1318 temp |= TRANS_DDI_PVSYNC; 1319 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1320 temp |= TRANS_DDI_PHSYNC; 1321 1322 if (cpu_transcoder == TRANSCODER_EDP) { 1323 switch (pipe) { 1324 case PIPE_A: 1325 /* On Haswell, can only use the always-on power well for 1326 * eDP when not using the panel fitter, and when not 1327 * using motion blur mitigation (which we don't 1328 * support). */ 1329 if (IS_HASWELL(dev) && 1330 (intel_crtc->config->pch_pfit.enabled || 1331 intel_crtc->config->pch_pfit.force_thru)) 1332 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1333 else 1334 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1335 break; 1336 case PIPE_B: 1337 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1338 break; 1339 case PIPE_C: 1340 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1341 break; 1342 default: 1343 BUG(); 1344 break; 1345 } 1346 } 1347 1348 if (type == INTEL_OUTPUT_HDMI) { 1349 if (intel_crtc->config->has_hdmi_sink) 1350 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1351 else 1352 temp |= TRANS_DDI_MODE_SELECT_DVI; 1353 1354 } else if (type == INTEL_OUTPUT_ANALOG) { 1355 temp |= TRANS_DDI_MODE_SELECT_FDI; 1356 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; 1357 1358 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1359 type == INTEL_OUTPUT_EDP) { 1360 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1361 1362 if (intel_dp->is_mst) { 1363 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1364 } else 1365 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1366 1367 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); 1368 } else if (type == INTEL_OUTPUT_DP_MST) { 1369 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; 1370 1371 if (intel_dp->is_mst) { 1372 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1373 } else 1374 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1375 1376 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); 1377 } else { 1378 WARN(1, "Invalid encoder type %d for pipe %c\n", 1379 intel_encoder->type, pipe_name(pipe)); 1380 } 1381 1382 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1383 } 1384 1385 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1386 enum transcoder cpu_transcoder) 1387 { 1388 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1389 uint32_t val = I915_READ(reg); 1390 1391 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1392 val |= TRANS_DDI_PORT_NONE; 1393 I915_WRITE(reg, val); 1394 } 1395 1396 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1397 { 1398 struct drm_device *dev = intel_connector->base.dev; 1399 struct drm_i915_private *dev_priv = dev->dev_private; 1400 struct intel_encoder *intel_encoder = intel_connector->encoder; 1401 int type = intel_connector->base.connector_type; 1402 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1403 enum i915_pipe pipe = 0; 1404 enum transcoder cpu_transcoder; 1405 enum intel_display_power_domain power_domain; 1406 uint32_t tmp; 1407 1408 power_domain = intel_display_port_power_domain(intel_encoder); 1409 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1410 return false; 1411 1412 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) 1413 return false; 1414 1415 if (port == PORT_A) 1416 cpu_transcoder = TRANSCODER_EDP; 1417 else 1418 cpu_transcoder = (enum transcoder) pipe; 1419 1420 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1421 1422 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1423 case TRANS_DDI_MODE_SELECT_HDMI: 1424 case TRANS_DDI_MODE_SELECT_DVI: 1425 return (type == DRM_MODE_CONNECTOR_HDMIA); 1426 1427 case TRANS_DDI_MODE_SELECT_DP_SST: 1428 if (type == DRM_MODE_CONNECTOR_eDP) 1429 return true; 1430 return (type == DRM_MODE_CONNECTOR_DisplayPort); 1431 case TRANS_DDI_MODE_SELECT_DP_MST: 1432 /* if the transcoder is in MST state then 1433 * connector isn't connected */ 1434 return false; 1435 1436 case TRANS_DDI_MODE_SELECT_FDI: 1437 return (type == DRM_MODE_CONNECTOR_VGA); 1438 1439 default: 1440 return false; 1441 } 1442 } 1443 1444 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1445 enum i915_pipe *pipe) 1446 { 1447 struct drm_device *dev = encoder->base.dev; 1448 struct drm_i915_private *dev_priv = dev->dev_private; 1449 enum port port = intel_ddi_get_encoder_port(encoder); 1450 enum intel_display_power_domain power_domain; 1451 u32 tmp; 1452 int i; 1453 1454 power_domain = intel_display_port_power_domain(encoder); 1455 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1456 return false; 1457 1458 tmp = I915_READ(DDI_BUF_CTL(port)); 1459 1460 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1461 return false; 1462 1463 if (port == PORT_A) { 1464 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1465 1466 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1467 case TRANS_DDI_EDP_INPUT_A_ON: 1468 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1469 *pipe = PIPE_A; 1470 break; 1471 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1472 *pipe = PIPE_B; 1473 break; 1474 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1475 *pipe = PIPE_C; 1476 break; 1477 } 1478 1479 return true; 1480 } else { 1481 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 1482 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 1483 1484 if ((tmp & TRANS_DDI_PORT_MASK) 1485 == TRANS_DDI_SELECT_PORT(port)) { 1486 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) 1487 return false; 1488 1489 *pipe = i; 1490 return true; 1491 } 1492 } 1493 } 1494 1495 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 1496 1497 return false; 1498 } 1499 1500 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 1501 { 1502 struct drm_crtc *crtc = &intel_crtc->base; 1503 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1504 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1505 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1506 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1507 1508 if (cpu_transcoder != TRANSCODER_EDP) 1509 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1510 TRANS_CLK_SEL_PORT(port)); 1511 } 1512 1513 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 1514 { 1515 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1516 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1517 1518 if (cpu_transcoder != TRANSCODER_EDP) 1519 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1520 TRANS_CLK_SEL_DISABLED); 1521 } 1522 1523 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 1524 { 1525 struct drm_encoder *encoder = &intel_encoder->base; 1526 struct drm_device *dev = encoder->dev; 1527 struct drm_i915_private *dev_priv = dev->dev_private; 1528 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 1529 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1530 int type = intel_encoder->type; 1531 1532 if (type == INTEL_OUTPUT_EDP) { 1533 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1534 intel_edp_panel_on(intel_dp); 1535 } 1536 1537 if (IS_SKYLAKE(dev)) { 1538 uint32_t dpll = crtc->config->ddi_pll_sel; 1539 uint32_t val; 1540 1541 /* 1542 * DPLL0 is used for eDP and is the only "private" DPLL (as 1543 * opposed to shared) on SKL 1544 */ 1545 if (type == INTEL_OUTPUT_EDP) { 1546 WARN_ON(dpll != SKL_DPLL0); 1547 1548 val = I915_READ(DPLL_CTRL1); 1549 1550 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | 1551 DPLL_CTRL1_SSC(dpll) | 1552 DPLL_CRTL1_LINK_RATE_MASK(dpll)); 1553 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); 1554 1555 I915_WRITE(DPLL_CTRL1, val); 1556 POSTING_READ(DPLL_CTRL1); 1557 } 1558 1559 /* DDI -> PLL mapping */ 1560 val = I915_READ(DPLL_CTRL2); 1561 1562 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 1563 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 1564 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | 1565 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1566 1567 I915_WRITE(DPLL_CTRL2, val); 1568 1569 } else { 1570 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); 1571 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); 1572 } 1573 1574 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1575 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1576 1577 intel_ddi_init_dp_buf_reg(intel_encoder); 1578 1579 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1580 intel_dp_start_link_train(intel_dp); 1581 intel_dp_complete_link_train(intel_dp); 1582 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) 1583 intel_dp_stop_link_train(intel_dp); 1584 } else if (type == INTEL_OUTPUT_HDMI) { 1585 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1586 1587 intel_hdmi->set_infoframes(encoder, 1588 crtc->config->has_hdmi_sink, 1589 &crtc->config->base.adjusted_mode); 1590 } 1591 } 1592 1593 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 1594 { 1595 struct drm_encoder *encoder = &intel_encoder->base; 1596 struct drm_device *dev = encoder->dev; 1597 struct drm_i915_private *dev_priv = dev->dev_private; 1598 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1599 int type = intel_encoder->type; 1600 uint32_t val; 1601 bool wait = false; 1602 1603 val = I915_READ(DDI_BUF_CTL(port)); 1604 if (val & DDI_BUF_CTL_ENABLE) { 1605 val &= ~DDI_BUF_CTL_ENABLE; 1606 I915_WRITE(DDI_BUF_CTL(port), val); 1607 wait = true; 1608 } 1609 1610 val = I915_READ(DP_TP_CTL(port)); 1611 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1612 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1613 I915_WRITE(DP_TP_CTL(port), val); 1614 1615 if (wait) 1616 intel_wait_ddi_buf_idle(dev_priv, port); 1617 1618 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1619 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1620 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1621 intel_edp_panel_vdd_on(intel_dp); 1622 intel_edp_panel_off(intel_dp); 1623 } 1624 1625 if (IS_SKYLAKE(dev)) 1626 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 1627 DPLL_CTRL2_DDI_CLK_OFF(port))); 1628 else 1629 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1630 } 1631 1632 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 1633 { 1634 struct drm_encoder *encoder = &intel_encoder->base; 1635 struct drm_crtc *crtc = encoder->crtc; 1636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1637 struct drm_device *dev = encoder->dev; 1638 struct drm_i915_private *dev_priv = dev->dev_private; 1639 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1640 int type = intel_encoder->type; 1641 1642 if (type == INTEL_OUTPUT_HDMI) { 1643 struct intel_digital_port *intel_dig_port = 1644 enc_to_dig_port(encoder); 1645 1646 /* In HDMI/DVI mode, the port width, and swing/emphasis values 1647 * are ignored so nothing special needs to be done besides 1648 * enabling the port. 1649 */ 1650 I915_WRITE(DDI_BUF_CTL(port), 1651 intel_dig_port->saved_port_bits | 1652 DDI_BUF_CTL_ENABLE); 1653 } else if (type == INTEL_OUTPUT_EDP) { 1654 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1655 1656 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) 1657 intel_dp_stop_link_train(intel_dp); 1658 1659 intel_edp_backlight_on(intel_dp); 1660 intel_psr_enable(intel_dp); 1661 intel_edp_drrs_enable(intel_dp); 1662 } 1663 1664 if (intel_crtc->config->has_audio) { 1665 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 1666 intel_audio_codec_enable(intel_encoder); 1667 } 1668 } 1669 1670 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 1671 { 1672 struct drm_encoder *encoder = &intel_encoder->base; 1673 struct drm_crtc *crtc = encoder->crtc; 1674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1675 int type = intel_encoder->type; 1676 struct drm_device *dev = encoder->dev; 1677 struct drm_i915_private *dev_priv = dev->dev_private; 1678 1679 if (intel_crtc->config->has_audio) { 1680 intel_audio_codec_disable(intel_encoder); 1681 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 1682 } 1683 1684 if (type == INTEL_OUTPUT_EDP) { 1685 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1686 1687 intel_edp_drrs_disable(intel_dp); 1688 intel_psr_disable(intel_dp); 1689 intel_edp_backlight_off(intel_dp); 1690 } 1691 } 1692 1693 static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv) 1694 { 1695 uint32_t lcpll1 = I915_READ(LCPLL1_CTL); 1696 uint32_t cdctl = I915_READ(CDCLK_CTL); 1697 uint32_t linkrate; 1698 1699 if (!(lcpll1 & LCPLL_PLL_ENABLE)) { 1700 WARN(1, "LCPLL1 not enabled\n"); 1701 return 24000; /* 24MHz is the cd freq with NSSC ref */ 1702 } 1703 1704 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) 1705 return 540000; 1706 1707 linkrate = (I915_READ(DPLL_CTRL1) & 1708 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; 1709 1710 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || 1711 linkrate == DPLL_CRTL1_LINK_RATE_1080) { 1712 /* vco 8640 */ 1713 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1714 case CDCLK_FREQ_450_432: 1715 return 432000; 1716 case CDCLK_FREQ_337_308: 1717 return 308570; 1718 case CDCLK_FREQ_675_617: 1719 return 617140; 1720 default: 1721 WARN(1, "Unknown cd freq selection\n"); 1722 } 1723 } else { 1724 /* vco 8100 */ 1725 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1726 case CDCLK_FREQ_450_432: 1727 return 450000; 1728 case CDCLK_FREQ_337_308: 1729 return 337500; 1730 case CDCLK_FREQ_675_617: 1731 return 675000; 1732 default: 1733 WARN(1, "Unknown cd freq selection\n"); 1734 } 1735 } 1736 1737 /* error case, do as if DPLL0 isn't enabled */ 1738 return 24000; 1739 } 1740 1741 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv) 1742 { 1743 uint32_t lcpll = I915_READ(LCPLL_CTL); 1744 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 1745 1746 if (lcpll & LCPLL_CD_SOURCE_FCLK) 1747 return 800000; 1748 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 1749 return 450000; 1750 else if (freq == LCPLL_CLK_FREQ_450) 1751 return 450000; 1752 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 1753 return 540000; 1754 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 1755 return 337500; 1756 else 1757 return 675000; 1758 } 1759 1760 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv) 1761 { 1762 struct drm_device *dev = dev_priv->dev; 1763 uint32_t lcpll = I915_READ(LCPLL_CTL); 1764 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 1765 1766 if (lcpll & LCPLL_CD_SOURCE_FCLK) 1767 return 800000; 1768 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 1769 return 450000; 1770 else if (freq == LCPLL_CLK_FREQ_450) 1771 return 450000; 1772 else if (IS_HSW_ULT(dev)) 1773 return 337500; 1774 else 1775 return 540000; 1776 } 1777 1778 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) 1779 { 1780 struct drm_device *dev = dev_priv->dev; 1781 1782 if (IS_SKYLAKE(dev)) 1783 return skl_get_cdclk_freq(dev_priv); 1784 1785 if (IS_BROADWELL(dev)) 1786 return bdw_get_cdclk_freq(dev_priv); 1787 1788 /* Haswell */ 1789 return hsw_get_cdclk_freq(dev_priv); 1790 } 1791 1792 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, 1793 struct intel_shared_dpll *pll) 1794 { 1795 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 1796 POSTING_READ(WRPLL_CTL(pll->id)); 1797 udelay(20); 1798 } 1799 1800 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, 1801 struct intel_shared_dpll *pll) 1802 { 1803 uint32_t val; 1804 1805 val = I915_READ(WRPLL_CTL(pll->id)); 1806 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 1807 POSTING_READ(WRPLL_CTL(pll->id)); 1808 } 1809 1810 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 1811 struct intel_shared_dpll *pll, 1812 struct intel_dpll_hw_state *hw_state) 1813 { 1814 uint32_t val; 1815 1816 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 1817 return false; 1818 1819 val = I915_READ(WRPLL_CTL(pll->id)); 1820 hw_state->wrpll = val; 1821 1822 return val & WRPLL_PLL_ENABLE; 1823 } 1824 1825 static const char * const hsw_ddi_pll_names[] = { 1826 "WRPLL 1", 1827 "WRPLL 2", 1828 }; 1829 1830 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) 1831 { 1832 int i; 1833 1834 dev_priv->num_shared_dpll = 2; 1835 1836 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 1837 dev_priv->shared_dplls[i].id = i; 1838 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 1839 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; 1840 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; 1841 dev_priv->shared_dplls[i].get_hw_state = 1842 hsw_ddi_pll_get_hw_state; 1843 } 1844 } 1845 1846 static const char * const skl_ddi_pll_names[] = { 1847 "DPLL 1", 1848 "DPLL 2", 1849 "DPLL 3", 1850 }; 1851 1852 struct skl_dpll_regs { 1853 u32 ctl, cfgcr1, cfgcr2; 1854 }; 1855 1856 /* this array is indexed by the *shared* pll id */ 1857 static const struct skl_dpll_regs skl_dpll_regs[3] = { 1858 { 1859 /* DPLL 1 */ 1860 .ctl = LCPLL2_CTL, 1861 .cfgcr1 = DPLL1_CFGCR1, 1862 .cfgcr2 = DPLL1_CFGCR2, 1863 }, 1864 { 1865 /* DPLL 2 */ 1866 .ctl = WRPLL_CTL1, 1867 .cfgcr1 = DPLL2_CFGCR1, 1868 .cfgcr2 = DPLL2_CFGCR2, 1869 }, 1870 { 1871 /* DPLL 3 */ 1872 .ctl = WRPLL_CTL2, 1873 .cfgcr1 = DPLL3_CFGCR1, 1874 .cfgcr2 = DPLL3_CFGCR2, 1875 }, 1876 }; 1877 1878 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 1879 struct intel_shared_dpll *pll) 1880 { 1881 uint32_t val; 1882 unsigned int dpll; 1883 const struct skl_dpll_regs *regs = skl_dpll_regs; 1884 1885 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 1886 dpll = pll->id + 1; 1887 1888 val = I915_READ(DPLL_CTRL1); 1889 1890 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | 1891 DPLL_CRTL1_LINK_RATE_MASK(dpll)); 1892 val |= pll->config.hw_state.ctrl1 << (dpll * 6); 1893 1894 I915_WRITE(DPLL_CTRL1, val); 1895 POSTING_READ(DPLL_CTRL1); 1896 1897 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 1898 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 1899 POSTING_READ(regs[pll->id].cfgcr1); 1900 POSTING_READ(regs[pll->id].cfgcr2); 1901 1902 /* the enable bit is always bit 31 */ 1903 I915_WRITE(regs[pll->id].ctl, 1904 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 1905 1906 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) 1907 DRM_ERROR("DPLL %d not locked\n", dpll); 1908 } 1909 1910 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 1911 struct intel_shared_dpll *pll) 1912 { 1913 const struct skl_dpll_regs *regs = skl_dpll_regs; 1914 1915 /* the enable bit is always bit 31 */ 1916 I915_WRITE(regs[pll->id].ctl, 1917 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 1918 POSTING_READ(regs[pll->id].ctl); 1919 } 1920 1921 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 1922 struct intel_shared_dpll *pll, 1923 struct intel_dpll_hw_state *hw_state) 1924 { 1925 uint32_t val; 1926 unsigned int dpll; 1927 const struct skl_dpll_regs *regs = skl_dpll_regs; 1928 1929 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 1930 return false; 1931 1932 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 1933 dpll = pll->id + 1; 1934 1935 val = I915_READ(regs[pll->id].ctl); 1936 if (!(val & LCPLL_PLL_ENABLE)) 1937 return false; 1938 1939 val = I915_READ(DPLL_CTRL1); 1940 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; 1941 1942 /* avoid reading back stale values if HDMI mode is not enabled */ 1943 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { 1944 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 1945 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 1946 } 1947 1948 return true; 1949 } 1950 1951 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) 1952 { 1953 int i; 1954 1955 dev_priv->num_shared_dpll = 3; 1956 1957 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 1958 dev_priv->shared_dplls[i].id = i; 1959 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; 1960 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; 1961 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; 1962 dev_priv->shared_dplls[i].get_hw_state = 1963 skl_ddi_pll_get_hw_state; 1964 } 1965 } 1966 1967 void intel_ddi_pll_init(struct drm_device *dev) 1968 { 1969 struct drm_i915_private *dev_priv = dev->dev_private; 1970 uint32_t val = I915_READ(LCPLL_CTL); 1971 1972 if (IS_SKYLAKE(dev)) 1973 skl_shared_dplls_init(dev_priv); 1974 else 1975 hsw_shared_dplls_init(dev_priv); 1976 1977 DRM_DEBUG_KMS("CDCLK running at %dKHz\n", 1978 intel_ddi_get_cdclk_freq(dev_priv)); 1979 1980 if (IS_SKYLAKE(dev)) { 1981 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) 1982 DRM_ERROR("LCPLL1 is disabled\n"); 1983 } else { 1984 /* 1985 * The LCPLL register should be turned on by the BIOS. For now 1986 * let's just check its state and print errors in case 1987 * something is wrong. Don't even try to turn it on. 1988 */ 1989 1990 if (val & LCPLL_CD_SOURCE_FCLK) 1991 DRM_ERROR("CDCLK source is not LCPLL\n"); 1992 1993 if (val & LCPLL_PLL_DISABLE) 1994 DRM_ERROR("LCPLL is disabled\n"); 1995 } 1996 } 1997 1998 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 1999 { 2000 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2001 struct intel_dp *intel_dp = &intel_dig_port->dp; 2002 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 2003 enum port port = intel_dig_port->port; 2004 uint32_t val; 2005 bool wait = false; 2006 2007 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 2008 val = I915_READ(DDI_BUF_CTL(port)); 2009 if (val & DDI_BUF_CTL_ENABLE) { 2010 val &= ~DDI_BUF_CTL_ENABLE; 2011 I915_WRITE(DDI_BUF_CTL(port), val); 2012 wait = true; 2013 } 2014 2015 val = I915_READ(DP_TP_CTL(port)); 2016 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2017 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2018 I915_WRITE(DP_TP_CTL(port), val); 2019 POSTING_READ(DP_TP_CTL(port)); 2020 2021 if (wait) 2022 intel_wait_ddi_buf_idle(dev_priv, port); 2023 } 2024 2025 val = DP_TP_CTL_ENABLE | 2026 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 2027 if (intel_dp->is_mst) 2028 val |= DP_TP_CTL_MODE_MST; 2029 else { 2030 val |= DP_TP_CTL_MODE_SST; 2031 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2032 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 2033 } 2034 I915_WRITE(DP_TP_CTL(port), val); 2035 POSTING_READ(DP_TP_CTL(port)); 2036 2037 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 2038 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 2039 POSTING_READ(DDI_BUF_CTL(port)); 2040 2041 udelay(600); 2042 } 2043 2044 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 2045 { 2046 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 2047 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2048 uint32_t val; 2049 2050 intel_ddi_post_disable(intel_encoder); 2051 2052 val = I915_READ(_FDI_RXA_CTL); 2053 val &= ~FDI_RX_ENABLE; 2054 I915_WRITE(_FDI_RXA_CTL, val); 2055 2056 val = I915_READ(_FDI_RXA_MISC); 2057 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 2058 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 2059 I915_WRITE(_FDI_RXA_MISC, val); 2060 2061 val = I915_READ(_FDI_RXA_CTL); 2062 val &= ~FDI_PCDCLK; 2063 I915_WRITE(_FDI_RXA_CTL, val); 2064 2065 val = I915_READ(_FDI_RXA_CTL); 2066 val &= ~FDI_RX_PLL_ENABLE; 2067 I915_WRITE(_FDI_RXA_CTL, val); 2068 } 2069 2070 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) 2071 { 2072 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base); 2073 int type = intel_dig_port->base.type; 2074 2075 if (type != INTEL_OUTPUT_DISPLAYPORT && 2076 type != INTEL_OUTPUT_EDP && 2077 type != INTEL_OUTPUT_UNKNOWN) { 2078 return; 2079 } 2080 2081 intel_dp_hot_plug(intel_encoder); 2082 } 2083 2084 void intel_ddi_get_config(struct intel_encoder *encoder, 2085 struct intel_crtc_state *pipe_config) 2086 { 2087 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 2088 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2089 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2090 struct intel_hdmi *intel_hdmi; 2091 u32 temp, flags = 0; 2092 2093 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2094 if (temp & TRANS_DDI_PHSYNC) 2095 flags |= DRM_MODE_FLAG_PHSYNC; 2096 else 2097 flags |= DRM_MODE_FLAG_NHSYNC; 2098 if (temp & TRANS_DDI_PVSYNC) 2099 flags |= DRM_MODE_FLAG_PVSYNC; 2100 else 2101 flags |= DRM_MODE_FLAG_NVSYNC; 2102 2103 pipe_config->base.adjusted_mode.flags |= flags; 2104 2105 switch (temp & TRANS_DDI_BPC_MASK) { 2106 case TRANS_DDI_BPC_6: 2107 pipe_config->pipe_bpp = 18; 2108 break; 2109 case TRANS_DDI_BPC_8: 2110 pipe_config->pipe_bpp = 24; 2111 break; 2112 case TRANS_DDI_BPC_10: 2113 pipe_config->pipe_bpp = 30; 2114 break; 2115 case TRANS_DDI_BPC_12: 2116 pipe_config->pipe_bpp = 36; 2117 break; 2118 default: 2119 break; 2120 } 2121 2122 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 2123 case TRANS_DDI_MODE_SELECT_HDMI: 2124 pipe_config->has_hdmi_sink = true; 2125 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 2126 2127 if (intel_hdmi->infoframe_enabled(&encoder->base)) 2128 pipe_config->has_infoframe = true; 2129 break; 2130 case TRANS_DDI_MODE_SELECT_DVI: 2131 case TRANS_DDI_MODE_SELECT_FDI: 2132 break; 2133 case TRANS_DDI_MODE_SELECT_DP_SST: 2134 case TRANS_DDI_MODE_SELECT_DP_MST: 2135 pipe_config->has_dp_encoder = true; 2136 intel_dp_get_m_n(intel_crtc, pipe_config); 2137 break; 2138 default: 2139 break; 2140 } 2141 2142 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 2143 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 2144 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 2145 pipe_config->has_audio = true; 2146 } 2147 2148 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && 2149 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 2150 /* 2151 * This is a big fat ugly hack. 2152 * 2153 * Some machines in UEFI boot mode provide us a VBT that has 18 2154 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 2155 * unknown we fail to light up. Yet the same BIOS boots up with 2156 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 2157 * max, not what it tells us to use. 2158 * 2159 * Note: This will still be broken if the eDP panel is not lit 2160 * up by the BIOS, and thus we can't get the mode at module 2161 * load. 2162 */ 2163 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 2164 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 2165 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 2166 } 2167 2168 intel_ddi_clock_get(encoder, pipe_config); 2169 } 2170 2171 static void intel_ddi_destroy(struct drm_encoder *encoder) 2172 { 2173 /* HDMI has nothing special to destroy, so we can go with this. */ 2174 intel_dp_encoder_destroy(encoder); 2175 } 2176 2177 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 2178 struct intel_crtc_state *pipe_config) 2179 { 2180 int type = encoder->type; 2181 int port = intel_ddi_get_encoder_port(encoder); 2182 2183 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 2184 2185 if (port == PORT_A) 2186 pipe_config->cpu_transcoder = TRANSCODER_EDP; 2187 2188 if (type == INTEL_OUTPUT_HDMI) 2189 return intel_hdmi_compute_config(encoder, pipe_config); 2190 else 2191 return intel_dp_compute_config(encoder, pipe_config); 2192 } 2193 2194 static const struct drm_encoder_funcs intel_ddi_funcs = { 2195 .destroy = intel_ddi_destroy, 2196 }; 2197 2198 static struct intel_connector * 2199 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 2200 { 2201 struct intel_connector *connector; 2202 enum port port = intel_dig_port->port; 2203 2204 connector = intel_connector_alloc(); 2205 if (!connector) 2206 return NULL; 2207 2208 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 2209 if (!intel_dp_init_connector(intel_dig_port, connector)) { 2210 kfree(connector); 2211 return NULL; 2212 } 2213 2214 return connector; 2215 } 2216 2217 static struct intel_connector * 2218 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 2219 { 2220 struct intel_connector *connector; 2221 enum port port = intel_dig_port->port; 2222 2223 connector = intel_connector_alloc(); 2224 if (!connector) 2225 return NULL; 2226 2227 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 2228 intel_hdmi_init_connector(intel_dig_port, connector); 2229 2230 return connector; 2231 } 2232 2233 void intel_ddi_init(struct drm_device *dev, enum port port) 2234 { 2235 struct drm_i915_private *dev_priv = dev->dev_private; 2236 struct intel_digital_port *intel_dig_port; 2237 struct intel_encoder *intel_encoder; 2238 struct drm_encoder *encoder; 2239 bool init_hdmi, init_dp; 2240 2241 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 2242 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 2243 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 2244 if (!init_dp && !init_hdmi) { 2245 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", 2246 port_name(port)); 2247 init_hdmi = true; 2248 init_dp = true; 2249 } 2250 2251 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2252 if (!intel_dig_port) 2253 return; 2254 2255 intel_encoder = &intel_dig_port->base; 2256 encoder = &intel_encoder->base; 2257 2258 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 2259 DRM_MODE_ENCODER_TMDS); 2260 2261 intel_encoder->compute_config = intel_ddi_compute_config; 2262 intel_encoder->enable = intel_enable_ddi; 2263 intel_encoder->pre_enable = intel_ddi_pre_enable; 2264 intel_encoder->disable = intel_disable_ddi; 2265 intel_encoder->post_disable = intel_ddi_post_disable; 2266 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 2267 intel_encoder->get_config = intel_ddi_get_config; 2268 2269 intel_dig_port->port = port; 2270 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 2271 (DDI_BUF_PORT_REVERSAL | 2272 DDI_A_4_LANES); 2273 2274 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 2275 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2276 intel_encoder->cloneable = 0; 2277 intel_encoder->hot_plug = intel_ddi_hot_plug; 2278 2279 if (init_dp) { 2280 if (!intel_ddi_init_dp_connector(intel_dig_port)) 2281 goto err; 2282 2283 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 2284 dev_priv->hpd_irq_port[port] = intel_dig_port; 2285 } 2286 2287 /* In theory we don't need the encoder->type check, but leave it just in 2288 * case we have some really bad VBTs... */ 2289 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 2290 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 2291 goto err; 2292 } 2293 2294 return; 2295 2296 err: 2297 drm_encoder_cleanup(encoder); 2298 kfree(intel_dig_port); 2299 } 2300