1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <asm/int-ll64.h> 31 32 struct ddi_buf_trans { 33 u32 trans1; /* balance leg enable, de-emph level */ 34 u32 trans2; /* vref sel, vswing */ 35 }; 36 37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 38 * them for both DP and FDI transports, allowing those ports to 39 * automatically adapt to HDMI connections as well 40 */ 41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 42 { 0x00FFFFFF, 0x0006000E }, 43 { 0x00D75FFF, 0x0005000A }, 44 { 0x00C30FFF, 0x00040006 }, 45 { 0x80AAAFFF, 0x000B0000 }, 46 { 0x00FFFFFF, 0x0005000A }, 47 { 0x00D75FFF, 0x000C0004 }, 48 { 0x80C30FFF, 0x000B0000 }, 49 { 0x00FFFFFF, 0x00040006 }, 50 { 0x80D75FFF, 0x000B0000 }, 51 }; 52 53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 54 { 0x00FFFFFF, 0x0007000E }, 55 { 0x00D75FFF, 0x000F000A }, 56 { 0x00C30FFF, 0x00060006 }, 57 { 0x00AAAFFF, 0x001E0000 }, 58 { 0x00FFFFFF, 0x000F000A }, 59 { 0x00D75FFF, 0x00160004 }, 60 { 0x00C30FFF, 0x001E0000 }, 61 { 0x00FFFFFF, 0x00060006 }, 62 { 0x00D75FFF, 0x001E0000 }, 63 }; 64 65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 66 /* Idx NT mV d T mV d db */ 67 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */ 68 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */ 69 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */ 70 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */ 71 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */ 72 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */ 73 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */ 74 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */ 75 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */ 76 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */ 77 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */ 78 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */ 79 }; 80 81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 82 { 0x00FFFFFF, 0x00000012 }, 83 { 0x00EBAFFF, 0x00020011 }, 84 { 0x00C71FFF, 0x0006000F }, 85 { 0x00AAAFFF, 0x000E000A }, 86 { 0x00FFFFFF, 0x00020011 }, 87 { 0x00DB6FFF, 0x0005000F }, 88 { 0x00BEEFFF, 0x000A000C }, 89 { 0x00FFFFFF, 0x0005000F }, 90 { 0x00DB6FFF, 0x000A000C }, 91 }; 92 93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 94 { 0x00FFFFFF, 0x0007000E }, 95 { 0x00D75FFF, 0x000E000A }, 96 { 0x00BEFFFF, 0x00140006 }, 97 { 0x80B2CFFF, 0x001B0002 }, 98 { 0x00FFFFFF, 0x000E000A }, 99 { 0x00DB6FFF, 0x00160005 }, 100 { 0x80C71FFF, 0x001A0002 }, 101 { 0x00F7DFFF, 0x00180004 }, 102 { 0x80D75FFF, 0x001B0002 }, 103 }; 104 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 106 { 0x00FFFFFF, 0x0001000E }, 107 { 0x00D75FFF, 0x0004000A }, 108 { 0x00C30FFF, 0x00070006 }, 109 { 0x00AAAFFF, 0x000C0000 }, 110 { 0x00FFFFFF, 0x0004000A }, 111 { 0x00D75FFF, 0x00090004 }, 112 { 0x00C30FFF, 0x000C0000 }, 113 { 0x00FFFFFF, 0x00070006 }, 114 { 0x00D75FFF, 0x000C0000 }, 115 }; 116 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 118 /* Idx NT mV d T mV df db */ 119 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */ 120 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */ 121 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */ 122 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */ 123 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */ 124 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */ 125 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */ 126 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */ 127 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */ 128 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */ 129 }; 130 131 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 132 { 0x00000018, 0x000000a2 }, 133 { 0x00004014, 0x0000009B }, 134 { 0x00006012, 0x00000088 }, 135 { 0x00008010, 0x00000087 }, 136 { 0x00000018, 0x0000009B }, 137 { 0x00004014, 0x00000088 }, 138 { 0x00006012, 0x00000087 }, 139 { 0x00000018, 0x00000088 }, 140 { 0x00004014, 0x00000087 }, 141 }; 142 143 /* eDP 1.4 low vswing translation parameters */ 144 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 145 { 0x00000018, 0x000000a8 }, 146 { 0x00002016, 0x000000ab }, 147 { 0x00006012, 0x000000a2 }, 148 { 0x00008010, 0x00000088 }, 149 { 0x00000018, 0x000000ab }, 150 { 0x00004014, 0x000000a2 }, 151 { 0x00006012, 0x000000a6 }, 152 { 0x00000018, 0x000000a2 }, 153 { 0x00005013, 0x0000009c }, 154 { 0x00000018, 0x00000088 }, 155 }; 156 157 158 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 159 { 0x00000018, 0x000000ac }, 160 { 0x00005012, 0x0000009d }, 161 { 0x00007011, 0x00000088 }, 162 { 0x00000018, 0x000000a1 }, 163 { 0x00000018, 0x00000098 }, 164 { 0x00004013, 0x00000088 }, 165 { 0x00006012, 0x00000087 }, 166 { 0x00000018, 0x000000df }, 167 { 0x00003015, 0x00000087 }, 168 { 0x00003015, 0x000000c7 }, 169 { 0x00000018, 0x000000c7 }, 170 }; 171 172 struct bxt_ddi_buf_trans { 173 u32 margin; /* swing value */ 174 u32 scale; /* scale value */ 175 u32 enable; /* scale enable */ 176 u32 deemphasis; 177 bool default_index; /* true if the entry represents default value */ 178 }; 179 180 /* BSpec does not define separate vswing/pre-emphasis values for eDP. 181 * Using DP values for eDP as well. 182 */ 183 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 184 /* Idx NT mV diff db */ 185 { 52, 0, 0, 128, true }, /* 0: 400 0 */ 186 { 78, 0, 0, 85, false }, /* 1: 400 3.5 */ 187 { 104, 0, 0, 64, false }, /* 2: 400 6 */ 188 { 154, 0, 0, 43, false }, /* 3: 400 9.5 */ 189 { 77, 0, 0, 128, false }, /* 4: 600 0 */ 190 { 116, 0, 0, 85, false }, /* 5: 600 3.5 */ 191 { 154, 0, 0, 64, false }, /* 6: 600 6 */ 192 { 102, 0, 0, 128, false }, /* 7: 800 0 */ 193 { 154, 0, 0, 85, false }, /* 8: 800 3.5 */ 194 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ 195 }; 196 197 /* BSpec has 2 recommended values - entries 0 and 8. 198 * Using the entry with higher vswing. 199 */ 200 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 201 /* Idx NT mV diff db */ 202 { 52, 0, 0, 128, false }, /* 0: 400 0 */ 203 { 52, 0, 0, 85, false }, /* 1: 400 3.5 */ 204 { 52, 0, 0, 64, false }, /* 2: 400 6 */ 205 { 42, 0, 0, 43, false }, /* 3: 400 9.5 */ 206 { 77, 0, 0, 128, false }, /* 4: 600 0 */ 207 { 77, 0, 0, 85, false }, /* 5: 600 3.5 */ 208 { 77, 0, 0, 64, false }, /* 6: 600 6 */ 209 { 102, 0, 0, 128, false }, /* 7: 800 0 */ 210 { 102, 0, 0, 85, false }, /* 8: 800 3.5 */ 211 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ 212 }; 213 214 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, 215 struct intel_digital_port **dig_port, 216 enum port *port) 217 { 218 struct drm_encoder *encoder = &intel_encoder->base; 219 int type = intel_encoder->type; 220 221 if (type == INTEL_OUTPUT_DP_MST) { 222 *dig_port = enc_to_mst(encoder)->primary; 223 *port = (*dig_port)->port; 224 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || 225 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { 226 *dig_port = enc_to_dig_port(encoder); 227 *port = (*dig_port)->port; 228 } else if (type == INTEL_OUTPUT_ANALOG) { 229 *dig_port = NULL; 230 *port = PORT_E; 231 } else { 232 DRM_ERROR("Invalid DDI encoder type %d\n", type); 233 BUG(); 234 } 235 } 236 237 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 238 { 239 struct intel_digital_port *dig_port; 240 enum port port; 241 242 ddi_get_encoder_port(intel_encoder, &dig_port, &port); 243 244 return port; 245 } 246 247 static bool 248 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) 249 { 250 return intel_dig_port->hdmi.hdmi_reg; 251 } 252 253 /* 254 * Starting with Haswell, DDI port buffers must be programmed with correct 255 * values in advance. The buffer values are different for FDI and DP modes, 256 * but the HDMI/DVI fields are shared among those. So we program the DDI 257 * in either FDI or DP modes only, as HDMI connections will work with both 258 * of those 259 */ 260 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, 261 bool supports_hdmi) 262 { 263 struct drm_i915_private *dev_priv = dev->dev_private; 264 u32 reg; 265 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, 266 size; 267 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 268 const struct ddi_buf_trans *ddi_translations_fdi; 269 const struct ddi_buf_trans *ddi_translations_dp; 270 const struct ddi_buf_trans *ddi_translations_edp; 271 const struct ddi_buf_trans *ddi_translations_hdmi; 272 const struct ddi_buf_trans *ddi_translations; 273 274 if (IS_BROXTON(dev)) { 275 if (!supports_hdmi) 276 return; 277 278 /* Vswing programming for HDMI */ 279 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 280 INTEL_OUTPUT_HDMI); 281 return; 282 } else if (IS_SKYLAKE(dev)) { 283 ddi_translations_fdi = NULL; 284 ddi_translations_dp = skl_ddi_translations_dp; 285 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp); 286 if (dev_priv->edp_low_vswing) { 287 ddi_translations_edp = skl_ddi_translations_edp; 288 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp); 289 } else { 290 ddi_translations_edp = skl_ddi_translations_dp; 291 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp); 292 } 293 294 ddi_translations_hdmi = skl_ddi_translations_hdmi; 295 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 296 hdmi_default_entry = 7; 297 } else if (IS_BROADWELL(dev)) { 298 ddi_translations_fdi = bdw_ddi_translations_fdi; 299 ddi_translations_dp = bdw_ddi_translations_dp; 300 ddi_translations_edp = bdw_ddi_translations_edp; 301 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 302 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 303 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 304 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 305 hdmi_default_entry = 7; 306 } else if (IS_HASWELL(dev)) { 307 ddi_translations_fdi = hsw_ddi_translations_fdi; 308 ddi_translations_dp = hsw_ddi_translations_dp; 309 ddi_translations_edp = hsw_ddi_translations_dp; 310 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 311 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 312 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 313 hdmi_default_entry = 6; 314 } else { 315 WARN(1, "ddi translation table missing\n"); 316 ddi_translations_edp = bdw_ddi_translations_dp; 317 ddi_translations_fdi = bdw_ddi_translations_fdi; 318 ddi_translations_dp = bdw_ddi_translations_dp; 319 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 320 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 321 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 322 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 323 hdmi_default_entry = 7; 324 } 325 326 switch (port) { 327 case PORT_A: 328 ddi_translations = ddi_translations_edp; 329 size = n_edp_entries; 330 break; 331 case PORT_B: 332 case PORT_C: 333 ddi_translations = ddi_translations_dp; 334 size = n_dp_entries; 335 break; 336 case PORT_D: 337 if (intel_dp_is_edp(dev, PORT_D)) { 338 ddi_translations = ddi_translations_edp; 339 size = n_edp_entries; 340 } else { 341 ddi_translations = ddi_translations_dp; 342 size = n_dp_entries; 343 } 344 break; 345 case PORT_E: 346 if (ddi_translations_fdi) 347 ddi_translations = ddi_translations_fdi; 348 else 349 ddi_translations = ddi_translations_dp; 350 size = n_dp_entries; 351 break; 352 default: 353 BUG(); 354 } 355 356 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) { 357 I915_WRITE(reg, ddi_translations[i].trans1); 358 reg += 4; 359 I915_WRITE(reg, ddi_translations[i].trans2); 360 reg += 4; 361 } 362 363 if (!supports_hdmi) 364 return; 365 366 /* Choose a good default if VBT is badly populated */ 367 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 368 hdmi_level >= n_hdmi_entries) 369 hdmi_level = hdmi_default_entry; 370 371 /* Entry 9 is for HDMI: */ 372 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1); 373 reg += 4; 374 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2); 375 reg += 4; 376 } 377 378 /* Program DDI buffers translations for DP. By default, program ports A-D in DP 379 * mode and port E for FDI. 380 */ 381 void intel_prepare_ddi(struct drm_device *dev) 382 { 383 struct intel_encoder *intel_encoder; 384 bool visited[I915_MAX_PORTS] = { 0, }; 385 386 if (!HAS_DDI(dev)) 387 return; 388 389 for_each_intel_encoder(dev, intel_encoder) { 390 struct intel_digital_port *intel_dig_port; 391 enum port port; 392 bool supports_hdmi; 393 394 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port); 395 396 if (visited[port]) 397 continue; 398 399 supports_hdmi = intel_dig_port && 400 intel_dig_port_supports_hdmi(intel_dig_port); 401 402 intel_prepare_ddi_buffers(dev, port, supports_hdmi); 403 visited[port] = true; 404 } 405 } 406 407 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 408 enum port port) 409 { 410 uint32_t reg = DDI_BUF_CTL(port); 411 int i; 412 413 for (i = 0; i < 16; i++) { 414 udelay(1); 415 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 416 return; 417 } 418 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 419 } 420 421 /* Starting with Haswell, different DDI ports can work in FDI mode for 422 * connection to the PCH-located connectors. For this, it is necessary to train 423 * both the DDI port and PCH receiver for the desired DDI buffer settings. 424 * 425 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 426 * please note that when FDI mode is active on DDI E, it shares 2 lines with 427 * DDI A (which is used for eDP) 428 */ 429 430 void hsw_fdi_link_train(struct drm_crtc *crtc) 431 { 432 struct drm_device *dev = crtc->dev; 433 struct drm_i915_private *dev_priv = dev->dev_private; 434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 435 u32 temp, i, rx_ctl_val; 436 437 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 438 * mode set "sequence for CRT port" document: 439 * - TP1 to TP2 time with the default value 440 * - FDI delay to 90h 441 * 442 * WaFDIAutoLinkSetTimingOverrride:hsw 443 */ 444 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | 445 FDI_RX_PWRDN_LANE0_VAL(2) | 446 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 447 448 /* Enable the PCH Receiver FDI PLL */ 449 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 450 FDI_RX_PLL_ENABLE | 451 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 452 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 453 POSTING_READ(_FDI_RXA_CTL); 454 udelay(220); 455 456 /* Switch from Rawclk to PCDclk */ 457 rx_ctl_val |= FDI_PCDCLK; 458 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 459 460 /* Configure Port Clock Select */ 461 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); 462 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); 463 464 /* Start the training iterating through available voltages and emphasis, 465 * testing each value twice. */ 466 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 467 /* Configure DP_TP_CTL with auto-training */ 468 I915_WRITE(DP_TP_CTL(PORT_E), 469 DP_TP_CTL_FDI_AUTOTRAIN | 470 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 471 DP_TP_CTL_LINK_TRAIN_PAT1 | 472 DP_TP_CTL_ENABLE); 473 474 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 475 * DDI E does not support port reversal, the functionality is 476 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 477 * port reversal bit */ 478 I915_WRITE(DDI_BUF_CTL(PORT_E), 479 DDI_BUF_CTL_ENABLE | 480 ((intel_crtc->config->fdi_lanes - 1) << 1) | 481 DDI_BUF_TRANS_SELECT(i / 2)); 482 POSTING_READ(DDI_BUF_CTL(PORT_E)); 483 484 udelay(600); 485 486 /* Program PCH FDI Receiver TU */ 487 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); 488 489 /* Enable PCH FDI Receiver with auto-training */ 490 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 491 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 492 POSTING_READ(_FDI_RXA_CTL); 493 494 /* Wait for FDI receiver lane calibration */ 495 udelay(30); 496 497 /* Unset FDI_RX_MISC pwrdn lanes */ 498 temp = I915_READ(_FDI_RXA_MISC); 499 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 500 I915_WRITE(_FDI_RXA_MISC, temp); 501 POSTING_READ(_FDI_RXA_MISC); 502 503 /* Wait for FDI auto training time */ 504 udelay(5); 505 506 temp = I915_READ(DP_TP_STATUS(PORT_E)); 507 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 508 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 509 510 /* Enable normal pixel sending for FDI */ 511 I915_WRITE(DP_TP_CTL(PORT_E), 512 DP_TP_CTL_FDI_AUTOTRAIN | 513 DP_TP_CTL_LINK_TRAIN_NORMAL | 514 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 515 DP_TP_CTL_ENABLE); 516 517 return; 518 } 519 520 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 521 temp &= ~DDI_BUF_CTL_ENABLE; 522 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 523 POSTING_READ(DDI_BUF_CTL(PORT_E)); 524 525 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 526 temp = I915_READ(DP_TP_CTL(PORT_E)); 527 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 528 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 529 I915_WRITE(DP_TP_CTL(PORT_E), temp); 530 POSTING_READ(DP_TP_CTL(PORT_E)); 531 532 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 533 534 rx_ctl_val &= ~FDI_RX_ENABLE; 535 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 536 POSTING_READ(_FDI_RXA_CTL); 537 538 /* Reset FDI_RX_MISC pwrdn lanes */ 539 temp = I915_READ(_FDI_RXA_MISC); 540 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 541 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 542 I915_WRITE(_FDI_RXA_MISC, temp); 543 POSTING_READ(_FDI_RXA_MISC); 544 } 545 546 DRM_ERROR("FDI link training failed!\n"); 547 } 548 549 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 550 { 551 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 552 struct intel_digital_port *intel_dig_port = 553 enc_to_dig_port(&encoder->base); 554 555 intel_dp->DP = intel_dig_port->saved_port_bits | 556 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 557 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 558 559 } 560 561 static struct intel_encoder * 562 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 563 { 564 struct drm_device *dev = crtc->dev; 565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 566 struct intel_encoder *intel_encoder, *ret = NULL; 567 int num_encoders = 0; 568 569 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 570 ret = intel_encoder; 571 num_encoders++; 572 } 573 574 if (num_encoders != 1) 575 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 576 pipe_name(intel_crtc->pipe)); 577 578 BUG_ON(ret == NULL); 579 return ret; 580 } 581 582 struct intel_encoder * 583 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 584 { 585 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 586 struct intel_encoder *ret = NULL; 587 struct drm_atomic_state *state; 588 struct drm_connector *connector; 589 struct drm_connector_state *connector_state; 590 int num_encoders = 0; 591 int i; 592 593 state = crtc_state->base.state; 594 595 for_each_connector_in_state(state, connector, connector_state, i) { 596 if (connector_state->crtc != crtc_state->base.crtc) 597 continue; 598 599 ret = to_intel_encoder(connector_state->best_encoder); 600 num_encoders++; 601 } 602 603 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 604 pipe_name(crtc->pipe)); 605 606 BUG_ON(ret == NULL); 607 return ret; 608 } 609 610 #define LC_FREQ 2700 611 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 612 613 #define P_MIN 2 614 #define P_MAX 64 615 #define P_INC 2 616 617 /* Constraints for PLL good behavior */ 618 #define REF_MIN 48 619 #define REF_MAX 400 620 #define VCO_MIN 2400 621 #define VCO_MAX 4800 622 623 #define abs_diff(a, b) ({ \ 624 typeof(a) __a = (a); \ 625 typeof(b) __b = (b); \ 626 (void) (&__a == &__b); \ 627 __a > __b ? (__a - __b) : (__b - __a); }) 628 629 struct wrpll_rnp { 630 unsigned p, n2, r2; 631 }; 632 633 static unsigned wrpll_get_budget_for_freq(int clock) 634 { 635 unsigned budget; 636 637 switch (clock) { 638 case 25175000: 639 case 25200000: 640 case 27000000: 641 case 27027000: 642 case 37762500: 643 case 37800000: 644 case 40500000: 645 case 40541000: 646 case 54000000: 647 case 54054000: 648 case 59341000: 649 case 59400000: 650 case 72000000: 651 case 74176000: 652 case 74250000: 653 case 81000000: 654 case 81081000: 655 case 89012000: 656 case 89100000: 657 case 108000000: 658 case 108108000: 659 case 111264000: 660 case 111375000: 661 case 148352000: 662 case 148500000: 663 case 162000000: 664 case 162162000: 665 case 222525000: 666 case 222750000: 667 case 296703000: 668 case 297000000: 669 budget = 0; 670 break; 671 case 233500000: 672 case 245250000: 673 case 247750000: 674 case 253250000: 675 case 298000000: 676 budget = 1500; 677 break; 678 case 169128000: 679 case 169500000: 680 case 179500000: 681 case 202000000: 682 budget = 2000; 683 break; 684 case 256250000: 685 case 262500000: 686 case 270000000: 687 case 272500000: 688 case 273750000: 689 case 280750000: 690 case 281250000: 691 case 286000000: 692 case 291750000: 693 budget = 4000; 694 break; 695 case 267250000: 696 case 268500000: 697 budget = 5000; 698 break; 699 default: 700 budget = 1000; 701 break; 702 } 703 704 return budget; 705 } 706 707 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, 708 unsigned r2, unsigned n2, unsigned p, 709 struct wrpll_rnp *best) 710 { 711 uint64_t a, b, c, d, diff, diff_best; 712 713 /* No best (r,n,p) yet */ 714 if (best->p == 0) { 715 best->p = p; 716 best->n2 = n2; 717 best->r2 = r2; 718 return; 719 } 720 721 /* 722 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 723 * freq2k. 724 * 725 * delta = 1e6 * 726 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 727 * freq2k; 728 * 729 * and we would like delta <= budget. 730 * 731 * If the discrepancy is above the PPM-based budget, always prefer to 732 * improve upon the previous solution. However, if you're within the 733 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 734 */ 735 a = freq2k * budget * p * r2; 736 b = freq2k * budget * best->p * best->r2; 737 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); 738 diff_best = abs_diff(freq2k * best->p * best->r2, 739 LC_FREQ_2K * best->n2); 740 c = 1000000 * diff; 741 d = 1000000 * diff_best; 742 743 if (a < c && b < d) { 744 /* If both are above the budget, pick the closer */ 745 if (best->p * best->r2 * diff < p * r2 * diff_best) { 746 best->p = p; 747 best->n2 = n2; 748 best->r2 = r2; 749 } 750 } else if (a >= c && b < d) { 751 /* If A is below the threshold but B is above it? Update. */ 752 best->p = p; 753 best->n2 = n2; 754 best->r2 = r2; 755 } else if (a >= c && b >= d) { 756 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 757 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 758 best->p = p; 759 best->n2 = n2; 760 best->r2 = r2; 761 } 762 } 763 /* Otherwise a < c && b >= d, do nothing */ 764 } 765 766 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 767 int reg) 768 { 769 int refclk = LC_FREQ; 770 int n, p, r; 771 u32 wrpll; 772 773 wrpll = I915_READ(reg); 774 switch (wrpll & WRPLL_PLL_REF_MASK) { 775 case WRPLL_PLL_SSC: 776 case WRPLL_PLL_NON_SSC: 777 /* 778 * We could calculate spread here, but our checking 779 * code only cares about 5% accuracy, and spread is a max of 780 * 0.5% downspread. 781 */ 782 refclk = 135; 783 break; 784 case WRPLL_PLL_LCPLL: 785 refclk = LC_FREQ; 786 break; 787 default: 788 WARN(1, "bad wrpll refclk\n"); 789 return 0; 790 } 791 792 r = wrpll & WRPLL_DIVIDER_REF_MASK; 793 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 794 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 795 796 /* Convert to KHz, p & r have a fixed point portion */ 797 return (refclk * n * 100) / (p * r); 798 } 799 800 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 801 uint32_t dpll) 802 { 803 uint32_t cfgcr1_reg, cfgcr2_reg; 804 uint32_t cfgcr1_val, cfgcr2_val; 805 uint32_t p0, p1, p2, dco_freq; 806 807 cfgcr1_reg = GET_CFG_CR1_REG(dpll); 808 cfgcr2_reg = GET_CFG_CR2_REG(dpll); 809 810 cfgcr1_val = I915_READ(cfgcr1_reg); 811 cfgcr2_val = I915_READ(cfgcr2_reg); 812 813 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 814 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 815 816 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 817 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 818 else 819 p1 = 1; 820 821 822 switch (p0) { 823 case DPLL_CFGCR2_PDIV_1: 824 p0 = 1; 825 break; 826 case DPLL_CFGCR2_PDIV_2: 827 p0 = 2; 828 break; 829 case DPLL_CFGCR2_PDIV_3: 830 p0 = 3; 831 break; 832 case DPLL_CFGCR2_PDIV_7: 833 p0 = 7; 834 break; 835 } 836 837 switch (p2) { 838 case DPLL_CFGCR2_KDIV_5: 839 p2 = 5; 840 break; 841 case DPLL_CFGCR2_KDIV_2: 842 p2 = 2; 843 break; 844 case DPLL_CFGCR2_KDIV_3: 845 p2 = 3; 846 break; 847 case DPLL_CFGCR2_KDIV_1: 848 p2 = 1; 849 break; 850 } 851 852 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 853 854 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 855 1000) / 0x8000; 856 857 return dco_freq / (p0 * p1 * p2 * 5); 858 } 859 860 861 static void skl_ddi_clock_get(struct intel_encoder *encoder, 862 struct intel_crtc_state *pipe_config) 863 { 864 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 865 int link_clock = 0; 866 uint32_t dpll_ctl1, dpll; 867 868 dpll = pipe_config->ddi_pll_sel; 869 870 dpll_ctl1 = I915_READ(DPLL_CTRL1); 871 872 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 873 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 874 } else { 875 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); 876 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); 877 878 switch (link_clock) { 879 case DPLL_CTRL1_LINK_RATE_810: 880 link_clock = 81000; 881 break; 882 case DPLL_CTRL1_LINK_RATE_1080: 883 link_clock = 108000; 884 break; 885 case DPLL_CTRL1_LINK_RATE_1350: 886 link_clock = 135000; 887 break; 888 case DPLL_CTRL1_LINK_RATE_1620: 889 link_clock = 162000; 890 break; 891 case DPLL_CTRL1_LINK_RATE_2160: 892 link_clock = 216000; 893 break; 894 case DPLL_CTRL1_LINK_RATE_2700: 895 link_clock = 270000; 896 break; 897 default: 898 WARN(1, "Unsupported link rate\n"); 899 break; 900 } 901 link_clock *= 2; 902 } 903 904 pipe_config->port_clock = link_clock; 905 906 if (pipe_config->has_dp_encoder) 907 pipe_config->base.adjusted_mode.crtc_clock = 908 intel_dotclock_calculate(pipe_config->port_clock, 909 &pipe_config->dp_m_n); 910 else 911 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 912 } 913 914 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 915 struct intel_crtc_state *pipe_config) 916 { 917 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 918 int link_clock = 0; 919 u32 val, pll; 920 921 val = pipe_config->ddi_pll_sel; 922 switch (val & PORT_CLK_SEL_MASK) { 923 case PORT_CLK_SEL_LCPLL_810: 924 link_clock = 81000; 925 break; 926 case PORT_CLK_SEL_LCPLL_1350: 927 link_clock = 135000; 928 break; 929 case PORT_CLK_SEL_LCPLL_2700: 930 link_clock = 270000; 931 break; 932 case PORT_CLK_SEL_WRPLL1: 933 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); 934 break; 935 case PORT_CLK_SEL_WRPLL2: 936 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); 937 break; 938 case PORT_CLK_SEL_SPLL: 939 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 940 if (pll == SPLL_PLL_FREQ_810MHz) 941 link_clock = 81000; 942 else if (pll == SPLL_PLL_FREQ_1350MHz) 943 link_clock = 135000; 944 else if (pll == SPLL_PLL_FREQ_2700MHz) 945 link_clock = 270000; 946 else { 947 WARN(1, "bad spll freq\n"); 948 return; 949 } 950 break; 951 default: 952 WARN(1, "bad port clock sel\n"); 953 return; 954 } 955 956 pipe_config->port_clock = link_clock * 2; 957 958 if (pipe_config->has_pch_encoder) 959 pipe_config->base.adjusted_mode.crtc_clock = 960 intel_dotclock_calculate(pipe_config->port_clock, 961 &pipe_config->fdi_m_n); 962 else if (pipe_config->has_dp_encoder) 963 pipe_config->base.adjusted_mode.crtc_clock = 964 intel_dotclock_calculate(pipe_config->port_clock, 965 &pipe_config->dp_m_n); 966 else 967 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 968 } 969 970 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, 971 enum intel_dpll_id dpll) 972 { 973 /* FIXME formula not available in bspec */ 974 return 0; 975 } 976 977 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 978 struct intel_crtc_state *pipe_config) 979 { 980 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 981 enum port port = intel_ddi_get_encoder_port(encoder); 982 uint32_t dpll = port; 983 984 pipe_config->port_clock = 985 bxt_calc_pll_link(dev_priv, dpll); 986 987 if (pipe_config->has_dp_encoder) 988 pipe_config->base.adjusted_mode.crtc_clock = 989 intel_dotclock_calculate(pipe_config->port_clock, 990 &pipe_config->dp_m_n); 991 else 992 pipe_config->base.adjusted_mode.crtc_clock = 993 pipe_config->port_clock; 994 } 995 996 void intel_ddi_clock_get(struct intel_encoder *encoder, 997 struct intel_crtc_state *pipe_config) 998 { 999 struct drm_device *dev = encoder->base.dev; 1000 1001 if (INTEL_INFO(dev)->gen <= 8) 1002 hsw_ddi_clock_get(encoder, pipe_config); 1003 else if (IS_SKYLAKE(dev)) 1004 skl_ddi_clock_get(encoder, pipe_config); 1005 else if (IS_BROXTON(dev)) 1006 bxt_ddi_clock_get(encoder, pipe_config); 1007 } 1008 1009 static void 1010 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 1011 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 1012 { 1013 uint64_t freq2k; 1014 unsigned p, n2, r2; 1015 struct wrpll_rnp best = { 0, 0, 0 }; 1016 unsigned budget; 1017 1018 freq2k = clock / 100; 1019 1020 budget = wrpll_get_budget_for_freq(clock); 1021 1022 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 1023 * and directly pass the LC PLL to it. */ 1024 if (freq2k == 5400000) { 1025 *n2_out = 2; 1026 *p_out = 1; 1027 *r2_out = 2; 1028 return; 1029 } 1030 1031 /* 1032 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 1033 * the WR PLL. 1034 * 1035 * We want R so that REF_MIN <= Ref <= REF_MAX. 1036 * Injecting R2 = 2 * R gives: 1037 * REF_MAX * r2 > LC_FREQ * 2 and 1038 * REF_MIN * r2 < LC_FREQ * 2 1039 * 1040 * Which means the desired boundaries for r2 are: 1041 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 1042 * 1043 */ 1044 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 1045 r2 <= LC_FREQ * 2 / REF_MIN; 1046 r2++) { 1047 1048 /* 1049 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 1050 * 1051 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 1052 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 1053 * VCO_MAX * r2 > n2 * LC_FREQ and 1054 * VCO_MIN * r2 < n2 * LC_FREQ) 1055 * 1056 * Which means the desired boundaries for n2 are: 1057 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 1058 */ 1059 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 1060 n2 <= VCO_MAX * r2 / LC_FREQ; 1061 n2++) { 1062 1063 for (p = P_MIN; p <= P_MAX; p += P_INC) 1064 wrpll_update_rnp(freq2k, budget, 1065 r2, n2, p, &best); 1066 } 1067 } 1068 1069 *n2_out = best.n2; 1070 *p_out = best.p; 1071 *r2_out = best.r2; 1072 } 1073 1074 static bool 1075 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 1076 struct intel_crtc_state *crtc_state, 1077 struct intel_encoder *intel_encoder, 1078 int clock) 1079 { 1080 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1081 struct intel_shared_dpll *pll; 1082 uint32_t val; 1083 unsigned p, n2, r2; 1084 1085 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 1086 1087 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 1088 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 1089 WRPLL_DIVIDER_POST(p); 1090 1091 memset(&crtc_state->dpll_hw_state, 0, 1092 sizeof(crtc_state->dpll_hw_state)); 1093 1094 crtc_state->dpll_hw_state.wrpll = val; 1095 1096 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1097 if (pll == NULL) { 1098 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1099 pipe_name(intel_crtc->pipe)); 1100 return false; 1101 } 1102 1103 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 1104 } 1105 1106 return true; 1107 } 1108 1109 struct skl_wrpll_params { 1110 uint32_t dco_fraction; 1111 uint32_t dco_integer; 1112 uint32_t qdiv_ratio; 1113 uint32_t qdiv_mode; 1114 uint32_t kdiv; 1115 uint32_t pdiv; 1116 uint32_t central_freq; 1117 }; 1118 1119 static void 1120 skl_ddi_calculate_wrpll(int clock /* in Hz */, 1121 struct skl_wrpll_params *wrpll_params) 1122 { 1123 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 1124 uint64_t dco_central_freq[3] = {8400000000ULL, 1125 9000000000ULL, 1126 9600000000ULL}; 1127 uint32_t min_dco_deviation = 400; 1128 uint32_t min_dco_index = 3; 1129 uint32_t P0[4] = {1, 2, 3, 7}; 1130 uint32_t P2[4] = {1, 2, 3, 5}; 1131 bool found = false; 1132 uint32_t candidate_p = 0; 1133 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0}; 1134 uint32_t candidate_p2[3] = {0}; 1135 uint32_t dco_central_freq_deviation[3]; 1136 uint32_t i, P1, k, dco_count; 1137 bool retry_with_odd = false; 1138 uint64_t dco_freq; 1139 1140 /* Determine P0, P1 or P2 */ 1141 for (dco_count = 0; dco_count < 3; dco_count++) { 1142 found = false; 1143 candidate_p = 1144 div64_u64(dco_central_freq[dco_count], afe_clock); 1145 if (retry_with_odd == false) 1146 candidate_p = (candidate_p % 2 == 0 ? 1147 candidate_p : candidate_p + 1); 1148 1149 for (P1 = 1; P1 < candidate_p; P1++) { 1150 for (i = 0; i < 4; i++) { 1151 if (!(P0[i] != 1 || P1 == 1)) 1152 continue; 1153 1154 for (k = 0; k < 4; k++) { 1155 if (P1 != 1 && P2[k] != 2) 1156 continue; 1157 1158 if (candidate_p == P0[i] * P1 * P2[k]) { 1159 /* Found possible P0, P1, P2 */ 1160 found = true; 1161 candidate_p0[dco_count] = P0[i]; 1162 candidate_p1[dco_count] = P1; 1163 candidate_p2[dco_count] = P2[k]; 1164 goto found; 1165 } 1166 1167 } 1168 } 1169 } 1170 1171 found: 1172 if (found) { 1173 dco_central_freq_deviation[dco_count] = 1174 div64_u64(10000 * 1175 abs_diff((candidate_p * afe_clock), 1176 dco_central_freq[dco_count]), 1177 dco_central_freq[dco_count]); 1178 1179 if (dco_central_freq_deviation[dco_count] < 1180 min_dco_deviation) { 1181 min_dco_deviation = 1182 dco_central_freq_deviation[dco_count]; 1183 min_dco_index = dco_count; 1184 } 1185 } 1186 1187 if (min_dco_index > 2 && dco_count == 2) { 1188 retry_with_odd = true; 1189 dco_count = 0; 1190 } 1191 } 1192 1193 if (min_dco_index > 2) { 1194 WARN(1, "No valid values found for the given pixel clock\n"); 1195 } else { 1196 wrpll_params->central_freq = dco_central_freq[min_dco_index]; 1197 1198 switch (dco_central_freq[min_dco_index]) { 1199 case 9600000000ULL: 1200 wrpll_params->central_freq = 0; 1201 break; 1202 case 9000000000ULL: 1203 wrpll_params->central_freq = 1; 1204 break; 1205 case 8400000000ULL: 1206 wrpll_params->central_freq = 3; 1207 } 1208 1209 switch (candidate_p0[min_dco_index]) { 1210 case 1: 1211 wrpll_params->pdiv = 0; 1212 break; 1213 case 2: 1214 wrpll_params->pdiv = 1; 1215 break; 1216 case 3: 1217 wrpll_params->pdiv = 2; 1218 break; 1219 case 7: 1220 wrpll_params->pdiv = 4; 1221 break; 1222 default: 1223 WARN(1, "Incorrect PDiv\n"); 1224 } 1225 1226 switch (candidate_p2[min_dco_index]) { 1227 case 5: 1228 wrpll_params->kdiv = 0; 1229 break; 1230 case 2: 1231 wrpll_params->kdiv = 1; 1232 break; 1233 case 3: 1234 wrpll_params->kdiv = 2; 1235 break; 1236 case 1: 1237 wrpll_params->kdiv = 3; 1238 break; 1239 default: 1240 WARN(1, "Incorrect KDiv\n"); 1241 } 1242 1243 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index]; 1244 wrpll_params->qdiv_mode = 1245 (wrpll_params->qdiv_ratio == 1) ? 0 : 1; 1246 1247 dco_freq = candidate_p0[min_dco_index] * 1248 candidate_p1[min_dco_index] * 1249 candidate_p2[min_dco_index] * afe_clock; 1250 1251 /* 1252 * Intermediate values are in Hz. 1253 * Divide by MHz to match bsepc 1254 */ 1255 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1))); 1256 wrpll_params->dco_fraction = 1257 div_u64(((div_u64(dco_freq, 24) - 1258 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1)); 1259 1260 } 1261 } 1262 1263 1264 static bool 1265 skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1266 struct intel_crtc_state *crtc_state, 1267 struct intel_encoder *intel_encoder, 1268 int clock) 1269 { 1270 struct intel_shared_dpll *pll; 1271 uint32_t ctrl1, cfgcr1, cfgcr2; 1272 1273 /* 1274 * See comment in intel_dpll_hw_state to understand why we always use 0 1275 * as the DPLL id in this function. 1276 */ 1277 1278 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1279 1280 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1281 struct skl_wrpll_params wrpll_params = { 0, }; 1282 1283 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1284 1285 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params); 1286 1287 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1288 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1289 wrpll_params.dco_integer; 1290 1291 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1292 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1293 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1294 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1295 wrpll_params.central_freq; 1296 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 1297 struct drm_encoder *encoder = &intel_encoder->base; 1298 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1299 1300 switch (intel_dp->link_bw) { 1301 case DP_LINK_BW_1_62: 1302 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); 1303 break; 1304 case DP_LINK_BW_2_7: 1305 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); 1306 break; 1307 case DP_LINK_BW_5_4: 1308 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); 1309 break; 1310 } 1311 1312 cfgcr1 = cfgcr2 = 0; 1313 } else /* eDP */ 1314 return true; 1315 1316 memset(&crtc_state->dpll_hw_state, 0, 1317 sizeof(crtc_state->dpll_hw_state)); 1318 1319 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1320 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1321 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1322 1323 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1324 if (pll == NULL) { 1325 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1326 pipe_name(intel_crtc->pipe)); 1327 return false; 1328 } 1329 1330 /* shared DPLL id 0 is DPLL 1 */ 1331 crtc_state->ddi_pll_sel = pll->id + 1; 1332 1333 return true; 1334 } 1335 1336 /* bxt clock parameters */ 1337 struct bxt_clk_div { 1338 uint32_t p1; 1339 uint32_t p2; 1340 uint32_t m2_int; 1341 uint32_t m2_frac; 1342 bool m2_frac_en; 1343 uint32_t n; 1344 }; 1345 1346 /* pre-calculated values for DP linkrates */ 1347 static struct bxt_clk_div bxt_dp_clk_val[7] = { 1348 /* 162 */ {4, 2, 32, 1677722, 1, 1}, 1349 /* 270 */ {4, 1, 27, 0, 0, 1}, 1350 /* 540 */ {2, 1, 27, 0, 0, 1}, 1351 /* 216 */ {3, 2, 32, 1677722, 1, 1}, 1352 /* 243 */ {4, 1, 24, 1258291, 1, 1}, 1353 /* 324 */ {4, 1, 32, 1677722, 1, 1}, 1354 /* 432 */ {3, 1, 32, 1677722, 1, 1} 1355 }; 1356 1357 static bool 1358 bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 1359 struct intel_crtc_state *crtc_state, 1360 struct intel_encoder *intel_encoder, 1361 int clock) 1362 { 1363 struct intel_shared_dpll *pll; 1364 struct bxt_clk_div clk_div = {0}; 1365 int vco = 0; 1366 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; 1367 uint32_t dcoampovr_en_h, dco_amp, lanestagger; 1368 1369 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1370 intel_clock_t best_clock; 1371 1372 /* Calculate HDMI div */ 1373 /* 1374 * FIXME: tie the following calculation into 1375 * i9xx_crtc_compute_clock 1376 */ 1377 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { 1378 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", 1379 clock, pipe_name(intel_crtc->pipe)); 1380 return false; 1381 } 1382 1383 clk_div.p1 = best_clock.p1; 1384 clk_div.p2 = best_clock.p2; 1385 WARN_ON(best_clock.m1 != 2); 1386 clk_div.n = best_clock.n; 1387 clk_div.m2_int = best_clock.m2 >> 22; 1388 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); 1389 clk_div.m2_frac_en = clk_div.m2_frac != 0; 1390 1391 vco = best_clock.vco; 1392 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1393 intel_encoder->type == INTEL_OUTPUT_EDP) { 1394 struct drm_encoder *encoder = &intel_encoder->base; 1395 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1396 1397 switch (intel_dp->link_bw) { 1398 case DP_LINK_BW_1_62: 1399 clk_div = bxt_dp_clk_val[0]; 1400 break; 1401 case DP_LINK_BW_2_7: 1402 clk_div = bxt_dp_clk_val[1]; 1403 break; 1404 case DP_LINK_BW_5_4: 1405 clk_div = bxt_dp_clk_val[2]; 1406 break; 1407 default: 1408 clk_div = bxt_dp_clk_val[0]; 1409 DRM_ERROR("Unknown link rate\n"); 1410 } 1411 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; 1412 } 1413 1414 dco_amp = 15; 1415 dcoampovr_en_h = 0; 1416 if (vco >= 6200000 && vco <= 6480000) { 1417 prop_coef = 4; 1418 int_coef = 9; 1419 gain_ctl = 3; 1420 targ_cnt = 8; 1421 } else if ((vco > 5400000 && vco < 6200000) || 1422 (vco >= 4800000 && vco < 5400000)) { 1423 prop_coef = 5; 1424 int_coef = 11; 1425 gain_ctl = 3; 1426 targ_cnt = 9; 1427 if (vco >= 4800000 && vco < 5400000) 1428 dcoampovr_en_h = 1; 1429 } else if (vco == 5400000) { 1430 prop_coef = 3; 1431 int_coef = 8; 1432 gain_ctl = 1; 1433 targ_cnt = 9; 1434 } else { 1435 DRM_ERROR("Invalid VCO\n"); 1436 return false; 1437 } 1438 1439 memset(&crtc_state->dpll_hw_state, 0, 1440 sizeof(crtc_state->dpll_hw_state)); 1441 1442 if (clock > 270000) 1443 lanestagger = 0x18; 1444 else if (clock > 135000) 1445 lanestagger = 0x0d; 1446 else if (clock > 67000) 1447 lanestagger = 0x07; 1448 else if (clock > 33000) 1449 lanestagger = 0x04; 1450 else 1451 lanestagger = 0x02; 1452 1453 crtc_state->dpll_hw_state.ebb0 = 1454 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); 1455 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; 1456 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); 1457 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; 1458 1459 if (clk_div.m2_frac_en) 1460 crtc_state->dpll_hw_state.pll3 = 1461 PORT_PLL_M2_FRAC_ENABLE; 1462 1463 crtc_state->dpll_hw_state.pll6 = 1464 prop_coef | PORT_PLL_INT_COEFF(int_coef); 1465 crtc_state->dpll_hw_state.pll6 |= 1466 PORT_PLL_GAIN_CTL(gain_ctl); 1467 1468 crtc_state->dpll_hw_state.pll8 = targ_cnt; 1469 1470 if (dcoampovr_en_h) 1471 crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; 1472 1473 crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); 1474 1475 crtc_state->dpll_hw_state.pcsdw12 = 1476 LANESTAGGER_STRAP_OVRD | lanestagger; 1477 1478 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1479 if (pll == NULL) { 1480 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1481 pipe_name(intel_crtc->pipe)); 1482 return false; 1483 } 1484 1485 /* shared DPLL id 0 is DPLL A */ 1486 crtc_state->ddi_pll_sel = pll->id; 1487 1488 return true; 1489 } 1490 1491 /* 1492 * Tries to find a *shared* PLL for the CRTC and store it in 1493 * intel_crtc->ddi_pll_sel. 1494 * 1495 * For private DPLLs, compute_config() should do the selection for us. This 1496 * function should be folded into compute_config() eventually. 1497 */ 1498 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, 1499 struct intel_crtc_state *crtc_state) 1500 { 1501 struct drm_device *dev = intel_crtc->base.dev; 1502 struct intel_encoder *intel_encoder = 1503 intel_ddi_get_crtc_new_encoder(crtc_state); 1504 int clock = crtc_state->port_clock; 1505 1506 if (IS_SKYLAKE(dev)) 1507 return skl_ddi_pll_select(intel_crtc, crtc_state, 1508 intel_encoder, clock); 1509 else if (IS_BROXTON(dev)) 1510 return bxt_ddi_pll_select(intel_crtc, crtc_state, 1511 intel_encoder, clock); 1512 else 1513 return hsw_ddi_pll_select(intel_crtc, crtc_state, 1514 intel_encoder, clock); 1515 } 1516 1517 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1518 { 1519 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1521 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1522 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1523 int type = intel_encoder->type; 1524 uint32_t temp; 1525 1526 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1527 temp = TRANS_MSA_SYNC_CLK; 1528 switch (intel_crtc->config->pipe_bpp) { 1529 case 18: 1530 temp |= TRANS_MSA_6_BPC; 1531 break; 1532 case 24: 1533 temp |= TRANS_MSA_8_BPC; 1534 break; 1535 case 30: 1536 temp |= TRANS_MSA_10_BPC; 1537 break; 1538 case 36: 1539 temp |= TRANS_MSA_12_BPC; 1540 break; 1541 default: 1542 BUG(); 1543 } 1544 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1545 } 1546 } 1547 1548 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) 1549 { 1550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1551 struct drm_device *dev = crtc->dev; 1552 struct drm_i915_private *dev_priv = dev->dev_private; 1553 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1554 uint32_t temp; 1555 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1556 if (state == true) 1557 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1558 else 1559 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1560 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1561 } 1562 1563 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 1564 { 1565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1566 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1567 struct drm_encoder *encoder = &intel_encoder->base; 1568 struct drm_device *dev = crtc->dev; 1569 struct drm_i915_private *dev_priv = dev->dev_private; 1570 enum i915_pipe pipe = intel_crtc->pipe; 1571 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1572 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1573 int type = intel_encoder->type; 1574 uint32_t temp; 1575 1576 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1577 temp = TRANS_DDI_FUNC_ENABLE; 1578 temp |= TRANS_DDI_SELECT_PORT(port); 1579 1580 switch (intel_crtc->config->pipe_bpp) { 1581 case 18: 1582 temp |= TRANS_DDI_BPC_6; 1583 break; 1584 case 24: 1585 temp |= TRANS_DDI_BPC_8; 1586 break; 1587 case 30: 1588 temp |= TRANS_DDI_BPC_10; 1589 break; 1590 case 36: 1591 temp |= TRANS_DDI_BPC_12; 1592 break; 1593 default: 1594 BUG(); 1595 } 1596 1597 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1598 temp |= TRANS_DDI_PVSYNC; 1599 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1600 temp |= TRANS_DDI_PHSYNC; 1601 1602 if (cpu_transcoder == TRANSCODER_EDP) { 1603 switch (pipe) { 1604 case PIPE_A: 1605 /* On Haswell, can only use the always-on power well for 1606 * eDP when not using the panel fitter, and when not 1607 * using motion blur mitigation (which we don't 1608 * support). */ 1609 if (IS_HASWELL(dev) && 1610 (intel_crtc->config->pch_pfit.enabled || 1611 intel_crtc->config->pch_pfit.force_thru)) 1612 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1613 else 1614 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1615 break; 1616 case PIPE_B: 1617 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1618 break; 1619 case PIPE_C: 1620 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1621 break; 1622 default: 1623 BUG(); 1624 break; 1625 } 1626 } 1627 1628 if (type == INTEL_OUTPUT_HDMI) { 1629 if (intel_crtc->config->has_hdmi_sink) 1630 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1631 else 1632 temp |= TRANS_DDI_MODE_SELECT_DVI; 1633 1634 } else if (type == INTEL_OUTPUT_ANALOG) { 1635 temp |= TRANS_DDI_MODE_SELECT_FDI; 1636 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; 1637 1638 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1639 type == INTEL_OUTPUT_EDP) { 1640 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1641 1642 if (intel_dp->is_mst) { 1643 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1644 } else 1645 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1646 1647 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); 1648 } else if (type == INTEL_OUTPUT_DP_MST) { 1649 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; 1650 1651 if (intel_dp->is_mst) { 1652 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1653 } else 1654 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1655 1656 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); 1657 } else { 1658 WARN(1, "Invalid encoder type %d for pipe %c\n", 1659 intel_encoder->type, pipe_name(pipe)); 1660 } 1661 1662 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1663 } 1664 1665 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1666 enum transcoder cpu_transcoder) 1667 { 1668 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1669 uint32_t val = I915_READ(reg); 1670 1671 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1672 val |= TRANS_DDI_PORT_NONE; 1673 I915_WRITE(reg, val); 1674 } 1675 1676 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1677 { 1678 struct drm_device *dev = intel_connector->base.dev; 1679 struct drm_i915_private *dev_priv = dev->dev_private; 1680 struct intel_encoder *intel_encoder = intel_connector->encoder; 1681 int type = intel_connector->base.connector_type; 1682 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1683 enum i915_pipe pipe = 0; 1684 enum transcoder cpu_transcoder; 1685 enum intel_display_power_domain power_domain; 1686 uint32_t tmp; 1687 1688 power_domain = intel_display_port_power_domain(intel_encoder); 1689 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1690 return false; 1691 1692 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) 1693 return false; 1694 1695 if (port == PORT_A) 1696 cpu_transcoder = TRANSCODER_EDP; 1697 else 1698 cpu_transcoder = (enum transcoder) pipe; 1699 1700 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1701 1702 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1703 case TRANS_DDI_MODE_SELECT_HDMI: 1704 case TRANS_DDI_MODE_SELECT_DVI: 1705 return (type == DRM_MODE_CONNECTOR_HDMIA); 1706 1707 case TRANS_DDI_MODE_SELECT_DP_SST: 1708 if (type == DRM_MODE_CONNECTOR_eDP) 1709 return true; 1710 return (type == DRM_MODE_CONNECTOR_DisplayPort); 1711 case TRANS_DDI_MODE_SELECT_DP_MST: 1712 /* if the transcoder is in MST state then 1713 * connector isn't connected */ 1714 return false; 1715 1716 case TRANS_DDI_MODE_SELECT_FDI: 1717 return (type == DRM_MODE_CONNECTOR_VGA); 1718 1719 default: 1720 return false; 1721 } 1722 } 1723 1724 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1725 enum i915_pipe *pipe) 1726 { 1727 struct drm_device *dev = encoder->base.dev; 1728 struct drm_i915_private *dev_priv = dev->dev_private; 1729 enum port port = intel_ddi_get_encoder_port(encoder); 1730 enum intel_display_power_domain power_domain; 1731 u32 tmp; 1732 int i; 1733 1734 power_domain = intel_display_port_power_domain(encoder); 1735 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1736 return false; 1737 1738 tmp = I915_READ(DDI_BUF_CTL(port)); 1739 1740 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1741 return false; 1742 1743 if (port == PORT_A) { 1744 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1745 1746 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1747 case TRANS_DDI_EDP_INPUT_A_ON: 1748 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1749 *pipe = PIPE_A; 1750 break; 1751 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1752 *pipe = PIPE_B; 1753 break; 1754 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1755 *pipe = PIPE_C; 1756 break; 1757 } 1758 1759 return true; 1760 } else { 1761 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 1762 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 1763 1764 if ((tmp & TRANS_DDI_PORT_MASK) 1765 == TRANS_DDI_SELECT_PORT(port)) { 1766 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) 1767 return false; 1768 1769 *pipe = i; 1770 return true; 1771 } 1772 } 1773 } 1774 1775 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 1776 1777 return false; 1778 } 1779 1780 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 1781 { 1782 struct drm_crtc *crtc = &intel_crtc->base; 1783 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1784 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1785 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1786 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1787 1788 if (cpu_transcoder != TRANSCODER_EDP) 1789 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1790 TRANS_CLK_SEL_PORT(port)); 1791 } 1792 1793 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 1794 { 1795 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1796 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1797 1798 if (cpu_transcoder != TRANSCODER_EDP) 1799 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1800 TRANS_CLK_SEL_DISABLED); 1801 } 1802 1803 void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, 1804 enum port port, int type) 1805 { 1806 struct drm_i915_private *dev_priv = dev->dev_private; 1807 const struct bxt_ddi_buf_trans *ddi_translations; 1808 u32 n_entries, i; 1809 uint32_t val; 1810 1811 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1812 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 1813 ddi_translations = bxt_ddi_translations_dp; 1814 } else if (type == INTEL_OUTPUT_HDMI) { 1815 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 1816 ddi_translations = bxt_ddi_translations_hdmi; 1817 } else { 1818 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", 1819 type); 1820 return; 1821 } 1822 1823 /* Check if default value has to be used */ 1824 if (level >= n_entries || 1825 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { 1826 for (i = 0; i < n_entries; i++) { 1827 if (ddi_translations[i].default_index) { 1828 level = i; 1829 break; 1830 } 1831 } 1832 } 1833 1834 /* 1835 * While we write to the group register to program all lanes at once we 1836 * can read only lane registers and we pick lanes 0/1 for that. 1837 */ 1838 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 1839 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 1840 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 1841 1842 val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); 1843 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 1844 val |= ddi_translations[level].margin << MARGIN_000_SHIFT | 1845 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; 1846 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); 1847 1848 val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); 1849 val &= ~UNIQE_TRANGE_EN_METHOD; 1850 if (ddi_translations[level].enable) 1851 val |= UNIQE_TRANGE_EN_METHOD; 1852 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); 1853 1854 val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); 1855 val &= ~DE_EMPHASIS; 1856 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; 1857 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); 1858 1859 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 1860 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 1861 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 1862 } 1863 1864 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 1865 { 1866 struct drm_encoder *encoder = &intel_encoder->base; 1867 struct drm_device *dev = encoder->dev; 1868 struct drm_i915_private *dev_priv = dev->dev_private; 1869 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 1870 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1871 int type = intel_encoder->type; 1872 int hdmi_level; 1873 1874 if (type == INTEL_OUTPUT_EDP) { 1875 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1876 intel_edp_panel_on(intel_dp); 1877 } 1878 1879 if (IS_SKYLAKE(dev)) { 1880 uint32_t dpll = crtc->config->ddi_pll_sel; 1881 uint32_t val; 1882 1883 /* 1884 * DPLL0 is used for eDP and is the only "private" DPLL (as 1885 * opposed to shared) on SKL 1886 */ 1887 if (type == INTEL_OUTPUT_EDP) { 1888 WARN_ON(dpll != SKL_DPLL0); 1889 1890 val = I915_READ(DPLL_CTRL1); 1891 1892 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | 1893 DPLL_CTRL1_SSC(dpll) | 1894 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 1895 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); 1896 1897 I915_WRITE(DPLL_CTRL1, val); 1898 POSTING_READ(DPLL_CTRL1); 1899 } 1900 1901 /* DDI -> PLL mapping */ 1902 val = I915_READ(DPLL_CTRL2); 1903 1904 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 1905 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 1906 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | 1907 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1908 1909 I915_WRITE(DPLL_CTRL2, val); 1910 1911 } else if (INTEL_INFO(dev)->gen < 9) { 1912 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); 1913 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); 1914 } 1915 1916 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1918 1919 intel_ddi_init_dp_buf_reg(intel_encoder); 1920 1921 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1922 intel_dp_start_link_train(intel_dp); 1923 intel_dp_complete_link_train(intel_dp); 1924 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) 1925 intel_dp_stop_link_train(intel_dp); 1926 } else if (type == INTEL_OUTPUT_HDMI) { 1927 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1928 1929 if (IS_BROXTON(dev)) { 1930 hdmi_level = dev_priv->vbt. 1931 ddi_port_info[port].hdmi_level_shift; 1932 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 1933 INTEL_OUTPUT_HDMI); 1934 } 1935 intel_hdmi->set_infoframes(encoder, 1936 crtc->config->has_hdmi_sink, 1937 &crtc->config->base.adjusted_mode); 1938 } 1939 } 1940 1941 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 1942 { 1943 struct drm_encoder *encoder = &intel_encoder->base; 1944 struct drm_device *dev = encoder->dev; 1945 struct drm_i915_private *dev_priv = dev->dev_private; 1946 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1947 int type = intel_encoder->type; 1948 uint32_t val; 1949 bool wait = false; 1950 1951 val = I915_READ(DDI_BUF_CTL(port)); 1952 if (val & DDI_BUF_CTL_ENABLE) { 1953 val &= ~DDI_BUF_CTL_ENABLE; 1954 I915_WRITE(DDI_BUF_CTL(port), val); 1955 wait = true; 1956 } 1957 1958 val = I915_READ(DP_TP_CTL(port)); 1959 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1960 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1961 I915_WRITE(DP_TP_CTL(port), val); 1962 1963 if (wait) 1964 intel_wait_ddi_buf_idle(dev_priv, port); 1965 1966 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1967 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1968 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1969 intel_edp_panel_vdd_on(intel_dp); 1970 intel_edp_panel_off(intel_dp); 1971 } 1972 1973 if (IS_SKYLAKE(dev)) 1974 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 1975 DPLL_CTRL2_DDI_CLK_OFF(port))); 1976 else if (INTEL_INFO(dev)->gen < 9) 1977 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1978 } 1979 1980 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 1981 { 1982 struct drm_encoder *encoder = &intel_encoder->base; 1983 struct drm_crtc *crtc = encoder->crtc; 1984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1985 struct drm_device *dev = encoder->dev; 1986 struct drm_i915_private *dev_priv = dev->dev_private; 1987 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1988 int type = intel_encoder->type; 1989 1990 if (type == INTEL_OUTPUT_HDMI) { 1991 struct intel_digital_port *intel_dig_port = 1992 enc_to_dig_port(encoder); 1993 1994 /* In HDMI/DVI mode, the port width, and swing/emphasis values 1995 * are ignored so nothing special needs to be done besides 1996 * enabling the port. 1997 */ 1998 I915_WRITE(DDI_BUF_CTL(port), 1999 intel_dig_port->saved_port_bits | 2000 DDI_BUF_CTL_ENABLE); 2001 } else if (type == INTEL_OUTPUT_EDP) { 2002 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2003 2004 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) 2005 intel_dp_stop_link_train(intel_dp); 2006 2007 intel_edp_backlight_on(intel_dp); 2008 intel_psr_enable(intel_dp); 2009 intel_edp_drrs_enable(intel_dp); 2010 } 2011 2012 if (intel_crtc->config->has_audio) { 2013 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 2014 intel_audio_codec_enable(intel_encoder); 2015 } 2016 } 2017 2018 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 2019 { 2020 struct drm_encoder *encoder = &intel_encoder->base; 2021 struct drm_crtc *crtc = encoder->crtc; 2022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2023 int type = intel_encoder->type; 2024 struct drm_device *dev = encoder->dev; 2025 struct drm_i915_private *dev_priv = dev->dev_private; 2026 2027 if (intel_crtc->config->has_audio) { 2028 intel_audio_codec_disable(intel_encoder); 2029 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 2030 } 2031 2032 if (type == INTEL_OUTPUT_EDP) { 2033 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2034 2035 intel_edp_drrs_disable(intel_dp); 2036 intel_psr_disable(intel_dp); 2037 intel_edp_backlight_off(intel_dp); 2038 } 2039 } 2040 2041 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, 2042 struct intel_shared_dpll *pll) 2043 { 2044 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 2045 POSTING_READ(WRPLL_CTL(pll->id)); 2046 udelay(20); 2047 } 2048 2049 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, 2050 struct intel_shared_dpll *pll) 2051 { 2052 uint32_t val; 2053 2054 val = I915_READ(WRPLL_CTL(pll->id)); 2055 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 2056 POSTING_READ(WRPLL_CTL(pll->id)); 2057 } 2058 2059 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2060 struct intel_shared_dpll *pll, 2061 struct intel_dpll_hw_state *hw_state) 2062 { 2063 uint32_t val; 2064 2065 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2066 return false; 2067 2068 val = I915_READ(WRPLL_CTL(pll->id)); 2069 hw_state->wrpll = val; 2070 2071 return val & WRPLL_PLL_ENABLE; 2072 } 2073 2074 static const char * const hsw_ddi_pll_names[] = { 2075 "WRPLL 1", 2076 "WRPLL 2", 2077 }; 2078 2079 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) 2080 { 2081 int i; 2082 2083 dev_priv->num_shared_dpll = 2; 2084 2085 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2086 dev_priv->shared_dplls[i].id = i; 2087 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2088 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; 2089 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; 2090 dev_priv->shared_dplls[i].get_hw_state = 2091 hsw_ddi_pll_get_hw_state; 2092 } 2093 } 2094 2095 static const char * const skl_ddi_pll_names[] = { 2096 "DPLL 1", 2097 "DPLL 2", 2098 "DPLL 3", 2099 }; 2100 2101 struct skl_dpll_regs { 2102 u32 ctl, cfgcr1, cfgcr2; 2103 }; 2104 2105 /* this array is indexed by the *shared* pll id */ 2106 static const struct skl_dpll_regs skl_dpll_regs[3] = { 2107 { 2108 /* DPLL 1 */ 2109 .ctl = LCPLL2_CTL, 2110 .cfgcr1 = DPLL1_CFGCR1, 2111 .cfgcr2 = DPLL1_CFGCR2, 2112 }, 2113 { 2114 /* DPLL 2 */ 2115 .ctl = WRPLL_CTL1, 2116 .cfgcr1 = DPLL2_CFGCR1, 2117 .cfgcr2 = DPLL2_CFGCR2, 2118 }, 2119 { 2120 /* DPLL 3 */ 2121 .ctl = WRPLL_CTL2, 2122 .cfgcr1 = DPLL3_CFGCR1, 2123 .cfgcr2 = DPLL3_CFGCR2, 2124 }, 2125 }; 2126 2127 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 2128 struct intel_shared_dpll *pll) 2129 { 2130 uint32_t val; 2131 unsigned int dpll; 2132 const struct skl_dpll_regs *regs = skl_dpll_regs; 2133 2134 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2135 dpll = pll->id + 1; 2136 2137 val = I915_READ(DPLL_CTRL1); 2138 2139 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | 2140 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2141 val |= pll->config.hw_state.ctrl1 << (dpll * 6); 2142 2143 I915_WRITE(DPLL_CTRL1, val); 2144 POSTING_READ(DPLL_CTRL1); 2145 2146 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 2147 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 2148 POSTING_READ(regs[pll->id].cfgcr1); 2149 POSTING_READ(regs[pll->id].cfgcr2); 2150 2151 /* the enable bit is always bit 31 */ 2152 I915_WRITE(regs[pll->id].ctl, 2153 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 2154 2155 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) 2156 DRM_ERROR("DPLL %d not locked\n", dpll); 2157 } 2158 2159 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 2160 struct intel_shared_dpll *pll) 2161 { 2162 const struct skl_dpll_regs *regs = skl_dpll_regs; 2163 2164 /* the enable bit is always bit 31 */ 2165 I915_WRITE(regs[pll->id].ctl, 2166 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 2167 POSTING_READ(regs[pll->id].ctl); 2168 } 2169 2170 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2171 struct intel_shared_dpll *pll, 2172 struct intel_dpll_hw_state *hw_state) 2173 { 2174 uint32_t val; 2175 unsigned int dpll; 2176 const struct skl_dpll_regs *regs = skl_dpll_regs; 2177 2178 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2179 return false; 2180 2181 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2182 dpll = pll->id + 1; 2183 2184 val = I915_READ(regs[pll->id].ctl); 2185 if (!(val & LCPLL_PLL_ENABLE)) 2186 return false; 2187 2188 val = I915_READ(DPLL_CTRL1); 2189 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; 2190 2191 /* avoid reading back stale values if HDMI mode is not enabled */ 2192 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { 2193 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 2194 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 2195 } 2196 2197 return true; 2198 } 2199 2200 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) 2201 { 2202 int i; 2203 2204 dev_priv->num_shared_dpll = 3; 2205 2206 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2207 dev_priv->shared_dplls[i].id = i; 2208 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; 2209 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; 2210 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; 2211 dev_priv->shared_dplls[i].get_hw_state = 2212 skl_ddi_pll_get_hw_state; 2213 } 2214 } 2215 2216 static void broxton_phy_init(struct drm_i915_private *dev_priv, 2217 enum dpio_phy phy) 2218 { 2219 enum port port; 2220 uint32_t val; 2221 2222 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 2223 val |= GT_DISPLAY_POWER_ON(phy); 2224 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 2225 2226 /* Considering 10ms timeout until BSpec is updated */ 2227 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) 2228 DRM_ERROR("timeout during PHY%d power on\n", phy); 2229 2230 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); 2231 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { 2232 int lane; 2233 2234 for (lane = 0; lane < 4; lane++) { 2235 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); 2236 /* 2237 * Note that on CHV this flag is called UPAR, but has 2238 * the same function. 2239 */ 2240 val &= ~LATENCY_OPTIM; 2241 if (lane != 1) 2242 val |= LATENCY_OPTIM; 2243 2244 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); 2245 } 2246 } 2247 2248 /* Program PLL Rcomp code offset */ 2249 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); 2250 val &= ~IREF0RC_OFFSET_MASK; 2251 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 2252 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); 2253 2254 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); 2255 val &= ~IREF1RC_OFFSET_MASK; 2256 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 2257 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); 2258 2259 /* Program power gating */ 2260 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); 2261 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 2262 SUS_CLK_CONFIG; 2263 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); 2264 2265 if (phy == DPIO_PHY0) { 2266 val = I915_READ(BXT_PORT_CL2CM_DW6_BC); 2267 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 2268 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); 2269 } 2270 2271 val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); 2272 val &= ~OCL2_LDOFUSE_PWR_DIS; 2273 /* 2274 * On PHY1 disable power on the second channel, since no port is 2275 * connected there. On PHY0 both channels have a port, so leave it 2276 * enabled. 2277 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should 2278 * power down the second channel on PHY0 as well. 2279 */ 2280 if (phy == DPIO_PHY1) 2281 val |= OCL2_LDOFUSE_PWR_DIS; 2282 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); 2283 2284 if (phy == DPIO_PHY0) { 2285 uint32_t grc_code; 2286 /* 2287 * PHY0 isn't connected to an RCOMP resistor so copy over 2288 * the corresponding calibrated value from PHY1, and disable 2289 * the automatic calibration on PHY0. 2290 */ 2291 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, 2292 10)) 2293 DRM_ERROR("timeout waiting for PHY1 GRC\n"); 2294 2295 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); 2296 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 2297 grc_code = val << GRC_CODE_FAST_SHIFT | 2298 val << GRC_CODE_SLOW_SHIFT | 2299 val; 2300 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); 2301 2302 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); 2303 val |= GRC_DIS | GRC_RDY_OVRD; 2304 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); 2305 } 2306 2307 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2308 val |= COMMON_RESET_DIS; 2309 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2310 } 2311 2312 void broxton_ddi_phy_init(struct drm_device *dev) 2313 { 2314 /* Enable PHY1 first since it provides Rcomp for PHY0 */ 2315 broxton_phy_init(dev->dev_private, DPIO_PHY1); 2316 broxton_phy_init(dev->dev_private, DPIO_PHY0); 2317 } 2318 2319 static void broxton_phy_uninit(struct drm_i915_private *dev_priv, 2320 enum dpio_phy phy) 2321 { 2322 uint32_t val; 2323 2324 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2325 val &= ~COMMON_RESET_DIS; 2326 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2327 } 2328 2329 void broxton_ddi_phy_uninit(struct drm_device *dev) 2330 { 2331 struct drm_i915_private *dev_priv = dev->dev_private; 2332 2333 broxton_phy_uninit(dev_priv, DPIO_PHY1); 2334 broxton_phy_uninit(dev_priv, DPIO_PHY0); 2335 2336 /* FIXME: do this in broxton_phy_uninit per phy */ 2337 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); 2338 } 2339 2340 static const char * const bxt_ddi_pll_names[] = { 2341 "PORT PLL A", 2342 "PORT PLL B", 2343 "PORT PLL C", 2344 }; 2345 2346 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 2347 struct intel_shared_dpll *pll) 2348 { 2349 uint32_t temp; 2350 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2351 2352 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2353 temp &= ~PORT_PLL_REF_SEL; 2354 /* Non-SSC reference */ 2355 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2356 2357 /* Disable 10 bit clock */ 2358 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2359 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2360 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2361 2362 /* Write P1 & P2 */ 2363 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2364 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); 2365 temp |= pll->config.hw_state.ebb0; 2366 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); 2367 2368 /* Write M2 integer */ 2369 temp = I915_READ(BXT_PORT_PLL(port, 0)); 2370 temp &= ~PORT_PLL_M2_MASK; 2371 temp |= pll->config.hw_state.pll0; 2372 I915_WRITE(BXT_PORT_PLL(port, 0), temp); 2373 2374 /* Write N */ 2375 temp = I915_READ(BXT_PORT_PLL(port, 1)); 2376 temp &= ~PORT_PLL_N_MASK; 2377 temp |= pll->config.hw_state.pll1; 2378 I915_WRITE(BXT_PORT_PLL(port, 1), temp); 2379 2380 /* Write M2 fraction */ 2381 temp = I915_READ(BXT_PORT_PLL(port, 2)); 2382 temp &= ~PORT_PLL_M2_FRAC_MASK; 2383 temp |= pll->config.hw_state.pll2; 2384 I915_WRITE(BXT_PORT_PLL(port, 2), temp); 2385 2386 /* Write M2 fraction enable */ 2387 temp = I915_READ(BXT_PORT_PLL(port, 3)); 2388 temp &= ~PORT_PLL_M2_FRAC_ENABLE; 2389 temp |= pll->config.hw_state.pll3; 2390 I915_WRITE(BXT_PORT_PLL(port, 3), temp); 2391 2392 /* Write coeff */ 2393 temp = I915_READ(BXT_PORT_PLL(port, 6)); 2394 temp &= ~PORT_PLL_PROP_COEFF_MASK; 2395 temp &= ~PORT_PLL_INT_COEFF_MASK; 2396 temp &= ~PORT_PLL_GAIN_CTL_MASK; 2397 temp |= pll->config.hw_state.pll6; 2398 I915_WRITE(BXT_PORT_PLL(port, 6), temp); 2399 2400 /* Write calibration val */ 2401 temp = I915_READ(BXT_PORT_PLL(port, 8)); 2402 temp &= ~PORT_PLL_TARGET_CNT_MASK; 2403 temp |= pll->config.hw_state.pll8; 2404 I915_WRITE(BXT_PORT_PLL(port, 8), temp); 2405 2406 temp = I915_READ(BXT_PORT_PLL(port, 9)); 2407 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; 2408 temp |= (5 << 1); 2409 I915_WRITE(BXT_PORT_PLL(port, 9), temp); 2410 2411 temp = I915_READ(BXT_PORT_PLL(port, 10)); 2412 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; 2413 temp &= ~PORT_PLL_DCO_AMP_MASK; 2414 temp |= pll->config.hw_state.pll10; 2415 I915_WRITE(BXT_PORT_PLL(port, 10), temp); 2416 2417 /* Recalibrate with new settings */ 2418 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2419 temp |= PORT_PLL_RECALIBRATE; 2420 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2421 /* Enable 10 bit clock */ 2422 temp |= PORT_PLL_10BIT_CLK_ENABLE; 2423 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2424 2425 /* Enable PLL */ 2426 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2427 temp |= PORT_PLL_ENABLE; 2428 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2429 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2430 2431 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & 2432 PORT_PLL_LOCK), 200)) 2433 DRM_ERROR("PLL %d not locked\n", port); 2434 2435 /* 2436 * While we write to the group register to program all lanes at once we 2437 * can read only lane registers and we pick lanes 0/1 for that. 2438 */ 2439 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2440 temp &= ~LANE_STAGGER_MASK; 2441 temp &= ~LANESTAGGER_STRAP_OVRD; 2442 temp |= pll->config.hw_state.pcsdw12; 2443 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); 2444 } 2445 2446 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, 2447 struct intel_shared_dpll *pll) 2448 { 2449 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2450 uint32_t temp; 2451 2452 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2453 temp &= ~PORT_PLL_ENABLE; 2454 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2455 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2456 } 2457 2458 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2459 struct intel_shared_dpll *pll, 2460 struct intel_dpll_hw_state *hw_state) 2461 { 2462 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2463 uint32_t val; 2464 2465 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2466 return false; 2467 2468 val = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2469 if (!(val & PORT_PLL_ENABLE)) 2470 return false; 2471 2472 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2473 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); 2474 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); 2475 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); 2476 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); 2477 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); 2478 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); 2479 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); 2480 /* 2481 * While we write to the group register to program all lanes at once we 2482 * can read only lane registers. We configure all lanes the same way, so 2483 * here just read out lanes 0/1 and output a note if lanes 2/3 differ. 2484 */ 2485 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2486 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12)) 2487 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", 2488 hw_state->pcsdw12, 2489 I915_READ(BXT_PORT_PCS_DW12_LN23(port))); 2490 2491 return true; 2492 } 2493 2494 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) 2495 { 2496 int i; 2497 2498 dev_priv->num_shared_dpll = 3; 2499 2500 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2501 dev_priv->shared_dplls[i].id = i; 2502 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; 2503 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; 2504 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; 2505 dev_priv->shared_dplls[i].get_hw_state = 2506 bxt_ddi_pll_get_hw_state; 2507 } 2508 } 2509 2510 void intel_ddi_pll_init(struct drm_device *dev) 2511 { 2512 struct drm_i915_private *dev_priv = dev->dev_private; 2513 uint32_t val = I915_READ(LCPLL_CTL); 2514 int cdclk_freq; 2515 2516 if (IS_SKYLAKE(dev)) 2517 skl_shared_dplls_init(dev_priv); 2518 else if (IS_BROXTON(dev)) 2519 bxt_shared_dplls_init(dev_priv); 2520 else 2521 hsw_shared_dplls_init(dev_priv); 2522 2523 cdclk_freq = dev_priv->display.get_display_clock_speed(dev); 2524 DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq); 2525 2526 if (IS_SKYLAKE(dev)) { 2527 dev_priv->skl_boot_cdclk = cdclk_freq; 2528 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) 2529 DRM_ERROR("LCPLL1 is disabled\n"); 2530 else 2531 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 2532 } else if (IS_BROXTON(dev)) { 2533 broxton_init_cdclk(dev); 2534 broxton_ddi_phy_init(dev); 2535 } else { 2536 /* 2537 * The LCPLL register should be turned on by the BIOS. For now 2538 * let's just check its state and print errors in case 2539 * something is wrong. Don't even try to turn it on. 2540 */ 2541 2542 if (val & LCPLL_CD_SOURCE_FCLK) 2543 DRM_ERROR("CDCLK source is not LCPLL\n"); 2544 2545 if (val & LCPLL_PLL_DISABLE) 2546 DRM_ERROR("LCPLL is disabled\n"); 2547 } 2548 } 2549 2550 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 2551 { 2552 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2553 struct intel_dp *intel_dp = &intel_dig_port->dp; 2554 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 2555 enum port port = intel_dig_port->port; 2556 uint32_t val; 2557 bool wait = false; 2558 2559 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 2560 val = I915_READ(DDI_BUF_CTL(port)); 2561 if (val & DDI_BUF_CTL_ENABLE) { 2562 val &= ~DDI_BUF_CTL_ENABLE; 2563 I915_WRITE(DDI_BUF_CTL(port), val); 2564 wait = true; 2565 } 2566 2567 val = I915_READ(DP_TP_CTL(port)); 2568 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2569 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2570 I915_WRITE(DP_TP_CTL(port), val); 2571 POSTING_READ(DP_TP_CTL(port)); 2572 2573 if (wait) 2574 intel_wait_ddi_buf_idle(dev_priv, port); 2575 } 2576 2577 val = DP_TP_CTL_ENABLE | 2578 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 2579 if (intel_dp->is_mst) 2580 val |= DP_TP_CTL_MODE_MST; 2581 else { 2582 val |= DP_TP_CTL_MODE_SST; 2583 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2584 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 2585 } 2586 I915_WRITE(DP_TP_CTL(port), val); 2587 POSTING_READ(DP_TP_CTL(port)); 2588 2589 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 2590 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 2591 POSTING_READ(DDI_BUF_CTL(port)); 2592 2593 udelay(600); 2594 } 2595 2596 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 2597 { 2598 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 2599 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2600 uint32_t val; 2601 2602 intel_ddi_post_disable(intel_encoder); 2603 2604 val = I915_READ(_FDI_RXA_CTL); 2605 val &= ~FDI_RX_ENABLE; 2606 I915_WRITE(_FDI_RXA_CTL, val); 2607 2608 val = I915_READ(_FDI_RXA_MISC); 2609 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 2610 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 2611 I915_WRITE(_FDI_RXA_MISC, val); 2612 2613 val = I915_READ(_FDI_RXA_CTL); 2614 val &= ~FDI_PCDCLK; 2615 I915_WRITE(_FDI_RXA_CTL, val); 2616 2617 val = I915_READ(_FDI_RXA_CTL); 2618 val &= ~FDI_RX_PLL_ENABLE; 2619 I915_WRITE(_FDI_RXA_CTL, val); 2620 } 2621 2622 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) 2623 { 2624 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base); 2625 int type = intel_dig_port->base.type; 2626 2627 if (type != INTEL_OUTPUT_DISPLAYPORT && 2628 type != INTEL_OUTPUT_EDP && 2629 type != INTEL_OUTPUT_UNKNOWN) { 2630 return; 2631 } 2632 2633 intel_dp_hot_plug(intel_encoder); 2634 } 2635 2636 void intel_ddi_get_config(struct intel_encoder *encoder, 2637 struct intel_crtc_state *pipe_config) 2638 { 2639 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 2640 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2641 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2642 struct intel_hdmi *intel_hdmi; 2643 u32 temp, flags = 0; 2644 2645 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2646 if (temp & TRANS_DDI_PHSYNC) 2647 flags |= DRM_MODE_FLAG_PHSYNC; 2648 else 2649 flags |= DRM_MODE_FLAG_NHSYNC; 2650 if (temp & TRANS_DDI_PVSYNC) 2651 flags |= DRM_MODE_FLAG_PVSYNC; 2652 else 2653 flags |= DRM_MODE_FLAG_NVSYNC; 2654 2655 pipe_config->base.adjusted_mode.flags |= flags; 2656 2657 switch (temp & TRANS_DDI_BPC_MASK) { 2658 case TRANS_DDI_BPC_6: 2659 pipe_config->pipe_bpp = 18; 2660 break; 2661 case TRANS_DDI_BPC_8: 2662 pipe_config->pipe_bpp = 24; 2663 break; 2664 case TRANS_DDI_BPC_10: 2665 pipe_config->pipe_bpp = 30; 2666 break; 2667 case TRANS_DDI_BPC_12: 2668 pipe_config->pipe_bpp = 36; 2669 break; 2670 default: 2671 break; 2672 } 2673 2674 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 2675 case TRANS_DDI_MODE_SELECT_HDMI: 2676 pipe_config->has_hdmi_sink = true; 2677 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 2678 2679 if (intel_hdmi->infoframe_enabled(&encoder->base)) 2680 pipe_config->has_infoframe = true; 2681 break; 2682 case TRANS_DDI_MODE_SELECT_DVI: 2683 case TRANS_DDI_MODE_SELECT_FDI: 2684 break; 2685 case TRANS_DDI_MODE_SELECT_DP_SST: 2686 case TRANS_DDI_MODE_SELECT_DP_MST: 2687 pipe_config->has_dp_encoder = true; 2688 intel_dp_get_m_n(intel_crtc, pipe_config); 2689 break; 2690 default: 2691 break; 2692 } 2693 2694 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 2695 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 2696 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 2697 pipe_config->has_audio = true; 2698 } 2699 2700 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && 2701 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 2702 /* 2703 * This is a big fat ugly hack. 2704 * 2705 * Some machines in UEFI boot mode provide us a VBT that has 18 2706 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 2707 * unknown we fail to light up. Yet the same BIOS boots up with 2708 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 2709 * max, not what it tells us to use. 2710 * 2711 * Note: This will still be broken if the eDP panel is not lit 2712 * up by the BIOS, and thus we can't get the mode at module 2713 * load. 2714 */ 2715 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 2716 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 2717 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 2718 } 2719 2720 intel_ddi_clock_get(encoder, pipe_config); 2721 } 2722 2723 static void intel_ddi_destroy(struct drm_encoder *encoder) 2724 { 2725 /* HDMI has nothing special to destroy, so we can go with this. */ 2726 intel_dp_encoder_destroy(encoder); 2727 } 2728 2729 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 2730 struct intel_crtc_state *pipe_config) 2731 { 2732 int type = encoder->type; 2733 int port = intel_ddi_get_encoder_port(encoder); 2734 2735 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 2736 2737 if (port == PORT_A) 2738 pipe_config->cpu_transcoder = TRANSCODER_EDP; 2739 2740 if (type == INTEL_OUTPUT_HDMI) 2741 return intel_hdmi_compute_config(encoder, pipe_config); 2742 else 2743 return intel_dp_compute_config(encoder, pipe_config); 2744 } 2745 2746 static const struct drm_encoder_funcs intel_ddi_funcs = { 2747 .destroy = intel_ddi_destroy, 2748 }; 2749 2750 static struct intel_connector * 2751 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 2752 { 2753 struct intel_connector *connector; 2754 enum port port = intel_dig_port->port; 2755 2756 connector = intel_connector_alloc(); 2757 if (!connector) 2758 return NULL; 2759 2760 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 2761 if (!intel_dp_init_connector(intel_dig_port, connector)) { 2762 kfree(connector); 2763 return NULL; 2764 } 2765 2766 return connector; 2767 } 2768 2769 static struct intel_connector * 2770 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 2771 { 2772 struct intel_connector *connector; 2773 enum port port = intel_dig_port->port; 2774 2775 connector = intel_connector_alloc(); 2776 if (!connector) 2777 return NULL; 2778 2779 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 2780 intel_hdmi_init_connector(intel_dig_port, connector); 2781 2782 return connector; 2783 } 2784 2785 void intel_ddi_init(struct drm_device *dev, enum port port) 2786 { 2787 struct drm_i915_private *dev_priv = dev->dev_private; 2788 struct intel_digital_port *intel_dig_port; 2789 struct intel_encoder *intel_encoder; 2790 struct drm_encoder *encoder; 2791 bool init_hdmi, init_dp; 2792 2793 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 2794 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 2795 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 2796 if (!init_dp && !init_hdmi) { 2797 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", 2798 port_name(port)); 2799 init_hdmi = true; 2800 init_dp = true; 2801 } 2802 2803 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2804 if (!intel_dig_port) 2805 return; 2806 2807 intel_encoder = &intel_dig_port->base; 2808 encoder = &intel_encoder->base; 2809 2810 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 2811 DRM_MODE_ENCODER_TMDS); 2812 2813 intel_encoder->compute_config = intel_ddi_compute_config; 2814 intel_encoder->enable = intel_enable_ddi; 2815 intel_encoder->pre_enable = intel_ddi_pre_enable; 2816 intel_encoder->disable = intel_disable_ddi; 2817 intel_encoder->post_disable = intel_ddi_post_disable; 2818 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 2819 intel_encoder->get_config = intel_ddi_get_config; 2820 2821 intel_dig_port->port = port; 2822 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 2823 (DDI_BUF_PORT_REVERSAL | 2824 DDI_A_4_LANES); 2825 2826 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 2827 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2828 intel_encoder->cloneable = 0; 2829 intel_encoder->hot_plug = intel_ddi_hot_plug; 2830 2831 if (init_dp) { 2832 if (!intel_ddi_init_dp_connector(intel_dig_port)) 2833 goto err; 2834 2835 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 2836 dev_priv->hpd_irq_port[port] = intel_dig_port; 2837 } 2838 2839 /* In theory we don't need the encoder->type check, but leave it just in 2840 * case we have some really bad VBTs... */ 2841 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 2842 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 2843 goto err; 2844 } 2845 2846 return; 2847 2848 err: 2849 drm_encoder_cleanup(encoder); 2850 kfree(intel_dig_port); 2851 } 2852