1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <asm/int-ll64.h> 31 32 struct ddi_buf_trans { 33 u32 trans1; /* balance leg enable, de-emph level */ 34 u32 trans2; /* vref sel, vswing */ 35 }; 36 37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 38 * them for both DP and FDI transports, allowing those ports to 39 * automatically adapt to HDMI connections as well 40 */ 41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 42 { 0x00FFFFFF, 0x0006000E }, 43 { 0x00D75FFF, 0x0005000A }, 44 { 0x00C30FFF, 0x00040006 }, 45 { 0x80AAAFFF, 0x000B0000 }, 46 { 0x00FFFFFF, 0x0005000A }, 47 { 0x00D75FFF, 0x000C0004 }, 48 { 0x80C30FFF, 0x000B0000 }, 49 { 0x00FFFFFF, 0x00040006 }, 50 { 0x80D75FFF, 0x000B0000 }, 51 }; 52 53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 54 { 0x00FFFFFF, 0x0007000E }, 55 { 0x00D75FFF, 0x000F000A }, 56 { 0x00C30FFF, 0x00060006 }, 57 { 0x00AAAFFF, 0x001E0000 }, 58 { 0x00FFFFFF, 0x000F000A }, 59 { 0x00D75FFF, 0x00160004 }, 60 { 0x00C30FFF, 0x001E0000 }, 61 { 0x00FFFFFF, 0x00060006 }, 62 { 0x00D75FFF, 0x001E0000 }, 63 }; 64 65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 66 /* Idx NT mV d T mV d db */ 67 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */ 68 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */ 69 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */ 70 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */ 71 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */ 72 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */ 73 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */ 74 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */ 75 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */ 76 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */ 77 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */ 78 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */ 79 }; 80 81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 82 { 0x00FFFFFF, 0x00000012 }, 83 { 0x00EBAFFF, 0x00020011 }, 84 { 0x00C71FFF, 0x0006000F }, 85 { 0x00AAAFFF, 0x000E000A }, 86 { 0x00FFFFFF, 0x00020011 }, 87 { 0x00DB6FFF, 0x0005000F }, 88 { 0x00BEEFFF, 0x000A000C }, 89 { 0x00FFFFFF, 0x0005000F }, 90 { 0x00DB6FFF, 0x000A000C }, 91 }; 92 93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 94 { 0x00FFFFFF, 0x0007000E }, 95 { 0x00D75FFF, 0x000E000A }, 96 { 0x00BEFFFF, 0x00140006 }, 97 { 0x80B2CFFF, 0x001B0002 }, 98 { 0x00FFFFFF, 0x000E000A }, 99 { 0x00DB6FFF, 0x00160005 }, 100 { 0x80C71FFF, 0x001A0002 }, 101 { 0x00F7DFFF, 0x00180004 }, 102 { 0x80D75FFF, 0x001B0002 }, 103 }; 104 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 106 { 0x00FFFFFF, 0x0001000E }, 107 { 0x00D75FFF, 0x0004000A }, 108 { 0x00C30FFF, 0x00070006 }, 109 { 0x00AAAFFF, 0x000C0000 }, 110 { 0x00FFFFFF, 0x0004000A }, 111 { 0x00D75FFF, 0x00090004 }, 112 { 0x00C30FFF, 0x000C0000 }, 113 { 0x00FFFFFF, 0x00070006 }, 114 { 0x00D75FFF, 0x000C0000 }, 115 }; 116 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 118 /* Idx NT mV d T mV df db */ 119 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */ 120 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */ 121 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */ 122 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */ 123 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */ 124 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */ 125 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */ 126 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */ 127 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */ 128 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */ 129 }; 130 131 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 132 { 0x00000018, 0x000000a2 }, 133 { 0x00004014, 0x0000009B }, 134 { 0x00006012, 0x00000088 }, 135 { 0x00008010, 0x00000087 }, 136 { 0x00000018, 0x0000009B }, 137 { 0x00004014, 0x00000088 }, 138 { 0x00006012, 0x00000087 }, 139 { 0x00000018, 0x00000088 }, 140 { 0x00004014, 0x00000087 }, 141 }; 142 143 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 144 /* Idx NT mV T mV db */ 145 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */ 146 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */ 147 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */ 148 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */ 149 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */ 150 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */ 151 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */ 152 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */ 153 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */ 154 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */ 155 }; 156 157 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 158 { 159 struct drm_encoder *encoder = &intel_encoder->base; 160 int type = intel_encoder->type; 161 162 if (type == INTEL_OUTPUT_DP_MST) { 163 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary; 164 return intel_dig_port->port; 165 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || 166 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { 167 struct intel_digital_port *intel_dig_port = 168 enc_to_dig_port(encoder); 169 return intel_dig_port->port; 170 171 } else if (type == INTEL_OUTPUT_ANALOG) { 172 return PORT_E; 173 174 } else { 175 DRM_ERROR("Invalid DDI encoder type %d\n", type); 176 BUG(); 177 } 178 } 179 180 /* 181 * Starting with Haswell, DDI port buffers must be programmed with correct 182 * values in advance. The buffer values are different for FDI and DP modes, 183 * but the HDMI/DVI fields are shared among those. So we program the DDI 184 * in either FDI or DP modes only, as HDMI connections will work with both 185 * of those 186 */ 187 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) 188 { 189 struct drm_i915_private *dev_priv = dev->dev_private; 190 u32 reg; 191 int i, n_hdmi_entries, hdmi_800mV_0dB; 192 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 193 const struct ddi_buf_trans *ddi_translations_fdi; 194 const struct ddi_buf_trans *ddi_translations_dp; 195 const struct ddi_buf_trans *ddi_translations_edp; 196 const struct ddi_buf_trans *ddi_translations_hdmi; 197 const struct ddi_buf_trans *ddi_translations; 198 199 if (IS_SKYLAKE(dev)) { 200 ddi_translations_fdi = NULL; 201 ddi_translations_dp = skl_ddi_translations_dp; 202 ddi_translations_edp = skl_ddi_translations_dp; 203 ddi_translations_hdmi = skl_ddi_translations_hdmi; 204 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 205 hdmi_800mV_0dB = 7; 206 } else if (IS_BROADWELL(dev)) { 207 ddi_translations_fdi = bdw_ddi_translations_fdi; 208 ddi_translations_dp = bdw_ddi_translations_dp; 209 ddi_translations_edp = bdw_ddi_translations_edp; 210 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 211 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 212 hdmi_800mV_0dB = 7; 213 } else if (IS_HASWELL(dev)) { 214 ddi_translations_fdi = hsw_ddi_translations_fdi; 215 ddi_translations_dp = hsw_ddi_translations_dp; 216 ddi_translations_edp = hsw_ddi_translations_dp; 217 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 218 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 219 hdmi_800mV_0dB = 6; 220 } else { 221 WARN(1, "ddi translation table missing\n"); 222 ddi_translations_edp = bdw_ddi_translations_dp; 223 ddi_translations_fdi = bdw_ddi_translations_fdi; 224 ddi_translations_dp = bdw_ddi_translations_dp; 225 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 226 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 227 hdmi_800mV_0dB = 7; 228 } 229 230 switch (port) { 231 case PORT_A: 232 ddi_translations = ddi_translations_edp; 233 break; 234 case PORT_B: 235 case PORT_C: 236 ddi_translations = ddi_translations_dp; 237 break; 238 case PORT_D: 239 if (intel_dp_is_edp(dev, PORT_D)) 240 ddi_translations = ddi_translations_edp; 241 else 242 ddi_translations = ddi_translations_dp; 243 break; 244 case PORT_E: 245 if (ddi_translations_fdi) 246 ddi_translations = ddi_translations_fdi; 247 else 248 ddi_translations = ddi_translations_dp; 249 break; 250 default: 251 BUG(); 252 } 253 254 for (i = 0, reg = DDI_BUF_TRANS(port); 255 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { 256 I915_WRITE(reg, ddi_translations[i].trans1); 257 reg += 4; 258 I915_WRITE(reg, ddi_translations[i].trans2); 259 reg += 4; 260 } 261 262 /* Choose a good default if VBT is badly populated */ 263 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 264 hdmi_level >= n_hdmi_entries) 265 hdmi_level = hdmi_800mV_0dB; 266 267 /* Entry 9 is for HDMI: */ 268 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1); 269 reg += 4; 270 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2); 271 reg += 4; 272 } 273 274 /* Program DDI buffers translations for DP. By default, program ports A-D in DP 275 * mode and port E for FDI. 276 */ 277 void intel_prepare_ddi(struct drm_device *dev) 278 { 279 int port; 280 281 if (!HAS_DDI(dev)) 282 return; 283 284 for (port = PORT_A; port <= PORT_E; port++) 285 intel_prepare_ddi_buffers(dev, port); 286 } 287 288 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 289 enum port port) 290 { 291 uint32_t reg = DDI_BUF_CTL(port); 292 int i; 293 294 for (i = 0; i < 8; i++) { 295 udelay(1); 296 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 297 return; 298 } 299 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 300 } 301 302 /* Starting with Haswell, different DDI ports can work in FDI mode for 303 * connection to the PCH-located connectors. For this, it is necessary to train 304 * both the DDI port and PCH receiver for the desired DDI buffer settings. 305 * 306 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 307 * please note that when FDI mode is active on DDI E, it shares 2 lines with 308 * DDI A (which is used for eDP) 309 */ 310 311 void hsw_fdi_link_train(struct drm_crtc *crtc) 312 { 313 struct drm_device *dev = crtc->dev; 314 struct drm_i915_private *dev_priv = dev->dev_private; 315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 316 u32 temp, i, rx_ctl_val; 317 318 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 319 * mode set "sequence for CRT port" document: 320 * - TP1 to TP2 time with the default value 321 * - FDI delay to 90h 322 * 323 * WaFDIAutoLinkSetTimingOverrride:hsw 324 */ 325 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | 326 FDI_RX_PWRDN_LANE0_VAL(2) | 327 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 328 329 /* Enable the PCH Receiver FDI PLL */ 330 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 331 FDI_RX_PLL_ENABLE | 332 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 333 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 334 POSTING_READ(_FDI_RXA_CTL); 335 udelay(220); 336 337 /* Switch from Rawclk to PCDclk */ 338 rx_ctl_val |= FDI_PCDCLK; 339 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 340 341 /* Configure Port Clock Select */ 342 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); 343 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); 344 345 /* Start the training iterating through available voltages and emphasis, 346 * testing each value twice. */ 347 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 348 /* Configure DP_TP_CTL with auto-training */ 349 I915_WRITE(DP_TP_CTL(PORT_E), 350 DP_TP_CTL_FDI_AUTOTRAIN | 351 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 352 DP_TP_CTL_LINK_TRAIN_PAT1 | 353 DP_TP_CTL_ENABLE); 354 355 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 356 * DDI E does not support port reversal, the functionality is 357 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 358 * port reversal bit */ 359 I915_WRITE(DDI_BUF_CTL(PORT_E), 360 DDI_BUF_CTL_ENABLE | 361 ((intel_crtc->config->fdi_lanes - 1) << 1) | 362 DDI_BUF_TRANS_SELECT(i / 2)); 363 POSTING_READ(DDI_BUF_CTL(PORT_E)); 364 365 udelay(600); 366 367 /* Program PCH FDI Receiver TU */ 368 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); 369 370 /* Enable PCH FDI Receiver with auto-training */ 371 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 372 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 373 POSTING_READ(_FDI_RXA_CTL); 374 375 /* Wait for FDI receiver lane calibration */ 376 udelay(30); 377 378 /* Unset FDI_RX_MISC pwrdn lanes */ 379 temp = I915_READ(_FDI_RXA_MISC); 380 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 381 I915_WRITE(_FDI_RXA_MISC, temp); 382 POSTING_READ(_FDI_RXA_MISC); 383 384 /* Wait for FDI auto training time */ 385 udelay(5); 386 387 temp = I915_READ(DP_TP_STATUS(PORT_E)); 388 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 389 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 390 391 /* Enable normal pixel sending for FDI */ 392 I915_WRITE(DP_TP_CTL(PORT_E), 393 DP_TP_CTL_FDI_AUTOTRAIN | 394 DP_TP_CTL_LINK_TRAIN_NORMAL | 395 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 396 DP_TP_CTL_ENABLE); 397 398 return; 399 } 400 401 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 402 temp &= ~DDI_BUF_CTL_ENABLE; 403 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 404 POSTING_READ(DDI_BUF_CTL(PORT_E)); 405 406 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 407 temp = I915_READ(DP_TP_CTL(PORT_E)); 408 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 409 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 410 I915_WRITE(DP_TP_CTL(PORT_E), temp); 411 POSTING_READ(DP_TP_CTL(PORT_E)); 412 413 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 414 415 rx_ctl_val &= ~FDI_RX_ENABLE; 416 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 417 POSTING_READ(_FDI_RXA_CTL); 418 419 /* Reset FDI_RX_MISC pwrdn lanes */ 420 temp = I915_READ(_FDI_RXA_MISC); 421 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 422 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 423 I915_WRITE(_FDI_RXA_MISC, temp); 424 POSTING_READ(_FDI_RXA_MISC); 425 } 426 427 DRM_ERROR("FDI link training failed!\n"); 428 } 429 430 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 431 { 432 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 433 struct intel_digital_port *intel_dig_port = 434 enc_to_dig_port(&encoder->base); 435 436 intel_dp->DP = intel_dig_port->saved_port_bits | 437 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 438 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 439 440 } 441 442 static struct intel_encoder * 443 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 444 { 445 struct drm_device *dev = crtc->dev; 446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 447 struct intel_encoder *intel_encoder, *ret = NULL; 448 int num_encoders = 0; 449 450 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 451 ret = intel_encoder; 452 num_encoders++; 453 } 454 455 if (num_encoders != 1) 456 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 457 pipe_name(intel_crtc->pipe)); 458 459 BUG_ON(ret == NULL); 460 return ret; 461 } 462 463 static struct intel_encoder * 464 intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc) 465 { 466 struct drm_device *dev = crtc->base.dev; 467 struct intel_encoder *intel_encoder, *ret = NULL; 468 int num_encoders = 0; 469 470 for_each_intel_encoder(dev, intel_encoder) { 471 if (intel_encoder->new_crtc == crtc) { 472 ret = intel_encoder; 473 num_encoders++; 474 } 475 } 476 477 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 478 pipe_name(crtc->pipe)); 479 480 BUG_ON(ret == NULL); 481 return ret; 482 } 483 484 #define LC_FREQ 2700 485 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 486 487 #define P_MIN 2 488 #define P_MAX 64 489 #define P_INC 2 490 491 /* Constraints for PLL good behavior */ 492 #define REF_MIN 48 493 #define REF_MAX 400 494 #define VCO_MIN 2400 495 #define VCO_MAX 4800 496 497 #define abs_diff(a, b) ({ \ 498 typeof(a) __a = (a); \ 499 typeof(b) __b = (b); \ 500 (void) (&__a == &__b); \ 501 __a > __b ? (__a - __b) : (__b - __a); }) 502 503 struct wrpll_rnp { 504 unsigned p, n2, r2; 505 }; 506 507 static unsigned wrpll_get_budget_for_freq(int clock) 508 { 509 unsigned budget; 510 511 switch (clock) { 512 case 25175000: 513 case 25200000: 514 case 27000000: 515 case 27027000: 516 case 37762500: 517 case 37800000: 518 case 40500000: 519 case 40541000: 520 case 54000000: 521 case 54054000: 522 case 59341000: 523 case 59400000: 524 case 72000000: 525 case 74176000: 526 case 74250000: 527 case 81000000: 528 case 81081000: 529 case 89012000: 530 case 89100000: 531 case 108000000: 532 case 108108000: 533 case 111264000: 534 case 111375000: 535 case 148352000: 536 case 148500000: 537 case 162000000: 538 case 162162000: 539 case 222525000: 540 case 222750000: 541 case 296703000: 542 case 297000000: 543 budget = 0; 544 break; 545 case 233500000: 546 case 245250000: 547 case 247750000: 548 case 253250000: 549 case 298000000: 550 budget = 1500; 551 break; 552 case 169128000: 553 case 169500000: 554 case 179500000: 555 case 202000000: 556 budget = 2000; 557 break; 558 case 256250000: 559 case 262500000: 560 case 270000000: 561 case 272500000: 562 case 273750000: 563 case 280750000: 564 case 281250000: 565 case 286000000: 566 case 291750000: 567 budget = 4000; 568 break; 569 case 267250000: 570 case 268500000: 571 budget = 5000; 572 break; 573 default: 574 budget = 1000; 575 break; 576 } 577 578 return budget; 579 } 580 581 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, 582 unsigned r2, unsigned n2, unsigned p, 583 struct wrpll_rnp *best) 584 { 585 uint64_t a, b, c, d, diff, diff_best; 586 587 /* No best (r,n,p) yet */ 588 if (best->p == 0) { 589 best->p = p; 590 best->n2 = n2; 591 best->r2 = r2; 592 return; 593 } 594 595 /* 596 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 597 * freq2k. 598 * 599 * delta = 1e6 * 600 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 601 * freq2k; 602 * 603 * and we would like delta <= budget. 604 * 605 * If the discrepancy is above the PPM-based budget, always prefer to 606 * improve upon the previous solution. However, if you're within the 607 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 608 */ 609 a = freq2k * budget * p * r2; 610 b = freq2k * budget * best->p * best->r2; 611 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); 612 diff_best = abs_diff(freq2k * best->p * best->r2, 613 LC_FREQ_2K * best->n2); 614 c = 1000000 * diff; 615 d = 1000000 * diff_best; 616 617 if (a < c && b < d) { 618 /* If both are above the budget, pick the closer */ 619 if (best->p * best->r2 * diff < p * r2 * diff_best) { 620 best->p = p; 621 best->n2 = n2; 622 best->r2 = r2; 623 } 624 } else if (a >= c && b < d) { 625 /* If A is below the threshold but B is above it? Update. */ 626 best->p = p; 627 best->n2 = n2; 628 best->r2 = r2; 629 } else if (a >= c && b >= d) { 630 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 631 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 632 best->p = p; 633 best->n2 = n2; 634 best->r2 = r2; 635 } 636 } 637 /* Otherwise a < c && b >= d, do nothing */ 638 } 639 640 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 641 int reg) 642 { 643 int refclk = LC_FREQ; 644 int n, p, r; 645 u32 wrpll; 646 647 wrpll = I915_READ(reg); 648 switch (wrpll & WRPLL_PLL_REF_MASK) { 649 case WRPLL_PLL_SSC: 650 case WRPLL_PLL_NON_SSC: 651 /* 652 * We could calculate spread here, but our checking 653 * code only cares about 5% accuracy, and spread is a max of 654 * 0.5% downspread. 655 */ 656 refclk = 135; 657 break; 658 case WRPLL_PLL_LCPLL: 659 refclk = LC_FREQ; 660 break; 661 default: 662 WARN(1, "bad wrpll refclk\n"); 663 return 0; 664 } 665 666 r = wrpll & WRPLL_DIVIDER_REF_MASK; 667 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 668 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 669 670 /* Convert to KHz, p & r have a fixed point portion */ 671 return (refclk * n * 100) / (p * r); 672 } 673 674 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 675 uint32_t dpll) 676 { 677 uint32_t cfgcr1_reg, cfgcr2_reg; 678 uint32_t cfgcr1_val, cfgcr2_val; 679 uint32_t p0, p1, p2, dco_freq; 680 681 cfgcr1_reg = GET_CFG_CR1_REG(dpll); 682 cfgcr2_reg = GET_CFG_CR2_REG(dpll); 683 684 cfgcr1_val = I915_READ(cfgcr1_reg); 685 cfgcr2_val = I915_READ(cfgcr2_reg); 686 687 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 688 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 689 690 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 691 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 692 else 693 p1 = 1; 694 695 696 switch (p0) { 697 case DPLL_CFGCR2_PDIV_1: 698 p0 = 1; 699 break; 700 case DPLL_CFGCR2_PDIV_2: 701 p0 = 2; 702 break; 703 case DPLL_CFGCR2_PDIV_3: 704 p0 = 3; 705 break; 706 case DPLL_CFGCR2_PDIV_7: 707 p0 = 7; 708 break; 709 } 710 711 switch (p2) { 712 case DPLL_CFGCR2_KDIV_5: 713 p2 = 5; 714 break; 715 case DPLL_CFGCR2_KDIV_2: 716 p2 = 2; 717 break; 718 case DPLL_CFGCR2_KDIV_3: 719 p2 = 3; 720 break; 721 case DPLL_CFGCR2_KDIV_1: 722 p2 = 1; 723 break; 724 } 725 726 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 727 728 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 729 1000) / 0x8000; 730 731 return dco_freq / (p0 * p1 * p2 * 5); 732 } 733 734 735 static void skl_ddi_clock_get(struct intel_encoder *encoder, 736 struct intel_crtc_state *pipe_config) 737 { 738 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 739 int link_clock = 0; 740 uint32_t dpll_ctl1, dpll; 741 742 dpll = pipe_config->ddi_pll_sel; 743 744 dpll_ctl1 = I915_READ(DPLL_CTRL1); 745 746 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 747 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 748 } else { 749 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll); 750 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll); 751 752 switch (link_clock) { 753 case DPLL_CRTL1_LINK_RATE_810: 754 link_clock = 81000; 755 break; 756 case DPLL_CRTL1_LINK_RATE_1350: 757 link_clock = 135000; 758 break; 759 case DPLL_CRTL1_LINK_RATE_2700: 760 link_clock = 270000; 761 break; 762 default: 763 WARN(1, "Unsupported link rate\n"); 764 break; 765 } 766 link_clock *= 2; 767 } 768 769 pipe_config->port_clock = link_clock; 770 771 if (pipe_config->has_dp_encoder) 772 pipe_config->base.adjusted_mode.crtc_clock = 773 intel_dotclock_calculate(pipe_config->port_clock, 774 &pipe_config->dp_m_n); 775 else 776 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 777 } 778 779 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 780 struct intel_crtc_state *pipe_config) 781 { 782 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 783 int link_clock = 0; 784 u32 val, pll; 785 786 val = pipe_config->ddi_pll_sel; 787 switch (val & PORT_CLK_SEL_MASK) { 788 case PORT_CLK_SEL_LCPLL_810: 789 link_clock = 81000; 790 break; 791 case PORT_CLK_SEL_LCPLL_1350: 792 link_clock = 135000; 793 break; 794 case PORT_CLK_SEL_LCPLL_2700: 795 link_clock = 270000; 796 break; 797 case PORT_CLK_SEL_WRPLL1: 798 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); 799 break; 800 case PORT_CLK_SEL_WRPLL2: 801 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); 802 break; 803 case PORT_CLK_SEL_SPLL: 804 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 805 if (pll == SPLL_PLL_FREQ_810MHz) 806 link_clock = 81000; 807 else if (pll == SPLL_PLL_FREQ_1350MHz) 808 link_clock = 135000; 809 else if (pll == SPLL_PLL_FREQ_2700MHz) 810 link_clock = 270000; 811 else { 812 WARN(1, "bad spll freq\n"); 813 return; 814 } 815 break; 816 default: 817 WARN(1, "bad port clock sel\n"); 818 return; 819 } 820 821 pipe_config->port_clock = link_clock * 2; 822 823 if (pipe_config->has_pch_encoder) 824 pipe_config->base.adjusted_mode.crtc_clock = 825 intel_dotclock_calculate(pipe_config->port_clock, 826 &pipe_config->fdi_m_n); 827 else if (pipe_config->has_dp_encoder) 828 pipe_config->base.adjusted_mode.crtc_clock = 829 intel_dotclock_calculate(pipe_config->port_clock, 830 &pipe_config->dp_m_n); 831 else 832 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 833 } 834 835 void intel_ddi_clock_get(struct intel_encoder *encoder, 836 struct intel_crtc_state *pipe_config) 837 { 838 struct drm_device *dev = encoder->base.dev; 839 840 if (INTEL_INFO(dev)->gen <= 8) 841 hsw_ddi_clock_get(encoder, pipe_config); 842 else 843 skl_ddi_clock_get(encoder, pipe_config); 844 } 845 846 static void 847 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 848 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 849 { 850 uint64_t freq2k; 851 unsigned p, n2, r2; 852 struct wrpll_rnp best = { 0, 0, 0 }; 853 unsigned budget; 854 855 freq2k = clock / 100; 856 857 budget = wrpll_get_budget_for_freq(clock); 858 859 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 860 * and directly pass the LC PLL to it. */ 861 if (freq2k == 5400000) { 862 *n2_out = 2; 863 *p_out = 1; 864 *r2_out = 2; 865 return; 866 } 867 868 /* 869 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 870 * the WR PLL. 871 * 872 * We want R so that REF_MIN <= Ref <= REF_MAX. 873 * Injecting R2 = 2 * R gives: 874 * REF_MAX * r2 > LC_FREQ * 2 and 875 * REF_MIN * r2 < LC_FREQ * 2 876 * 877 * Which means the desired boundaries for r2 are: 878 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 879 * 880 */ 881 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 882 r2 <= LC_FREQ * 2 / REF_MIN; 883 r2++) { 884 885 /* 886 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 887 * 888 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 889 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 890 * VCO_MAX * r2 > n2 * LC_FREQ and 891 * VCO_MIN * r2 < n2 * LC_FREQ) 892 * 893 * Which means the desired boundaries for n2 are: 894 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 895 */ 896 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 897 n2 <= VCO_MAX * r2 / LC_FREQ; 898 n2++) { 899 900 for (p = P_MIN; p <= P_MAX; p += P_INC) 901 wrpll_update_rnp(freq2k, budget, 902 r2, n2, p, &best); 903 } 904 } 905 906 *n2_out = best.n2; 907 *p_out = best.p; 908 *r2_out = best.r2; 909 } 910 911 static bool 912 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 913 struct intel_crtc_state *crtc_state, 914 struct intel_encoder *intel_encoder, 915 int clock) 916 { 917 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 918 struct intel_shared_dpll *pll; 919 uint32_t val; 920 unsigned p, n2, r2; 921 922 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 923 924 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 925 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 926 WRPLL_DIVIDER_POST(p); 927 928 crtc_state->dpll_hw_state.wrpll = val; 929 930 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 931 if (pll == NULL) { 932 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 933 pipe_name(intel_crtc->pipe)); 934 return false; 935 } 936 937 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 938 } 939 940 return true; 941 } 942 943 struct skl_wrpll_params { 944 uint32_t dco_fraction; 945 uint32_t dco_integer; 946 uint32_t qdiv_ratio; 947 uint32_t qdiv_mode; 948 uint32_t kdiv; 949 uint32_t pdiv; 950 uint32_t central_freq; 951 }; 952 953 static void 954 skl_ddi_calculate_wrpll(int clock /* in Hz */, 955 struct skl_wrpll_params *wrpll_params) 956 { 957 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 958 uint64_t dco_central_freq[3] = {8400000000ULL, 959 9000000000ULL, 960 9600000000ULL}; 961 uint32_t min_dco_deviation = 400; 962 uint32_t min_dco_index = 3; 963 uint32_t P0[4] = {1, 2, 3, 7}; 964 uint32_t P2[4] = {1, 2, 3, 5}; 965 bool found = false; 966 uint32_t candidate_p = 0; 967 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0}; 968 uint32_t candidate_p2[3] = {0}; 969 uint32_t dco_central_freq_deviation[3]; 970 uint32_t i, P1, k, dco_count; 971 bool retry_with_odd = false; 972 uint64_t dco_freq; 973 974 /* Determine P0, P1 or P2 */ 975 for (dco_count = 0; dco_count < 3; dco_count++) { 976 found = false; 977 candidate_p = 978 div64_u64(dco_central_freq[dco_count], afe_clock); 979 if (retry_with_odd == false) 980 candidate_p = (candidate_p % 2 == 0 ? 981 candidate_p : candidate_p + 1); 982 983 for (P1 = 1; P1 < candidate_p; P1++) { 984 for (i = 0; i < 4; i++) { 985 if (!(P0[i] != 1 || P1 == 1)) 986 continue; 987 988 for (k = 0; k < 4; k++) { 989 if (P1 != 1 && P2[k] != 2) 990 continue; 991 992 if (candidate_p == P0[i] * P1 * P2[k]) { 993 /* Found possible P0, P1, P2 */ 994 found = true; 995 candidate_p0[dco_count] = P0[i]; 996 candidate_p1[dco_count] = P1; 997 candidate_p2[dco_count] = P2[k]; 998 goto found; 999 } 1000 1001 } 1002 } 1003 } 1004 1005 found: 1006 if (found) { 1007 dco_central_freq_deviation[dco_count] = 1008 div64_u64(10000 * 1009 abs_diff((candidate_p * afe_clock), 1010 dco_central_freq[dco_count]), 1011 dco_central_freq[dco_count]); 1012 1013 if (dco_central_freq_deviation[dco_count] < 1014 min_dco_deviation) { 1015 min_dco_deviation = 1016 dco_central_freq_deviation[dco_count]; 1017 min_dco_index = dco_count; 1018 } 1019 } 1020 1021 if (min_dco_index > 2 && dco_count == 2) { 1022 retry_with_odd = true; 1023 dco_count = 0; 1024 } 1025 } 1026 1027 if (min_dco_index > 2) { 1028 WARN(1, "No valid values found for the given pixel clock\n"); 1029 } else { 1030 wrpll_params->central_freq = dco_central_freq[min_dco_index]; 1031 1032 switch (dco_central_freq[min_dco_index]) { 1033 case 9600000000ULL: 1034 wrpll_params->central_freq = 0; 1035 break; 1036 case 9000000000ULL: 1037 wrpll_params->central_freq = 1; 1038 break; 1039 case 8400000000ULL: 1040 wrpll_params->central_freq = 3; 1041 } 1042 1043 switch (candidate_p0[min_dco_index]) { 1044 case 1: 1045 wrpll_params->pdiv = 0; 1046 break; 1047 case 2: 1048 wrpll_params->pdiv = 1; 1049 break; 1050 case 3: 1051 wrpll_params->pdiv = 2; 1052 break; 1053 case 7: 1054 wrpll_params->pdiv = 4; 1055 break; 1056 default: 1057 WARN(1, "Incorrect PDiv\n"); 1058 } 1059 1060 switch (candidate_p2[min_dco_index]) { 1061 case 5: 1062 wrpll_params->kdiv = 0; 1063 break; 1064 case 2: 1065 wrpll_params->kdiv = 1; 1066 break; 1067 case 3: 1068 wrpll_params->kdiv = 2; 1069 break; 1070 case 1: 1071 wrpll_params->kdiv = 3; 1072 break; 1073 default: 1074 WARN(1, "Incorrect KDiv\n"); 1075 } 1076 1077 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index]; 1078 wrpll_params->qdiv_mode = 1079 (wrpll_params->qdiv_ratio == 1) ? 0 : 1; 1080 1081 dco_freq = candidate_p0[min_dco_index] * 1082 candidate_p1[min_dco_index] * 1083 candidate_p2[min_dco_index] * afe_clock; 1084 1085 /* 1086 * Intermediate values are in Hz. 1087 * Divide by MHz to match bsepc 1088 */ 1089 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1))); 1090 wrpll_params->dco_fraction = 1091 div_u64(((div_u64(dco_freq, 24) - 1092 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1)); 1093 1094 } 1095 } 1096 1097 1098 static bool 1099 skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1100 struct intel_crtc_state *crtc_state, 1101 struct intel_encoder *intel_encoder, 1102 int clock) 1103 { 1104 struct intel_shared_dpll *pll; 1105 uint32_t ctrl1, cfgcr1, cfgcr2; 1106 1107 /* 1108 * See comment in intel_dpll_hw_state to understand why we always use 0 1109 * as the DPLL id in this function. 1110 */ 1111 1112 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1113 1114 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1115 struct skl_wrpll_params wrpll_params = { 0, }; 1116 1117 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1118 1119 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params); 1120 1121 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1122 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1123 wrpll_params.dco_integer; 1124 1125 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1126 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1127 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1128 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1129 wrpll_params.central_freq; 1130 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 1131 struct drm_encoder *encoder = &intel_encoder->base; 1132 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1133 1134 switch (intel_dp->link_bw) { 1135 case DP_LINK_BW_1_62: 1136 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0); 1137 break; 1138 case DP_LINK_BW_2_7: 1139 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0); 1140 break; 1141 case DP_LINK_BW_5_4: 1142 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0); 1143 break; 1144 } 1145 1146 cfgcr1 = cfgcr2 = 0; 1147 } else /* eDP */ 1148 return true; 1149 1150 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1151 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1152 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1153 1154 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1155 if (pll == NULL) { 1156 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1157 pipe_name(intel_crtc->pipe)); 1158 return false; 1159 } 1160 1161 /* shared DPLL id 0 is DPLL 1 */ 1162 crtc_state->ddi_pll_sel = pll->id + 1; 1163 1164 return true; 1165 } 1166 1167 /* 1168 * Tries to find a *shared* PLL for the CRTC and store it in 1169 * intel_crtc->ddi_pll_sel. 1170 * 1171 * For private DPLLs, compute_config() should do the selection for us. This 1172 * function should be folded into compute_config() eventually. 1173 */ 1174 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, 1175 struct intel_crtc_state *crtc_state) 1176 { 1177 struct drm_device *dev = intel_crtc->base.dev; 1178 struct intel_encoder *intel_encoder = 1179 intel_ddi_get_crtc_new_encoder(intel_crtc); 1180 int clock = crtc_state->port_clock; 1181 1182 if (IS_SKYLAKE(dev)) 1183 return skl_ddi_pll_select(intel_crtc, crtc_state, 1184 intel_encoder, clock); 1185 else 1186 return hsw_ddi_pll_select(intel_crtc, crtc_state, 1187 intel_encoder, clock); 1188 } 1189 1190 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1191 { 1192 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1194 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1195 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1196 int type = intel_encoder->type; 1197 uint32_t temp; 1198 1199 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1200 temp = TRANS_MSA_SYNC_CLK; 1201 switch (intel_crtc->config->pipe_bpp) { 1202 case 18: 1203 temp |= TRANS_MSA_6_BPC; 1204 break; 1205 case 24: 1206 temp |= TRANS_MSA_8_BPC; 1207 break; 1208 case 30: 1209 temp |= TRANS_MSA_10_BPC; 1210 break; 1211 case 36: 1212 temp |= TRANS_MSA_12_BPC; 1213 break; 1214 default: 1215 BUG(); 1216 } 1217 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1218 } 1219 } 1220 1221 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) 1222 { 1223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1224 struct drm_device *dev = crtc->dev; 1225 struct drm_i915_private *dev_priv = dev->dev_private; 1226 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1227 uint32_t temp; 1228 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1229 if (state == true) 1230 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1231 else 1232 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1233 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1234 } 1235 1236 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 1237 { 1238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1239 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1240 struct drm_encoder *encoder = &intel_encoder->base; 1241 struct drm_device *dev = crtc->dev; 1242 struct drm_i915_private *dev_priv = dev->dev_private; 1243 enum i915_pipe pipe = intel_crtc->pipe; 1244 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1245 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1246 int type = intel_encoder->type; 1247 uint32_t temp; 1248 1249 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1250 temp = TRANS_DDI_FUNC_ENABLE; 1251 temp |= TRANS_DDI_SELECT_PORT(port); 1252 1253 switch (intel_crtc->config->pipe_bpp) { 1254 case 18: 1255 temp |= TRANS_DDI_BPC_6; 1256 break; 1257 case 24: 1258 temp |= TRANS_DDI_BPC_8; 1259 break; 1260 case 30: 1261 temp |= TRANS_DDI_BPC_10; 1262 break; 1263 case 36: 1264 temp |= TRANS_DDI_BPC_12; 1265 break; 1266 default: 1267 BUG(); 1268 } 1269 1270 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1271 temp |= TRANS_DDI_PVSYNC; 1272 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1273 temp |= TRANS_DDI_PHSYNC; 1274 1275 if (cpu_transcoder == TRANSCODER_EDP) { 1276 switch (pipe) { 1277 case PIPE_A: 1278 /* On Haswell, can only use the always-on power well for 1279 * eDP when not using the panel fitter, and when not 1280 * using motion blur mitigation (which we don't 1281 * support). */ 1282 if (IS_HASWELL(dev) && 1283 (intel_crtc->config->pch_pfit.enabled || 1284 intel_crtc->config->pch_pfit.force_thru)) 1285 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1286 else 1287 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1288 break; 1289 case PIPE_B: 1290 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1291 break; 1292 case PIPE_C: 1293 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1294 break; 1295 default: 1296 BUG(); 1297 break; 1298 } 1299 } 1300 1301 if (type == INTEL_OUTPUT_HDMI) { 1302 if (intel_crtc->config->has_hdmi_sink) 1303 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1304 else 1305 temp |= TRANS_DDI_MODE_SELECT_DVI; 1306 1307 } else if (type == INTEL_OUTPUT_ANALOG) { 1308 temp |= TRANS_DDI_MODE_SELECT_FDI; 1309 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; 1310 1311 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1312 type == INTEL_OUTPUT_EDP) { 1313 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1314 1315 if (intel_dp->is_mst) { 1316 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1317 } else 1318 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1319 1320 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); 1321 } else if (type == INTEL_OUTPUT_DP_MST) { 1322 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; 1323 1324 if (intel_dp->is_mst) { 1325 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1326 } else 1327 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1328 1329 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); 1330 } else { 1331 WARN(1, "Invalid encoder type %d for pipe %c\n", 1332 intel_encoder->type, pipe_name(pipe)); 1333 } 1334 1335 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1336 } 1337 1338 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1339 enum transcoder cpu_transcoder) 1340 { 1341 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1342 uint32_t val = I915_READ(reg); 1343 1344 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1345 val |= TRANS_DDI_PORT_NONE; 1346 I915_WRITE(reg, val); 1347 } 1348 1349 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1350 { 1351 struct drm_device *dev = intel_connector->base.dev; 1352 struct drm_i915_private *dev_priv = dev->dev_private; 1353 struct intel_encoder *intel_encoder = intel_connector->encoder; 1354 int type = intel_connector->base.connector_type; 1355 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1356 enum i915_pipe pipe = 0; 1357 enum transcoder cpu_transcoder; 1358 enum intel_display_power_domain power_domain; 1359 uint32_t tmp; 1360 1361 power_domain = intel_display_port_power_domain(intel_encoder); 1362 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1363 return false; 1364 1365 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) 1366 return false; 1367 1368 if (port == PORT_A) 1369 cpu_transcoder = TRANSCODER_EDP; 1370 else 1371 cpu_transcoder = (enum transcoder) pipe; 1372 1373 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1374 1375 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1376 case TRANS_DDI_MODE_SELECT_HDMI: 1377 case TRANS_DDI_MODE_SELECT_DVI: 1378 return (type == DRM_MODE_CONNECTOR_HDMIA); 1379 1380 case TRANS_DDI_MODE_SELECT_DP_SST: 1381 if (type == DRM_MODE_CONNECTOR_eDP) 1382 return true; 1383 return (type == DRM_MODE_CONNECTOR_DisplayPort); 1384 case TRANS_DDI_MODE_SELECT_DP_MST: 1385 /* if the transcoder is in MST state then 1386 * connector isn't connected */ 1387 return false; 1388 1389 case TRANS_DDI_MODE_SELECT_FDI: 1390 return (type == DRM_MODE_CONNECTOR_VGA); 1391 1392 default: 1393 return false; 1394 } 1395 } 1396 1397 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1398 enum i915_pipe *pipe) 1399 { 1400 struct drm_device *dev = encoder->base.dev; 1401 struct drm_i915_private *dev_priv = dev->dev_private; 1402 enum port port = intel_ddi_get_encoder_port(encoder); 1403 enum intel_display_power_domain power_domain; 1404 u32 tmp; 1405 int i; 1406 1407 power_domain = intel_display_port_power_domain(encoder); 1408 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1409 return false; 1410 1411 tmp = I915_READ(DDI_BUF_CTL(port)); 1412 1413 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1414 return false; 1415 1416 if (port == PORT_A) { 1417 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1418 1419 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1420 case TRANS_DDI_EDP_INPUT_A_ON: 1421 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1422 *pipe = PIPE_A; 1423 break; 1424 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1425 *pipe = PIPE_B; 1426 break; 1427 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1428 *pipe = PIPE_C; 1429 break; 1430 } 1431 1432 return true; 1433 } else { 1434 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 1435 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 1436 1437 if ((tmp & TRANS_DDI_PORT_MASK) 1438 == TRANS_DDI_SELECT_PORT(port)) { 1439 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) 1440 return false; 1441 1442 *pipe = i; 1443 return true; 1444 } 1445 } 1446 } 1447 1448 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 1449 1450 return false; 1451 } 1452 1453 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 1454 { 1455 struct drm_crtc *crtc = &intel_crtc->base; 1456 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1457 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1458 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1459 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1460 1461 if (cpu_transcoder != TRANSCODER_EDP) 1462 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1463 TRANS_CLK_SEL_PORT(port)); 1464 } 1465 1466 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 1467 { 1468 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1469 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1470 1471 if (cpu_transcoder != TRANSCODER_EDP) 1472 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1473 TRANS_CLK_SEL_DISABLED); 1474 } 1475 1476 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 1477 { 1478 struct drm_encoder *encoder = &intel_encoder->base; 1479 struct drm_device *dev = encoder->dev; 1480 struct drm_i915_private *dev_priv = dev->dev_private; 1481 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 1482 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1483 int type = intel_encoder->type; 1484 1485 if (type == INTEL_OUTPUT_EDP) { 1486 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1487 intel_edp_panel_on(intel_dp); 1488 } 1489 1490 if (IS_SKYLAKE(dev)) { 1491 uint32_t dpll = crtc->config->ddi_pll_sel; 1492 uint32_t val; 1493 1494 /* 1495 * DPLL0 is used for eDP and is the only "private" DPLL (as 1496 * opposed to shared) on SKL 1497 */ 1498 if (type == INTEL_OUTPUT_EDP) { 1499 WARN_ON(dpll != SKL_DPLL0); 1500 1501 val = I915_READ(DPLL_CTRL1); 1502 1503 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | 1504 DPLL_CTRL1_SSC(dpll) | 1505 DPLL_CRTL1_LINK_RATE_MASK(dpll)); 1506 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); 1507 1508 I915_WRITE(DPLL_CTRL1, val); 1509 POSTING_READ(DPLL_CTRL1); 1510 } 1511 1512 /* DDI -> PLL mapping */ 1513 val = I915_READ(DPLL_CTRL2); 1514 1515 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 1516 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 1517 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | 1518 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1519 1520 I915_WRITE(DPLL_CTRL2, val); 1521 1522 } else { 1523 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); 1524 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); 1525 } 1526 1527 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1528 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1529 1530 intel_ddi_init_dp_buf_reg(intel_encoder); 1531 1532 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1533 intel_dp_start_link_train(intel_dp); 1534 intel_dp_complete_link_train(intel_dp); 1535 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) 1536 intel_dp_stop_link_train(intel_dp); 1537 } else if (type == INTEL_OUTPUT_HDMI) { 1538 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1539 1540 intel_hdmi->set_infoframes(encoder, 1541 crtc->config->has_hdmi_sink, 1542 &crtc->config->base.adjusted_mode); 1543 } 1544 } 1545 1546 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 1547 { 1548 struct drm_encoder *encoder = &intel_encoder->base; 1549 struct drm_device *dev = encoder->dev; 1550 struct drm_i915_private *dev_priv = dev->dev_private; 1551 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1552 int type = intel_encoder->type; 1553 uint32_t val; 1554 bool wait = false; 1555 1556 val = I915_READ(DDI_BUF_CTL(port)); 1557 if (val & DDI_BUF_CTL_ENABLE) { 1558 val &= ~DDI_BUF_CTL_ENABLE; 1559 I915_WRITE(DDI_BUF_CTL(port), val); 1560 wait = true; 1561 } 1562 1563 val = I915_READ(DP_TP_CTL(port)); 1564 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1565 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1566 I915_WRITE(DP_TP_CTL(port), val); 1567 1568 if (wait) 1569 intel_wait_ddi_buf_idle(dev_priv, port); 1570 1571 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1572 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1573 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1574 intel_edp_panel_vdd_on(intel_dp); 1575 intel_edp_panel_off(intel_dp); 1576 } 1577 1578 if (IS_SKYLAKE(dev)) 1579 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 1580 DPLL_CTRL2_DDI_CLK_OFF(port))); 1581 else 1582 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1583 } 1584 1585 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 1586 { 1587 struct drm_encoder *encoder = &intel_encoder->base; 1588 struct drm_crtc *crtc = encoder->crtc; 1589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1590 struct drm_device *dev = encoder->dev; 1591 struct drm_i915_private *dev_priv = dev->dev_private; 1592 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1593 int type = intel_encoder->type; 1594 1595 if (type == INTEL_OUTPUT_HDMI) { 1596 struct intel_digital_port *intel_dig_port = 1597 enc_to_dig_port(encoder); 1598 1599 /* In HDMI/DVI mode, the port width, and swing/emphasis values 1600 * are ignored so nothing special needs to be done besides 1601 * enabling the port. 1602 */ 1603 I915_WRITE(DDI_BUF_CTL(port), 1604 intel_dig_port->saved_port_bits | 1605 DDI_BUF_CTL_ENABLE); 1606 } else if (type == INTEL_OUTPUT_EDP) { 1607 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1608 1609 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) 1610 intel_dp_stop_link_train(intel_dp); 1611 1612 intel_edp_backlight_on(intel_dp); 1613 intel_psr_enable(intel_dp); 1614 intel_edp_drrs_enable(intel_dp); 1615 } 1616 1617 if (intel_crtc->config->has_audio) { 1618 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 1619 intel_audio_codec_enable(intel_encoder); 1620 } 1621 } 1622 1623 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 1624 { 1625 struct drm_encoder *encoder = &intel_encoder->base; 1626 struct drm_crtc *crtc = encoder->crtc; 1627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1628 int type = intel_encoder->type; 1629 struct drm_device *dev = encoder->dev; 1630 struct drm_i915_private *dev_priv = dev->dev_private; 1631 1632 if (intel_crtc->config->has_audio) { 1633 intel_audio_codec_disable(intel_encoder); 1634 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 1635 } 1636 1637 if (type == INTEL_OUTPUT_EDP) { 1638 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1639 1640 intel_edp_drrs_disable(intel_dp); 1641 intel_psr_disable(intel_dp); 1642 intel_edp_backlight_off(intel_dp); 1643 } 1644 } 1645 1646 static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv) 1647 { 1648 uint32_t lcpll1 = I915_READ(LCPLL1_CTL); 1649 uint32_t cdctl = I915_READ(CDCLK_CTL); 1650 uint32_t linkrate; 1651 1652 if (!(lcpll1 & LCPLL_PLL_ENABLE)) { 1653 WARN(1, "LCPLL1 not enabled\n"); 1654 return 24000; /* 24MHz is the cd freq with NSSC ref */ 1655 } 1656 1657 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) 1658 return 540000; 1659 1660 linkrate = (I915_READ(DPLL_CTRL1) & 1661 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; 1662 1663 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || 1664 linkrate == DPLL_CRTL1_LINK_RATE_1080) { 1665 /* vco 8640 */ 1666 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1667 case CDCLK_FREQ_450_432: 1668 return 432000; 1669 case CDCLK_FREQ_337_308: 1670 return 308570; 1671 case CDCLK_FREQ_675_617: 1672 return 617140; 1673 default: 1674 WARN(1, "Unknown cd freq selection\n"); 1675 } 1676 } else { 1677 /* vco 8100 */ 1678 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1679 case CDCLK_FREQ_450_432: 1680 return 450000; 1681 case CDCLK_FREQ_337_308: 1682 return 337500; 1683 case CDCLK_FREQ_675_617: 1684 return 675000; 1685 default: 1686 WARN(1, "Unknown cd freq selection\n"); 1687 } 1688 } 1689 1690 /* error case, do as if DPLL0 isn't enabled */ 1691 return 24000; 1692 } 1693 1694 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv) 1695 { 1696 uint32_t lcpll = I915_READ(LCPLL_CTL); 1697 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 1698 1699 if (lcpll & LCPLL_CD_SOURCE_FCLK) 1700 return 800000; 1701 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 1702 return 450000; 1703 else if (freq == LCPLL_CLK_FREQ_450) 1704 return 450000; 1705 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 1706 return 540000; 1707 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 1708 return 337500; 1709 else 1710 return 675000; 1711 } 1712 1713 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv) 1714 { 1715 struct drm_device *dev = dev_priv->dev; 1716 uint32_t lcpll = I915_READ(LCPLL_CTL); 1717 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 1718 1719 if (lcpll & LCPLL_CD_SOURCE_FCLK) 1720 return 800000; 1721 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 1722 return 450000; 1723 else if (freq == LCPLL_CLK_FREQ_450) 1724 return 450000; 1725 else if (IS_HSW_ULT(dev)) 1726 return 337500; 1727 else 1728 return 540000; 1729 } 1730 1731 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) 1732 { 1733 struct drm_device *dev = dev_priv->dev; 1734 1735 if (IS_SKYLAKE(dev)) 1736 return skl_get_cdclk_freq(dev_priv); 1737 1738 if (IS_BROADWELL(dev)) 1739 return bdw_get_cdclk_freq(dev_priv); 1740 1741 /* Haswell */ 1742 return hsw_get_cdclk_freq(dev_priv); 1743 } 1744 1745 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, 1746 struct intel_shared_dpll *pll) 1747 { 1748 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 1749 POSTING_READ(WRPLL_CTL(pll->id)); 1750 udelay(20); 1751 } 1752 1753 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, 1754 struct intel_shared_dpll *pll) 1755 { 1756 uint32_t val; 1757 1758 val = I915_READ(WRPLL_CTL(pll->id)); 1759 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 1760 POSTING_READ(WRPLL_CTL(pll->id)); 1761 } 1762 1763 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 1764 struct intel_shared_dpll *pll, 1765 struct intel_dpll_hw_state *hw_state) 1766 { 1767 uint32_t val; 1768 1769 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 1770 return false; 1771 1772 val = I915_READ(WRPLL_CTL(pll->id)); 1773 hw_state->wrpll = val; 1774 1775 return val & WRPLL_PLL_ENABLE; 1776 } 1777 1778 static const char * const hsw_ddi_pll_names[] = { 1779 "WRPLL 1", 1780 "WRPLL 2", 1781 }; 1782 1783 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) 1784 { 1785 int i; 1786 1787 dev_priv->num_shared_dpll = 2; 1788 1789 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 1790 dev_priv->shared_dplls[i].id = i; 1791 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 1792 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; 1793 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; 1794 dev_priv->shared_dplls[i].get_hw_state = 1795 hsw_ddi_pll_get_hw_state; 1796 } 1797 } 1798 1799 static const char * const skl_ddi_pll_names[] = { 1800 "DPLL 1", 1801 "DPLL 2", 1802 "DPLL 3", 1803 }; 1804 1805 struct skl_dpll_regs { 1806 u32 ctl, cfgcr1, cfgcr2; 1807 }; 1808 1809 /* this array is indexed by the *shared* pll id */ 1810 static const struct skl_dpll_regs skl_dpll_regs[3] = { 1811 { 1812 /* DPLL 1 */ 1813 .ctl = LCPLL2_CTL, 1814 .cfgcr1 = DPLL1_CFGCR1, 1815 .cfgcr2 = DPLL1_CFGCR2, 1816 }, 1817 { 1818 /* DPLL 2 */ 1819 .ctl = WRPLL_CTL1, 1820 .cfgcr1 = DPLL2_CFGCR1, 1821 .cfgcr2 = DPLL2_CFGCR2, 1822 }, 1823 { 1824 /* DPLL 3 */ 1825 .ctl = WRPLL_CTL2, 1826 .cfgcr1 = DPLL3_CFGCR1, 1827 .cfgcr2 = DPLL3_CFGCR2, 1828 }, 1829 }; 1830 1831 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 1832 struct intel_shared_dpll *pll) 1833 { 1834 uint32_t val; 1835 unsigned int dpll; 1836 const struct skl_dpll_regs *regs = skl_dpll_regs; 1837 1838 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 1839 dpll = pll->id + 1; 1840 1841 val = I915_READ(DPLL_CTRL1); 1842 1843 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | 1844 DPLL_CRTL1_LINK_RATE_MASK(dpll)); 1845 val |= pll->config.hw_state.ctrl1 << (dpll * 6); 1846 1847 I915_WRITE(DPLL_CTRL1, val); 1848 POSTING_READ(DPLL_CTRL1); 1849 1850 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 1851 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 1852 POSTING_READ(regs[pll->id].cfgcr1); 1853 POSTING_READ(regs[pll->id].cfgcr2); 1854 1855 /* the enable bit is always bit 31 */ 1856 I915_WRITE(regs[pll->id].ctl, 1857 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 1858 1859 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) 1860 DRM_ERROR("DPLL %d not locked\n", dpll); 1861 } 1862 1863 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 1864 struct intel_shared_dpll *pll) 1865 { 1866 const struct skl_dpll_regs *regs = skl_dpll_regs; 1867 1868 /* the enable bit is always bit 31 */ 1869 I915_WRITE(regs[pll->id].ctl, 1870 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 1871 POSTING_READ(regs[pll->id].ctl); 1872 } 1873 1874 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 1875 struct intel_shared_dpll *pll, 1876 struct intel_dpll_hw_state *hw_state) 1877 { 1878 uint32_t val; 1879 unsigned int dpll; 1880 const struct skl_dpll_regs *regs = skl_dpll_regs; 1881 1882 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 1883 return false; 1884 1885 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 1886 dpll = pll->id + 1; 1887 1888 val = I915_READ(regs[pll->id].ctl); 1889 if (!(val & LCPLL_PLL_ENABLE)) 1890 return false; 1891 1892 val = I915_READ(DPLL_CTRL1); 1893 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; 1894 1895 /* avoid reading back stale values if HDMI mode is not enabled */ 1896 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { 1897 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 1898 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 1899 } 1900 1901 return true; 1902 } 1903 1904 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) 1905 { 1906 int i; 1907 1908 dev_priv->num_shared_dpll = 3; 1909 1910 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 1911 dev_priv->shared_dplls[i].id = i; 1912 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; 1913 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; 1914 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; 1915 dev_priv->shared_dplls[i].get_hw_state = 1916 skl_ddi_pll_get_hw_state; 1917 } 1918 } 1919 1920 void intel_ddi_pll_init(struct drm_device *dev) 1921 { 1922 struct drm_i915_private *dev_priv = dev->dev_private; 1923 uint32_t val = I915_READ(LCPLL_CTL); 1924 1925 if (IS_SKYLAKE(dev)) 1926 skl_shared_dplls_init(dev_priv); 1927 else 1928 hsw_shared_dplls_init(dev_priv); 1929 1930 DRM_DEBUG_KMS("CDCLK running at %dKHz\n", 1931 intel_ddi_get_cdclk_freq(dev_priv)); 1932 1933 if (IS_SKYLAKE(dev)) { 1934 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) 1935 DRM_ERROR("LCPLL1 is disabled\n"); 1936 } else { 1937 /* 1938 * The LCPLL register should be turned on by the BIOS. For now 1939 * let's just check its state and print errors in case 1940 * something is wrong. Don't even try to turn it on. 1941 */ 1942 1943 if (val & LCPLL_CD_SOURCE_FCLK) 1944 DRM_ERROR("CDCLK source is not LCPLL\n"); 1945 1946 if (val & LCPLL_PLL_DISABLE) 1947 DRM_ERROR("LCPLL is disabled\n"); 1948 } 1949 } 1950 1951 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 1952 { 1953 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 1954 struct intel_dp *intel_dp = &intel_dig_port->dp; 1955 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1956 enum port port = intel_dig_port->port; 1957 uint32_t val; 1958 bool wait = false; 1959 1960 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 1961 val = I915_READ(DDI_BUF_CTL(port)); 1962 if (val & DDI_BUF_CTL_ENABLE) { 1963 val &= ~DDI_BUF_CTL_ENABLE; 1964 I915_WRITE(DDI_BUF_CTL(port), val); 1965 wait = true; 1966 } 1967 1968 val = I915_READ(DP_TP_CTL(port)); 1969 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1970 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1971 I915_WRITE(DP_TP_CTL(port), val); 1972 POSTING_READ(DP_TP_CTL(port)); 1973 1974 if (wait) 1975 intel_wait_ddi_buf_idle(dev_priv, port); 1976 } 1977 1978 val = DP_TP_CTL_ENABLE | 1979 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 1980 if (intel_dp->is_mst) 1981 val |= DP_TP_CTL_MODE_MST; 1982 else { 1983 val |= DP_TP_CTL_MODE_SST; 1984 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1985 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 1986 } 1987 I915_WRITE(DP_TP_CTL(port), val); 1988 POSTING_READ(DP_TP_CTL(port)); 1989 1990 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 1991 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 1992 POSTING_READ(DDI_BUF_CTL(port)); 1993 1994 udelay(600); 1995 } 1996 1997 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 1998 { 1999 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 2000 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2001 uint32_t val; 2002 2003 intel_ddi_post_disable(intel_encoder); 2004 2005 val = I915_READ(_FDI_RXA_CTL); 2006 val &= ~FDI_RX_ENABLE; 2007 I915_WRITE(_FDI_RXA_CTL, val); 2008 2009 val = I915_READ(_FDI_RXA_MISC); 2010 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 2011 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 2012 I915_WRITE(_FDI_RXA_MISC, val); 2013 2014 val = I915_READ(_FDI_RXA_CTL); 2015 val &= ~FDI_PCDCLK; 2016 I915_WRITE(_FDI_RXA_CTL, val); 2017 2018 val = I915_READ(_FDI_RXA_CTL); 2019 val &= ~FDI_RX_PLL_ENABLE; 2020 I915_WRITE(_FDI_RXA_CTL, val); 2021 } 2022 2023 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) 2024 { 2025 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base); 2026 int type = intel_dig_port->base.type; 2027 2028 if (type != INTEL_OUTPUT_DISPLAYPORT && 2029 type != INTEL_OUTPUT_EDP && 2030 type != INTEL_OUTPUT_UNKNOWN) { 2031 return; 2032 } 2033 2034 intel_dp_hot_plug(intel_encoder); 2035 } 2036 2037 void intel_ddi_get_config(struct intel_encoder *encoder, 2038 struct intel_crtc_state *pipe_config) 2039 { 2040 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 2041 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2042 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2043 struct intel_hdmi *intel_hdmi; 2044 u32 temp, flags = 0; 2045 2046 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2047 if (temp & TRANS_DDI_PHSYNC) 2048 flags |= DRM_MODE_FLAG_PHSYNC; 2049 else 2050 flags |= DRM_MODE_FLAG_NHSYNC; 2051 if (temp & TRANS_DDI_PVSYNC) 2052 flags |= DRM_MODE_FLAG_PVSYNC; 2053 else 2054 flags |= DRM_MODE_FLAG_NVSYNC; 2055 2056 pipe_config->base.adjusted_mode.flags |= flags; 2057 2058 switch (temp & TRANS_DDI_BPC_MASK) { 2059 case TRANS_DDI_BPC_6: 2060 pipe_config->pipe_bpp = 18; 2061 break; 2062 case TRANS_DDI_BPC_8: 2063 pipe_config->pipe_bpp = 24; 2064 break; 2065 case TRANS_DDI_BPC_10: 2066 pipe_config->pipe_bpp = 30; 2067 break; 2068 case TRANS_DDI_BPC_12: 2069 pipe_config->pipe_bpp = 36; 2070 break; 2071 default: 2072 break; 2073 } 2074 2075 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 2076 case TRANS_DDI_MODE_SELECT_HDMI: 2077 pipe_config->has_hdmi_sink = true; 2078 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 2079 2080 if (intel_hdmi->infoframe_enabled(&encoder->base)) 2081 pipe_config->has_infoframe = true; 2082 break; 2083 case TRANS_DDI_MODE_SELECT_DVI: 2084 case TRANS_DDI_MODE_SELECT_FDI: 2085 break; 2086 case TRANS_DDI_MODE_SELECT_DP_SST: 2087 case TRANS_DDI_MODE_SELECT_DP_MST: 2088 pipe_config->has_dp_encoder = true; 2089 intel_dp_get_m_n(intel_crtc, pipe_config); 2090 break; 2091 default: 2092 break; 2093 } 2094 2095 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 2096 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 2097 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 2098 pipe_config->has_audio = true; 2099 } 2100 2101 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && 2102 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 2103 /* 2104 * This is a big fat ugly hack. 2105 * 2106 * Some machines in UEFI boot mode provide us a VBT that has 18 2107 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 2108 * unknown we fail to light up. Yet the same BIOS boots up with 2109 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 2110 * max, not what it tells us to use. 2111 * 2112 * Note: This will still be broken if the eDP panel is not lit 2113 * up by the BIOS, and thus we can't get the mode at module 2114 * load. 2115 */ 2116 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 2117 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 2118 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 2119 } 2120 2121 intel_ddi_clock_get(encoder, pipe_config); 2122 } 2123 2124 static void intel_ddi_destroy(struct drm_encoder *encoder) 2125 { 2126 /* HDMI has nothing special to destroy, so we can go with this. */ 2127 intel_dp_encoder_destroy(encoder); 2128 } 2129 2130 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 2131 struct intel_crtc_state *pipe_config) 2132 { 2133 int type = encoder->type; 2134 int port = intel_ddi_get_encoder_port(encoder); 2135 2136 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 2137 2138 if (port == PORT_A) 2139 pipe_config->cpu_transcoder = TRANSCODER_EDP; 2140 2141 if (type == INTEL_OUTPUT_HDMI) 2142 return intel_hdmi_compute_config(encoder, pipe_config); 2143 else 2144 return intel_dp_compute_config(encoder, pipe_config); 2145 } 2146 2147 static const struct drm_encoder_funcs intel_ddi_funcs = { 2148 .destroy = intel_ddi_destroy, 2149 }; 2150 2151 static struct intel_connector * 2152 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 2153 { 2154 struct intel_connector *connector; 2155 enum port port = intel_dig_port->port; 2156 2157 connector = kzalloc(sizeof(*connector), GFP_KERNEL); 2158 if (!connector) 2159 return NULL; 2160 2161 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 2162 if (!intel_dp_init_connector(intel_dig_port, connector)) { 2163 kfree(connector); 2164 return NULL; 2165 } 2166 2167 return connector; 2168 } 2169 2170 static struct intel_connector * 2171 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 2172 { 2173 struct intel_connector *connector; 2174 enum port port = intel_dig_port->port; 2175 2176 connector = kzalloc(sizeof(*connector), GFP_KERNEL); 2177 if (!connector) 2178 return NULL; 2179 2180 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 2181 intel_hdmi_init_connector(intel_dig_port, connector); 2182 2183 return connector; 2184 } 2185 2186 void intel_ddi_init(struct drm_device *dev, enum port port) 2187 { 2188 struct drm_i915_private *dev_priv = dev->dev_private; 2189 struct intel_digital_port *intel_dig_port; 2190 struct intel_encoder *intel_encoder; 2191 struct drm_encoder *encoder; 2192 bool init_hdmi, init_dp; 2193 2194 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 2195 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 2196 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 2197 if (!init_dp && !init_hdmi) { 2198 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", 2199 port_name(port)); 2200 init_hdmi = true; 2201 init_dp = true; 2202 } 2203 2204 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2205 if (!intel_dig_port) 2206 return; 2207 2208 intel_encoder = &intel_dig_port->base; 2209 encoder = &intel_encoder->base; 2210 2211 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 2212 DRM_MODE_ENCODER_TMDS); 2213 2214 intel_encoder->compute_config = intel_ddi_compute_config; 2215 intel_encoder->enable = intel_enable_ddi; 2216 intel_encoder->pre_enable = intel_ddi_pre_enable; 2217 intel_encoder->disable = intel_disable_ddi; 2218 intel_encoder->post_disable = intel_ddi_post_disable; 2219 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 2220 intel_encoder->get_config = intel_ddi_get_config; 2221 2222 intel_dig_port->port = port; 2223 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 2224 (DDI_BUF_PORT_REVERSAL | 2225 DDI_A_4_LANES); 2226 2227 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 2228 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2229 intel_encoder->cloneable = 0; 2230 intel_encoder->hot_plug = intel_ddi_hot_plug; 2231 2232 if (init_dp) { 2233 if (!intel_ddi_init_dp_connector(intel_dig_port)) 2234 goto err; 2235 2236 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 2237 dev_priv->hpd_irq_port[port] = intel_dig_port; 2238 } 2239 2240 /* In theory we don't need the encoder->type check, but leave it just in 2241 * case we have some really bad VBTs... */ 2242 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 2243 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 2244 goto err; 2245 } 2246 2247 return; 2248 2249 err: 2250 drm_encoder_cleanup(encoder); 2251 kfree(intel_dig_port); 2252 } 2253