1 /* 2 * Copyright © 2006-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "intel_drv.h" 25 #include <asm/int-ll64.h> 26 27 struct intel_shared_dpll * 28 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, 29 enum intel_dpll_id id) 30 { 31 return &dev_priv->shared_dplls[id]; 32 } 33 34 enum intel_dpll_id 35 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, 36 struct intel_shared_dpll *pll) 37 { 38 if (WARN_ON(pll < dev_priv->shared_dplls|| 39 pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) 40 return -1; 41 42 return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); 43 } 44 45 void 46 intel_shared_dpll_config_get(struct intel_shared_dpll_config *config, 47 struct intel_shared_dpll *pll, 48 struct intel_crtc *crtc) 49 { 50 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 51 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll); 52 53 config[id].crtc_mask |= 1 << crtc->pipe; 54 } 55 56 void 57 intel_shared_dpll_config_put(struct intel_shared_dpll_config *config, 58 struct intel_shared_dpll *pll, 59 struct intel_crtc *crtc) 60 { 61 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 62 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll); 63 64 config[id].crtc_mask &= ~(1 << crtc->pipe); 65 } 66 67 /* For ILK+ */ 68 void assert_shared_dpll(struct drm_i915_private *dev_priv, 69 struct intel_shared_dpll *pll, 70 bool state) 71 { 72 bool cur_state; 73 struct intel_dpll_hw_state hw_state; 74 75 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) 76 return; 77 78 cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state); 79 I915_STATE_WARN(cur_state != state, 80 "%s assertion failure (expected %s, current %s)\n", 81 pll->name, onoff(state), onoff(cur_state)); 82 } 83 84 void intel_prepare_shared_dpll(struct intel_crtc *crtc) 85 { 86 struct drm_device *dev = crtc->base.dev; 87 struct drm_i915_private *dev_priv = to_i915(dev); 88 struct intel_shared_dpll *pll = crtc->config->shared_dpll; 89 90 if (WARN_ON(pll == NULL)) 91 return; 92 93 mutex_lock(&dev_priv->dpll_lock); 94 WARN_ON(!pll->config.crtc_mask); 95 if (!pll->active_mask) { 96 DRM_DEBUG_DRIVER("setting up %s\n", pll->name); 97 WARN_ON(pll->on); 98 assert_shared_dpll_disabled(dev_priv, pll); 99 100 pll->funcs.mode_set(dev_priv, pll); 101 } 102 mutex_unlock(&dev_priv->dpll_lock); 103 } 104 105 /** 106 * intel_enable_shared_dpll - enable PCH PLL 107 * @dev_priv: i915 private structure 108 * @pipe: pipe PLL to enable 109 * 110 * The PCH PLL needs to be enabled before the PCH transcoder, since it 111 * drives the transcoder clock. 112 */ 113 void intel_enable_shared_dpll(struct intel_crtc *crtc) 114 { 115 struct drm_device *dev = crtc->base.dev; 116 struct drm_i915_private *dev_priv = to_i915(dev); 117 struct intel_shared_dpll *pll = crtc->config->shared_dpll; 118 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); 119 unsigned old_mask; 120 121 if (WARN_ON(pll == NULL)) 122 return; 123 124 mutex_lock(&dev_priv->dpll_lock); 125 old_mask = pll->active_mask; 126 127 if (WARN_ON(!(pll->config.crtc_mask & crtc_mask)) || 128 WARN_ON(pll->active_mask & crtc_mask)) 129 goto out; 130 131 pll->active_mask |= crtc_mask; 132 133 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n", 134 pll->name, pll->active_mask, pll->on, 135 crtc->base.base.id); 136 137 if (old_mask) { 138 WARN_ON(!pll->on); 139 assert_shared_dpll_enabled(dev_priv, pll); 140 goto out; 141 } 142 WARN_ON(pll->on); 143 144 DRM_DEBUG_KMS("enabling %s\n", pll->name); 145 pll->funcs.enable(dev_priv, pll); 146 pll->on = true; 147 148 out: 149 mutex_unlock(&dev_priv->dpll_lock); 150 } 151 152 void intel_disable_shared_dpll(struct intel_crtc *crtc) 153 { 154 struct drm_device *dev = crtc->base.dev; 155 struct drm_i915_private *dev_priv = to_i915(dev); 156 struct intel_shared_dpll *pll = crtc->config->shared_dpll; 157 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); 158 159 /* PCH only available on ILK+ */ 160 if (INTEL_INFO(dev)->gen < 5) 161 return; 162 163 if (pll == NULL) 164 return; 165 166 mutex_lock(&dev_priv->dpll_lock); 167 if (WARN_ON(!(pll->active_mask & crtc_mask))) 168 goto out; 169 170 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n", 171 pll->name, pll->active_mask, pll->on, 172 crtc->base.base.id); 173 174 assert_shared_dpll_enabled(dev_priv, pll); 175 WARN_ON(!pll->on); 176 177 pll->active_mask &= ~crtc_mask; 178 if (pll->active_mask) 179 goto out; 180 181 DRM_DEBUG_KMS("disabling %s\n", pll->name); 182 pll->funcs.disable(dev_priv, pll); 183 pll->on = false; 184 185 out: 186 mutex_unlock(&dev_priv->dpll_lock); 187 } 188 189 static struct intel_shared_dpll * 190 intel_find_shared_dpll(struct intel_crtc *crtc, 191 struct intel_crtc_state *crtc_state, 192 enum intel_dpll_id range_min, 193 enum intel_dpll_id range_max) 194 { 195 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 196 struct intel_shared_dpll *pll; 197 struct intel_shared_dpll_config *shared_dpll; 198 enum intel_dpll_id i; 199 200 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); 201 202 for (i = range_min; i <= range_max; i++) { 203 pll = &dev_priv->shared_dplls[i]; 204 205 /* Only want to check enabled timings first */ 206 if (shared_dpll[i].crtc_mask == 0) 207 continue; 208 209 if (memcmp(&crtc_state->dpll_hw_state, 210 &shared_dpll[i].hw_state, 211 sizeof(crtc_state->dpll_hw_state)) == 0) { 212 DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n", 213 crtc->base.base.id, crtc->base.name, pll->name, 214 shared_dpll[i].crtc_mask, 215 pll->active_mask); 216 return pll; 217 } 218 } 219 220 /* Ok no matching timings, maybe there's a free one? */ 221 for (i = range_min; i <= range_max; i++) { 222 pll = &dev_priv->shared_dplls[i]; 223 if (shared_dpll[i].crtc_mask == 0) { 224 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n", 225 crtc->base.base.id, crtc->base.name, pll->name); 226 return pll; 227 } 228 } 229 230 return NULL; 231 } 232 233 static void 234 intel_reference_shared_dpll(struct intel_shared_dpll *pll, 235 struct intel_crtc_state *crtc_state) 236 { 237 struct intel_shared_dpll_config *shared_dpll; 238 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 239 enum intel_dpll_id i = pll->id; 240 241 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); 242 243 if (shared_dpll[i].crtc_mask == 0) 244 shared_dpll[i].hw_state = 245 crtc_state->dpll_hw_state; 246 247 crtc_state->shared_dpll = pll; 248 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, 249 pipe_name(crtc->pipe)); 250 251 intel_shared_dpll_config_get(shared_dpll, pll, crtc); 252 } 253 254 void intel_shared_dpll_commit(struct drm_atomic_state *state) 255 { 256 struct drm_i915_private *dev_priv = to_i915(state->dev); 257 struct intel_shared_dpll_config *shared_dpll; 258 struct intel_shared_dpll *pll; 259 enum intel_dpll_id i; 260 261 if (!to_intel_atomic_state(state)->dpll_set) 262 return; 263 264 shared_dpll = to_intel_atomic_state(state)->shared_dpll; 265 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 266 pll = &dev_priv->shared_dplls[i]; 267 pll->config = shared_dpll[i]; 268 } 269 } 270 271 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, 272 struct intel_shared_dpll *pll, 273 struct intel_dpll_hw_state *hw_state) 274 { 275 uint32_t val; 276 277 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 278 return false; 279 280 val = I915_READ(PCH_DPLL(pll->id)); 281 hw_state->dpll = val; 282 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); 283 hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); 284 285 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 286 287 return val & DPLL_VCO_ENABLE; 288 } 289 290 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, 291 struct intel_shared_dpll *pll) 292 { 293 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); 294 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); 295 } 296 297 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 298 { 299 u32 val; 300 bool enabled; 301 302 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 303 304 val = I915_READ(PCH_DREF_CONTROL); 305 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 306 DREF_SUPERSPREAD_SOURCE_MASK)); 307 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); 308 } 309 310 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, 311 struct intel_shared_dpll *pll) 312 { 313 /* PCH refclock must be enabled first */ 314 ibx_assert_pch_refclk_enabled(dev_priv); 315 316 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); 317 318 /* Wait for the clocks to stabilize. */ 319 POSTING_READ(PCH_DPLL(pll->id)); 320 udelay(150); 321 322 /* The pixel multiplier can only be updated once the 323 * DPLL is enabled and the clocks are stable. 324 * 325 * So write it again. 326 */ 327 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); 328 POSTING_READ(PCH_DPLL(pll->id)); 329 udelay(200); 330 } 331 332 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, 333 struct intel_shared_dpll *pll) 334 { 335 struct drm_device *dev = &dev_priv->drm; 336 struct intel_crtc *crtc; 337 338 /* Make sure no transcoder isn't still depending on us. */ 339 for_each_intel_crtc(dev, crtc) { 340 if (crtc->config->shared_dpll == pll) 341 assert_pch_transcoder_disabled(dev_priv, crtc->pipe); 342 } 343 344 I915_WRITE(PCH_DPLL(pll->id), 0); 345 POSTING_READ(PCH_DPLL(pll->id)); 346 udelay(200); 347 } 348 349 static struct intel_shared_dpll * 350 ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 351 struct intel_encoder *encoder) 352 { 353 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 354 struct intel_shared_dpll *pll; 355 enum intel_dpll_id i; 356 357 if (HAS_PCH_IBX(dev_priv)) { 358 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ 359 i = (enum intel_dpll_id) crtc->pipe; 360 pll = &dev_priv->shared_dplls[i]; 361 362 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", 363 crtc->base.base.id, crtc->base.name, pll->name); 364 } else { 365 pll = intel_find_shared_dpll(crtc, crtc_state, 366 DPLL_ID_PCH_PLL_A, 367 DPLL_ID_PCH_PLL_B); 368 } 369 370 if (!pll) 371 return NULL; 372 373 /* reference the pll */ 374 intel_reference_shared_dpll(pll, crtc_state); 375 376 return pll; 377 } 378 379 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { 380 .mode_set = ibx_pch_dpll_mode_set, 381 .enable = ibx_pch_dpll_enable, 382 .disable = ibx_pch_dpll_disable, 383 .get_hw_state = ibx_pch_dpll_get_hw_state, 384 }; 385 386 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, 387 struct intel_shared_dpll *pll) 388 { 389 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 390 POSTING_READ(WRPLL_CTL(pll->id)); 391 udelay(20); 392 } 393 394 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, 395 struct intel_shared_dpll *pll) 396 { 397 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); 398 POSTING_READ(SPLL_CTL); 399 udelay(20); 400 } 401 402 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, 403 struct intel_shared_dpll *pll) 404 { 405 uint32_t val; 406 407 val = I915_READ(WRPLL_CTL(pll->id)); 408 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 409 POSTING_READ(WRPLL_CTL(pll->id)); 410 } 411 412 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, 413 struct intel_shared_dpll *pll) 414 { 415 uint32_t val; 416 417 val = I915_READ(SPLL_CTL); 418 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 419 POSTING_READ(SPLL_CTL); 420 } 421 422 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, 423 struct intel_shared_dpll *pll, 424 struct intel_dpll_hw_state *hw_state) 425 { 426 uint32_t val; 427 428 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 429 return false; 430 431 val = I915_READ(WRPLL_CTL(pll->id)); 432 hw_state->wrpll = val; 433 434 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 435 436 return val & WRPLL_PLL_ENABLE; 437 } 438 439 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, 440 struct intel_shared_dpll *pll, 441 struct intel_dpll_hw_state *hw_state) 442 { 443 uint32_t val; 444 445 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 446 return false; 447 448 val = I915_READ(SPLL_CTL); 449 hw_state->spll = val; 450 451 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 452 453 return val & SPLL_PLL_ENABLE; 454 } 455 456 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll) 457 { 458 switch (pll->id) { 459 case DPLL_ID_WRPLL1: 460 return PORT_CLK_SEL_WRPLL1; 461 case DPLL_ID_WRPLL2: 462 return PORT_CLK_SEL_WRPLL2; 463 case DPLL_ID_SPLL: 464 return PORT_CLK_SEL_SPLL; 465 case DPLL_ID_LCPLL_810: 466 return PORT_CLK_SEL_LCPLL_810; 467 case DPLL_ID_LCPLL_1350: 468 return PORT_CLK_SEL_LCPLL_1350; 469 case DPLL_ID_LCPLL_2700: 470 return PORT_CLK_SEL_LCPLL_2700; 471 default: 472 return PORT_CLK_SEL_NONE; 473 } 474 } 475 476 #define LC_FREQ 2700 477 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 478 479 #define P_MIN 2 480 #define P_MAX 64 481 #define P_INC 2 482 483 /* Constraints for PLL good behavior */ 484 #define REF_MIN 48 485 #define REF_MAX 400 486 #define VCO_MIN 2400 487 #define VCO_MAX 4800 488 489 struct hsw_wrpll_rnp { 490 unsigned p, n2, r2; 491 }; 492 493 static unsigned hsw_wrpll_get_budget_for_freq(int clock) 494 { 495 unsigned budget; 496 497 switch (clock) { 498 case 25175000: 499 case 25200000: 500 case 27000000: 501 case 27027000: 502 case 37762500: 503 case 37800000: 504 case 40500000: 505 case 40541000: 506 case 54000000: 507 case 54054000: 508 case 59341000: 509 case 59400000: 510 case 72000000: 511 case 74176000: 512 case 74250000: 513 case 81000000: 514 case 81081000: 515 case 89012000: 516 case 89100000: 517 case 108000000: 518 case 108108000: 519 case 111264000: 520 case 111375000: 521 case 148352000: 522 case 148500000: 523 case 162000000: 524 case 162162000: 525 case 222525000: 526 case 222750000: 527 case 296703000: 528 case 297000000: 529 budget = 0; 530 break; 531 case 233500000: 532 case 245250000: 533 case 247750000: 534 case 253250000: 535 case 298000000: 536 budget = 1500; 537 break; 538 case 169128000: 539 case 169500000: 540 case 179500000: 541 case 202000000: 542 budget = 2000; 543 break; 544 case 256250000: 545 case 262500000: 546 case 270000000: 547 case 272500000: 548 case 273750000: 549 case 280750000: 550 case 281250000: 551 case 286000000: 552 case 291750000: 553 budget = 4000; 554 break; 555 case 267250000: 556 case 268500000: 557 budget = 5000; 558 break; 559 default: 560 budget = 1000; 561 break; 562 } 563 564 return budget; 565 } 566 567 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, 568 unsigned r2, unsigned n2, unsigned p, 569 struct hsw_wrpll_rnp *best) 570 { 571 uint64_t a, b, c, d, diff, diff_best; 572 573 /* No best (r,n,p) yet */ 574 if (best->p == 0) { 575 best->p = p; 576 best->n2 = n2; 577 best->r2 = r2; 578 return; 579 } 580 581 /* 582 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 583 * freq2k. 584 * 585 * delta = 1e6 * 586 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 587 * freq2k; 588 * 589 * and we would like delta <= budget. 590 * 591 * If the discrepancy is above the PPM-based budget, always prefer to 592 * improve upon the previous solution. However, if you're within the 593 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 594 */ 595 a = freq2k * budget * p * r2; 596 b = freq2k * budget * best->p * best->r2; 597 diff = abs_diff((u64)freq2k * p * r2, LC_FREQ_2K * n2); 598 diff_best = abs_diff((u64)freq2k * best->p * best->r2, 599 LC_FREQ_2K * best->n2); 600 c = 1000000 * diff; 601 d = 1000000 * diff_best; 602 603 if (a < c && b < d) { 604 /* If both are above the budget, pick the closer */ 605 if (best->p * best->r2 * diff < p * r2 * diff_best) { 606 best->p = p; 607 best->n2 = n2; 608 best->r2 = r2; 609 } 610 } else if (a >= c && b < d) { 611 /* If A is below the threshold but B is above it? Update. */ 612 best->p = p; 613 best->n2 = n2; 614 best->r2 = r2; 615 } else if (a >= c && b >= d) { 616 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 617 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 618 best->p = p; 619 best->n2 = n2; 620 best->r2 = r2; 621 } 622 } 623 /* Otherwise a < c && b >= d, do nothing */ 624 } 625 626 static void 627 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 628 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 629 { 630 uint64_t freq2k; 631 unsigned p, n2, r2; 632 struct hsw_wrpll_rnp best = { 0, 0, 0 }; 633 unsigned budget; 634 635 freq2k = clock / 100; 636 637 budget = hsw_wrpll_get_budget_for_freq(clock); 638 639 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 640 * and directly pass the LC PLL to it. */ 641 if (freq2k == 5400000) { 642 *n2_out = 2; 643 *p_out = 1; 644 *r2_out = 2; 645 return; 646 } 647 648 /* 649 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 650 * the WR PLL. 651 * 652 * We want R so that REF_MIN <= Ref <= REF_MAX. 653 * Injecting R2 = 2 * R gives: 654 * REF_MAX * r2 > LC_FREQ * 2 and 655 * REF_MIN * r2 < LC_FREQ * 2 656 * 657 * Which means the desired boundaries for r2 are: 658 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 659 * 660 */ 661 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 662 r2 <= LC_FREQ * 2 / REF_MIN; 663 r2++) { 664 665 /* 666 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 667 * 668 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 669 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 670 * VCO_MAX * r2 > n2 * LC_FREQ and 671 * VCO_MIN * r2 < n2 * LC_FREQ) 672 * 673 * Which means the desired boundaries for n2 are: 674 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 675 */ 676 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 677 n2 <= VCO_MAX * r2 / LC_FREQ; 678 n2++) { 679 680 for (p = P_MIN; p <= P_MAX; p += P_INC) 681 hsw_wrpll_update_rnp(freq2k, budget, 682 r2, n2, p, &best); 683 } 684 } 685 686 *n2_out = best.n2; 687 *p_out = best.p; 688 *r2_out = best.r2; 689 } 690 691 static struct intel_shared_dpll * 692 hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 693 struct intel_encoder *encoder) 694 { 695 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 696 struct intel_shared_dpll *pll; 697 int clock = crtc_state->port_clock; 698 699 memset(&crtc_state->dpll_hw_state, 0, 700 sizeof(crtc_state->dpll_hw_state)); 701 702 if (encoder->type == INTEL_OUTPUT_HDMI) { 703 uint32_t val; 704 unsigned p, n2, r2; 705 706 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 707 708 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 709 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 710 WRPLL_DIVIDER_POST(p); 711 712 crtc_state->dpll_hw_state.wrpll = val; 713 714 pll = intel_find_shared_dpll(crtc, crtc_state, 715 DPLL_ID_WRPLL1, DPLL_ID_WRPLL2); 716 717 } else if (encoder->type == INTEL_OUTPUT_DP || 718 encoder->type == INTEL_OUTPUT_DP_MST || 719 encoder->type == INTEL_OUTPUT_EDP) { 720 enum intel_dpll_id pll_id; 721 722 switch (clock / 2) { 723 case 81000: 724 pll_id = DPLL_ID_LCPLL_810; 725 break; 726 case 135000: 727 pll_id = DPLL_ID_LCPLL_1350; 728 break; 729 case 270000: 730 pll_id = DPLL_ID_LCPLL_2700; 731 break; 732 default: 733 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); 734 return NULL; 735 } 736 737 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); 738 739 } else if (encoder->type == INTEL_OUTPUT_ANALOG) { 740 if (WARN_ON(crtc_state->port_clock / 2 != 135000)) 741 return NULL; 742 743 crtc_state->dpll_hw_state.spll = 744 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; 745 746 pll = intel_find_shared_dpll(crtc, crtc_state, 747 DPLL_ID_SPLL, DPLL_ID_SPLL); 748 } else { 749 return NULL; 750 } 751 752 if (!pll) 753 return NULL; 754 755 crtc_state->ddi_pll_sel = hsw_pll_to_ddi_pll_sel(pll); 756 757 intel_reference_shared_dpll(pll, crtc_state); 758 759 return pll; 760 } 761 762 763 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { 764 .enable = hsw_ddi_wrpll_enable, 765 .disable = hsw_ddi_wrpll_disable, 766 .get_hw_state = hsw_ddi_wrpll_get_hw_state, 767 }; 768 769 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { 770 .enable = hsw_ddi_spll_enable, 771 .disable = hsw_ddi_spll_disable, 772 .get_hw_state = hsw_ddi_spll_get_hw_state, 773 }; 774 775 static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv, 776 struct intel_shared_dpll *pll) 777 { 778 } 779 780 static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv, 781 struct intel_shared_dpll *pll) 782 { 783 } 784 785 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv, 786 struct intel_shared_dpll *pll, 787 struct intel_dpll_hw_state *hw_state) 788 { 789 return true; 790 } 791 792 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = { 793 .enable = hsw_ddi_lcpll_enable, 794 .disable = hsw_ddi_lcpll_disable, 795 .get_hw_state = hsw_ddi_lcpll_get_hw_state, 796 }; 797 798 struct skl_dpll_regs { 799 i915_reg_t ctl, cfgcr1, cfgcr2; 800 }; 801 802 /* this array is indexed by the *shared* pll id */ 803 static const struct skl_dpll_regs skl_dpll_regs[4] = { 804 { 805 /* DPLL 0 */ 806 .ctl = LCPLL1_CTL, 807 /* DPLL 0 doesn't support HDMI mode */ 808 }, 809 { 810 /* DPLL 1 */ 811 .ctl = LCPLL2_CTL, 812 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), 813 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), 814 }, 815 { 816 /* DPLL 2 */ 817 .ctl = WRPLL_CTL(0), 818 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), 819 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), 820 }, 821 { 822 /* DPLL 3 */ 823 .ctl = WRPLL_CTL(1), 824 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), 825 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), 826 }, 827 }; 828 829 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv, 830 struct intel_shared_dpll *pll) 831 { 832 uint32_t val; 833 834 val = I915_READ(DPLL_CTRL1); 835 836 val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) | 837 DPLL_CTRL1_LINK_RATE_MASK(pll->id)); 838 val |= pll->config.hw_state.ctrl1 << (pll->id * 6); 839 840 I915_WRITE(DPLL_CTRL1, val); 841 POSTING_READ(DPLL_CTRL1); 842 } 843 844 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 845 struct intel_shared_dpll *pll) 846 { 847 const struct skl_dpll_regs *regs = skl_dpll_regs; 848 849 skl_ddi_pll_write_ctrl1(dev_priv, pll); 850 851 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 852 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 853 POSTING_READ(regs[pll->id].cfgcr1); 854 POSTING_READ(regs[pll->id].cfgcr2); 855 856 /* the enable bit is always bit 31 */ 857 I915_WRITE(regs[pll->id].ctl, 858 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 859 860 if (intel_wait_for_register(dev_priv, 861 DPLL_STATUS, 862 DPLL_LOCK(pll->id), 863 DPLL_LOCK(pll->id), 864 5)) 865 DRM_ERROR("DPLL %d not locked\n", pll->id); 866 } 867 868 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv, 869 struct intel_shared_dpll *pll) 870 { 871 skl_ddi_pll_write_ctrl1(dev_priv, pll); 872 } 873 874 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 875 struct intel_shared_dpll *pll) 876 { 877 const struct skl_dpll_regs *regs = skl_dpll_regs; 878 879 /* the enable bit is always bit 31 */ 880 I915_WRITE(regs[pll->id].ctl, 881 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 882 POSTING_READ(regs[pll->id].ctl); 883 } 884 885 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv, 886 struct intel_shared_dpll *pll) 887 { 888 } 889 890 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 891 struct intel_shared_dpll *pll, 892 struct intel_dpll_hw_state *hw_state) 893 { 894 uint32_t val; 895 const struct skl_dpll_regs *regs = skl_dpll_regs; 896 bool ret; 897 898 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 899 return false; 900 901 ret = false; 902 903 val = I915_READ(regs[pll->id].ctl); 904 if (!(val & LCPLL_PLL_ENABLE)) 905 goto out; 906 907 val = I915_READ(DPLL_CTRL1); 908 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f; 909 910 /* avoid reading back stale values if HDMI mode is not enabled */ 911 if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) { 912 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 913 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 914 } 915 ret = true; 916 917 out: 918 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 919 920 return ret; 921 } 922 923 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, 924 struct intel_shared_dpll *pll, 925 struct intel_dpll_hw_state *hw_state) 926 { 927 uint32_t val; 928 const struct skl_dpll_regs *regs = skl_dpll_regs; 929 bool ret; 930 931 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 932 return false; 933 934 ret = false; 935 936 /* DPLL0 is always enabled since it drives CDCLK */ 937 val = I915_READ(regs[pll->id].ctl); 938 if (WARN_ON(!(val & LCPLL_PLL_ENABLE))) 939 goto out; 940 941 val = I915_READ(DPLL_CTRL1); 942 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f; 943 944 ret = true; 945 946 out: 947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 948 949 return ret; 950 } 951 952 struct skl_wrpll_context { 953 uint64_t min_deviation; /* current minimal deviation */ 954 uint64_t central_freq; /* chosen central freq */ 955 uint64_t dco_freq; /* chosen dco freq */ 956 unsigned int p; /* chosen divider */ 957 }; 958 959 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) 960 { 961 memset(ctx, 0, sizeof(*ctx)); 962 963 ctx->min_deviation = U64_MAX; 964 } 965 966 /* DCO freq must be within +1%/-6% of the DCO central freq */ 967 #define SKL_DCO_MAX_PDEVIATION 100 968 #define SKL_DCO_MAX_NDEVIATION 600 969 970 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, 971 uint64_t central_freq, 972 uint64_t dco_freq, 973 unsigned int divider) 974 { 975 uint64_t deviation; 976 977 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), 978 central_freq); 979 980 /* positive deviation */ 981 if (dco_freq >= central_freq) { 982 if (deviation < SKL_DCO_MAX_PDEVIATION && 983 deviation < ctx->min_deviation) { 984 ctx->min_deviation = deviation; 985 ctx->central_freq = central_freq; 986 ctx->dco_freq = dco_freq; 987 ctx->p = divider; 988 } 989 /* negative deviation */ 990 } else if (deviation < SKL_DCO_MAX_NDEVIATION && 991 deviation < ctx->min_deviation) { 992 ctx->min_deviation = deviation; 993 ctx->central_freq = central_freq; 994 ctx->dco_freq = dco_freq; 995 ctx->p = divider; 996 } 997 } 998 999 static void skl_wrpll_get_multipliers(unsigned int p, 1000 unsigned int *p0 /* out */, 1001 unsigned int *p1 /* out */, 1002 unsigned int *p2 /* out */) 1003 { 1004 /* even dividers */ 1005 if (p % 2 == 0) { 1006 unsigned int half = p / 2; 1007 1008 if (half == 1 || half == 2 || half == 3 || half == 5) { 1009 *p0 = 2; 1010 *p1 = 1; 1011 *p2 = half; 1012 } else if (half % 2 == 0) { 1013 *p0 = 2; 1014 *p1 = half / 2; 1015 *p2 = 2; 1016 } else if (half % 3 == 0) { 1017 *p0 = 3; 1018 *p1 = half / 3; 1019 *p2 = 2; 1020 } else if (half % 7 == 0) { 1021 *p0 = 7; 1022 *p1 = half / 7; 1023 *p2 = 2; 1024 } 1025 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ 1026 *p0 = 3; 1027 *p1 = 1; 1028 *p2 = p / 3; 1029 } else if (p == 5 || p == 7) { 1030 *p0 = p; 1031 *p1 = 1; 1032 *p2 = 1; 1033 } else if (p == 15) { 1034 *p0 = 3; 1035 *p1 = 1; 1036 *p2 = 5; 1037 } else if (p == 21) { 1038 *p0 = 7; 1039 *p1 = 1; 1040 *p2 = 3; 1041 } else if (p == 35) { 1042 *p0 = 7; 1043 *p1 = 1; 1044 *p2 = 5; 1045 } 1046 } 1047 1048 struct skl_wrpll_params { 1049 uint32_t dco_fraction; 1050 uint32_t dco_integer; 1051 uint32_t qdiv_ratio; 1052 uint32_t qdiv_mode; 1053 uint32_t kdiv; 1054 uint32_t pdiv; 1055 uint32_t central_freq; 1056 }; 1057 1058 static void skl_wrpll_params_populate(struct skl_wrpll_params *params, 1059 uint64_t afe_clock, 1060 uint64_t central_freq, 1061 uint32_t p0, uint32_t p1, uint32_t p2) 1062 { 1063 uint64_t dco_freq; 1064 1065 switch (central_freq) { 1066 case 9600000000ULL: 1067 params->central_freq = 0; 1068 break; 1069 case 9000000000ULL: 1070 params->central_freq = 1; 1071 break; 1072 case 8400000000ULL: 1073 params->central_freq = 3; 1074 } 1075 1076 switch (p0) { 1077 case 1: 1078 params->pdiv = 0; 1079 break; 1080 case 2: 1081 params->pdiv = 1; 1082 break; 1083 case 3: 1084 params->pdiv = 2; 1085 break; 1086 case 7: 1087 params->pdiv = 4; 1088 break; 1089 default: 1090 WARN(1, "Incorrect PDiv\n"); 1091 } 1092 1093 switch (p2) { 1094 case 5: 1095 params->kdiv = 0; 1096 break; 1097 case 2: 1098 params->kdiv = 1; 1099 break; 1100 case 3: 1101 params->kdiv = 2; 1102 break; 1103 case 1: 1104 params->kdiv = 3; 1105 break; 1106 default: 1107 WARN(1, "Incorrect KDiv\n"); 1108 } 1109 1110 params->qdiv_ratio = p1; 1111 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; 1112 1113 dco_freq = p0 * p1 * p2 * afe_clock; 1114 1115 /* 1116 * Intermediate values are in Hz. 1117 * Divide by MHz to match bsepc 1118 */ 1119 params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); 1120 params->dco_fraction = 1121 div_u64((div_u64(dco_freq, 24) - 1122 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); 1123 } 1124 1125 static bool 1126 skl_ddi_calculate_wrpll(int clock /* in Hz */, 1127 struct skl_wrpll_params *wrpll_params) 1128 { 1129 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 1130 uint64_t dco_central_freq[3] = {8400000000ULL, 1131 9000000000ULL, 1132 9600000000ULL}; 1133 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, 1134 24, 28, 30, 32, 36, 40, 42, 44, 1135 48, 52, 54, 56, 60, 64, 66, 68, 1136 70, 72, 76, 78, 80, 84, 88, 90, 1137 92, 96, 98 }; 1138 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; 1139 static const struct { 1140 const int *list; 1141 int n_dividers; 1142 } dividers[] = { 1143 { even_dividers, ARRAY_SIZE(even_dividers) }, 1144 { odd_dividers, ARRAY_SIZE(odd_dividers) }, 1145 }; 1146 struct skl_wrpll_context ctx; 1147 unsigned int dco, d, i; 1148 unsigned int p0, p1, p2; 1149 1150 skl_wrpll_context_init(&ctx); 1151 1152 for (d = 0; d < ARRAY_SIZE(dividers); d++) { 1153 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { 1154 for (i = 0; i < dividers[d].n_dividers; i++) { 1155 unsigned int p = dividers[d].list[i]; 1156 uint64_t dco_freq = p * afe_clock; 1157 1158 skl_wrpll_try_divider(&ctx, 1159 dco_central_freq[dco], 1160 dco_freq, 1161 p); 1162 /* 1163 * Skip the remaining dividers if we're sure to 1164 * have found the definitive divider, we can't 1165 * improve a 0 deviation. 1166 */ 1167 if (ctx.min_deviation == 0) 1168 goto skip_remaining_dividers; 1169 } 1170 } 1171 1172 skip_remaining_dividers: 1173 /* 1174 * If a solution is found with an even divider, prefer 1175 * this one. 1176 */ 1177 if (d == 0 && ctx.p) 1178 break; 1179 } 1180 1181 if (!ctx.p) { 1182 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); 1183 return false; 1184 } 1185 1186 /* 1187 * gcc incorrectly analyses that these can be used without being 1188 * initialized. To be fair, it's hard to guess. 1189 */ 1190 p0 = p1 = p2 = 0; 1191 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); 1192 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, 1193 p0, p1, p2); 1194 1195 return true; 1196 } 1197 1198 static struct intel_shared_dpll * 1199 skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 1200 struct intel_encoder *encoder) 1201 { 1202 struct intel_shared_dpll *pll; 1203 uint32_t ctrl1, cfgcr1, cfgcr2; 1204 int clock = crtc_state->port_clock; 1205 1206 /* 1207 * See comment in intel_dpll_hw_state to understand why we always use 0 1208 * as the DPLL id in this function. 1209 */ 1210 1211 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1212 1213 if (encoder->type == INTEL_OUTPUT_HDMI) { 1214 struct skl_wrpll_params wrpll_params = { 0, }; 1215 1216 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1217 1218 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) 1219 return NULL; 1220 1221 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1222 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1223 wrpll_params.dco_integer; 1224 1225 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1226 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1227 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1228 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1229 wrpll_params.central_freq; 1230 } else if (encoder->type == INTEL_OUTPUT_DP || 1231 encoder->type == INTEL_OUTPUT_DP_MST || 1232 encoder->type == INTEL_OUTPUT_EDP) { 1233 switch (crtc_state->port_clock / 2) { 1234 case 81000: 1235 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); 1236 break; 1237 case 135000: 1238 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); 1239 break; 1240 case 270000: 1241 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); 1242 break; 1243 /* eDP 1.4 rates */ 1244 case 162000: 1245 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0); 1246 break; 1247 case 108000: 1248 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0); 1249 break; 1250 case 216000: 1251 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0); 1252 break; 1253 } 1254 1255 cfgcr1 = cfgcr2 = 0; 1256 } else { 1257 return NULL; 1258 } 1259 1260 memset(&crtc_state->dpll_hw_state, 0, 1261 sizeof(crtc_state->dpll_hw_state)); 1262 1263 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1264 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1265 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1266 1267 if (encoder->type == INTEL_OUTPUT_EDP) 1268 pll = intel_find_shared_dpll(crtc, crtc_state, 1269 DPLL_ID_SKL_DPLL0, 1270 DPLL_ID_SKL_DPLL0); 1271 else 1272 pll = intel_find_shared_dpll(crtc, crtc_state, 1273 DPLL_ID_SKL_DPLL1, 1274 DPLL_ID_SKL_DPLL3); 1275 if (!pll) 1276 return NULL; 1277 1278 crtc_state->ddi_pll_sel = pll->id; 1279 1280 intel_reference_shared_dpll(pll, crtc_state); 1281 1282 return pll; 1283 } 1284 1285 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = { 1286 .enable = skl_ddi_pll_enable, 1287 .disable = skl_ddi_pll_disable, 1288 .get_hw_state = skl_ddi_pll_get_hw_state, 1289 }; 1290 1291 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = { 1292 .enable = skl_ddi_dpll0_enable, 1293 .disable = skl_ddi_dpll0_disable, 1294 .get_hw_state = skl_ddi_dpll0_get_hw_state, 1295 }; 1296 1297 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 1298 struct intel_shared_dpll *pll) 1299 { 1300 uint32_t temp; 1301 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 1302 1303 /* Non-SSC reference */ 1304 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 1305 temp |= PORT_PLL_REF_SEL; 1306 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 1307 1308 /* Disable 10 bit clock */ 1309 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 1310 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 1311 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 1312 1313 /* Write P1 & P2 */ 1314 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); 1315 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); 1316 temp |= pll->config.hw_state.ebb0; 1317 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); 1318 1319 /* Write M2 integer */ 1320 temp = I915_READ(BXT_PORT_PLL(port, 0)); 1321 temp &= ~PORT_PLL_M2_MASK; 1322 temp |= pll->config.hw_state.pll0; 1323 I915_WRITE(BXT_PORT_PLL(port, 0), temp); 1324 1325 /* Write N */ 1326 temp = I915_READ(BXT_PORT_PLL(port, 1)); 1327 temp &= ~PORT_PLL_N_MASK; 1328 temp |= pll->config.hw_state.pll1; 1329 I915_WRITE(BXT_PORT_PLL(port, 1), temp); 1330 1331 /* Write M2 fraction */ 1332 temp = I915_READ(BXT_PORT_PLL(port, 2)); 1333 temp &= ~PORT_PLL_M2_FRAC_MASK; 1334 temp |= pll->config.hw_state.pll2; 1335 I915_WRITE(BXT_PORT_PLL(port, 2), temp); 1336 1337 /* Write M2 fraction enable */ 1338 temp = I915_READ(BXT_PORT_PLL(port, 3)); 1339 temp &= ~PORT_PLL_M2_FRAC_ENABLE; 1340 temp |= pll->config.hw_state.pll3; 1341 I915_WRITE(BXT_PORT_PLL(port, 3), temp); 1342 1343 /* Write coeff */ 1344 temp = I915_READ(BXT_PORT_PLL(port, 6)); 1345 temp &= ~PORT_PLL_PROP_COEFF_MASK; 1346 temp &= ~PORT_PLL_INT_COEFF_MASK; 1347 temp &= ~PORT_PLL_GAIN_CTL_MASK; 1348 temp |= pll->config.hw_state.pll6; 1349 I915_WRITE(BXT_PORT_PLL(port, 6), temp); 1350 1351 /* Write calibration val */ 1352 temp = I915_READ(BXT_PORT_PLL(port, 8)); 1353 temp &= ~PORT_PLL_TARGET_CNT_MASK; 1354 temp |= pll->config.hw_state.pll8; 1355 I915_WRITE(BXT_PORT_PLL(port, 8), temp); 1356 1357 temp = I915_READ(BXT_PORT_PLL(port, 9)); 1358 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; 1359 temp |= pll->config.hw_state.pll9; 1360 I915_WRITE(BXT_PORT_PLL(port, 9), temp); 1361 1362 temp = I915_READ(BXT_PORT_PLL(port, 10)); 1363 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; 1364 temp &= ~PORT_PLL_DCO_AMP_MASK; 1365 temp |= pll->config.hw_state.pll10; 1366 I915_WRITE(BXT_PORT_PLL(port, 10), temp); 1367 1368 /* Recalibrate with new settings */ 1369 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 1370 temp |= PORT_PLL_RECALIBRATE; 1371 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 1372 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 1373 temp |= pll->config.hw_state.ebb4; 1374 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 1375 1376 /* Enable PLL */ 1377 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 1378 temp |= PORT_PLL_ENABLE; 1379 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 1380 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 1381 1382 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), 1383 200)) 1384 DRM_ERROR("PLL %d not locked\n", port); 1385 1386 /* 1387 * While we write to the group register to program all lanes at once we 1388 * can read only lane registers and we pick lanes 0/1 for that. 1389 */ 1390 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 1391 temp &= ~LANE_STAGGER_MASK; 1392 temp &= ~LANESTAGGER_STRAP_OVRD; 1393 temp |= pll->config.hw_state.pcsdw12; 1394 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); 1395 } 1396 1397 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, 1398 struct intel_shared_dpll *pll) 1399 { 1400 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 1401 uint32_t temp; 1402 1403 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 1404 temp &= ~PORT_PLL_ENABLE; 1405 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 1406 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 1407 } 1408 1409 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 1410 struct intel_shared_dpll *pll, 1411 struct intel_dpll_hw_state *hw_state) 1412 { 1413 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 1414 uint32_t val; 1415 bool ret; 1416 1417 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 1418 return false; 1419 1420 ret = false; 1421 1422 val = I915_READ(BXT_PORT_PLL_ENABLE(port)); 1423 if (!(val & PORT_PLL_ENABLE)) 1424 goto out; 1425 1426 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); 1427 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; 1428 1429 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); 1430 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; 1431 1432 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); 1433 hw_state->pll0 &= PORT_PLL_M2_MASK; 1434 1435 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); 1436 hw_state->pll1 &= PORT_PLL_N_MASK; 1437 1438 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); 1439 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; 1440 1441 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); 1442 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; 1443 1444 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); 1445 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | 1446 PORT_PLL_INT_COEFF_MASK | 1447 PORT_PLL_GAIN_CTL_MASK; 1448 1449 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); 1450 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; 1451 1452 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); 1453 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; 1454 1455 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); 1456 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | 1457 PORT_PLL_DCO_AMP_MASK; 1458 1459 /* 1460 * While we write to the group register to program all lanes at once we 1461 * can read only lane registers. We configure all lanes the same way, so 1462 * here just read out lanes 0/1 and output a note if lanes 2/3 differ. 1463 */ 1464 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 1465 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) 1466 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", 1467 hw_state->pcsdw12, 1468 I915_READ(BXT_PORT_PCS_DW12_LN23(port))); 1469 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; 1470 1471 ret = true; 1472 1473 out: 1474 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 1475 1476 return ret; 1477 } 1478 1479 /* bxt clock parameters */ 1480 struct bxt_clk_div { 1481 int clock; 1482 uint32_t p1; 1483 uint32_t p2; 1484 uint32_t m2_int; 1485 uint32_t m2_frac; 1486 bool m2_frac_en; 1487 uint32_t n; 1488 }; 1489 1490 /* pre-calculated values for DP linkrates */ 1491 static const struct bxt_clk_div bxt_dp_clk_val[] = { 1492 {162000, 4, 2, 32, 1677722, 1, 1}, 1493 {270000, 4, 1, 27, 0, 0, 1}, 1494 {540000, 2, 1, 27, 0, 0, 1}, 1495 {216000, 3, 2, 32, 1677722, 1, 1}, 1496 {243000, 4, 1, 24, 1258291, 1, 1}, 1497 {324000, 4, 1, 32, 1677722, 1, 1}, 1498 {432000, 3, 1, 32, 1677722, 1, 1} 1499 }; 1500 1501 static struct intel_shared_dpll * 1502 bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, 1503 struct intel_encoder *encoder) 1504 { 1505 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1506 struct intel_shared_dpll *pll; 1507 enum intel_dpll_id i; 1508 struct intel_digital_port *intel_dig_port; 1509 struct bxt_clk_div clk_div = {0}; 1510 int vco = 0; 1511 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; 1512 uint32_t lanestagger; 1513 int clock = crtc_state->port_clock; 1514 1515 if (encoder->type == INTEL_OUTPUT_HDMI) { 1516 struct dpll best_clock; 1517 1518 /* Calculate HDMI div */ 1519 /* 1520 * FIXME: tie the following calculation into 1521 * i9xx_crtc_compute_clock 1522 */ 1523 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { 1524 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", 1525 clock, pipe_name(crtc->pipe)); 1526 return NULL; 1527 } 1528 1529 clk_div.p1 = best_clock.p1; 1530 clk_div.p2 = best_clock.p2; 1531 WARN_ON(best_clock.m1 != 2); 1532 clk_div.n = best_clock.n; 1533 clk_div.m2_int = best_clock.m2 >> 22; 1534 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); 1535 clk_div.m2_frac_en = clk_div.m2_frac != 0; 1536 1537 vco = best_clock.vco; 1538 } else if (encoder->type == INTEL_OUTPUT_DP || 1539 encoder->type == INTEL_OUTPUT_EDP) { 1540 int i; 1541 1542 clk_div = bxt_dp_clk_val[0]; 1543 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { 1544 if (bxt_dp_clk_val[i].clock == clock) { 1545 clk_div = bxt_dp_clk_val[i]; 1546 break; 1547 } 1548 } 1549 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; 1550 } 1551 1552 if (vco >= 6200000 && vco <= 6700000) { 1553 prop_coef = 4; 1554 int_coef = 9; 1555 gain_ctl = 3; 1556 targ_cnt = 8; 1557 } else if ((vco > 5400000 && vco < 6200000) || 1558 (vco >= 4800000 && vco < 5400000)) { 1559 prop_coef = 5; 1560 int_coef = 11; 1561 gain_ctl = 3; 1562 targ_cnt = 9; 1563 } else if (vco == 5400000) { 1564 prop_coef = 3; 1565 int_coef = 8; 1566 gain_ctl = 1; 1567 targ_cnt = 9; 1568 } else { 1569 DRM_ERROR("Invalid VCO\n"); 1570 return NULL; 1571 } 1572 1573 memset(&crtc_state->dpll_hw_state, 0, 1574 sizeof(crtc_state->dpll_hw_state)); 1575 1576 if (clock > 270000) 1577 lanestagger = 0x18; 1578 else if (clock > 135000) 1579 lanestagger = 0x0d; 1580 else if (clock > 67000) 1581 lanestagger = 0x07; 1582 else if (clock > 33000) 1583 lanestagger = 0x04; 1584 else 1585 lanestagger = 0x02; 1586 1587 crtc_state->dpll_hw_state.ebb0 = 1588 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); 1589 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; 1590 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); 1591 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; 1592 1593 if (clk_div.m2_frac_en) 1594 crtc_state->dpll_hw_state.pll3 = 1595 PORT_PLL_M2_FRAC_ENABLE; 1596 1597 crtc_state->dpll_hw_state.pll6 = 1598 prop_coef | PORT_PLL_INT_COEFF(int_coef); 1599 crtc_state->dpll_hw_state.pll6 |= 1600 PORT_PLL_GAIN_CTL(gain_ctl); 1601 1602 crtc_state->dpll_hw_state.pll8 = targ_cnt; 1603 1604 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; 1605 1606 crtc_state->dpll_hw_state.pll10 = 1607 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) 1608 | PORT_PLL_DCO_AMP_OVR_EN_H; 1609 1610 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; 1611 1612 crtc_state->dpll_hw_state.pcsdw12 = 1613 LANESTAGGER_STRAP_OVRD | lanestagger; 1614 1615 intel_dig_port = enc_to_dig_port(&encoder->base); 1616 1617 /* 1:1 mapping between ports and PLLs */ 1618 i = (enum intel_dpll_id) intel_dig_port->port; 1619 pll = intel_get_shared_dpll_by_id(dev_priv, i); 1620 1621 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", 1622 crtc->base.base.id, crtc->base.name, pll->name); 1623 1624 intel_reference_shared_dpll(pll, crtc_state); 1625 1626 /* shared DPLL id 0 is DPLL A */ 1627 crtc_state->ddi_pll_sel = pll->id; 1628 1629 return pll; 1630 } 1631 1632 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { 1633 .enable = bxt_ddi_pll_enable, 1634 .disable = bxt_ddi_pll_disable, 1635 .get_hw_state = bxt_ddi_pll_get_hw_state, 1636 }; 1637 1638 static void intel_ddi_pll_init(struct drm_device *dev) 1639 { 1640 struct drm_i915_private *dev_priv = to_i915(dev); 1641 1642 if (INTEL_GEN(dev_priv) < 9) { 1643 uint32_t val = I915_READ(LCPLL_CTL); 1644 1645 /* 1646 * The LCPLL register should be turned on by the BIOS. For now 1647 * let's just check its state and print errors in case 1648 * something is wrong. Don't even try to turn it on. 1649 */ 1650 1651 if (val & LCPLL_CD_SOURCE_FCLK) 1652 DRM_ERROR("CDCLK source is not LCPLL\n"); 1653 1654 if (val & LCPLL_PLL_DISABLE) 1655 DRM_ERROR("LCPLL is disabled\n"); 1656 } 1657 } 1658 1659 struct dpll_info { 1660 const char *name; 1661 const int id; 1662 const struct intel_shared_dpll_funcs *funcs; 1663 uint32_t flags; 1664 }; 1665 1666 struct intel_dpll_mgr { 1667 const struct dpll_info *dpll_info; 1668 1669 struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc, 1670 struct intel_crtc_state *crtc_state, 1671 struct intel_encoder *encoder); 1672 }; 1673 1674 static const struct dpll_info pch_plls[] = { 1675 { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 }, 1676 { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 }, 1677 { NULL, -1, NULL, 0 }, 1678 }; 1679 1680 static const struct intel_dpll_mgr pch_pll_mgr = { 1681 .dpll_info = pch_plls, 1682 .get_dpll = ibx_get_dpll, 1683 }; 1684 1685 static const struct dpll_info hsw_plls[] = { 1686 { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs, 0 }, 1687 { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs, 0 }, 1688 { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs, 0 }, 1689 { "LCPLL 810", DPLL_ID_LCPLL_810, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON }, 1690 { "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON }, 1691 { "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON }, 1692 { NULL, -1, NULL, }, 1693 }; 1694 1695 static const struct intel_dpll_mgr hsw_pll_mgr = { 1696 .dpll_info = hsw_plls, 1697 .get_dpll = hsw_get_dpll, 1698 }; 1699 1700 static const struct dpll_info skl_plls[] = { 1701 { "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON }, 1702 { "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs, 0 }, 1703 { "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs, 0 }, 1704 { "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs, 0 }, 1705 { NULL, -1, NULL, }, 1706 }; 1707 1708 static const struct intel_dpll_mgr skl_pll_mgr = { 1709 .dpll_info = skl_plls, 1710 .get_dpll = skl_get_dpll, 1711 }; 1712 1713 static const struct dpll_info bxt_plls[] = { 1714 { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 }, 1715 { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 }, 1716 { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 }, 1717 { NULL, -1, NULL, }, 1718 }; 1719 1720 static const struct intel_dpll_mgr bxt_pll_mgr = { 1721 .dpll_info = bxt_plls, 1722 .get_dpll = bxt_get_dpll, 1723 }; 1724 1725 void intel_shared_dpll_init(struct drm_device *dev) 1726 { 1727 struct drm_i915_private *dev_priv = to_i915(dev); 1728 const struct intel_dpll_mgr *dpll_mgr = NULL; 1729 const struct dpll_info *dpll_info; 1730 int i; 1731 1732 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 1733 dpll_mgr = &skl_pll_mgr; 1734 else if (IS_BROXTON(dev)) 1735 dpll_mgr = &bxt_pll_mgr; 1736 else if (HAS_DDI(dev)) 1737 dpll_mgr = &hsw_pll_mgr; 1738 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 1739 dpll_mgr = &pch_pll_mgr; 1740 1741 if (!dpll_mgr) { 1742 dev_priv->num_shared_dpll = 0; 1743 return; 1744 } 1745 1746 dpll_info = dpll_mgr->dpll_info; 1747 1748 for (i = 0; dpll_info[i].id >= 0; i++) { 1749 WARN_ON(i != dpll_info[i].id); 1750 1751 dev_priv->shared_dplls[i].id = dpll_info[i].id; 1752 dev_priv->shared_dplls[i].name = dpll_info[i].name; 1753 dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs; 1754 dev_priv->shared_dplls[i].flags = dpll_info[i].flags; 1755 } 1756 1757 dev_priv->dpll_mgr = dpll_mgr; 1758 dev_priv->num_shared_dpll = i; 1759 lockinit(&dev_priv->dpll_lock, "dpll_lock", 0, LK_CANRECURSE); 1760 1761 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); 1762 1763 /* FIXME: Move this to a more suitable place */ 1764 if (HAS_DDI(dev)) 1765 intel_ddi_pll_init(dev); 1766 } 1767 1768 struct intel_shared_dpll * 1769 intel_get_shared_dpll(struct intel_crtc *crtc, 1770 struct intel_crtc_state *crtc_state, 1771 struct intel_encoder *encoder) 1772 { 1773 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1774 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; 1775 1776 if (WARN_ON(!dpll_mgr)) 1777 return NULL; 1778 1779 return dpll_mgr->get_dpll(crtc, crtc_state, encoder); 1780 } 1781