1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 #ifndef __INTEL_DRV_H__ 26 #define __INTEL_DRV_H__ 27 28 #include <linux/async.h> 29 #include <linux/i2c.h> 30 #include <linux/hdmi.h> 31 #include <drm/i915_drm.h> 32 #include "i915_drv.h" 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_fb_helper.h> 36 #include <drm/drm_dp_mst_helper.h> 37 #include <drm/drm_rect.h> 38 #include <drm/drm_atomic.h> 39 40 /** 41 * _wait_for - magic (register) wait macro 42 * 43 * Does the right thing for modeset paths when run under kdgb or similar atomic 44 * contexts. Note that it's important that we check the condition again after 45 * having timed out, since the timeout could be due to preemption or similar and 46 * we've never had a chance to check the condition before the timeout. 47 */ 48 #define _wait_for(COND, MS, W) ({ \ 49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 50 int ret__ = 0; \ 51 while (!(COND)) { \ 52 if (time_after(jiffies, timeout__)) { \ 53 if (!(COND)) \ 54 ret__ = -ETIMEDOUT; \ 55 break; \ 56 } \ 57 if ((W) && drm_can_sleep()) { \ 58 usleep_range((W)*1000, (W)*2000); \ 59 } else { \ 60 cpu_pause(); \ 61 } \ 62 } \ 63 ret__; \ 64 }) 65 66 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) 68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \ 69 DIV_ROUND_UP((US), 1000), 0) 70 71 #define KHz(x) (1000 * (x)) 72 #define MHz(x) KHz(1000 * (x)) 73 74 /* 75 * Display related stuff 76 */ 77 78 /* store information about an Ixxx DVO */ 79 /* The i830->i865 use multiple DVOs with multiple i2cs */ 80 /* the i915, i945 have a single sDVO i2c bus - which is different */ 81 #define MAX_OUTPUTS 6 82 /* maximum connectors per crtcs in the mode set */ 83 84 /* Maximum cursor sizes */ 85 #define GEN2_CURSOR_WIDTH 64 86 #define GEN2_CURSOR_HEIGHT 64 87 #define MAX_CURSOR_WIDTH 256 88 #define MAX_CURSOR_HEIGHT 256 89 90 #define INTEL_I2C_BUS_DVO 1 91 #define INTEL_I2C_BUS_SDVO 2 92 93 /* these are outputs from the chip - integrated only 94 external chips are via DVO or SDVO output */ 95 enum intel_output_type { 96 INTEL_OUTPUT_UNUSED = 0, 97 INTEL_OUTPUT_ANALOG = 1, 98 INTEL_OUTPUT_DVO = 2, 99 INTEL_OUTPUT_SDVO = 3, 100 INTEL_OUTPUT_LVDS = 4, 101 INTEL_OUTPUT_TVOUT = 5, 102 INTEL_OUTPUT_HDMI = 6, 103 INTEL_OUTPUT_DISPLAYPORT = 7, 104 INTEL_OUTPUT_EDP = 8, 105 INTEL_OUTPUT_DSI = 9, 106 INTEL_OUTPUT_UNKNOWN = 10, 107 INTEL_OUTPUT_DP_MST = 11, 108 }; 109 110 #define INTEL_DVO_CHIP_NONE 0 111 #define INTEL_DVO_CHIP_LVDS 1 112 #define INTEL_DVO_CHIP_TMDS 2 113 #define INTEL_DVO_CHIP_TVOUT 4 114 115 #define INTEL_DSI_VIDEO_MODE 0 116 #define INTEL_DSI_COMMAND_MODE 1 117 118 struct intel_framebuffer { 119 struct drm_framebuffer base; 120 struct drm_i915_gem_object *obj; 121 }; 122 123 struct intel_fbdev { 124 struct drm_fb_helper helper; 125 struct intel_framebuffer *fb; 126 struct list_head fbdev_list; 127 struct drm_display_mode *our_mode; 128 int preferred_bpp; 129 }; 130 131 struct intel_encoder { 132 struct drm_encoder base; 133 /* 134 * The new crtc this encoder will be driven from. Only differs from 135 * base->crtc while a modeset is in progress. 136 */ 137 struct intel_crtc *new_crtc; 138 139 enum intel_output_type type; 140 unsigned int cloneable; 141 bool connectors_active; 142 void (*hot_plug)(struct intel_encoder *); 143 bool (*compute_config)(struct intel_encoder *, 144 struct intel_crtc_state *); 145 void (*pre_pll_enable)(struct intel_encoder *); 146 void (*pre_enable)(struct intel_encoder *); 147 void (*enable)(struct intel_encoder *); 148 void (*mode_set)(struct intel_encoder *intel_encoder); 149 void (*disable)(struct intel_encoder *); 150 void (*post_disable)(struct intel_encoder *); 151 /* Read out the current hw state of this connector, returning true if 152 * the encoder is active. If the encoder is enabled it also set the pipe 153 * it is connected to in the pipe parameter. */ 154 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe); 155 /* Reconstructs the equivalent mode flags for the current hardware 156 * state. This must be called _after_ display->get_pipe_config has 157 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 158 * be set correctly before calling this function. */ 159 void (*get_config)(struct intel_encoder *, 160 struct intel_crtc_state *pipe_config); 161 /* 162 * Called during system suspend after all pending requests for the 163 * encoder are flushed (for example for DP AUX transactions) and 164 * device interrupts are disabled. 165 */ 166 void (*suspend)(struct intel_encoder *); 167 int crtc_mask; 168 enum hpd_pin hpd_pin; 169 }; 170 171 struct intel_panel { 172 struct drm_display_mode *fixed_mode; 173 struct drm_display_mode *downclock_mode; 174 int fitting_mode; 175 176 /* backlight */ 177 struct { 178 bool present; 179 u32 level; 180 u32 min; 181 u32 max; 182 bool enabled; 183 bool combination_mode; /* gen 2/4 only */ 184 bool active_low_pwm; 185 struct backlight_device *device; 186 } backlight; 187 188 void (*backlight_power)(struct intel_connector *, bool enable); 189 }; 190 191 struct intel_connector { 192 struct drm_connector base; 193 /* 194 * The fixed encoder this connector is connected to. 195 */ 196 struct intel_encoder *encoder; 197 198 /* 199 * The new encoder this connector will be driven. Only differs from 200 * encoder while a modeset is in progress. 201 */ 202 struct intel_encoder *new_encoder; 203 204 /* Reads out the current hw, returning true if the connector is enabled 205 * and active (i.e. dpms ON state). */ 206 bool (*get_hw_state)(struct intel_connector *); 207 208 /* 209 * Removes all interfaces through which the connector is accessible 210 * - like sysfs, debugfs entries -, so that no new operations can be 211 * started on the connector. Also makes sure all currently pending 212 * operations finish before returing. 213 */ 214 void (*unregister)(struct intel_connector *); 215 216 /* Panel info for eDP and LVDS */ 217 struct intel_panel panel; 218 219 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 220 struct edid *edid; 221 struct edid *detect_edid; 222 223 /* since POLL and HPD connectors may use the same HPD line keep the native 224 state of connector->polled in case hotplug storm detection changes it */ 225 u8 polled; 226 227 void *port; /* store this opaque as its illegal to dereference it */ 228 229 struct intel_dp *mst_port; 230 }; 231 232 typedef struct dpll { 233 /* given values */ 234 int n; 235 int m1, m2; 236 int p1, p2; 237 /* derived values */ 238 int dot; 239 int vco; 240 int m; 241 int p; 242 } intel_clock_t; 243 244 struct intel_plane_state { 245 struct drm_plane_state base; 246 struct drm_rect src; 247 struct drm_rect dst; 248 struct drm_rect clip; 249 bool visible; 250 251 /* 252 * used only for sprite planes to determine when to implicitly 253 * enable/disable the primary plane 254 */ 255 bool hides_primary; 256 }; 257 258 struct intel_initial_plane_config { 259 struct intel_framebuffer *fb; 260 unsigned int tiling; 261 int size; 262 u32 base; 263 }; 264 265 struct intel_crtc_state { 266 struct drm_crtc_state base; 267 268 /** 269 * quirks - bitfield with hw state readout quirks 270 * 271 * For various reasons the hw state readout code might not be able to 272 * completely faithfully read out the current state. These cases are 273 * tracked with quirk flags so that fastboot and state checker can act 274 * accordingly. 275 */ 276 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 277 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ 278 unsigned long quirks; 279 280 /* Pipe source size (ie. panel fitter input size) 281 * All planes will be positioned inside this space, 282 * and get clipped at the edges. */ 283 int pipe_src_w, pipe_src_h; 284 285 /* Whether to set up the PCH/FDI. Note that we never allow sharing 286 * between pch encoders and cpu encoders. */ 287 bool has_pch_encoder; 288 289 /* Are we sending infoframes on the attached port */ 290 bool has_infoframe; 291 292 /* CPU Transcoder for the pipe. Currently this can only differ from the 293 * pipe on Haswell (where we have a special eDP transcoder). */ 294 enum transcoder cpu_transcoder; 295 296 /* 297 * Use reduced/limited/broadcast rbg range, compressing from the full 298 * range fed into the crtcs. 299 */ 300 bool limited_color_range; 301 302 /* DP has a bunch of special case unfortunately, so mark the pipe 303 * accordingly. */ 304 bool has_dp_encoder; 305 306 /* Whether we should send NULL infoframes. Required for audio. */ 307 bool has_hdmi_sink; 308 309 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 310 * has_dp_encoder is set. */ 311 bool has_audio; 312 313 /* 314 * Enable dithering, used when the selected pipe bpp doesn't match the 315 * plane bpp. 316 */ 317 bool dither; 318 319 /* Controls for the clock computation, to override various stages. */ 320 bool clock_set; 321 322 /* SDVO TV has a bunch of special case. To make multifunction encoders 323 * work correctly, we need to track this at runtime.*/ 324 bool sdvo_tv_clock; 325 326 /* 327 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 328 * required. This is set in the 2nd loop of calling encoder's 329 * ->compute_config if the first pick doesn't work out. 330 */ 331 bool bw_constrained; 332 333 /* Settings for the intel dpll used on pretty much everything but 334 * haswell. */ 335 struct dpll dpll; 336 337 /* Selected dpll when shared or DPLL_ID_PRIVATE. */ 338 enum intel_dpll_id shared_dpll; 339 340 /* 341 * - PORT_CLK_SEL for DDI ports on HSW/BDW. 342 * - enum skl_dpll on SKL 343 */ 344 uint32_t ddi_pll_sel; 345 346 /* Actual register state of the dpll, for shared dpll cross-checking. */ 347 struct intel_dpll_hw_state dpll_hw_state; 348 349 int pipe_bpp; 350 struct intel_link_m_n dp_m_n; 351 352 /* m2_n2 for eDP downclock */ 353 struct intel_link_m_n dp_m2_n2; 354 bool has_drrs; 355 356 /* 357 * Frequence the dpll for the port should run at. Differs from the 358 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also 359 * already multiplied by pixel_multiplier. 360 */ 361 int port_clock; 362 363 /* Used by SDVO (and if we ever fix it, HDMI). */ 364 unsigned pixel_multiplier; 365 366 /* Panel fitter controls for gen2-gen4 + VLV */ 367 struct { 368 u32 control; 369 u32 pgm_ratios; 370 u32 lvds_border_bits; 371 } gmch_pfit; 372 373 /* Panel fitter placement and size for Ironlake+ */ 374 struct { 375 u32 pos; 376 u32 size; 377 bool enabled; 378 bool force_thru; 379 } pch_pfit; 380 381 /* FDI configuration, only valid if has_pch_encoder is set. */ 382 int fdi_lanes; 383 struct intel_link_m_n fdi_m_n; 384 385 bool ips_enabled; 386 387 bool double_wide; 388 389 bool dp_encoder_is_mst; 390 int pbn; 391 }; 392 393 struct intel_pipe_wm { 394 struct intel_wm_level wm[5]; 395 uint32_t linetime; 396 bool fbc_wm_enabled; 397 bool pipe_enabled; 398 bool sprites_enabled; 399 bool sprites_scaled; 400 }; 401 402 struct intel_mmio_flip { 403 struct drm_i915_gem_request *req; 404 struct work_struct work; 405 }; 406 407 struct skl_pipe_wm { 408 struct skl_wm_level wm[8]; 409 struct skl_wm_level trans_wm; 410 uint32_t linetime; 411 }; 412 413 /* 414 * Tracking of operations that need to be performed at the beginning/end of an 415 * atomic commit, outside the atomic section where interrupts are disabled. 416 * These are generally operations that grab mutexes or might otherwise sleep 417 * and thus can't be run with interrupts disabled. 418 */ 419 struct intel_crtc_atomic_commit { 420 /* vblank evasion */ 421 bool evade; 422 unsigned start_vbl_count; 423 424 /* Sleepable operations to perform before commit */ 425 bool wait_for_flips; 426 bool disable_fbc; 427 bool pre_disable_primary; 428 bool update_wm; 429 unsigned disabled_planes; 430 431 /* Sleepable operations to perform after commit */ 432 unsigned fb_bits; 433 bool wait_vblank; 434 bool update_fbc; 435 bool post_enable_primary; 436 unsigned update_sprite_watermarks; 437 }; 438 439 struct intel_crtc { 440 struct drm_crtc base; 441 enum i915_pipe pipe; 442 enum plane plane; 443 u8 lut_r[256], lut_g[256], lut_b[256]; 444 /* 445 * Whether the crtc and the connected output pipeline is active. Implies 446 * that crtc->enabled is set, i.e. the current mode configuration has 447 * some outputs connected to this crtc. 448 */ 449 bool active; 450 unsigned long enabled_power_domains; 451 bool primary_enabled; /* is the primary plane (partially) visible? */ 452 bool lowfreq_avail; 453 struct intel_overlay *overlay; 454 struct intel_unpin_work *unpin_work; 455 456 atomic_t unpin_work_count; 457 458 /* Display surface base address adjustement for pageflips. Note that on 459 * gen4+ this only adjusts up to a tile, offsets within a tile are 460 * handled in the hw itself (with the TILEOFF register). */ 461 unsigned long dspaddr_offset; 462 463 struct drm_i915_gem_object *cursor_bo; 464 uint32_t cursor_addr; 465 uint32_t cursor_cntl; 466 uint32_t cursor_size; 467 uint32_t cursor_base; 468 469 struct intel_initial_plane_config plane_config; 470 struct intel_crtc_state *config; 471 struct intel_crtc_state *new_config; 472 bool new_enabled; 473 474 /* reset counter value when the last flip was submitted */ 475 unsigned int reset_counter; 476 477 /* Access to these should be protected by dev_priv->irq_lock. */ 478 bool cpu_fifo_underrun_disabled; 479 bool pch_fifo_underrun_disabled; 480 481 /* per-pipe watermark state */ 482 struct { 483 /* watermarks currently being used */ 484 struct intel_pipe_wm active; 485 /* SKL wm values currently in use */ 486 struct skl_pipe_wm skl_active; 487 } wm; 488 489 int scanline_offset; 490 struct intel_mmio_flip mmio_flip; 491 492 struct intel_crtc_atomic_commit atomic; 493 }; 494 495 struct intel_plane_wm_parameters { 496 uint32_t horiz_pixels; 497 uint32_t vert_pixels; 498 uint8_t bytes_per_pixel; 499 bool enabled; 500 bool scaled; 501 u64 tiling; 502 unsigned int rotation; 503 }; 504 505 struct intel_plane { 506 struct drm_plane base; 507 int plane; 508 enum i915_pipe pipe; 509 bool can_scale; 510 int max_downscale; 511 512 /* FIXME convert to properties */ 513 struct drm_intel_sprite_colorkey ckey; 514 515 /* Since we need to change the watermarks before/after 516 * enabling/disabling the planes, we need to store the parameters here 517 * as the other pieces of the struct may not reflect the values we want 518 * for the watermark calculations. Currently only Haswell uses this. 519 */ 520 struct intel_plane_wm_parameters wm; 521 522 /* 523 * NOTE: Do not place new plane state fields here (e.g., when adding 524 * new plane properties). New runtime state should now be placed in 525 * the intel_plane_state structure and accessed via drm_plane->state. 526 */ 527 528 void (*update_plane)(struct drm_plane *plane, 529 struct drm_crtc *crtc, 530 struct drm_framebuffer *fb, 531 int crtc_x, int crtc_y, 532 unsigned int crtc_w, unsigned int crtc_h, 533 uint32_t x, uint32_t y, 534 uint32_t src_w, uint32_t src_h); 535 void (*disable_plane)(struct drm_plane *plane, 536 struct drm_crtc *crtc); 537 int (*check_plane)(struct drm_plane *plane, 538 struct intel_plane_state *state); 539 void (*commit_plane)(struct drm_plane *plane, 540 struct intel_plane_state *state); 541 }; 542 543 struct intel_watermark_params { 544 unsigned long fifo_size; 545 unsigned long max_wm; 546 unsigned long default_wm; 547 unsigned long guard_size; 548 unsigned long cacheline_size; 549 }; 550 551 struct cxsr_latency { 552 int is_desktop; 553 int is_ddr3; 554 unsigned long fsb_freq; 555 unsigned long mem_freq; 556 unsigned long display_sr; 557 unsigned long display_hpll_disable; 558 unsigned long cursor_sr; 559 unsigned long cursor_hpll_disable; 560 }; 561 562 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 563 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) 564 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 565 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 566 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 567 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 568 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) 569 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) 570 571 struct intel_hdmi { 572 u32 hdmi_reg; 573 int ddc_bus; 574 uint32_t color_range; 575 bool color_range_auto; 576 bool has_hdmi_sink; 577 bool has_audio; 578 enum hdmi_force_audio force_audio; 579 bool rgb_quant_range_selectable; 580 enum hdmi_picture_aspect aspect_ratio; 581 void (*write_infoframe)(struct drm_encoder *encoder, 582 enum hdmi_infoframe_type type, 583 const void *frame, ssize_t len); 584 void (*set_infoframes)(struct drm_encoder *encoder, 585 bool enable, 586 struct drm_display_mode *adjusted_mode); 587 bool (*infoframe_enabled)(struct drm_encoder *encoder); 588 }; 589 590 struct intel_dp_mst_encoder; 591 #define DP_MAX_DOWNSTREAM_PORTS 0x10 592 593 /* 594 * enum link_m_n_set: 595 * When platform provides two set of M_N registers for dp, we can 596 * program them and switch between them incase of DRRS. 597 * But When only one such register is provided, we have to program the 598 * required divider value on that registers itself based on the DRRS state. 599 * 600 * M1_N1 : Program dp_m_n on M1_N1 registers 601 * dp_m2_n2 on M2_N2 registers (If supported) 602 * 603 * M2_N2 : Program dp_m2_n2 on M1_N1 registers 604 * M2_N2 registers are not supported 605 */ 606 607 enum link_m_n_set { 608 /* Sets the m1_n1 and m2_n2 */ 609 M1_N1 = 0, 610 M2_N2 611 }; 612 613 struct intel_dp { 614 uint32_t output_reg; 615 uint32_t aux_ch_ctl_reg; 616 uint32_t DP; 617 bool has_audio; 618 enum hdmi_force_audio force_audio; 619 uint32_t color_range; 620 bool color_range_auto; 621 uint8_t link_bw; 622 uint8_t rate_select; 623 uint8_t lane_count; 624 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 625 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 626 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 627 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ 628 uint8_t num_sink_rates; 629 int sink_rates[DP_MAX_SUPPORTED_RATES]; 630 struct drm_dp_aux aux; 631 device_t dp_iic_bus; 632 uint8_t train_set[4]; 633 int panel_power_up_delay; 634 int panel_power_down_delay; 635 int panel_power_cycle_delay; 636 int backlight_on_delay; 637 int backlight_off_delay; 638 struct delayed_work panel_vdd_work; 639 bool want_panel_vdd; 640 unsigned long last_power_cycle; 641 unsigned long last_power_on; 642 unsigned long last_backlight_off; 643 644 struct notifier_block edp_notifier; 645 646 /* 647 * Pipe whose power sequencer is currently locked into 648 * this port. Only relevant on VLV/CHV. 649 */ 650 enum i915_pipe pps_pipe; 651 struct edp_power_seq pps_delays; 652 653 bool use_tps3; 654 bool can_mst; /* this port supports mst */ 655 bool is_mst; 656 int active_mst_links; 657 /* connector directly attached - won't be use for modeset in mst world */ 658 struct intel_connector *attached_connector; 659 660 /* mst connector list */ 661 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 662 struct drm_dp_mst_topology_mgr mst_mgr; 663 664 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); 665 /* 666 * This function returns the value we have to program the AUX_CTL 667 * register with to kick off an AUX transaction. 668 */ 669 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, 670 bool has_aux_irq, 671 int send_bytes, 672 uint32_t aux_clock_divider); 673 }; 674 675 struct intel_digital_port { 676 struct intel_encoder base; 677 enum port port; 678 u32 saved_port_bits; 679 struct intel_dp dp; 680 struct intel_hdmi hdmi; 681 bool (*hpd_pulse)(struct intel_digital_port *, bool); 682 }; 683 684 struct intel_dp_mst_encoder { 685 struct intel_encoder base; 686 enum i915_pipe pipe; 687 struct intel_digital_port *primary; 688 void *port; /* store this opaque as its illegal to dereference it */ 689 }; 690 691 static inline int 692 vlv_dport_to_channel(struct intel_digital_port *dport) 693 { 694 switch (dport->port) { 695 case PORT_B: 696 case PORT_D: 697 return DPIO_CH0; 698 case PORT_C: 699 return DPIO_CH1; 700 default: 701 BUG(); 702 } 703 } 704 705 static inline int 706 vlv_pipe_to_channel(enum i915_pipe pipe) 707 { 708 switch (pipe) { 709 case PIPE_A: 710 case PIPE_C: 711 return DPIO_CH0; 712 case PIPE_B: 713 return DPIO_CH1; 714 default: 715 BUG(); 716 } 717 } 718 719 static inline struct drm_crtc * 720 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 721 { 722 struct drm_i915_private *dev_priv = dev->dev_private; 723 return dev_priv->pipe_to_crtc_mapping[pipe]; 724 } 725 726 static inline struct drm_crtc * 727 intel_get_crtc_for_plane(struct drm_device *dev, int plane) 728 { 729 struct drm_i915_private *dev_priv = dev->dev_private; 730 return dev_priv->plane_to_crtc_mapping[plane]; 731 } 732 733 struct intel_unpin_work { 734 struct work_struct work; 735 struct drm_crtc *crtc; 736 struct drm_framebuffer *old_fb; 737 struct drm_i915_gem_object *pending_flip_obj; 738 struct drm_pending_vblank_event *event; 739 atomic_t pending; 740 #define INTEL_FLIP_INACTIVE 0 741 #define INTEL_FLIP_PENDING 1 742 #define INTEL_FLIP_COMPLETE 2 743 u32 flip_count; 744 u32 gtt_offset; 745 struct drm_i915_gem_request *flip_queued_req; 746 int flip_queued_vblank; 747 int flip_ready_vblank; 748 bool enable_stall_check; 749 }; 750 751 struct intel_set_config { 752 struct drm_encoder **save_connector_encoders; 753 struct drm_crtc **save_encoder_crtcs; 754 bool *save_crtc_enabled; 755 756 bool fb_changed; 757 bool mode_changed; 758 }; 759 760 struct intel_load_detect_pipe { 761 struct drm_framebuffer *release_fb; 762 bool load_detect_temp; 763 int dpms_mode; 764 }; 765 766 static inline struct intel_encoder * 767 intel_attached_encoder(struct drm_connector *connector) 768 { 769 return to_intel_connector(connector)->encoder; 770 } 771 772 static inline struct intel_digital_port * 773 enc_to_dig_port(struct drm_encoder *encoder) 774 { 775 return container_of(encoder, struct intel_digital_port, base.base); 776 } 777 778 static inline struct intel_dp_mst_encoder * 779 enc_to_mst(struct drm_encoder *encoder) 780 { 781 return container_of(encoder, struct intel_dp_mst_encoder, base.base); 782 } 783 784 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 785 { 786 return &enc_to_dig_port(encoder)->dp; 787 } 788 789 static inline struct intel_digital_port * 790 dp_to_dig_port(struct intel_dp *intel_dp) 791 { 792 return container_of(intel_dp, struct intel_digital_port, dp); 793 } 794 795 static inline struct intel_digital_port * 796 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 797 { 798 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 799 } 800 801 /* 802 * Returns the number of planes for this pipe, ie the number of sprites + 1 803 * (primary plane). This doesn't count the cursor plane then. 804 */ 805 static inline unsigned int intel_num_planes(struct intel_crtc *crtc) 806 { 807 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; 808 } 809 810 /* intel_fifo_underrun.c */ 811 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 812 enum i915_pipe pipe, bool enable); 813 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, 814 enum transcoder pch_transcoder, 815 bool enable); 816 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 817 enum i915_pipe pipe); 818 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, 819 enum transcoder pch_transcoder); 820 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv); 821 822 /* i915_irq.c */ 823 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 824 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 825 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 826 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); 827 void gen6_reset_rps_interrupts(struct drm_device *dev); 828 void gen6_enable_rps_interrupts(struct drm_device *dev); 829 void gen6_disable_rps_interrupts(struct drm_device *dev); 830 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); 831 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); 832 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); 833 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 834 { 835 /* 836 * We only use drm_irq_uninstall() at unload and VT switch, so 837 * this is the only thing we need to check. 838 */ 839 return dev_priv->pm.irqs_enabled; 840 } 841 842 int intel_get_crtc_scanline(struct intel_crtc *crtc); 843 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 844 unsigned int pipe_mask); 845 846 /* intel_crt.c */ 847 void intel_crt_init(struct drm_device *dev); 848 849 850 /* intel_ddi.c */ 851 void intel_prepare_ddi(struct drm_device *dev); 852 void hsw_fdi_link_train(struct drm_crtc *crtc); 853 void intel_ddi_init(struct drm_device *dev, enum port port); 854 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); 855 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe); 856 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); 857 void intel_ddi_pll_init(struct drm_device *dev); 858 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); 859 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 860 enum transcoder cpu_transcoder); 861 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 862 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 863 bool intel_ddi_pll_select(struct intel_crtc *crtc, 864 struct intel_crtc_state *crtc_state); 865 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 866 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); 867 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 868 void intel_ddi_fdi_disable(struct drm_crtc *crtc); 869 void intel_ddi_get_config(struct intel_encoder *encoder, 870 struct intel_crtc_state *pipe_config); 871 872 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); 873 void intel_ddi_clock_get(struct intel_encoder *encoder, 874 struct intel_crtc_state *pipe_config); 875 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); 876 877 /* intel_frontbuffer.c */ 878 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, 879 struct intel_engine_cs *ring, 880 enum fb_op_origin origin); 881 void intel_frontbuffer_flip_prepare(struct drm_device *dev, 882 unsigned frontbuffer_bits); 883 void intel_frontbuffer_flip_complete(struct drm_device *dev, 884 unsigned frontbuffer_bits); 885 void intel_frontbuffer_flush(struct drm_device *dev, 886 unsigned frontbuffer_bits); 887 /** 888 * intel_frontbuffer_flip - synchronous frontbuffer flip 889 * @dev: DRM device 890 * @frontbuffer_bits: frontbuffer plane tracking bits 891 * 892 * This function gets called after scheduling a flip on @obj. This is for 893 * synchronous plane updates which will happen on the next vblank and which will 894 * not get delayed by pending gpu rendering. 895 * 896 * Can be called without any locks held. 897 */ 898 static inline 899 void intel_frontbuffer_flip(struct drm_device *dev, 900 unsigned frontbuffer_bits) 901 { 902 intel_frontbuffer_flush(dev, frontbuffer_bits); 903 } 904 905 unsigned int intel_fb_align_height(struct drm_device *dev, 906 unsigned int height, 907 uint32_t pixel_format, 908 uint64_t fb_format_modifier); 909 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); 910 911 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, 912 uint32_t pixel_format); 913 914 /* intel_audio.c */ 915 void intel_init_audio(struct drm_device *dev); 916 void intel_audio_codec_enable(struct intel_encoder *encoder); 917 void intel_audio_codec_disable(struct intel_encoder *encoder); 918 void i915_audio_component_init(struct drm_i915_private *dev_priv); 919 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); 920 921 /* intel_display.c */ 922 extern const struct drm_plane_funcs intel_plane_funcs; 923 bool intel_has_pending_fb_unpin(struct drm_device *dev); 924 int intel_pch_rawclk(struct drm_device *dev); 925 void intel_mark_busy(struct drm_device *dev); 926 void intel_mark_idle(struct drm_device *dev); 927 void intel_crtc_restore_mode(struct drm_crtc *crtc); 928 void intel_crtc_control(struct drm_crtc *crtc, bool enable); 929 void intel_crtc_update_dpms(struct drm_crtc *crtc); 930 void intel_encoder_destroy(struct drm_encoder *encoder); 931 int intel_connector_init(struct intel_connector *); 932 struct intel_connector *intel_connector_alloc(void); 933 void intel_connector_dpms(struct drm_connector *, int mode); 934 bool intel_connector_get_hw_state(struct intel_connector *connector); 935 void intel_modeset_check_state(struct drm_device *dev); 936 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 937 struct intel_digital_port *port); 938 void intel_connector_attach_encoder(struct intel_connector *connector, 939 struct intel_encoder *encoder); 940 struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 941 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 942 struct drm_crtc *crtc); 943 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector); 944 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 945 struct drm_file *file_priv); 946 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 947 enum i915_pipe pipe); 948 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); 949 static inline void 950 intel_wait_for_vblank(struct drm_device *dev, int pipe) 951 { 952 drm_wait_one_vblank(dev, pipe); 953 } 954 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 955 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 956 struct intel_digital_port *dport); 957 bool intel_get_load_detect_pipe(struct drm_connector *connector, 958 struct drm_display_mode *mode, 959 struct intel_load_detect_pipe *old, 960 struct drm_modeset_acquire_ctx *ctx); 961 void intel_release_load_detect_pipe(struct drm_connector *connector, 962 struct intel_load_detect_pipe *old, 963 struct drm_modeset_acquire_ctx *ctx); 964 int intel_pin_and_fence_fb_obj(struct drm_plane *plane, 965 struct drm_framebuffer *fb, 966 const struct drm_plane_state *plane_state, 967 struct intel_engine_cs *pipelined); 968 struct drm_framebuffer * 969 __intel_framebuffer_create(struct drm_device *dev, 970 struct drm_mode_fb_cmd2 *mode_cmd, 971 struct drm_i915_gem_object *obj); 972 void intel_prepare_page_flip(struct drm_device *dev, int plane); 973 void intel_finish_page_flip(struct drm_device *dev, int pipe); 974 void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 975 void intel_check_page_flip(struct drm_device *dev, int pipe); 976 int intel_prepare_plane_fb(struct drm_plane *plane, 977 struct drm_framebuffer *fb, 978 const struct drm_plane_state *new_state); 979 void intel_cleanup_plane_fb(struct drm_plane *plane, 980 struct drm_framebuffer *fb, 981 const struct drm_plane_state *old_state); 982 int intel_plane_atomic_get_property(struct drm_plane *plane, 983 const struct drm_plane_state *state, 984 struct drm_property *property, 985 uint64_t *val); 986 int intel_plane_atomic_set_property(struct drm_plane *plane, 987 struct drm_plane_state *state, 988 struct drm_property *property, 989 uint64_t val); 990 991 unsigned int 992 intel_tile_height(struct drm_device *dev, uint32_t pixel_format, 993 uint64_t fb_format_modifier); 994 995 static inline bool 996 intel_rotation_90_or_270(unsigned int rotation) 997 { 998 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); 999 } 1000 1001 bool intel_wm_need_update(struct drm_plane *plane, 1002 struct drm_plane_state *state); 1003 1004 /* shared dpll functions */ 1005 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); 1006 void assert_shared_dpll(struct drm_i915_private *dev_priv, 1007 struct intel_shared_dpll *pll, 1008 bool state); 1009 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 1010 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 1011 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 1012 struct intel_crtc_state *state); 1013 void intel_put_shared_dpll(struct intel_crtc *crtc); 1014 1015 void vlv_force_pll_on(struct drm_device *dev, enum i915_pipe pipe, 1016 const struct dpll *dpll); 1017 void vlv_force_pll_off(struct drm_device *dev, enum i915_pipe pipe); 1018 1019 /* modesetting asserts */ 1020 void assert_panel_unlocked(struct drm_i915_private *dev_priv, 1021 enum i915_pipe pipe); 1022 void assert_pll(struct drm_i915_private *dev_priv, 1023 enum i915_pipe pipe, bool state); 1024 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 1025 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 1026 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, 1027 enum i915_pipe pipe, bool state); 1028 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) 1029 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) 1030 void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state); 1031 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 1032 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 1033 unsigned long intel_gen4_compute_page_offset(int *x, int *y, 1034 unsigned int tiling_mode, 1035 unsigned int bpp, 1036 unsigned int pitch); 1037 void intel_prepare_reset(struct drm_device *dev); 1038 void intel_finish_reset(struct drm_device *dev); 1039 void hsw_enable_pc8(struct drm_i915_private *dev_priv); 1040 void hsw_disable_pc8(struct drm_i915_private *dev_priv); 1041 void intel_dp_get_m_n(struct intel_crtc *crtc, 1042 struct intel_crtc_state *pipe_config); 1043 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); 1044 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 1045 void 1046 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, 1047 int dotclock); 1048 bool intel_crtc_active(struct drm_crtc *crtc); 1049 void hsw_enable_ips(struct intel_crtc *crtc); 1050 void hsw_disable_ips(struct intel_crtc *crtc); 1051 enum intel_display_power_domain 1052 intel_display_port_power_domain(struct intel_encoder *intel_encoder); 1053 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 1054 struct intel_crtc_state *pipe_config); 1055 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); 1056 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); 1057 1058 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, 1059 struct drm_i915_gem_object *obj); 1060 1061 /* intel_dp.c */ 1062 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); 1063 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 1064 struct intel_connector *intel_connector); 1065 void intel_dp_start_link_train(struct intel_dp *intel_dp); 1066 void intel_dp_complete_link_train(struct intel_dp *intel_dp); 1067 void intel_dp_stop_link_train(struct intel_dp *intel_dp); 1068 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 1069 void intel_dp_encoder_destroy(struct drm_encoder *encoder); 1070 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); 1071 bool intel_dp_compute_config(struct intel_encoder *encoder, 1072 struct intel_crtc_state *pipe_config); 1073 bool intel_dp_is_edp(struct drm_device *dev, enum port port); 1074 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, 1075 bool long_hpd); 1076 void intel_edp_backlight_on(struct intel_dp *intel_dp); 1077 void intel_edp_backlight_off(struct intel_dp *intel_dp); 1078 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); 1079 void intel_edp_panel_on(struct intel_dp *intel_dp); 1080 void intel_edp_panel_off(struct intel_dp *intel_dp); 1081 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); 1082 void intel_dp_mst_suspend(struct drm_device *dev); 1083 void intel_dp_mst_resume(struct drm_device *dev); 1084 int intel_dp_max_link_rate(struct intel_dp *intel_dp); 1085 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); 1086 void intel_dp_hot_plug(struct intel_encoder *intel_encoder); 1087 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); 1088 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); 1089 void intel_plane_destroy(struct drm_plane *plane); 1090 void intel_edp_drrs_enable(struct intel_dp *intel_dp); 1091 void intel_edp_drrs_disable(struct intel_dp *intel_dp); 1092 void intel_edp_drrs_invalidate(struct drm_device *dev, 1093 unsigned frontbuffer_bits); 1094 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); 1095 1096 /* intel_dp_mst.c */ 1097 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); 1098 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); 1099 /* intel_dsi.c */ 1100 void intel_dsi_init(struct drm_device *dev); 1101 1102 1103 /* intel_dvo.c */ 1104 void intel_dvo_init(struct drm_device *dev); 1105 1106 1107 /* legacy fbdev emulation in intel_fbdev.c */ 1108 #ifdef CONFIG_DRM_I915_FBDEV 1109 extern int intel_fbdev_init(struct drm_device *dev); 1110 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie); 1111 extern void intel_fbdev_fini(struct drm_device *dev); 1112 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); 1113 extern void intel_fbdev_output_poll_changed(struct drm_device *dev); 1114 extern void intel_fbdev_restore_mode(struct drm_device *dev); 1115 #else 1116 static inline int intel_fbdev_init(struct drm_device *dev) 1117 { 1118 return 0; 1119 } 1120 1121 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie) 1122 { 1123 } 1124 1125 static inline void intel_fbdev_fini(struct drm_device *dev) 1126 { 1127 } 1128 1129 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) 1130 { 1131 } 1132 1133 static inline void intel_fbdev_restore_mode(struct drm_device *dev) 1134 { 1135 } 1136 #endif 1137 1138 /* intel_fbc.c */ 1139 bool intel_fbc_enabled(struct drm_device *dev); 1140 void intel_fbc_update(struct drm_device *dev); 1141 void intel_fbc_init(struct drm_i915_private *dev_priv); 1142 void intel_fbc_disable(struct drm_device *dev); 1143 void intel_fbc_invalidate(struct drm_i915_private *dev_priv, 1144 unsigned int frontbuffer_bits, 1145 enum fb_op_origin origin); 1146 void intel_fbc_flush(struct drm_i915_private *dev_priv, 1147 unsigned int frontbuffer_bits); 1148 1149 /* intel_hdmi.c */ 1150 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); 1151 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1152 struct intel_connector *intel_connector); 1153 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 1154 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1155 struct intel_crtc_state *pipe_config); 1156 1157 1158 /* intel_lvds.c */ 1159 void intel_lvds_init(struct drm_device *dev); 1160 bool intel_is_dual_link_lvds(struct drm_device *dev); 1161 1162 1163 /* intel_modes.c */ 1164 int intel_connector_update_modes(struct drm_connector *connector, 1165 struct edid *edid); 1166 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); 1167 void intel_attach_force_audio_property(struct drm_connector *connector); 1168 void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 1169 1170 1171 /* intel_overlay.c */ 1172 void intel_setup_overlay(struct drm_device *dev); 1173 void intel_cleanup_overlay(struct drm_device *dev); 1174 int intel_overlay_switch_off(struct intel_overlay *overlay); 1175 int intel_overlay_put_image(struct drm_device *dev, void *data, 1176 struct drm_file *file_priv); 1177 int intel_overlay_attrs(struct drm_device *dev, void *data, 1178 struct drm_file *file_priv); 1179 void intel_overlay_reset(struct drm_i915_private *dev_priv); 1180 1181 1182 /* intel_panel.c */ 1183 int intel_panel_init(struct intel_panel *panel, 1184 struct drm_display_mode *fixed_mode, 1185 struct drm_display_mode *downclock_mode); 1186 void intel_panel_fini(struct intel_panel *panel); 1187 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, 1188 struct drm_display_mode *adjusted_mode); 1189 void intel_pch_panel_fitting(struct intel_crtc *crtc, 1190 struct intel_crtc_state *pipe_config, 1191 int fitting_mode); 1192 void intel_gmch_panel_fitting(struct intel_crtc *crtc, 1193 struct intel_crtc_state *pipe_config, 1194 int fitting_mode); 1195 void intel_panel_set_backlight_acpi(struct intel_connector *connector, 1196 u32 level, u32 max); 1197 int intel_panel_setup_backlight(struct drm_connector *connector, enum i915_pipe pipe); 1198 void intel_panel_enable_backlight(struct intel_connector *connector); 1199 void intel_panel_disable_backlight(struct intel_connector *connector); 1200 void intel_panel_destroy_backlight(struct drm_connector *connector); 1201 void intel_panel_init_backlight_funcs(struct drm_device *dev); 1202 enum drm_connector_status intel_panel_detect(struct drm_device *dev); 1203 extern struct drm_display_mode *intel_find_panel_downclock( 1204 struct drm_device *dev, 1205 struct drm_display_mode *fixed_mode, 1206 struct drm_connector *connector); 1207 void intel_backlight_register(struct drm_device *dev); 1208 void intel_backlight_unregister(struct drm_device *dev); 1209 1210 1211 /* intel_psr.c */ 1212 void intel_psr_enable(struct intel_dp *intel_dp); 1213 void intel_psr_disable(struct intel_dp *intel_dp); 1214 void intel_psr_invalidate(struct drm_device *dev, 1215 unsigned frontbuffer_bits); 1216 void intel_psr_flush(struct drm_device *dev, 1217 unsigned frontbuffer_bits); 1218 void intel_psr_init(struct drm_device *dev); 1219 1220 /* intel_runtime_pm.c */ 1221 int intel_power_domains_init(struct drm_i915_private *); 1222 void intel_power_domains_fini(struct drm_i915_private *); 1223 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); 1224 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); 1225 1226 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 1227 enum intel_display_power_domain domain); 1228 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 1229 enum intel_display_power_domain domain); 1230 void intel_display_power_get(struct drm_i915_private *dev_priv, 1231 enum intel_display_power_domain domain); 1232 void intel_display_power_put(struct drm_i915_private *dev_priv, 1233 enum intel_display_power_domain domain); 1234 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); 1235 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); 1236 void intel_runtime_pm_get(struct drm_i915_private *dev_priv); 1237 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); 1238 void intel_runtime_pm_put(struct drm_i915_private *dev_priv); 1239 1240 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); 1241 1242 /* intel_pm.c */ 1243 void intel_init_clock_gating(struct drm_device *dev); 1244 void intel_suspend_hw(struct drm_device *dev); 1245 int ilk_wm_max_level(const struct drm_device *dev); 1246 void intel_update_watermarks(struct drm_crtc *crtc); 1247 void intel_update_sprite_watermarks(struct drm_plane *plane, 1248 struct drm_crtc *crtc, 1249 uint32_t sprite_width, 1250 uint32_t sprite_height, 1251 int pixel_size, 1252 bool enabled, bool scaled); 1253 void intel_init_pm(struct drm_device *dev); 1254 void intel_pm_setup(struct drm_device *dev); 1255 void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 1256 void intel_gpu_ips_teardown(void); 1257 void intel_init_gt_powersave(struct drm_device *dev); 1258 void intel_cleanup_gt_powersave(struct drm_device *dev); 1259 void intel_enable_gt_powersave(struct drm_device *dev); 1260 void intel_disable_gt_powersave(struct drm_device *dev); 1261 void intel_suspend_gt_powersave(struct drm_device *dev); 1262 void intel_reset_gt_powersave(struct drm_device *dev); 1263 void gen6_update_ring_freq(struct drm_device *dev); 1264 void gen6_rps_busy(struct drm_i915_private *dev_priv); 1265 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); 1266 void gen6_rps_idle(struct drm_i915_private *dev_priv); 1267 void gen6_rps_boost(struct drm_i915_private *dev_priv); 1268 void ilk_wm_get_hw_state(struct drm_device *dev); 1269 void skl_wm_get_hw_state(struct drm_device *dev); 1270 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 1271 struct skl_ddb_allocation *ddb /* out */); 1272 1273 1274 /* intel_sdvo.c */ 1275 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); 1276 1277 1278 /* intel_sprite.c */ 1279 int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane); 1280 void intel_flush_primary_plane(struct drm_i915_private *dev_priv, 1281 enum plane plane); 1282 int intel_plane_restore(struct drm_plane *plane); 1283 int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 1284 struct drm_file *file_priv); 1285 bool intel_pipe_update_start(struct intel_crtc *crtc, 1286 uint32_t *start_vbl_count); 1287 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); 1288 void intel_post_enable_primary(struct drm_crtc *crtc); 1289 void intel_pre_disable_primary(struct drm_crtc *crtc); 1290 1291 /* intel_tv.c */ 1292 void intel_tv_init(struct drm_device *dev); 1293 1294 /* intel_atomic.c */ 1295 int intel_atomic_check(struct drm_device *dev, 1296 struct drm_atomic_state *state); 1297 int intel_atomic_commit(struct drm_device *dev, 1298 struct drm_atomic_state *state, 1299 bool async); 1300 int intel_connector_atomic_get_property(struct drm_connector *connector, 1301 const struct drm_connector_state *state, 1302 struct drm_property *property, 1303 uint64_t *val); 1304 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); 1305 void intel_crtc_destroy_state(struct drm_crtc *crtc, 1306 struct drm_crtc_state *state); 1307 static inline struct intel_crtc_state * 1308 intel_atomic_get_crtc_state(struct drm_atomic_state *state, 1309 struct intel_crtc *crtc) 1310 { 1311 struct drm_crtc_state *crtc_state; 1312 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); 1313 if (IS_ERR(crtc_state)) 1314 return ERR_PTR(PTR_ERR(crtc_state)); 1315 1316 return to_intel_crtc_state(crtc_state); 1317 } 1318 1319 /* intel_atomic_plane.c */ 1320 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); 1321 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); 1322 void intel_plane_destroy_state(struct drm_plane *plane, 1323 struct drm_plane_state *state); 1324 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; 1325 1326 #endif /* __INTEL_DRV_H__ */ 1327