1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Shobhit Kumar <shobhit.kumar@intel.com> 25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> 26 */ 27 28 #include <linux/kernel.h> 29 #include "intel_drv.h" 30 #include "i915_drv.h" 31 #include "intel_dsi.h" 32 33 #define DSI_HSS_PACKET_SIZE 4 34 #define DSI_HSE_PACKET_SIZE 4 35 #define DSI_HSA_PACKET_EXTRA_SIZE 6 36 #define DSI_HBP_PACKET_EXTRA_SIZE 6 37 #define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 38 #define DSI_HFP_PACKET_EXTRA_SIZE 6 39 #define DSI_EOTP_PACKET_SIZE 4 40 41 struct dsi_mnp { 42 u32 dsi_pll_ctrl; 43 u32 dsi_pll_div; 44 }; 45 46 static const u32 lfsr_converts[] = { 47 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ 48 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ 49 106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */ 50 71, 35 /* 91 - 92 */ 51 }; 52 53 #ifdef DSI_CLK_FROM_RR 54 55 static u32 dsi_rr_formula(const struct drm_display_mode *mode, 56 int pixel_format, int video_mode_format, 57 int lane_count, bool eotp) 58 { 59 u32 bpp; 60 u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; 61 u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; 62 u32 bytes_per_line, bytes_per_frame; 63 u32 num_frames; 64 u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; 65 u32 dsi_bit_clock_hz; 66 u32 dsi_clk; 67 68 switch (pixel_format) { 69 default: 70 case VID_MODE_FORMAT_RGB888: 71 case VID_MODE_FORMAT_RGB666_LOOSE: 72 bpp = 24; 73 break; 74 case VID_MODE_FORMAT_RGB666: 75 bpp = 18; 76 break; 77 case VID_MODE_FORMAT_RGB565: 78 bpp = 16; 79 break; 80 } 81 82 hactive = mode->hdisplay; 83 vactive = mode->vdisplay; 84 hfp = mode->hsync_start - mode->hdisplay; 85 hsync = mode->hsync_end - mode->hsync_start; 86 hbp = mode->htotal - mode->hsync_end; 87 88 vfp = mode->vsync_start - mode->vdisplay; 89 vsync = mode->vsync_end - mode->vsync_start; 90 vbp = mode->vtotal - mode->vsync_end; 91 92 hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); 93 hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); 94 hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); 95 hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); 96 97 bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + 98 DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + 99 hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + 100 hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + 101 hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; 102 103 /* 104 * XXX: Need to accurately calculate LP to HS transition timeout and add 105 * it to bytes_per_line/bytes_per_frame. 106 */ 107 108 if (eotp && video_mode_format == VIDEO_MODE_BURST) 109 bytes_per_line += DSI_EOTP_PACKET_SIZE; 110 111 bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + 112 vactive * bytes_per_line + vfp * bytes_per_line; 113 114 if (eotp && 115 (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || 116 video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) 117 bytes_per_frame += DSI_EOTP_PACKET_SIZE; 118 119 num_frames = drm_mode_vrefresh(mode); 120 bytes_per_x_frames = num_frames * bytes_per_frame; 121 122 bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; 123 124 /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ 125 dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; 126 dsi_clk = dsi_bit_clock_hz / 1000; 127 128 if (eotp && video_mode_format == VIDEO_MODE_BURST) 129 dsi_clk *= 2; 130 131 return dsi_clk; 132 } 133 134 #else 135 136 /* Get DSI clock from pixel clock */ 137 static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) 138 { 139 u32 dsi_clk_khz; 140 u32 bpp; 141 142 switch (pixel_format) { 143 default: 144 case VID_MODE_FORMAT_RGB888: 145 case VID_MODE_FORMAT_RGB666_LOOSE: 146 bpp = 24; 147 break; 148 case VID_MODE_FORMAT_RGB666: 149 bpp = 18; 150 break; 151 case VID_MODE_FORMAT_RGB565: 152 bpp = 16; 153 break; 154 } 155 156 /* DSI data rate = pixel clock * bits per pixel / lane count 157 pixel clock is converted from KHz to Hz */ 158 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); 159 160 return dsi_clk_khz; 161 } 162 163 #endif 164 165 static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) 166 { 167 u32 m, n, p; 168 u32 ref_clk; 169 u32 error; 170 u32 tmp_error; 171 int target_dsi_clk; 172 int calc_dsi_clk; 173 u32 calc_m; 174 u32 calc_p; 175 u32 m_seed; 176 177 /* dsi_clk is expected in KHZ */ 178 if (dsi_clk < 300000 || dsi_clk > 1150000) { 179 DRM_ERROR("DSI CLK Out of Range\n"); 180 return -ECHRNG; 181 } 182 183 ref_clk = 25000; 184 target_dsi_clk = dsi_clk; 185 error = 0xFFFFFFFF; 186 tmp_error = 0xFFFFFFFF; 187 calc_m = 0; 188 calc_p = 0; 189 190 for (m = 62; m <= 92; m++) { 191 for (p = 2; p <= 6; p++) { 192 /* Find the optimal m and p divisors 193 with minimal error +/- the required clock */ 194 calc_dsi_clk = (m * ref_clk) / p; 195 if (calc_dsi_clk == target_dsi_clk) { 196 calc_m = m; 197 calc_p = p; 198 error = 0; 199 break; 200 } else 201 tmp_error = abs(target_dsi_clk - calc_dsi_clk); 202 203 if (tmp_error < error) { 204 error = tmp_error; 205 calc_m = m; 206 calc_p = p; 207 } 208 } 209 210 if (error == 0) 211 break; 212 } 213 214 m_seed = lfsr_converts[calc_m - 62]; 215 n = 1; 216 dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); 217 dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT | 218 m_seed << DSI_PLL_M1_DIV_SHIFT; 219 220 return 0; 221 } 222 223 /* 224 * XXX: The muxing and gating is hard coded for now. Need to add support for 225 * sharing PLLs with two DSI outputs. 226 */ 227 static void vlv_configure_dsi_pll(struct intel_encoder *encoder) 228 { 229 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 230 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 231 int ret; 232 struct dsi_mnp dsi_mnp; 233 u32 dsi_clk; 234 235 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 236 intel_dsi->lane_count); 237 238 ret = dsi_calc_mnp(dsi_clk, &dsi_mnp); 239 if (ret) { 240 DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); 241 return; 242 } 243 244 if (intel_dsi->ports & (1 << PORT_A)) 245 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; 246 247 if (intel_dsi->ports & (1 << PORT_C)) 248 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; 249 250 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", 251 dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); 252 253 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); 254 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); 255 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); 256 } 257 258 void vlv_enable_dsi_pll(struct intel_encoder *encoder) 259 { 260 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 261 u32 tmp; 262 263 DRM_DEBUG_KMS("\n"); 264 265 mutex_lock(&dev_priv->dpio_lock); 266 267 vlv_configure_dsi_pll(encoder); 268 269 /* wait at least 0.5 us after ungating before enabling VCO */ 270 usleep_range(1, 10); 271 272 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 273 tmp |= DSI_PLL_VCO_EN; 274 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 275 276 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & 277 DSI_PLL_LOCK, 20)) { 278 279 mutex_unlock(&dev_priv->dpio_lock); 280 DRM_ERROR("DSI PLL lock failed\n"); 281 return; 282 } 283 mutex_unlock(&dev_priv->dpio_lock); 284 285 DRM_DEBUG_KMS("DSI PLL locked\n"); 286 } 287 288 void vlv_disable_dsi_pll(struct intel_encoder *encoder) 289 { 290 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 291 u32 tmp; 292 293 DRM_DEBUG_KMS("\n"); 294 295 mutex_lock(&dev_priv->dpio_lock); 296 297 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 298 tmp &= ~DSI_PLL_VCO_EN; 299 tmp |= DSI_PLL_LDO_GATE; 300 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 301 302 mutex_unlock(&dev_priv->dpio_lock); 303 } 304 305 static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) 306 { 307 int bpp; 308 309 switch (pixel_format) { 310 default: 311 case VID_MODE_FORMAT_RGB888: 312 case VID_MODE_FORMAT_RGB666_LOOSE: 313 bpp = 24; 314 break; 315 case VID_MODE_FORMAT_RGB666: 316 bpp = 18; 317 break; 318 case VID_MODE_FORMAT_RGB565: 319 bpp = 16; 320 break; 321 } 322 323 WARN(bpp != pipe_bpp, 324 "bpp match assertion failure (expected %d, current %d)\n", 325 bpp, pipe_bpp); 326 } 327 328 u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) 329 { 330 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 332 u32 dsi_clock, pclk; 333 u32 pll_ctl, pll_div; 334 u32 m = 0, p = 0; 335 int refclk = 25000; 336 int i; 337 338 DRM_DEBUG_KMS("\n"); 339 340 mutex_lock(&dev_priv->dpio_lock); 341 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 342 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); 343 mutex_unlock(&dev_priv->dpio_lock); 344 345 /* mask out other bits and extract the P1 divisor */ 346 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; 347 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); 348 349 /* mask out the other bits and extract the M1 divisor */ 350 pll_div &= DSI_PLL_M1_DIV_MASK; 351 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; 352 353 while (pll_ctl) { 354 pll_ctl = pll_ctl >> 1; 355 p++; 356 } 357 p--; 358 359 if (!p) { 360 DRM_ERROR("wrong P1 divisor\n"); 361 return 0; 362 } 363 364 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { 365 if (lfsr_converts[i] == pll_div) 366 break; 367 } 368 369 if (i == ARRAY_SIZE(lfsr_converts)) { 370 DRM_ERROR("wrong m_seed programmed\n"); 371 return 0; 372 } 373 374 m = i + 62; 375 376 dsi_clock = (m * refclk) / p; 377 378 /* pixel_format and pipe_bpp should agree */ 379 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); 380 381 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); 382 383 return pclk; 384 } 385