1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/delay.h> 31 #include <linux/hdmi.h> 32 #include <drm/drmP.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include "intel_drv.h" 37 #include <drm/i915_drm.h> 38 #include "i915_drv.h" 39 40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 41 { 42 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 43 } 44 45 static void 46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 47 { 48 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 49 struct drm_i915_private *dev_priv = dev->dev_private; 50 uint32_t enabled_bits; 51 52 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 53 54 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 55 "HDMI port enabled, expecting disabled\n"); 56 } 57 58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 59 { 60 struct intel_digital_port *intel_dig_port = 61 container_of(encoder, struct intel_digital_port, base.base); 62 return &intel_dig_port->hdmi; 63 } 64 65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 66 { 67 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 68 } 69 70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) 71 { 72 switch (type) { 73 case HDMI_INFOFRAME_TYPE_AVI: 74 return VIDEO_DIP_SELECT_AVI; 75 case HDMI_INFOFRAME_TYPE_SPD: 76 return VIDEO_DIP_SELECT_SPD; 77 case HDMI_INFOFRAME_TYPE_VENDOR: 78 return VIDEO_DIP_SELECT_VENDOR; 79 default: 80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 81 return 0; 82 } 83 } 84 85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) 86 { 87 switch (type) { 88 case HDMI_INFOFRAME_TYPE_AVI: 89 return VIDEO_DIP_ENABLE_AVI; 90 case HDMI_INFOFRAME_TYPE_SPD: 91 return VIDEO_DIP_ENABLE_SPD; 92 case HDMI_INFOFRAME_TYPE_VENDOR: 93 return VIDEO_DIP_ENABLE_VENDOR; 94 default: 95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 96 return 0; 97 } 98 } 99 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) 101 { 102 switch (type) { 103 case HDMI_INFOFRAME_TYPE_AVI: 104 return VIDEO_DIP_ENABLE_AVI_HSW; 105 case HDMI_INFOFRAME_TYPE_SPD: 106 return VIDEO_DIP_ENABLE_SPD_HSW; 107 case HDMI_INFOFRAME_TYPE_VENDOR: 108 return VIDEO_DIP_ENABLE_VS_HSW; 109 default: 110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 111 return 0; 112 } 113 } 114 115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, 116 enum transcoder cpu_transcoder, 117 struct drm_i915_private *dev_priv) 118 { 119 switch (type) { 120 case HDMI_INFOFRAME_TYPE_AVI: 121 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); 122 case HDMI_INFOFRAME_TYPE_SPD: 123 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); 124 case HDMI_INFOFRAME_TYPE_VENDOR: 125 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); 126 default: 127 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 128 return 0; 129 } 130 } 131 132 static void g4x_write_infoframe(struct drm_encoder *encoder, 133 enum hdmi_infoframe_type type, 134 const void *frame, ssize_t len) 135 { 136 const uint32_t *data = frame; 137 struct drm_device *dev = encoder->dev; 138 struct drm_i915_private *dev_priv = dev->dev_private; 139 u32 val = I915_READ(VIDEO_DIP_CTL); 140 int i; 141 142 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 143 144 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 145 val |= g4x_infoframe_index(type); 146 147 val &= ~g4x_infoframe_enable(type); 148 149 I915_WRITE(VIDEO_DIP_CTL, val); 150 151 mmiowb(); 152 for (i = 0; i < len; i += 4) { 153 I915_WRITE(VIDEO_DIP_DATA, *data); 154 data++; 155 } 156 /* Write every possible data byte to force correct ECC calculation. */ 157 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 158 I915_WRITE(VIDEO_DIP_DATA, 0); 159 mmiowb(); 160 161 val |= g4x_infoframe_enable(type); 162 val &= ~VIDEO_DIP_FREQ_MASK; 163 val |= VIDEO_DIP_FREQ_VSYNC; 164 165 I915_WRITE(VIDEO_DIP_CTL, val); 166 POSTING_READ(VIDEO_DIP_CTL); 167 } 168 169 static bool g4x_infoframe_enabled(struct drm_encoder *encoder) 170 { 171 struct drm_device *dev = encoder->dev; 172 struct drm_i915_private *dev_priv = dev->dev_private; 173 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 174 u32 val = I915_READ(VIDEO_DIP_CTL); 175 176 if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) 177 return val & VIDEO_DIP_ENABLE; 178 179 return false; 180 } 181 182 static void ibx_write_infoframe(struct drm_encoder *encoder, 183 enum hdmi_infoframe_type type, 184 const void *frame, ssize_t len) 185 { 186 const uint32_t *data = frame; 187 struct drm_device *dev = encoder->dev; 188 struct drm_i915_private *dev_priv = dev->dev_private; 189 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 190 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 191 u32 val = I915_READ(reg); 192 193 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 194 195 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 196 val |= g4x_infoframe_index(type); 197 198 val &= ~g4x_infoframe_enable(type); 199 200 I915_WRITE(reg, val); 201 202 mmiowb(); 203 for (i = 0; i < len; i += 4) { 204 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 205 data++; 206 } 207 /* Write every possible data byte to force correct ECC calculation. */ 208 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 209 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 210 mmiowb(); 211 212 val |= g4x_infoframe_enable(type); 213 val &= ~VIDEO_DIP_FREQ_MASK; 214 val |= VIDEO_DIP_FREQ_VSYNC; 215 216 I915_WRITE(reg, val); 217 POSTING_READ(reg); 218 } 219 220 static bool ibx_infoframe_enabled(struct drm_encoder *encoder) 221 { 222 struct drm_device *dev = encoder->dev; 223 struct drm_i915_private *dev_priv = dev->dev_private; 224 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 225 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 226 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 227 u32 val = I915_READ(reg); 228 229 if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) 230 return val & VIDEO_DIP_ENABLE; 231 232 return false; 233 } 234 235 static void cpt_write_infoframe(struct drm_encoder *encoder, 236 enum hdmi_infoframe_type type, 237 const void *frame, ssize_t len) 238 { 239 const uint32_t *data = frame; 240 struct drm_device *dev = encoder->dev; 241 struct drm_i915_private *dev_priv = dev->dev_private; 242 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 243 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 244 u32 val = I915_READ(reg); 245 246 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 247 248 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 249 val |= g4x_infoframe_index(type); 250 251 /* The DIP control register spec says that we need to update the AVI 252 * infoframe without clearing its enable bit */ 253 if (type != HDMI_INFOFRAME_TYPE_AVI) 254 val &= ~g4x_infoframe_enable(type); 255 256 I915_WRITE(reg, val); 257 258 mmiowb(); 259 for (i = 0; i < len; i += 4) { 260 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 261 data++; 262 } 263 /* Write every possible data byte to force correct ECC calculation. */ 264 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 265 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 266 mmiowb(); 267 268 val |= g4x_infoframe_enable(type); 269 val &= ~VIDEO_DIP_FREQ_MASK; 270 val |= VIDEO_DIP_FREQ_VSYNC; 271 272 I915_WRITE(reg, val); 273 POSTING_READ(reg); 274 } 275 276 static bool cpt_infoframe_enabled(struct drm_encoder *encoder) 277 { 278 struct drm_device *dev = encoder->dev; 279 struct drm_i915_private *dev_priv = dev->dev_private; 280 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 281 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 282 u32 val = I915_READ(reg); 283 284 return val & VIDEO_DIP_ENABLE; 285 } 286 287 static void vlv_write_infoframe(struct drm_encoder *encoder, 288 enum hdmi_infoframe_type type, 289 const void *frame, ssize_t len) 290 { 291 const uint32_t *data = frame; 292 struct drm_device *dev = encoder->dev; 293 struct drm_i915_private *dev_priv = dev->dev_private; 294 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 295 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 296 u32 val = I915_READ(reg); 297 298 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 299 300 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 301 val |= g4x_infoframe_index(type); 302 303 val &= ~g4x_infoframe_enable(type); 304 305 I915_WRITE(reg, val); 306 307 mmiowb(); 308 for (i = 0; i < len; i += 4) { 309 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 310 data++; 311 } 312 /* Write every possible data byte to force correct ECC calculation. */ 313 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 314 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 315 mmiowb(); 316 317 val |= g4x_infoframe_enable(type); 318 val &= ~VIDEO_DIP_FREQ_MASK; 319 val |= VIDEO_DIP_FREQ_VSYNC; 320 321 I915_WRITE(reg, val); 322 POSTING_READ(reg); 323 } 324 325 static bool vlv_infoframe_enabled(struct drm_encoder *encoder) 326 { 327 struct drm_device *dev = encoder->dev; 328 struct drm_i915_private *dev_priv = dev->dev_private; 329 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 330 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 331 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 332 u32 val = I915_READ(reg); 333 334 if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) 335 return val & VIDEO_DIP_ENABLE; 336 337 return false; 338 } 339 340 static void hsw_write_infoframe(struct drm_encoder *encoder, 341 enum hdmi_infoframe_type type, 342 const void *frame, ssize_t len) 343 { 344 const uint32_t *data = frame; 345 struct drm_device *dev = encoder->dev; 346 struct drm_i915_private *dev_priv = dev->dev_private; 347 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 348 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 349 u32 data_reg; 350 int i; 351 u32 val = I915_READ(ctl_reg); 352 353 data_reg = hsw_infoframe_data_reg(type, 354 intel_crtc->config->cpu_transcoder, 355 dev_priv); 356 if (data_reg == 0) 357 return; 358 359 val &= ~hsw_infoframe_enable(type); 360 I915_WRITE(ctl_reg, val); 361 362 mmiowb(); 363 for (i = 0; i < len; i += 4) { 364 I915_WRITE(data_reg + i, *data); 365 data++; 366 } 367 /* Write every possible data byte to force correct ECC calculation. */ 368 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 369 I915_WRITE(data_reg + i, 0); 370 mmiowb(); 371 372 val |= hsw_infoframe_enable(type); 373 I915_WRITE(ctl_reg, val); 374 POSTING_READ(ctl_reg); 375 } 376 377 static bool hsw_infoframe_enabled(struct drm_encoder *encoder) 378 { 379 struct drm_device *dev = encoder->dev; 380 struct drm_i915_private *dev_priv = dev->dev_private; 381 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 382 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 383 u32 val = I915_READ(ctl_reg); 384 385 return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 386 VIDEO_DIP_ENABLE_VS_HSW); 387 } 388 389 /* 390 * The data we write to the DIP data buffer registers is 1 byte bigger than the 391 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 392 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 393 * used for both technologies. 394 * 395 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 396 * DW1: DB3 | DB2 | DB1 | DB0 397 * DW2: DB7 | DB6 | DB5 | DB4 398 * DW3: ... 399 * 400 * (HB is Header Byte, DB is Data Byte) 401 * 402 * The hdmi pack() functions don't know about that hardware specific hole so we 403 * trick them by giving an offset into the buffer and moving back the header 404 * bytes by one. 405 */ 406 static void intel_write_infoframe(struct drm_encoder *encoder, 407 union hdmi_infoframe *frame) 408 { 409 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 410 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 411 ssize_t len; 412 413 /* see comment above for the reason for this offset */ 414 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 415 if (len < 0) 416 return; 417 418 /* Insert the 'hole' (see big comment above) at position 3 */ 419 buffer[0] = buffer[1]; 420 buffer[1] = buffer[2]; 421 buffer[2] = buffer[3]; 422 buffer[3] = 0; 423 len++; 424 425 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); 426 } 427 428 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 429 struct drm_display_mode *adjusted_mode) 430 { 431 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 432 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 433 union hdmi_infoframe frame; 434 int ret; 435 436 /* Set user selected PAR to incoming mode's member */ 437 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; 438 439 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 440 adjusted_mode); 441 if (ret < 0) { 442 DRM_ERROR("couldn't fill AVI infoframe\n"); 443 return; 444 } 445 446 if (intel_hdmi->rgb_quant_range_selectable) { 447 if (intel_crtc->config->limited_color_range) 448 frame.avi.quantization_range = 449 HDMI_QUANTIZATION_RANGE_LIMITED; 450 else 451 frame.avi.quantization_range = 452 HDMI_QUANTIZATION_RANGE_FULL; 453 } 454 455 intel_write_infoframe(encoder, &frame); 456 } 457 458 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 459 { 460 union hdmi_infoframe frame; 461 int ret; 462 463 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 464 if (ret < 0) { 465 DRM_ERROR("couldn't fill SPD infoframe\n"); 466 return; 467 } 468 469 frame.spd.sdi = HDMI_SPD_SDI_PC; 470 471 intel_write_infoframe(encoder, &frame); 472 } 473 474 static void 475 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 476 struct drm_display_mode *adjusted_mode) 477 { 478 union hdmi_infoframe frame; 479 int ret; 480 481 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 482 adjusted_mode); 483 if (ret < 0) 484 return; 485 486 intel_write_infoframe(encoder, &frame); 487 } 488 489 static void g4x_set_infoframes(struct drm_encoder *encoder, 490 bool enable, 491 struct drm_display_mode *adjusted_mode) 492 { 493 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 494 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 495 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 496 u32 reg = VIDEO_DIP_CTL; 497 u32 val = I915_READ(reg); 498 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 499 500 assert_hdmi_port_disabled(intel_hdmi); 501 502 /* If the registers were not initialized yet, they might be zeroes, 503 * which means we're selecting the AVI DIP and we're setting its 504 * frequency to once. This seems to really confuse the HW and make 505 * things stop working (the register spec says the AVI always needs to 506 * be sent every VSync). So here we avoid writing to the register more 507 * than we need and also explicitly select the AVI DIP and explicitly 508 * set its frequency to every VSync. Avoiding to write it twice seems to 509 * be enough to solve the problem, but being defensive shouldn't hurt us 510 * either. */ 511 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 512 513 if (!enable) { 514 if (!(val & VIDEO_DIP_ENABLE)) 515 return; 516 val &= ~VIDEO_DIP_ENABLE; 517 I915_WRITE(reg, val); 518 POSTING_READ(reg); 519 return; 520 } 521 522 if (port != (val & VIDEO_DIP_PORT_MASK)) { 523 if (val & VIDEO_DIP_ENABLE) { 524 val &= ~VIDEO_DIP_ENABLE; 525 I915_WRITE(reg, val); 526 POSTING_READ(reg); 527 } 528 val &= ~VIDEO_DIP_PORT_MASK; 529 val |= port; 530 } 531 532 val |= VIDEO_DIP_ENABLE; 533 val &= ~VIDEO_DIP_ENABLE_VENDOR; 534 535 I915_WRITE(reg, val); 536 POSTING_READ(reg); 537 538 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 539 intel_hdmi_set_spd_infoframe(encoder); 540 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 541 } 542 543 static void ibx_set_infoframes(struct drm_encoder *encoder, 544 bool enable, 545 struct drm_display_mode *adjusted_mode) 546 { 547 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 548 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 549 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 550 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 551 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 552 u32 val = I915_READ(reg); 553 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 554 555 assert_hdmi_port_disabled(intel_hdmi); 556 557 /* See the big comment in g4x_set_infoframes() */ 558 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 559 560 if (!enable) { 561 if (!(val & VIDEO_DIP_ENABLE)) 562 return; 563 val &= ~VIDEO_DIP_ENABLE; 564 I915_WRITE(reg, val); 565 POSTING_READ(reg); 566 return; 567 } 568 569 if (port != (val & VIDEO_DIP_PORT_MASK)) { 570 if (val & VIDEO_DIP_ENABLE) { 571 val &= ~VIDEO_DIP_ENABLE; 572 I915_WRITE(reg, val); 573 POSTING_READ(reg); 574 } 575 val &= ~VIDEO_DIP_PORT_MASK; 576 val |= port; 577 } 578 579 val |= VIDEO_DIP_ENABLE; 580 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 581 VIDEO_DIP_ENABLE_GCP); 582 583 I915_WRITE(reg, val); 584 POSTING_READ(reg); 585 586 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 587 intel_hdmi_set_spd_infoframe(encoder); 588 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 589 } 590 591 static void cpt_set_infoframes(struct drm_encoder *encoder, 592 bool enable, 593 struct drm_display_mode *adjusted_mode) 594 { 595 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 596 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 597 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 598 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 599 u32 val = I915_READ(reg); 600 601 assert_hdmi_port_disabled(intel_hdmi); 602 603 /* See the big comment in g4x_set_infoframes() */ 604 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 605 606 if (!enable) { 607 if (!(val & VIDEO_DIP_ENABLE)) 608 return; 609 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); 610 I915_WRITE(reg, val); 611 POSTING_READ(reg); 612 return; 613 } 614 615 /* Set both together, unset both together: see the spec. */ 616 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 617 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 618 VIDEO_DIP_ENABLE_GCP); 619 620 I915_WRITE(reg, val); 621 POSTING_READ(reg); 622 623 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 624 intel_hdmi_set_spd_infoframe(encoder); 625 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 626 } 627 628 static void vlv_set_infoframes(struct drm_encoder *encoder, 629 bool enable, 630 struct drm_display_mode *adjusted_mode) 631 { 632 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 633 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 634 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 635 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 636 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 637 u32 val = I915_READ(reg); 638 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 639 640 assert_hdmi_port_disabled(intel_hdmi); 641 642 /* See the big comment in g4x_set_infoframes() */ 643 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 644 645 if (!enable) { 646 if (!(val & VIDEO_DIP_ENABLE)) 647 return; 648 val &= ~VIDEO_DIP_ENABLE; 649 I915_WRITE(reg, val); 650 POSTING_READ(reg); 651 return; 652 } 653 654 if (port != (val & VIDEO_DIP_PORT_MASK)) { 655 if (val & VIDEO_DIP_ENABLE) { 656 val &= ~VIDEO_DIP_ENABLE; 657 I915_WRITE(reg, val); 658 POSTING_READ(reg); 659 } 660 val &= ~VIDEO_DIP_PORT_MASK; 661 val |= port; 662 } 663 664 val |= VIDEO_DIP_ENABLE; 665 val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | 666 VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); 667 668 I915_WRITE(reg, val); 669 POSTING_READ(reg); 670 671 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 672 intel_hdmi_set_spd_infoframe(encoder); 673 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 674 } 675 676 static void hsw_set_infoframes(struct drm_encoder *encoder, 677 bool enable, 678 struct drm_display_mode *adjusted_mode) 679 { 680 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 681 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 682 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 683 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 684 u32 val = I915_READ(reg); 685 686 assert_hdmi_port_disabled(intel_hdmi); 687 688 if (!enable) { 689 I915_WRITE(reg, 0); 690 POSTING_READ(reg); 691 return; 692 } 693 694 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 695 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); 696 697 I915_WRITE(reg, val); 698 POSTING_READ(reg); 699 700 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 701 intel_hdmi_set_spd_infoframe(encoder); 702 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 703 } 704 705 static void intel_hdmi_prepare(struct intel_encoder *encoder) 706 { 707 struct drm_device *dev = encoder->base.dev; 708 struct drm_i915_private *dev_priv = dev->dev_private; 709 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 710 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 711 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 712 u32 hdmi_val; 713 714 hdmi_val = SDVO_ENCODING_HDMI; 715 if (!HAS_PCH_SPLIT(dev)) 716 hdmi_val |= intel_hdmi->color_range; 717 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 718 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 719 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 720 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 721 722 if (crtc->config->pipe_bpp > 24) 723 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 724 else 725 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 726 727 if (crtc->config->has_hdmi_sink) 728 hdmi_val |= HDMI_MODE_SELECT_HDMI; 729 730 if (HAS_PCH_CPT(dev)) 731 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 732 else if (IS_CHERRYVIEW(dev)) 733 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 734 else 735 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 736 737 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 738 POSTING_READ(intel_hdmi->hdmi_reg); 739 } 740 741 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 742 enum i915_pipe *pipe) 743 { 744 struct drm_device *dev = encoder->base.dev; 745 struct drm_i915_private *dev_priv = dev->dev_private; 746 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 747 enum intel_display_power_domain power_domain; 748 u32 tmp; 749 750 power_domain = intel_display_port_power_domain(encoder); 751 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 752 return false; 753 754 tmp = I915_READ(intel_hdmi->hdmi_reg); 755 756 if (!(tmp & SDVO_ENABLE)) 757 return false; 758 759 if (HAS_PCH_CPT(dev)) 760 *pipe = PORT_TO_PIPE_CPT(tmp); 761 else if (IS_CHERRYVIEW(dev)) 762 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 763 else 764 *pipe = PORT_TO_PIPE(tmp); 765 766 return true; 767 } 768 769 static void intel_hdmi_get_config(struct intel_encoder *encoder, 770 struct intel_crtc_state *pipe_config) 771 { 772 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 773 struct drm_device *dev = encoder->base.dev; 774 struct drm_i915_private *dev_priv = dev->dev_private; 775 u32 tmp, flags = 0; 776 int dotclock; 777 778 tmp = I915_READ(intel_hdmi->hdmi_reg); 779 780 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 781 flags |= DRM_MODE_FLAG_PHSYNC; 782 else 783 flags |= DRM_MODE_FLAG_NHSYNC; 784 785 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 786 flags |= DRM_MODE_FLAG_PVSYNC; 787 else 788 flags |= DRM_MODE_FLAG_NVSYNC; 789 790 if (tmp & HDMI_MODE_SELECT_HDMI) 791 pipe_config->has_hdmi_sink = true; 792 793 if (intel_hdmi->infoframe_enabled(&encoder->base)) 794 pipe_config->has_infoframe = true; 795 796 if (tmp & SDVO_AUDIO_ENABLE) 797 pipe_config->has_audio = true; 798 799 if (!HAS_PCH_SPLIT(dev) && 800 tmp & HDMI_COLOR_RANGE_16_235) 801 pipe_config->limited_color_range = true; 802 803 pipe_config->base.adjusted_mode.flags |= flags; 804 805 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 806 dotclock = pipe_config->port_clock * 2 / 3; 807 else 808 dotclock = pipe_config->port_clock; 809 810 if (HAS_PCH_SPLIT(dev_priv->dev)) 811 ironlake_check_encoder_dotclock(pipe_config, dotclock); 812 813 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 814 } 815 816 static void intel_enable_hdmi(struct intel_encoder *encoder) 817 { 818 struct drm_device *dev = encoder->base.dev; 819 struct drm_i915_private *dev_priv = dev->dev_private; 820 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 821 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 822 u32 temp; 823 u32 enable_bits = SDVO_ENABLE; 824 825 if (intel_crtc->config->has_audio) 826 enable_bits |= SDVO_AUDIO_ENABLE; 827 828 temp = I915_READ(intel_hdmi->hdmi_reg); 829 830 /* HW workaround for IBX, we need to move the port to transcoder A 831 * before disabling it, so restore the transcoder select bit here. */ 832 if (HAS_PCH_IBX(dev)) 833 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); 834 835 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 836 * we do this anyway which shows more stable in testing. 837 */ 838 if (HAS_PCH_SPLIT(dev)) { 839 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 840 POSTING_READ(intel_hdmi->hdmi_reg); 841 } 842 843 temp |= enable_bits; 844 845 I915_WRITE(intel_hdmi->hdmi_reg, temp); 846 POSTING_READ(intel_hdmi->hdmi_reg); 847 848 /* HW workaround, need to write this twice for issue that may result 849 * in first write getting masked. 850 */ 851 if (HAS_PCH_SPLIT(dev)) { 852 I915_WRITE(intel_hdmi->hdmi_reg, temp); 853 POSTING_READ(intel_hdmi->hdmi_reg); 854 } 855 856 if (intel_crtc->config->has_audio) { 857 WARN_ON(!intel_crtc->config->has_hdmi_sink); 858 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 859 pipe_name(intel_crtc->pipe)); 860 intel_audio_codec_enable(encoder); 861 } 862 } 863 864 static void vlv_enable_hdmi(struct intel_encoder *encoder) 865 { 866 } 867 868 static void intel_disable_hdmi(struct intel_encoder *encoder) 869 { 870 struct drm_device *dev = encoder->base.dev; 871 struct drm_i915_private *dev_priv = dev->dev_private; 872 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 873 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 874 u32 temp; 875 876 temp = I915_READ(intel_hdmi->hdmi_reg); 877 878 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); 879 I915_WRITE(intel_hdmi->hdmi_reg, temp); 880 POSTING_READ(intel_hdmi->hdmi_reg); 881 882 /* 883 * HW workaround for IBX, we need to move the port 884 * to transcoder A after disabling it to allow the 885 * matching DP port to be enabled on transcoder A. 886 */ 887 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { 888 temp &= ~SDVO_PIPE_B_SELECT; 889 temp |= SDVO_ENABLE; 890 /* 891 * HW workaround, need to write this twice for issue 892 * that may result in first write getting masked. 893 */ 894 I915_WRITE(intel_hdmi->hdmi_reg, temp); 895 POSTING_READ(intel_hdmi->hdmi_reg); 896 I915_WRITE(intel_hdmi->hdmi_reg, temp); 897 POSTING_READ(intel_hdmi->hdmi_reg); 898 899 temp &= ~SDVO_ENABLE; 900 I915_WRITE(intel_hdmi->hdmi_reg, temp); 901 POSTING_READ(intel_hdmi->hdmi_reg); 902 } 903 } 904 905 static void g4x_disable_hdmi(struct intel_encoder *encoder) 906 { 907 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 908 909 if (crtc->config->has_audio) 910 intel_audio_codec_disable(encoder); 911 912 intel_disable_hdmi(encoder); 913 } 914 915 static void pch_disable_hdmi(struct intel_encoder *encoder) 916 { 917 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 918 919 if (crtc->config->has_audio) 920 intel_audio_codec_disable(encoder); 921 } 922 923 static void pch_post_disable_hdmi(struct intel_encoder *encoder) 924 { 925 intel_disable_hdmi(encoder); 926 } 927 928 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) 929 { 930 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 931 932 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) 933 return 165000; 934 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) 935 return 300000; 936 else 937 return 225000; 938 } 939 940 static enum drm_mode_status 941 intel_hdmi_mode_valid(struct drm_connector *connector, 942 struct drm_display_mode *mode) 943 { 944 int clock = mode->clock; 945 946 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 947 clock *= 2; 948 949 if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector), 950 true)) 951 return MODE_CLOCK_HIGH; 952 if (clock < 20000) 953 return MODE_CLOCK_LOW; 954 955 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 956 return MODE_NO_DBLESCAN; 957 958 return MODE_OK; 959 } 960 961 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) 962 { 963 struct drm_device *dev = crtc_state->base.crtc->dev; 964 struct drm_atomic_state *state; 965 struct intel_encoder *encoder; 966 struct drm_connector *connector; 967 struct drm_connector_state *connector_state; 968 int count = 0, count_hdmi = 0; 969 int i; 970 971 if (HAS_GMCH_DISPLAY(dev)) 972 return false; 973 974 state = crtc_state->base.state; 975 976 for_each_connector_in_state(state, connector, connector_state, i) { 977 if (connector_state->crtc != crtc_state->base.crtc) 978 continue; 979 980 encoder = to_intel_encoder(connector_state->best_encoder); 981 982 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; 983 count++; 984 } 985 986 /* 987 * HDMI 12bpc affects the clocks, so it's only possible 988 * when not cloning with other encoder types. 989 */ 990 return count_hdmi > 0 && count_hdmi == count; 991 } 992 993 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 994 struct intel_crtc_state *pipe_config) 995 { 996 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 997 struct drm_device *dev = encoder->base.dev; 998 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 999 int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2; 1000 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); 1001 int desired_bpp; 1002 1003 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; 1004 1005 if (pipe_config->has_hdmi_sink) 1006 pipe_config->has_infoframe = true; 1007 1008 if (intel_hdmi->color_range_auto) { 1009 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1010 if (pipe_config->has_hdmi_sink && 1011 drm_match_cea_mode(adjusted_mode) > 1) 1012 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 1013 else 1014 intel_hdmi->color_range = 0; 1015 } 1016 1017 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { 1018 pipe_config->pixel_multiplier = 2; 1019 } 1020 1021 if (intel_hdmi->color_range) 1022 pipe_config->limited_color_range = true; 1023 1024 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) 1025 pipe_config->has_pch_encoder = true; 1026 1027 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) 1028 pipe_config->has_audio = true; 1029 1030 /* 1031 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 1032 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 1033 * outputs. We also need to check that the higher clock still fits 1034 * within limits. 1035 */ 1036 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && 1037 clock_12bpc <= portclock_limit && 1038 hdmi_12bpc_possible(pipe_config) && 1039 0 /* FIXME 12bpc support totally broken */) { 1040 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 1041 desired_bpp = 12*3; 1042 1043 /* Need to adjust the port link by 1.5x for 12bpc. */ 1044 pipe_config->port_clock = clock_12bpc; 1045 } else { 1046 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 1047 desired_bpp = 8*3; 1048 } 1049 1050 if (!pipe_config->bw_constrained) { 1051 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); 1052 pipe_config->pipe_bpp = desired_bpp; 1053 } 1054 1055 if (adjusted_mode->crtc_clock > portclock_limit) { 1056 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); 1057 return false; 1058 } 1059 1060 return true; 1061 } 1062 1063 static void 1064 intel_hdmi_unset_edid(struct drm_connector *connector) 1065 { 1066 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1067 1068 intel_hdmi->has_hdmi_sink = false; 1069 intel_hdmi->has_audio = false; 1070 intel_hdmi->rgb_quant_range_selectable = false; 1071 1072 kfree(to_intel_connector(connector)->detect_edid); 1073 to_intel_connector(connector)->detect_edid = NULL; 1074 } 1075 1076 static bool 1077 intel_hdmi_set_edid(struct drm_connector *connector) 1078 { 1079 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1080 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1081 struct intel_encoder *intel_encoder = 1082 &hdmi_to_dig_port(intel_hdmi)->base; 1083 enum intel_display_power_domain power_domain; 1084 struct edid *edid; 1085 bool connected = false; 1086 1087 power_domain = intel_display_port_power_domain(intel_encoder); 1088 intel_display_power_get(dev_priv, power_domain); 1089 1090 edid = drm_get_edid(connector, 1091 intel_gmbus_get_adapter(dev_priv, 1092 intel_hdmi->ddc_bus)); 1093 1094 intel_display_power_put(dev_priv, power_domain); 1095 1096 to_intel_connector(connector)->detect_edid = edid; 1097 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 1098 intel_hdmi->rgb_quant_range_selectable = 1099 drm_rgb_quant_range_selectable(edid); 1100 1101 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 1102 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1103 intel_hdmi->has_audio = 1104 intel_hdmi->force_audio == HDMI_AUDIO_ON; 1105 1106 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 1107 intel_hdmi->has_hdmi_sink = 1108 drm_detect_hdmi_monitor(edid); 1109 1110 connected = true; 1111 } 1112 1113 return connected; 1114 } 1115 1116 static enum drm_connector_status 1117 intel_hdmi_detect(struct drm_connector *connector, bool force) 1118 { 1119 enum drm_connector_status status; 1120 1121 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1122 connector->base.id, connector->name); 1123 1124 intel_hdmi_unset_edid(connector); 1125 1126 if (intel_hdmi_set_edid(connector)) { 1127 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1128 1129 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1130 status = connector_status_connected; 1131 } else 1132 status = connector_status_disconnected; 1133 1134 return status; 1135 } 1136 1137 static void 1138 intel_hdmi_force(struct drm_connector *connector) 1139 { 1140 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1141 1142 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1143 connector->base.id, connector->name); 1144 1145 intel_hdmi_unset_edid(connector); 1146 1147 if (connector->status != connector_status_connected) 1148 return; 1149 1150 intel_hdmi_set_edid(connector); 1151 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1152 } 1153 1154 static int intel_hdmi_get_modes(struct drm_connector *connector) 1155 { 1156 struct edid *edid; 1157 1158 edid = to_intel_connector(connector)->detect_edid; 1159 if (edid == NULL) 1160 return 0; 1161 1162 return intel_connector_update_modes(connector, edid); 1163 } 1164 1165 static bool 1166 intel_hdmi_detect_audio(struct drm_connector *connector) 1167 { 1168 bool has_audio = false; 1169 struct edid *edid; 1170 1171 edid = to_intel_connector(connector)->detect_edid; 1172 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) 1173 has_audio = drm_detect_monitor_audio(edid); 1174 1175 return has_audio; 1176 } 1177 1178 static int 1179 intel_hdmi_set_property(struct drm_connector *connector, 1180 struct drm_property *property, 1181 uint64_t val) 1182 { 1183 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1184 struct intel_digital_port *intel_dig_port = 1185 hdmi_to_dig_port(intel_hdmi); 1186 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1187 int ret; 1188 1189 ret = drm_object_property_set_value(&connector->base, property, val); 1190 if (ret) 1191 return ret; 1192 1193 if (property == dev_priv->force_audio_property) { 1194 enum hdmi_force_audio i = val; 1195 bool has_audio; 1196 1197 if (i == intel_hdmi->force_audio) 1198 return 0; 1199 1200 intel_hdmi->force_audio = i; 1201 1202 if (i == HDMI_AUDIO_AUTO) 1203 has_audio = intel_hdmi_detect_audio(connector); 1204 else 1205 has_audio = (i == HDMI_AUDIO_ON); 1206 1207 if (i == HDMI_AUDIO_OFF_DVI) 1208 intel_hdmi->has_hdmi_sink = 0; 1209 1210 intel_hdmi->has_audio = has_audio; 1211 goto done; 1212 } 1213 1214 if (property == dev_priv->broadcast_rgb_property) { 1215 bool old_auto = intel_hdmi->color_range_auto; 1216 uint32_t old_range = intel_hdmi->color_range; 1217 1218 switch (val) { 1219 case INTEL_BROADCAST_RGB_AUTO: 1220 intel_hdmi->color_range_auto = true; 1221 break; 1222 case INTEL_BROADCAST_RGB_FULL: 1223 intel_hdmi->color_range_auto = false; 1224 intel_hdmi->color_range = 0; 1225 break; 1226 case INTEL_BROADCAST_RGB_LIMITED: 1227 intel_hdmi->color_range_auto = false; 1228 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 1229 break; 1230 default: 1231 return -EINVAL; 1232 } 1233 1234 if (old_auto == intel_hdmi->color_range_auto && 1235 old_range == intel_hdmi->color_range) 1236 return 0; 1237 1238 goto done; 1239 } 1240 1241 if (property == connector->dev->mode_config.aspect_ratio_property) { 1242 switch (val) { 1243 case DRM_MODE_PICTURE_ASPECT_NONE: 1244 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1245 break; 1246 case DRM_MODE_PICTURE_ASPECT_4_3: 1247 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 1248 break; 1249 case DRM_MODE_PICTURE_ASPECT_16_9: 1250 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 1251 break; 1252 default: 1253 return -EINVAL; 1254 } 1255 goto done; 1256 } 1257 1258 return -EINVAL; 1259 1260 done: 1261 if (intel_dig_port->base.base.crtc) 1262 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 1263 1264 return 0; 1265 } 1266 1267 static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 1268 { 1269 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1270 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1271 struct drm_display_mode *adjusted_mode = 1272 &intel_crtc->config->base.adjusted_mode; 1273 1274 intel_hdmi_prepare(encoder); 1275 1276 intel_hdmi->set_infoframes(&encoder->base, 1277 intel_crtc->config->has_hdmi_sink, 1278 adjusted_mode); 1279 } 1280 1281 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 1282 { 1283 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1284 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1285 struct drm_device *dev = encoder->base.dev; 1286 struct drm_i915_private *dev_priv = dev->dev_private; 1287 struct intel_crtc *intel_crtc = 1288 to_intel_crtc(encoder->base.crtc); 1289 struct drm_display_mode *adjusted_mode = 1290 &intel_crtc->config->base.adjusted_mode; 1291 enum dpio_channel port = vlv_dport_to_channel(dport); 1292 int pipe = intel_crtc->pipe; 1293 u32 val; 1294 1295 /* Enable clock channels for this port */ 1296 mutex_lock(&dev_priv->sb_lock); 1297 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1298 val = 0; 1299 if (pipe) 1300 val |= (1<<21); 1301 else 1302 val &= ~(1<<21); 1303 val |= 0x001000c4; 1304 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1305 1306 /* HDMI 1.0V-2dB */ 1307 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); 1308 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); 1309 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); 1310 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); 1311 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); 1312 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1313 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1314 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1315 1316 /* Program lane clock */ 1317 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1318 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1319 mutex_unlock(&dev_priv->sb_lock); 1320 1321 intel_hdmi->set_infoframes(&encoder->base, 1322 intel_crtc->config->has_hdmi_sink, 1323 adjusted_mode); 1324 1325 intel_enable_hdmi(encoder); 1326 1327 vlv_wait_port_ready(dev_priv, dport, 0x0); 1328 } 1329 1330 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1331 { 1332 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1333 struct drm_device *dev = encoder->base.dev; 1334 struct drm_i915_private *dev_priv = dev->dev_private; 1335 struct intel_crtc *intel_crtc = 1336 to_intel_crtc(encoder->base.crtc); 1337 enum dpio_channel port = vlv_dport_to_channel(dport); 1338 int pipe = intel_crtc->pipe; 1339 1340 intel_hdmi_prepare(encoder); 1341 1342 /* Program Tx lane resets to default */ 1343 mutex_lock(&dev_priv->sb_lock); 1344 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1345 DPIO_PCS_TX_LANE2_RESET | 1346 DPIO_PCS_TX_LANE1_RESET); 1347 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1348 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1349 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1350 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1351 DPIO_PCS_CLK_SOFT_RESET); 1352 1353 /* Fix up inter-pair skew failure */ 1354 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1355 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1356 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1357 1358 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1359 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1360 mutex_unlock(&dev_priv->sb_lock); 1361 } 1362 1363 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1364 { 1365 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1366 struct drm_device *dev = encoder->base.dev; 1367 struct drm_i915_private *dev_priv = dev->dev_private; 1368 struct intel_crtc *intel_crtc = 1369 to_intel_crtc(encoder->base.crtc); 1370 enum dpio_channel ch = vlv_dport_to_channel(dport); 1371 enum i915_pipe pipe = intel_crtc->pipe; 1372 u32 val; 1373 1374 intel_hdmi_prepare(encoder); 1375 1376 mutex_lock(&dev_priv->sb_lock); 1377 1378 /* program left/right clock distribution */ 1379 if (pipe != PIPE_B) { 1380 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1381 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1382 if (ch == DPIO_CH0) 1383 val |= CHV_BUFLEFTENA1_FORCE; 1384 if (ch == DPIO_CH1) 1385 val |= CHV_BUFRIGHTENA1_FORCE; 1386 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1387 } else { 1388 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1389 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1390 if (ch == DPIO_CH0) 1391 val |= CHV_BUFLEFTENA2_FORCE; 1392 if (ch == DPIO_CH1) 1393 val |= CHV_BUFRIGHTENA2_FORCE; 1394 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1395 } 1396 1397 /* program clock channel usage */ 1398 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 1399 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1400 if (pipe != PIPE_B) 1401 val &= ~CHV_PCS_USEDCLKCHANNEL; 1402 else 1403 val |= CHV_PCS_USEDCLKCHANNEL; 1404 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 1405 1406 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 1407 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1408 if (pipe != PIPE_B) 1409 val &= ~CHV_PCS_USEDCLKCHANNEL; 1410 else 1411 val |= CHV_PCS_USEDCLKCHANNEL; 1412 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 1413 1414 /* 1415 * This a a bit weird since generally CL 1416 * matches the pipe, but here we need to 1417 * pick the CL based on the port. 1418 */ 1419 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 1420 if (pipe != PIPE_B) 1421 val &= ~CHV_CMN_USEDCLKCHANNEL; 1422 else 1423 val |= CHV_CMN_USEDCLKCHANNEL; 1424 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 1425 1426 mutex_unlock(&dev_priv->sb_lock); 1427 } 1428 1429 static void vlv_hdmi_post_disable(struct intel_encoder *encoder) 1430 { 1431 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1432 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1433 struct intel_crtc *intel_crtc = 1434 to_intel_crtc(encoder->base.crtc); 1435 enum dpio_channel port = vlv_dport_to_channel(dport); 1436 int pipe = intel_crtc->pipe; 1437 1438 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1439 mutex_lock(&dev_priv->sb_lock); 1440 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1441 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1442 mutex_unlock(&dev_priv->sb_lock); 1443 } 1444 1445 static void chv_hdmi_post_disable(struct intel_encoder *encoder) 1446 { 1447 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1448 struct drm_device *dev = encoder->base.dev; 1449 struct drm_i915_private *dev_priv = dev->dev_private; 1450 struct intel_crtc *intel_crtc = 1451 to_intel_crtc(encoder->base.crtc); 1452 enum dpio_channel ch = vlv_dport_to_channel(dport); 1453 enum i915_pipe pipe = intel_crtc->pipe; 1454 u32 val; 1455 1456 mutex_lock(&dev_priv->sb_lock); 1457 1458 /* Propagate soft reset to data lane reset */ 1459 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1460 val |= CHV_PCS_REQ_SOFTRESET_EN; 1461 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1462 1463 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1464 val |= CHV_PCS_REQ_SOFTRESET_EN; 1465 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1466 1467 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1468 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1469 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1470 1471 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1472 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1473 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1474 1475 mutex_unlock(&dev_priv->sb_lock); 1476 } 1477 1478 static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 1479 { 1480 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1481 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1482 struct drm_device *dev = encoder->base.dev; 1483 struct drm_i915_private *dev_priv = dev->dev_private; 1484 struct intel_crtc *intel_crtc = 1485 to_intel_crtc(encoder->base.crtc); 1486 struct drm_display_mode *adjusted_mode = 1487 &intel_crtc->config->base.adjusted_mode; 1488 enum dpio_channel ch = vlv_dport_to_channel(dport); 1489 int pipe = intel_crtc->pipe; 1490 int data, i, stagger; 1491 u32 val; 1492 1493 mutex_lock(&dev_priv->sb_lock); 1494 1495 /* allow hardware to manage TX FIFO reset source */ 1496 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1497 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1498 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1499 1500 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1501 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1502 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1503 1504 /* Deassert soft data lane reset*/ 1505 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1506 val |= CHV_PCS_REQ_SOFTRESET_EN; 1507 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1508 1509 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1510 val |= CHV_PCS_REQ_SOFTRESET_EN; 1511 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1512 1513 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1514 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1515 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1516 1517 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1518 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1519 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1520 1521 /* Program Tx latency optimal setting */ 1522 for (i = 0; i < 4; i++) { 1523 /* Set the upar bit */ 1524 data = (i == 1) ? 0x0 : 0x1; 1525 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 1526 data << DPIO_UPAR_SHIFT); 1527 } 1528 1529 /* Data lane stagger programming */ 1530 if (intel_crtc->config->port_clock > 270000) 1531 stagger = 0x18; 1532 else if (intel_crtc->config->port_clock > 135000) 1533 stagger = 0xd; 1534 else if (intel_crtc->config->port_clock > 67500) 1535 stagger = 0x7; 1536 else if (intel_crtc->config->port_clock > 33750) 1537 stagger = 0x4; 1538 else 1539 stagger = 0x2; 1540 1541 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1542 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1543 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1544 1545 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1546 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1547 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1548 1549 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 1550 DPIO_LANESTAGGER_STRAP(stagger) | 1551 DPIO_LANESTAGGER_STRAP_OVRD | 1552 DPIO_TX1_STAGGER_MASK(0x1f) | 1553 DPIO_TX1_STAGGER_MULT(6) | 1554 DPIO_TX2_STAGGER_MULT(0)); 1555 1556 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 1557 DPIO_LANESTAGGER_STRAP(stagger) | 1558 DPIO_LANESTAGGER_STRAP_OVRD | 1559 DPIO_TX1_STAGGER_MASK(0x1f) | 1560 DPIO_TX1_STAGGER_MULT(7) | 1561 DPIO_TX2_STAGGER_MULT(5)); 1562 1563 /* Clear calc init */ 1564 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1565 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1566 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 1567 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 1568 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1569 1570 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1571 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1572 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 1573 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 1574 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1575 1576 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 1577 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 1578 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 1579 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 1580 1581 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 1582 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 1583 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 1584 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 1585 1586 /* FIXME: Program the support xxx V-dB */ 1587 /* Use 800mV-0dB */ 1588 for (i = 0; i < 4; i++) { 1589 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 1590 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 1591 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; 1592 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 1593 } 1594 1595 for (i = 0; i < 4; i++) { 1596 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 1597 val &= ~DPIO_SWING_MARGIN000_MASK; 1598 val |= 102 << DPIO_SWING_MARGIN000_SHIFT; 1599 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 1600 } 1601 1602 /* Disable unique transition scale */ 1603 for (i = 0; i < 4; i++) { 1604 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 1605 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 1606 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 1607 } 1608 1609 /* Additional steps for 1200mV-0dB */ 1610 #if 0 1611 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); 1612 if (ch) 1613 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; 1614 else 1615 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; 1616 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); 1617 1618 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), 1619 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | 1620 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); 1621 #endif 1622 /* Start swing calculation */ 1623 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1624 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1625 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1626 1627 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1628 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1629 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1630 1631 /* LRC Bypass */ 1632 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1633 val |= DPIO_LRC_BYPASS; 1634 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); 1635 1636 mutex_unlock(&dev_priv->sb_lock); 1637 1638 intel_hdmi->set_infoframes(&encoder->base, 1639 intel_crtc->config->has_hdmi_sink, 1640 adjusted_mode); 1641 1642 intel_enable_hdmi(encoder); 1643 1644 vlv_wait_port_ready(dev_priv, dport, 0x0); 1645 } 1646 1647 static void intel_hdmi_destroy(struct drm_connector *connector) 1648 { 1649 kfree(to_intel_connector(connector)->detect_edid); 1650 drm_connector_cleanup(connector); 1651 kfree(connector); 1652 } 1653 1654 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 1655 .dpms = intel_connector_dpms, 1656 .detect = intel_hdmi_detect, 1657 .force = intel_hdmi_force, 1658 .fill_modes = drm_helper_probe_single_connector_modes, 1659 .set_property = intel_hdmi_set_property, 1660 .atomic_get_property = intel_connector_atomic_get_property, 1661 .destroy = intel_hdmi_destroy, 1662 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1663 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1664 }; 1665 1666 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 1667 .get_modes = intel_hdmi_get_modes, 1668 .mode_valid = intel_hdmi_mode_valid, 1669 .best_encoder = intel_best_encoder, 1670 }; 1671 1672 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 1673 .destroy = intel_encoder_destroy, 1674 }; 1675 1676 static void 1677 intel_attach_aspect_ratio_property(struct drm_connector *connector) 1678 { 1679 if (!drm_mode_create_aspect_ratio_property(connector->dev)) 1680 drm_object_attach_property(&connector->base, 1681 connector->dev->mode_config.aspect_ratio_property, 1682 DRM_MODE_PICTURE_ASPECT_NONE); 1683 } 1684 1685 static void 1686 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 1687 { 1688 intel_attach_force_audio_property(connector); 1689 intel_attach_broadcast_rgb_property(connector); 1690 intel_hdmi->color_range_auto = true; 1691 intel_attach_aspect_ratio_property(connector); 1692 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1693 } 1694 1695 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1696 struct intel_connector *intel_connector) 1697 { 1698 struct drm_connector *connector = &intel_connector->base; 1699 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1700 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1701 struct drm_device *dev = intel_encoder->base.dev; 1702 struct drm_i915_private *dev_priv = dev->dev_private; 1703 enum port port = intel_dig_port->port; 1704 1705 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 1706 DRM_MODE_CONNECTOR_HDMIA); 1707 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 1708 1709 connector->interlace_allowed = 1; 1710 connector->doublescan_allowed = 0; 1711 connector->stereo_allowed = 1; 1712 1713 switch (port) { 1714 case PORT_B: 1715 if (IS_BROXTON(dev_priv)) 1716 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; 1717 else 1718 intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 1719 intel_encoder->hpd_pin = HPD_PORT_B; 1720 break; 1721 case PORT_C: 1722 if (IS_BROXTON(dev_priv)) 1723 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; 1724 else 1725 intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 1726 intel_encoder->hpd_pin = HPD_PORT_C; 1727 break; 1728 case PORT_D: 1729 if (WARN_ON(IS_BROXTON(dev_priv))) 1730 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; 1731 else if (IS_CHERRYVIEW(dev_priv)) 1732 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; 1733 else 1734 intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 1735 intel_encoder->hpd_pin = HPD_PORT_D; 1736 break; 1737 case PORT_A: 1738 intel_encoder->hpd_pin = HPD_PORT_A; 1739 /* Internal port only for eDP. */ 1740 default: 1741 BUG(); 1742 } 1743 1744 if (IS_VALLEYVIEW(dev)) { 1745 intel_hdmi->write_infoframe = vlv_write_infoframe; 1746 intel_hdmi->set_infoframes = vlv_set_infoframes; 1747 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; 1748 } else if (IS_G4X(dev)) { 1749 intel_hdmi->write_infoframe = g4x_write_infoframe; 1750 intel_hdmi->set_infoframes = g4x_set_infoframes; 1751 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; 1752 } else if (HAS_DDI(dev)) { 1753 intel_hdmi->write_infoframe = hsw_write_infoframe; 1754 intel_hdmi->set_infoframes = hsw_set_infoframes; 1755 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; 1756 } else if (HAS_PCH_IBX(dev)) { 1757 intel_hdmi->write_infoframe = ibx_write_infoframe; 1758 intel_hdmi->set_infoframes = ibx_set_infoframes; 1759 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; 1760 } else { 1761 intel_hdmi->write_infoframe = cpt_write_infoframe; 1762 intel_hdmi->set_infoframes = cpt_set_infoframes; 1763 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; 1764 } 1765 1766 if (HAS_DDI(dev)) 1767 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 1768 else 1769 intel_connector->get_hw_state = intel_connector_get_hw_state; 1770 intel_connector->unregister = intel_connector_unregister; 1771 1772 intel_hdmi_add_properties(intel_hdmi, connector); 1773 1774 intel_connector_attach_encoder(intel_connector, intel_encoder); 1775 drm_connector_register(connector); 1776 1777 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1778 * 0xd. Failure to do so will result in spurious interrupts being 1779 * generated on the port when a cable is not attached. 1780 */ 1781 if (IS_G4X(dev) && !IS_GM45(dev)) { 1782 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1783 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1784 } 1785 } 1786 1787 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) 1788 { 1789 struct intel_digital_port *intel_dig_port; 1790 struct intel_encoder *intel_encoder; 1791 struct intel_connector *intel_connector; 1792 1793 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 1794 if (!intel_dig_port) 1795 return; 1796 1797 intel_connector = intel_connector_alloc(); 1798 if (!intel_connector) { 1799 kfree(intel_dig_port); 1800 return; 1801 } 1802 1803 intel_encoder = &intel_dig_port->base; 1804 1805 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 1806 DRM_MODE_ENCODER_TMDS); 1807 1808 intel_encoder->compute_config = intel_hdmi_compute_config; 1809 if (HAS_PCH_SPLIT(dev)) { 1810 intel_encoder->disable = pch_disable_hdmi; 1811 intel_encoder->post_disable = pch_post_disable_hdmi; 1812 } else { 1813 intel_encoder->disable = g4x_disable_hdmi; 1814 } 1815 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 1816 intel_encoder->get_config = intel_hdmi_get_config; 1817 if (IS_CHERRYVIEW(dev)) { 1818 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 1819 intel_encoder->pre_enable = chv_hdmi_pre_enable; 1820 intel_encoder->enable = vlv_enable_hdmi; 1821 intel_encoder->post_disable = chv_hdmi_post_disable; 1822 } else if (IS_VALLEYVIEW(dev)) { 1823 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 1824 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 1825 intel_encoder->enable = vlv_enable_hdmi; 1826 intel_encoder->post_disable = vlv_hdmi_post_disable; 1827 } else { 1828 intel_encoder->pre_enable = intel_hdmi_pre_enable; 1829 intel_encoder->enable = intel_enable_hdmi; 1830 } 1831 1832 intel_encoder->type = INTEL_OUTPUT_HDMI; 1833 if (IS_CHERRYVIEW(dev)) { 1834 if (port == PORT_D) 1835 intel_encoder->crtc_mask = 1 << 2; 1836 else 1837 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1838 } else { 1839 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1840 } 1841 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 1842 /* 1843 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 1844 * to work on real hardware. And since g4x can send infoframes to 1845 * only one port anyway, nothing is lost by allowing it. 1846 */ 1847 if (IS_G4X(dev)) 1848 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 1849 1850 intel_dig_port->port = port; 1851 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 1852 intel_dig_port->dp.output_reg = 0; 1853 1854 intel_hdmi_init_connector(intel_dig_port, intel_connector); 1855 } 1856