1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/i2c.h> 30 #include <linux/delay.h> 31 #include <linux/hdmi.h> 32 #include <drm/drmP.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include "intel_drv.h" 37 #include <drm/i915_drm.h> 38 #include "i915_drv.h" 39 40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 41 { 42 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 43 } 44 45 static void 46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 47 { 48 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 49 struct drm_i915_private *dev_priv = dev->dev_private; 50 uint32_t enabled_bits; 51 52 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 53 54 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, 55 "HDMI port enabled, expecting disabled\n"); 56 } 57 58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 59 { 60 struct intel_digital_port *intel_dig_port = 61 container_of(encoder, struct intel_digital_port, base.base); 62 return &intel_dig_port->hdmi; 63 } 64 65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 66 { 67 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); 68 } 69 70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) 71 { 72 switch (type) { 73 case HDMI_INFOFRAME_TYPE_AVI: 74 return VIDEO_DIP_SELECT_AVI; 75 case HDMI_INFOFRAME_TYPE_SPD: 76 return VIDEO_DIP_SELECT_SPD; 77 case HDMI_INFOFRAME_TYPE_VENDOR: 78 return VIDEO_DIP_SELECT_VENDOR; 79 default: 80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 81 return 0; 82 } 83 } 84 85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) 86 { 87 switch (type) { 88 case HDMI_INFOFRAME_TYPE_AVI: 89 return VIDEO_DIP_ENABLE_AVI; 90 case HDMI_INFOFRAME_TYPE_SPD: 91 return VIDEO_DIP_ENABLE_SPD; 92 case HDMI_INFOFRAME_TYPE_VENDOR: 93 return VIDEO_DIP_ENABLE_VENDOR; 94 default: 95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 96 return 0; 97 } 98 } 99 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) 101 { 102 switch (type) { 103 case HDMI_INFOFRAME_TYPE_AVI: 104 return VIDEO_DIP_ENABLE_AVI_HSW; 105 case HDMI_INFOFRAME_TYPE_SPD: 106 return VIDEO_DIP_ENABLE_SPD_HSW; 107 case HDMI_INFOFRAME_TYPE_VENDOR: 108 return VIDEO_DIP_ENABLE_VS_HSW; 109 default: 110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 111 return 0; 112 } 113 } 114 115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, 116 enum transcoder cpu_transcoder, 117 struct drm_i915_private *dev_priv) 118 { 119 switch (type) { 120 case HDMI_INFOFRAME_TYPE_AVI: 121 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); 122 case HDMI_INFOFRAME_TYPE_SPD: 123 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); 124 case HDMI_INFOFRAME_TYPE_VENDOR: 125 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); 126 default: 127 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); 128 return 0; 129 } 130 } 131 132 static void g4x_write_infoframe(struct drm_encoder *encoder, 133 enum hdmi_infoframe_type type, 134 const void *frame, ssize_t len) 135 { 136 const uint32_t *data = frame; 137 struct drm_device *dev = encoder->dev; 138 struct drm_i915_private *dev_priv = dev->dev_private; 139 u32 val = I915_READ(VIDEO_DIP_CTL); 140 int i; 141 142 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 143 144 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 145 val |= g4x_infoframe_index(type); 146 147 val &= ~g4x_infoframe_enable(type); 148 149 I915_WRITE(VIDEO_DIP_CTL, val); 150 151 mmiowb(); 152 for (i = 0; i < len; i += 4) { 153 I915_WRITE(VIDEO_DIP_DATA, *data); 154 data++; 155 } 156 /* Write every possible data byte to force correct ECC calculation. */ 157 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 158 I915_WRITE(VIDEO_DIP_DATA, 0); 159 mmiowb(); 160 161 val |= g4x_infoframe_enable(type); 162 val &= ~VIDEO_DIP_FREQ_MASK; 163 val |= VIDEO_DIP_FREQ_VSYNC; 164 165 I915_WRITE(VIDEO_DIP_CTL, val); 166 POSTING_READ(VIDEO_DIP_CTL); 167 } 168 169 static bool g4x_infoframe_enabled(struct drm_encoder *encoder) 170 { 171 struct drm_device *dev = encoder->dev; 172 struct drm_i915_private *dev_priv = dev->dev_private; 173 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 174 u32 val = I915_READ(VIDEO_DIP_CTL); 175 176 if ((val & VIDEO_DIP_ENABLE) == 0) 177 return false; 178 179 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 180 return false; 181 182 return val & (VIDEO_DIP_ENABLE_AVI | 183 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 184 } 185 186 static void ibx_write_infoframe(struct drm_encoder *encoder, 187 enum hdmi_infoframe_type type, 188 const void *frame, ssize_t len) 189 { 190 const uint32_t *data = frame; 191 struct drm_device *dev = encoder->dev; 192 struct drm_i915_private *dev_priv = dev->dev_private; 193 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 194 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 195 u32 val = I915_READ(reg); 196 197 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 198 199 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 200 val |= g4x_infoframe_index(type); 201 202 val &= ~g4x_infoframe_enable(type); 203 204 I915_WRITE(reg, val); 205 206 mmiowb(); 207 for (i = 0; i < len; i += 4) { 208 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 209 data++; 210 } 211 /* Write every possible data byte to force correct ECC calculation. */ 212 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 213 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 214 mmiowb(); 215 216 val |= g4x_infoframe_enable(type); 217 val &= ~VIDEO_DIP_FREQ_MASK; 218 val |= VIDEO_DIP_FREQ_VSYNC; 219 220 I915_WRITE(reg, val); 221 POSTING_READ(reg); 222 } 223 224 static bool ibx_infoframe_enabled(struct drm_encoder *encoder) 225 { 226 struct drm_device *dev = encoder->dev; 227 struct drm_i915_private *dev_priv = dev->dev_private; 228 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 229 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 230 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 231 u32 val = I915_READ(reg); 232 233 if ((val & VIDEO_DIP_ENABLE) == 0) 234 return false; 235 236 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 237 return false; 238 239 return val & (VIDEO_DIP_ENABLE_AVI | 240 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 241 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 242 } 243 244 static void cpt_write_infoframe(struct drm_encoder *encoder, 245 enum hdmi_infoframe_type type, 246 const void *frame, ssize_t len) 247 { 248 const uint32_t *data = frame; 249 struct drm_device *dev = encoder->dev; 250 struct drm_i915_private *dev_priv = dev->dev_private; 251 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 252 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 253 u32 val = I915_READ(reg); 254 255 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 256 257 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 258 val |= g4x_infoframe_index(type); 259 260 /* The DIP control register spec says that we need to update the AVI 261 * infoframe without clearing its enable bit */ 262 if (type != HDMI_INFOFRAME_TYPE_AVI) 263 val &= ~g4x_infoframe_enable(type); 264 265 I915_WRITE(reg, val); 266 267 mmiowb(); 268 for (i = 0; i < len; i += 4) { 269 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 270 data++; 271 } 272 /* Write every possible data byte to force correct ECC calculation. */ 273 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 275 mmiowb(); 276 277 val |= g4x_infoframe_enable(type); 278 val &= ~VIDEO_DIP_FREQ_MASK; 279 val |= VIDEO_DIP_FREQ_VSYNC; 280 281 I915_WRITE(reg, val); 282 POSTING_READ(reg); 283 } 284 285 static bool cpt_infoframe_enabled(struct drm_encoder *encoder) 286 { 287 struct drm_device *dev = encoder->dev; 288 struct drm_i915_private *dev_priv = dev->dev_private; 289 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 290 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 291 u32 val = I915_READ(reg); 292 293 if ((val & VIDEO_DIP_ENABLE) == 0) 294 return false; 295 296 return val & (VIDEO_DIP_ENABLE_AVI | 297 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 298 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 299 } 300 301 static void vlv_write_infoframe(struct drm_encoder *encoder, 302 enum hdmi_infoframe_type type, 303 const void *frame, ssize_t len) 304 { 305 const uint32_t *data = frame; 306 struct drm_device *dev = encoder->dev; 307 struct drm_i915_private *dev_priv = dev->dev_private; 308 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 309 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 310 u32 val = I915_READ(reg); 311 312 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); 313 314 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 315 val |= g4x_infoframe_index(type); 316 317 val &= ~g4x_infoframe_enable(type); 318 319 I915_WRITE(reg, val); 320 321 mmiowb(); 322 for (i = 0; i < len; i += 4) { 323 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 324 data++; 325 } 326 /* Write every possible data byte to force correct ECC calculation. */ 327 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 329 mmiowb(); 330 331 val |= g4x_infoframe_enable(type); 332 val &= ~VIDEO_DIP_FREQ_MASK; 333 val |= VIDEO_DIP_FREQ_VSYNC; 334 335 I915_WRITE(reg, val); 336 POSTING_READ(reg); 337 } 338 339 static bool vlv_infoframe_enabled(struct drm_encoder *encoder) 340 { 341 struct drm_device *dev = encoder->dev; 342 struct drm_i915_private *dev_priv = dev->dev_private; 343 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 344 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 345 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 346 u32 val = I915_READ(reg); 347 348 if ((val & VIDEO_DIP_ENABLE) == 0) 349 return false; 350 351 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) 352 return false; 353 354 return val & (VIDEO_DIP_ENABLE_AVI | 355 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 356 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 357 } 358 359 static void hsw_write_infoframe(struct drm_encoder *encoder, 360 enum hdmi_infoframe_type type, 361 const void *frame, ssize_t len) 362 { 363 const uint32_t *data = frame; 364 struct drm_device *dev = encoder->dev; 365 struct drm_i915_private *dev_priv = dev->dev_private; 366 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 367 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 368 u32 data_reg; 369 int i; 370 u32 val = I915_READ(ctl_reg); 371 372 data_reg = hsw_infoframe_data_reg(type, 373 intel_crtc->config->cpu_transcoder, 374 dev_priv); 375 if (data_reg == 0) 376 return; 377 378 val &= ~hsw_infoframe_enable(type); 379 I915_WRITE(ctl_reg, val); 380 381 mmiowb(); 382 for (i = 0; i < len; i += 4) { 383 I915_WRITE(data_reg + i, *data); 384 data++; 385 } 386 /* Write every possible data byte to force correct ECC calculation. */ 387 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 388 I915_WRITE(data_reg + i, 0); 389 mmiowb(); 390 391 val |= hsw_infoframe_enable(type); 392 I915_WRITE(ctl_reg, val); 393 POSTING_READ(ctl_reg); 394 } 395 396 static bool hsw_infoframe_enabled(struct drm_encoder *encoder) 397 { 398 struct drm_device *dev = encoder->dev; 399 struct drm_i915_private *dev_priv = dev->dev_private; 400 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 401 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 402 u32 val = I915_READ(ctl_reg); 403 404 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 405 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 406 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 407 } 408 409 /* 410 * The data we write to the DIP data buffer registers is 1 byte bigger than the 411 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 412 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 413 * used for both technologies. 414 * 415 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 416 * DW1: DB3 | DB2 | DB1 | DB0 417 * DW2: DB7 | DB6 | DB5 | DB4 418 * DW3: ... 419 * 420 * (HB is Header Byte, DB is Data Byte) 421 * 422 * The hdmi pack() functions don't know about that hardware specific hole so we 423 * trick them by giving an offset into the buffer and moving back the header 424 * bytes by one. 425 */ 426 static void intel_write_infoframe(struct drm_encoder *encoder, 427 union hdmi_infoframe *frame) 428 { 429 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 430 uint8_t buffer[VIDEO_DIP_DATA_SIZE]; 431 ssize_t len; 432 433 /* see comment above for the reason for this offset */ 434 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); 435 if (len < 0) 436 return; 437 438 /* Insert the 'hole' (see big comment above) at position 3 */ 439 buffer[0] = buffer[1]; 440 buffer[1] = buffer[2]; 441 buffer[2] = buffer[3]; 442 buffer[3] = 0; 443 len++; 444 445 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); 446 } 447 448 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, 449 struct drm_display_mode *adjusted_mode) 450 { 451 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 452 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 453 union hdmi_infoframe frame; 454 int ret; 455 456 /* Set user selected PAR to incoming mode's member */ 457 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; 458 459 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 460 adjusted_mode); 461 if (ret < 0) { 462 DRM_ERROR("couldn't fill AVI infoframe\n"); 463 return; 464 } 465 466 if (intel_hdmi->rgb_quant_range_selectable) { 467 if (intel_crtc->config->limited_color_range) 468 frame.avi.quantization_range = 469 HDMI_QUANTIZATION_RANGE_LIMITED; 470 else 471 frame.avi.quantization_range = 472 HDMI_QUANTIZATION_RANGE_FULL; 473 } 474 475 intel_write_infoframe(encoder, &frame); 476 } 477 478 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 479 { 480 union hdmi_infoframe frame; 481 int ret; 482 483 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); 484 if (ret < 0) { 485 DRM_ERROR("couldn't fill SPD infoframe\n"); 486 return; 487 } 488 489 frame.spd.sdi = HDMI_SPD_SDI_PC; 490 491 intel_write_infoframe(encoder, &frame); 492 } 493 494 static void 495 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, 496 struct drm_display_mode *adjusted_mode) 497 { 498 union hdmi_infoframe frame; 499 int ret; 500 501 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 502 adjusted_mode); 503 if (ret < 0) 504 return; 505 506 intel_write_infoframe(encoder, &frame); 507 } 508 509 static void g4x_set_infoframes(struct drm_encoder *encoder, 510 bool enable, 511 struct drm_display_mode *adjusted_mode) 512 { 513 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 514 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 515 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 516 u32 reg = VIDEO_DIP_CTL; 517 u32 val = I915_READ(reg); 518 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 519 520 assert_hdmi_port_disabled(intel_hdmi); 521 522 /* If the registers were not initialized yet, they might be zeroes, 523 * which means we're selecting the AVI DIP and we're setting its 524 * frequency to once. This seems to really confuse the HW and make 525 * things stop working (the register spec says the AVI always needs to 526 * be sent every VSync). So here we avoid writing to the register more 527 * than we need and also explicitly select the AVI DIP and explicitly 528 * set its frequency to every VSync. Avoiding to write it twice seems to 529 * be enough to solve the problem, but being defensive shouldn't hurt us 530 * either. */ 531 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 532 533 if (!enable) { 534 if (!(val & VIDEO_DIP_ENABLE)) 535 return; 536 if (port != (val & VIDEO_DIP_PORT_MASK)) { 537 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 538 (val & VIDEO_DIP_PORT_MASK) >> 29); 539 return; 540 } 541 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 542 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 543 I915_WRITE(reg, val); 544 POSTING_READ(reg); 545 return; 546 } 547 548 if (port != (val & VIDEO_DIP_PORT_MASK)) { 549 if (val & VIDEO_DIP_ENABLE) { 550 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 551 (val & VIDEO_DIP_PORT_MASK) >> 29); 552 return; 553 } 554 val &= ~VIDEO_DIP_PORT_MASK; 555 val |= port; 556 } 557 558 val |= VIDEO_DIP_ENABLE; 559 val &= ~(VIDEO_DIP_ENABLE_AVI | 560 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 561 562 I915_WRITE(reg, val); 563 POSTING_READ(reg); 564 565 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 566 intel_hdmi_set_spd_infoframe(encoder); 567 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 568 } 569 570 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) 571 { 572 struct drm_device *dev = encoder->dev; 573 struct drm_connector *connector; 574 575 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 576 577 /* 578 * HDMI cloning is only supported on g4x which doesn't 579 * support deep color or GCP infoframes anyway so no 580 * need to worry about multiple HDMI sinks here. 581 */ 582 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 583 if (connector->encoder == encoder) 584 return connector->display_info.bpc > 8; 585 586 return false; 587 } 588 589 /* 590 * Determine if default_phase=1 can be indicated in the GCP infoframe. 591 * 592 * From HDMI specification 1.4a: 593 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 594 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 595 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 596 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 597 * phase of 0 598 */ 599 static bool gcp_default_phase_possible(int pipe_bpp, 600 const struct drm_display_mode *mode) 601 { 602 unsigned int pixels_per_group; 603 604 switch (pipe_bpp) { 605 case 30: 606 /* 4 pixels in 5 clocks */ 607 pixels_per_group = 4; 608 break; 609 case 36: 610 /* 2 pixels in 3 clocks */ 611 pixels_per_group = 2; 612 break; 613 case 48: 614 /* 1 pixel in 2 clocks */ 615 pixels_per_group = 1; 616 break; 617 default: 618 /* phase information not relevant for 8bpc */ 619 return false; 620 } 621 622 return mode->crtc_hdisplay % pixels_per_group == 0 && 623 mode->crtc_htotal % pixels_per_group == 0 && 624 mode->crtc_hblank_start % pixels_per_group == 0 && 625 mode->crtc_hblank_end % pixels_per_group == 0 && 626 mode->crtc_hsync_start % pixels_per_group == 0 && 627 mode->crtc_hsync_end % pixels_per_group == 0 && 628 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 629 mode->crtc_htotal/2 % pixels_per_group == 0); 630 } 631 632 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) 633 { 634 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 635 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 636 u32 reg, val = 0; 637 638 if (HAS_DDI(dev_priv)) 639 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); 640 else if (IS_VALLEYVIEW(dev_priv)) 641 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 642 else if (HAS_PCH_SPLIT(dev_priv->dev)) 643 reg = TVIDEO_DIP_GCP(crtc->pipe); 644 else 645 return false; 646 647 /* Indicate color depth whenever the sink supports deep color */ 648 if (hdmi_sink_is_deep_color(encoder)) 649 val |= GCP_COLOR_INDICATION; 650 651 /* Enable default_phase whenever the display mode is suitably aligned */ 652 if (gcp_default_phase_possible(crtc->config->pipe_bpp, 653 &crtc->config->base.adjusted_mode)) 654 val |= GCP_DEFAULT_PHASE_ENABLE; 655 656 I915_WRITE(reg, val); 657 658 return val != 0; 659 } 660 661 static void ibx_set_infoframes(struct drm_encoder *encoder, 662 bool enable, 663 struct drm_display_mode *adjusted_mode) 664 { 665 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 666 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 667 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 668 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 669 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 670 u32 val = I915_READ(reg); 671 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 672 673 assert_hdmi_port_disabled(intel_hdmi); 674 675 /* See the big comment in g4x_set_infoframes() */ 676 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 677 678 if (!enable) { 679 if (!(val & VIDEO_DIP_ENABLE)) 680 return; 681 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 682 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 683 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 684 I915_WRITE(reg, val); 685 POSTING_READ(reg); 686 return; 687 } 688 689 if (port != (val & VIDEO_DIP_PORT_MASK)) { 690 WARN(val & VIDEO_DIP_ENABLE, 691 "DIP already enabled on port %c\n", 692 (val & VIDEO_DIP_PORT_MASK) >> 29); 693 val &= ~VIDEO_DIP_PORT_MASK; 694 val |= port; 695 } 696 697 val |= VIDEO_DIP_ENABLE; 698 val &= ~(VIDEO_DIP_ENABLE_AVI | 699 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 700 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 701 702 if (intel_hdmi_set_gcp_infoframe(encoder)) 703 val |= VIDEO_DIP_ENABLE_GCP; 704 705 I915_WRITE(reg, val); 706 POSTING_READ(reg); 707 708 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 709 intel_hdmi_set_spd_infoframe(encoder); 710 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 711 } 712 713 static void cpt_set_infoframes(struct drm_encoder *encoder, 714 bool enable, 715 struct drm_display_mode *adjusted_mode) 716 { 717 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 718 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 719 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 720 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 721 u32 val = I915_READ(reg); 722 723 assert_hdmi_port_disabled(intel_hdmi); 724 725 /* See the big comment in g4x_set_infoframes() */ 726 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 727 728 if (!enable) { 729 if (!(val & VIDEO_DIP_ENABLE)) 730 return; 731 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 732 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 733 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 734 I915_WRITE(reg, val); 735 POSTING_READ(reg); 736 return; 737 } 738 739 /* Set both together, unset both together: see the spec. */ 740 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 741 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 742 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 743 744 if (intel_hdmi_set_gcp_infoframe(encoder)) 745 val |= VIDEO_DIP_ENABLE_GCP; 746 747 I915_WRITE(reg, val); 748 POSTING_READ(reg); 749 750 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 751 intel_hdmi_set_spd_infoframe(encoder); 752 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 753 } 754 755 static void vlv_set_infoframes(struct drm_encoder *encoder, 756 bool enable, 757 struct drm_display_mode *adjusted_mode) 758 { 759 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 760 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 761 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 762 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 763 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 764 u32 val = I915_READ(reg); 765 u32 port = VIDEO_DIP_PORT(intel_dig_port->port); 766 767 assert_hdmi_port_disabled(intel_hdmi); 768 769 /* See the big comment in g4x_set_infoframes() */ 770 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 771 772 if (!enable) { 773 if (!(val & VIDEO_DIP_ENABLE)) 774 return; 775 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 776 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 777 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 778 I915_WRITE(reg, val); 779 POSTING_READ(reg); 780 return; 781 } 782 783 if (port != (val & VIDEO_DIP_PORT_MASK)) { 784 WARN(val & VIDEO_DIP_ENABLE, 785 "DIP already enabled on port %c\n", 786 (val & VIDEO_DIP_PORT_MASK) >> 29); 787 val &= ~VIDEO_DIP_PORT_MASK; 788 val |= port; 789 } 790 791 val |= VIDEO_DIP_ENABLE; 792 val &= ~(VIDEO_DIP_ENABLE_AVI | 793 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 794 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 795 796 if (intel_hdmi_set_gcp_infoframe(encoder)) 797 val |= VIDEO_DIP_ENABLE_GCP; 798 799 I915_WRITE(reg, val); 800 POSTING_READ(reg); 801 802 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 803 intel_hdmi_set_spd_infoframe(encoder); 804 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 805 } 806 807 static void hsw_set_infoframes(struct drm_encoder *encoder, 808 bool enable, 809 struct drm_display_mode *adjusted_mode) 810 { 811 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 812 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 813 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 814 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); 815 u32 val = I915_READ(reg); 816 817 assert_hdmi_port_disabled(intel_hdmi); 818 819 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 820 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 821 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 822 823 if (!enable) { 824 I915_WRITE(reg, val); 825 POSTING_READ(reg); 826 return; 827 } 828 829 if (intel_hdmi_set_gcp_infoframe(encoder)) 830 val |= VIDEO_DIP_ENABLE_GCP_HSW; 831 832 I915_WRITE(reg, val); 833 POSTING_READ(reg); 834 835 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); 836 intel_hdmi_set_spd_infoframe(encoder); 837 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); 838 } 839 840 static void intel_hdmi_prepare(struct intel_encoder *encoder) 841 { 842 struct drm_device *dev = encoder->base.dev; 843 struct drm_i915_private *dev_priv = dev->dev_private; 844 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 845 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 846 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 847 u32 hdmi_val; 848 849 hdmi_val = SDVO_ENCODING_HDMI; 850 if (!HAS_PCH_SPLIT(dev)) 851 hdmi_val |= intel_hdmi->color_range; 852 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 853 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 854 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 855 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 856 857 if (crtc->config->pipe_bpp > 24) 858 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 859 else 860 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 861 862 if (crtc->config->has_hdmi_sink) 863 hdmi_val |= HDMI_MODE_SELECT_HDMI; 864 865 if (HAS_PCH_CPT(dev)) 866 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 867 else if (IS_CHERRYVIEW(dev)) 868 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 869 else 870 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 871 872 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); 873 POSTING_READ(intel_hdmi->hdmi_reg); 874 } 875 876 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 877 enum i915_pipe *pipe) 878 { 879 struct drm_device *dev = encoder->base.dev; 880 struct drm_i915_private *dev_priv = dev->dev_private; 881 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 882 enum intel_display_power_domain power_domain; 883 u32 tmp; 884 885 power_domain = intel_display_port_power_domain(encoder); 886 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 887 return false; 888 889 tmp = I915_READ(intel_hdmi->hdmi_reg); 890 891 if (!(tmp & SDVO_ENABLE)) 892 return false; 893 894 if (HAS_PCH_CPT(dev)) 895 *pipe = PORT_TO_PIPE_CPT(tmp); 896 else if (IS_CHERRYVIEW(dev)) 897 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); 898 else 899 *pipe = PORT_TO_PIPE(tmp); 900 901 return true; 902 } 903 904 static void intel_hdmi_get_config(struct intel_encoder *encoder, 905 struct intel_crtc_state *pipe_config) 906 { 907 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 908 struct drm_device *dev = encoder->base.dev; 909 struct drm_i915_private *dev_priv = dev->dev_private; 910 u32 tmp, flags = 0; 911 int dotclock; 912 913 tmp = I915_READ(intel_hdmi->hdmi_reg); 914 915 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 916 flags |= DRM_MODE_FLAG_PHSYNC; 917 else 918 flags |= DRM_MODE_FLAG_NHSYNC; 919 920 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 921 flags |= DRM_MODE_FLAG_PVSYNC; 922 else 923 flags |= DRM_MODE_FLAG_NVSYNC; 924 925 if (tmp & HDMI_MODE_SELECT_HDMI) 926 pipe_config->has_hdmi_sink = true; 927 928 if (intel_hdmi->infoframe_enabled(&encoder->base)) 929 pipe_config->has_infoframe = true; 930 931 if (tmp & SDVO_AUDIO_ENABLE) 932 pipe_config->has_audio = true; 933 934 if (!HAS_PCH_SPLIT(dev) && 935 tmp & HDMI_COLOR_RANGE_16_235) 936 pipe_config->limited_color_range = true; 937 938 pipe_config->base.adjusted_mode.flags |= flags; 939 940 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 941 dotclock = pipe_config->port_clock * 2 / 3; 942 else 943 dotclock = pipe_config->port_clock; 944 945 if (pipe_config->pixel_multiplier) 946 dotclock /= pipe_config->pixel_multiplier; 947 948 if (HAS_PCH_SPLIT(dev_priv->dev)) 949 ironlake_check_encoder_dotclock(pipe_config, dotclock); 950 951 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 952 } 953 954 static void intel_enable_hdmi_audio(struct intel_encoder *encoder) 955 { 956 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 957 958 WARN_ON(!crtc->config->has_hdmi_sink); 959 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 960 pipe_name(crtc->pipe)); 961 intel_audio_codec_enable(encoder); 962 } 963 964 static void g4x_enable_hdmi(struct intel_encoder *encoder) 965 { 966 struct drm_device *dev = encoder->base.dev; 967 struct drm_i915_private *dev_priv = dev->dev_private; 968 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 969 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 970 u32 temp; 971 972 temp = I915_READ(intel_hdmi->hdmi_reg); 973 974 temp |= SDVO_ENABLE; 975 if (crtc->config->has_audio) 976 temp |= SDVO_AUDIO_ENABLE; 977 978 I915_WRITE(intel_hdmi->hdmi_reg, temp); 979 POSTING_READ(intel_hdmi->hdmi_reg); 980 981 if (crtc->config->has_audio) 982 intel_enable_hdmi_audio(encoder); 983 } 984 985 static void ibx_enable_hdmi(struct intel_encoder *encoder) 986 { 987 struct drm_device *dev = encoder->base.dev; 988 struct drm_i915_private *dev_priv = dev->dev_private; 989 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 990 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 991 u32 temp; 992 993 temp = I915_READ(intel_hdmi->hdmi_reg); 994 995 temp |= SDVO_ENABLE; 996 if (crtc->config->has_audio) 997 temp |= SDVO_AUDIO_ENABLE; 998 999 /* 1000 * HW workaround, need to write this twice for issue 1001 * that may result in first write getting masked. 1002 */ 1003 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1004 POSTING_READ(intel_hdmi->hdmi_reg); 1005 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1006 POSTING_READ(intel_hdmi->hdmi_reg); 1007 1008 /* 1009 * HW workaround, need to toggle enable bit off and on 1010 * for 12bpc with pixel repeat. 1011 * 1012 * FIXME: BSpec says this should be done at the end of 1013 * of the modeset sequence, so not sure if this isn't too soon. 1014 */ 1015 if (crtc->config->pipe_bpp > 24 && 1016 crtc->config->pixel_multiplier > 1) { 1017 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); 1018 POSTING_READ(intel_hdmi->hdmi_reg); 1019 1020 /* 1021 * HW workaround, need to write this twice for issue 1022 * that may result in first write getting masked. 1023 */ 1024 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1025 POSTING_READ(intel_hdmi->hdmi_reg); 1026 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1027 POSTING_READ(intel_hdmi->hdmi_reg); 1028 } 1029 1030 if (crtc->config->has_audio) 1031 intel_enable_hdmi_audio(encoder); 1032 } 1033 1034 static void cpt_enable_hdmi(struct intel_encoder *encoder) 1035 { 1036 struct drm_device *dev = encoder->base.dev; 1037 struct drm_i915_private *dev_priv = dev->dev_private; 1038 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1039 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1040 enum i915_pipe pipe = crtc->pipe; 1041 u32 temp; 1042 1043 temp = I915_READ(intel_hdmi->hdmi_reg); 1044 1045 temp |= SDVO_ENABLE; 1046 if (crtc->config->has_audio) 1047 temp |= SDVO_AUDIO_ENABLE; 1048 1049 /* 1050 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1051 * 1052 * The procedure for 12bpc is as follows: 1053 * 1. disable HDMI clock gating 1054 * 2. enable HDMI with 8bpc 1055 * 3. enable HDMI with 12bpc 1056 * 4. enable HDMI clock gating 1057 */ 1058 1059 if (crtc->config->pipe_bpp > 24) { 1060 I915_WRITE(TRANS_CHICKEN1(pipe), 1061 I915_READ(TRANS_CHICKEN1(pipe)) | 1062 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1063 1064 temp &= ~SDVO_COLOR_FORMAT_MASK; 1065 temp |= SDVO_COLOR_FORMAT_8bpc; 1066 } 1067 1068 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1069 POSTING_READ(intel_hdmi->hdmi_reg); 1070 1071 if (crtc->config->pipe_bpp > 24) { 1072 temp &= ~SDVO_COLOR_FORMAT_MASK; 1073 temp |= HDMI_COLOR_FORMAT_12bpc; 1074 1075 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1076 POSTING_READ(intel_hdmi->hdmi_reg); 1077 1078 I915_WRITE(TRANS_CHICKEN1(pipe), 1079 I915_READ(TRANS_CHICKEN1(pipe)) & 1080 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1081 } 1082 1083 if (crtc->config->has_audio) 1084 intel_enable_hdmi_audio(encoder); 1085 } 1086 1087 static void vlv_enable_hdmi(struct intel_encoder *encoder) 1088 { 1089 } 1090 1091 static void intel_disable_hdmi(struct intel_encoder *encoder) 1092 { 1093 struct drm_device *dev = encoder->base.dev; 1094 struct drm_i915_private *dev_priv = dev->dev_private; 1095 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1096 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1097 u32 temp; 1098 1099 temp = I915_READ(intel_hdmi->hdmi_reg); 1100 1101 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); 1102 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1103 POSTING_READ(intel_hdmi->hdmi_reg); 1104 1105 /* 1106 * HW workaround for IBX, we need to move the port 1107 * to transcoder A after disabling it to allow the 1108 * matching DP port to be enabled on transcoder A. 1109 */ 1110 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { 1111 temp &= ~SDVO_PIPE_B_SELECT; 1112 temp |= SDVO_ENABLE; 1113 /* 1114 * HW workaround, need to write this twice for issue 1115 * that may result in first write getting masked. 1116 */ 1117 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1118 POSTING_READ(intel_hdmi->hdmi_reg); 1119 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1120 POSTING_READ(intel_hdmi->hdmi_reg); 1121 1122 temp &= ~SDVO_ENABLE; 1123 I915_WRITE(intel_hdmi->hdmi_reg, temp); 1124 POSTING_READ(intel_hdmi->hdmi_reg); 1125 } 1126 1127 intel_hdmi->set_infoframes(&encoder->base, false, NULL); 1128 } 1129 1130 static void g4x_disable_hdmi(struct intel_encoder *encoder) 1131 { 1132 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1133 1134 if (crtc->config->has_audio) 1135 intel_audio_codec_disable(encoder); 1136 1137 intel_disable_hdmi(encoder); 1138 } 1139 1140 static void pch_disable_hdmi(struct intel_encoder *encoder) 1141 { 1142 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1143 1144 if (crtc->config->has_audio) 1145 intel_audio_codec_disable(encoder); 1146 } 1147 1148 static void pch_post_disable_hdmi(struct intel_encoder *encoder) 1149 { 1150 intel_disable_hdmi(encoder); 1151 } 1152 1153 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) 1154 { 1155 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1156 1157 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) 1158 return 165000; 1159 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) 1160 return 300000; 1161 else 1162 return 225000; 1163 } 1164 1165 static enum drm_mode_status 1166 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1167 int clock, bool respect_dvi_limit) 1168 { 1169 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1170 1171 if (clock < 25000) 1172 return MODE_CLOCK_LOW; 1173 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) 1174 return MODE_CLOCK_HIGH; 1175 1176 /* BXT DPLL can't generate 223-240 MHz */ 1177 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) 1178 return MODE_CLOCK_RANGE; 1179 1180 /* CHV DPLL can't generate 216-240 MHz */ 1181 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) 1182 return MODE_CLOCK_RANGE; 1183 1184 return MODE_OK; 1185 } 1186 1187 static enum drm_mode_status 1188 intel_hdmi_mode_valid(struct drm_connector *connector, 1189 struct drm_display_mode *mode) 1190 { 1191 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1192 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1193 enum drm_mode_status status; 1194 int clock; 1195 1196 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1197 return MODE_NO_DBLESCAN; 1198 1199 clock = mode->clock; 1200 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1201 clock *= 2; 1202 1203 /* check if we can do 8bpc */ 1204 status = hdmi_port_clock_valid(hdmi, clock, true); 1205 1206 /* if we can't do 8bpc we may still be able to do 12bpc */ 1207 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) 1208 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); 1209 1210 return status; 1211 } 1212 1213 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) 1214 { 1215 struct drm_device *dev = crtc_state->base.crtc->dev; 1216 struct drm_atomic_state *state; 1217 struct intel_encoder *encoder; 1218 struct drm_connector *connector; 1219 struct drm_connector_state *connector_state; 1220 int count = 0, count_hdmi = 0; 1221 int i; 1222 1223 if (HAS_GMCH_DISPLAY(dev)) 1224 return false; 1225 1226 state = crtc_state->base.state; 1227 1228 for_each_connector_in_state(state, connector, connector_state, i) { 1229 if (connector_state->crtc != crtc_state->base.crtc) 1230 continue; 1231 1232 encoder = to_intel_encoder(connector_state->best_encoder); 1233 1234 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; 1235 count++; 1236 } 1237 1238 /* 1239 * HDMI 12bpc affects the clocks, so it's only possible 1240 * when not cloning with other encoder types. 1241 */ 1242 return count_hdmi > 0 && count_hdmi == count; 1243 } 1244 1245 bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1246 struct intel_crtc_state *pipe_config) 1247 { 1248 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1249 struct drm_device *dev = encoder->base.dev; 1250 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1251 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; 1252 int clock_12bpc = clock_8bpc * 3 / 2; 1253 int desired_bpp; 1254 1255 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; 1256 1257 if (pipe_config->has_hdmi_sink) 1258 pipe_config->has_infoframe = true; 1259 1260 if (intel_hdmi->color_range_auto) { 1261 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1262 if (pipe_config->has_hdmi_sink && 1263 drm_match_cea_mode(adjusted_mode) > 1) 1264 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 1265 else 1266 intel_hdmi->color_range = 0; 1267 } 1268 1269 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { 1270 pipe_config->pixel_multiplier = 2; 1271 clock_8bpc *= 2; 1272 clock_12bpc *= 2; 1273 } 1274 1275 if (intel_hdmi->color_range) 1276 pipe_config->limited_color_range = true; 1277 1278 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) 1279 pipe_config->has_pch_encoder = true; 1280 1281 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) 1282 pipe_config->has_audio = true; 1283 1284 /* 1285 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 1286 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi 1287 * outputs. We also need to check that the higher clock still fits 1288 * within limits. 1289 */ 1290 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && 1291 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && 1292 hdmi_12bpc_possible(pipe_config)) { 1293 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 1294 desired_bpp = 12*3; 1295 1296 /* Need to adjust the port link by 1.5x for 12bpc. */ 1297 pipe_config->port_clock = clock_12bpc; 1298 } else { 1299 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); 1300 desired_bpp = 8*3; 1301 1302 pipe_config->port_clock = clock_8bpc; 1303 } 1304 1305 if (!pipe_config->bw_constrained) { 1306 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); 1307 pipe_config->pipe_bpp = desired_bpp; 1308 } 1309 1310 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, 1311 false) != MODE_OK) { 1312 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); 1313 return false; 1314 } 1315 1316 return true; 1317 } 1318 1319 static void 1320 intel_hdmi_unset_edid(struct drm_connector *connector) 1321 { 1322 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1323 1324 intel_hdmi->has_hdmi_sink = false; 1325 intel_hdmi->has_audio = false; 1326 intel_hdmi->rgb_quant_range_selectable = false; 1327 1328 kfree(to_intel_connector(connector)->detect_edid); 1329 to_intel_connector(connector)->detect_edid = NULL; 1330 } 1331 1332 static bool 1333 intel_hdmi_set_edid(struct drm_connector *connector) 1334 { 1335 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1336 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1337 struct intel_encoder *intel_encoder = 1338 &hdmi_to_dig_port(intel_hdmi)->base; 1339 enum intel_display_power_domain power_domain; 1340 struct edid *edid; 1341 bool connected = false; 1342 1343 power_domain = intel_display_port_power_domain(intel_encoder); 1344 intel_display_power_get(dev_priv, power_domain); 1345 1346 edid = drm_get_edid(connector, 1347 intel_gmbus_get_adapter(dev_priv, 1348 intel_hdmi->ddc_bus)); 1349 1350 intel_display_power_put(dev_priv, power_domain); 1351 1352 to_intel_connector(connector)->detect_edid = edid; 1353 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 1354 intel_hdmi->rgb_quant_range_selectable = 1355 drm_rgb_quant_range_selectable(edid); 1356 1357 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 1358 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1359 intel_hdmi->has_audio = 1360 intel_hdmi->force_audio == HDMI_AUDIO_ON; 1361 1362 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 1363 intel_hdmi->has_hdmi_sink = 1364 drm_detect_hdmi_monitor(edid); 1365 1366 connected = true; 1367 } 1368 1369 return connected; 1370 } 1371 1372 static enum drm_connector_status 1373 intel_hdmi_detect(struct drm_connector *connector, bool force) 1374 { 1375 enum drm_connector_status status; 1376 1377 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1378 connector->base.id, connector->name); 1379 1380 intel_hdmi_unset_edid(connector); 1381 1382 if (intel_hdmi_set_edid(connector)) { 1383 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1384 1385 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1386 status = connector_status_connected; 1387 } else 1388 status = connector_status_disconnected; 1389 1390 return status; 1391 } 1392 1393 static void 1394 intel_hdmi_force(struct drm_connector *connector) 1395 { 1396 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1397 1398 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1399 connector->base.id, connector->name); 1400 1401 intel_hdmi_unset_edid(connector); 1402 1403 if (connector->status != connector_status_connected) 1404 return; 1405 1406 intel_hdmi_set_edid(connector); 1407 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; 1408 } 1409 1410 static int intel_hdmi_get_modes(struct drm_connector *connector) 1411 { 1412 struct edid *edid; 1413 1414 edid = to_intel_connector(connector)->detect_edid; 1415 if (edid == NULL) 1416 return 0; 1417 1418 return intel_connector_update_modes(connector, edid); 1419 } 1420 1421 static bool 1422 intel_hdmi_detect_audio(struct drm_connector *connector) 1423 { 1424 bool has_audio = false; 1425 struct edid *edid; 1426 1427 edid = to_intel_connector(connector)->detect_edid; 1428 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) 1429 has_audio = drm_detect_monitor_audio(edid); 1430 1431 return has_audio; 1432 } 1433 1434 static int 1435 intel_hdmi_set_property(struct drm_connector *connector, 1436 struct drm_property *property, 1437 uint64_t val) 1438 { 1439 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1440 struct intel_digital_port *intel_dig_port = 1441 hdmi_to_dig_port(intel_hdmi); 1442 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1443 int ret; 1444 1445 ret = drm_object_property_set_value(&connector->base, property, val); 1446 if (ret) 1447 return ret; 1448 1449 if (property == dev_priv->force_audio_property) { 1450 enum hdmi_force_audio i = val; 1451 bool has_audio; 1452 1453 if (i == intel_hdmi->force_audio) 1454 return 0; 1455 1456 intel_hdmi->force_audio = i; 1457 1458 if (i == HDMI_AUDIO_AUTO) 1459 has_audio = intel_hdmi_detect_audio(connector); 1460 else 1461 has_audio = (i == HDMI_AUDIO_ON); 1462 1463 if (i == HDMI_AUDIO_OFF_DVI) 1464 intel_hdmi->has_hdmi_sink = 0; 1465 1466 intel_hdmi->has_audio = has_audio; 1467 goto done; 1468 } 1469 1470 if (property == dev_priv->broadcast_rgb_property) { 1471 bool old_auto = intel_hdmi->color_range_auto; 1472 uint32_t old_range = intel_hdmi->color_range; 1473 1474 switch (val) { 1475 case INTEL_BROADCAST_RGB_AUTO: 1476 intel_hdmi->color_range_auto = true; 1477 break; 1478 case INTEL_BROADCAST_RGB_FULL: 1479 intel_hdmi->color_range_auto = false; 1480 intel_hdmi->color_range = 0; 1481 break; 1482 case INTEL_BROADCAST_RGB_LIMITED: 1483 intel_hdmi->color_range_auto = false; 1484 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; 1485 break; 1486 default: 1487 return -EINVAL; 1488 } 1489 1490 if (old_auto == intel_hdmi->color_range_auto && 1491 old_range == intel_hdmi->color_range) 1492 return 0; 1493 1494 goto done; 1495 } 1496 1497 if (property == connector->dev->mode_config.aspect_ratio_property) { 1498 switch (val) { 1499 case DRM_MODE_PICTURE_ASPECT_NONE: 1500 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1501 break; 1502 case DRM_MODE_PICTURE_ASPECT_4_3: 1503 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 1504 break; 1505 case DRM_MODE_PICTURE_ASPECT_16_9: 1506 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 1507 break; 1508 default: 1509 return -EINVAL; 1510 } 1511 goto done; 1512 } 1513 1514 return -EINVAL; 1515 1516 done: 1517 if (intel_dig_port->base.base.crtc) 1518 intel_crtc_restore_mode(intel_dig_port->base.base.crtc); 1519 1520 return 0; 1521 } 1522 1523 static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 1524 { 1525 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1526 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1527 struct drm_display_mode *adjusted_mode = 1528 &intel_crtc->config->base.adjusted_mode; 1529 1530 intel_hdmi_prepare(encoder); 1531 1532 intel_hdmi->set_infoframes(&encoder->base, 1533 intel_crtc->config->has_hdmi_sink, 1534 adjusted_mode); 1535 } 1536 1537 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) 1538 { 1539 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1540 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1541 struct drm_device *dev = encoder->base.dev; 1542 struct drm_i915_private *dev_priv = dev->dev_private; 1543 struct intel_crtc *intel_crtc = 1544 to_intel_crtc(encoder->base.crtc); 1545 struct drm_display_mode *adjusted_mode = 1546 &intel_crtc->config->base.adjusted_mode; 1547 enum dpio_channel port = vlv_dport_to_channel(dport); 1548 int pipe = intel_crtc->pipe; 1549 u32 val; 1550 1551 /* Enable clock channels for this port */ 1552 mutex_lock(&dev_priv->sb_lock); 1553 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1554 val = 0; 1555 if (pipe) 1556 val |= (1<<21); 1557 else 1558 val &= ~(1<<21); 1559 val |= 0x001000c4; 1560 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1561 1562 /* HDMI 1.0V-2dB */ 1563 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); 1564 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); 1565 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); 1566 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); 1567 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); 1568 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1569 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1570 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1571 1572 /* Program lane clock */ 1573 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1574 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1575 mutex_unlock(&dev_priv->sb_lock); 1576 1577 intel_hdmi->set_infoframes(&encoder->base, 1578 intel_crtc->config->has_hdmi_sink, 1579 adjusted_mode); 1580 1581 g4x_enable_hdmi(encoder); 1582 1583 vlv_wait_port_ready(dev_priv, dport, 0x0); 1584 } 1585 1586 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1587 { 1588 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1589 struct drm_device *dev = encoder->base.dev; 1590 struct drm_i915_private *dev_priv = dev->dev_private; 1591 struct intel_crtc *intel_crtc = 1592 to_intel_crtc(encoder->base.crtc); 1593 enum dpio_channel port = vlv_dport_to_channel(dport); 1594 int pipe = intel_crtc->pipe; 1595 1596 intel_hdmi_prepare(encoder); 1597 1598 /* Program Tx lane resets to default */ 1599 mutex_lock(&dev_priv->sb_lock); 1600 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1601 DPIO_PCS_TX_LANE2_RESET | 1602 DPIO_PCS_TX_LANE1_RESET); 1603 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1604 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1605 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1606 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1607 DPIO_PCS_CLK_SOFT_RESET); 1608 1609 /* Fix up inter-pair skew failure */ 1610 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1611 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1612 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1613 1614 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); 1615 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1616 mutex_unlock(&dev_priv->sb_lock); 1617 } 1618 1619 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1620 { 1621 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1622 struct drm_device *dev = encoder->base.dev; 1623 struct drm_i915_private *dev_priv = dev->dev_private; 1624 struct intel_crtc *intel_crtc = 1625 to_intel_crtc(encoder->base.crtc); 1626 enum dpio_channel ch = vlv_dport_to_channel(dport); 1627 enum i915_pipe pipe = intel_crtc->pipe; 1628 u32 val; 1629 1630 intel_hdmi_prepare(encoder); 1631 1632 mutex_lock(&dev_priv->sb_lock); 1633 1634 /* program left/right clock distribution */ 1635 if (pipe != PIPE_B) { 1636 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1637 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1638 if (ch == DPIO_CH0) 1639 val |= CHV_BUFLEFTENA1_FORCE; 1640 if (ch == DPIO_CH1) 1641 val |= CHV_BUFRIGHTENA1_FORCE; 1642 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1643 } else { 1644 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1645 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1646 if (ch == DPIO_CH0) 1647 val |= CHV_BUFLEFTENA2_FORCE; 1648 if (ch == DPIO_CH1) 1649 val |= CHV_BUFRIGHTENA2_FORCE; 1650 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1651 } 1652 1653 /* program clock channel usage */ 1654 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 1655 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1656 if (pipe != PIPE_B) 1657 val &= ~CHV_PCS_USEDCLKCHANNEL; 1658 else 1659 val |= CHV_PCS_USEDCLKCHANNEL; 1660 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 1661 1662 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 1663 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 1664 if (pipe != PIPE_B) 1665 val &= ~CHV_PCS_USEDCLKCHANNEL; 1666 else 1667 val |= CHV_PCS_USEDCLKCHANNEL; 1668 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 1669 1670 /* 1671 * This a a bit weird since generally CL 1672 * matches the pipe, but here we need to 1673 * pick the CL based on the port. 1674 */ 1675 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 1676 if (pipe != PIPE_B) 1677 val &= ~CHV_CMN_USEDCLKCHANNEL; 1678 else 1679 val |= CHV_CMN_USEDCLKCHANNEL; 1680 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 1681 1682 mutex_unlock(&dev_priv->sb_lock); 1683 } 1684 1685 static void vlv_hdmi_post_disable(struct intel_encoder *encoder) 1686 { 1687 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1688 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1689 struct intel_crtc *intel_crtc = 1690 to_intel_crtc(encoder->base.crtc); 1691 enum dpio_channel port = vlv_dport_to_channel(dport); 1692 int pipe = intel_crtc->pipe; 1693 1694 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1695 mutex_lock(&dev_priv->sb_lock); 1696 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1697 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1698 mutex_unlock(&dev_priv->sb_lock); 1699 } 1700 1701 static void chv_hdmi_post_disable(struct intel_encoder *encoder) 1702 { 1703 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1704 struct drm_device *dev = encoder->base.dev; 1705 struct drm_i915_private *dev_priv = dev->dev_private; 1706 struct intel_crtc *intel_crtc = 1707 to_intel_crtc(encoder->base.crtc); 1708 enum dpio_channel ch = vlv_dport_to_channel(dport); 1709 enum i915_pipe pipe = intel_crtc->pipe; 1710 u32 val; 1711 1712 mutex_lock(&dev_priv->sb_lock); 1713 1714 /* Propagate soft reset to data lane reset */ 1715 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1716 val |= CHV_PCS_REQ_SOFTRESET_EN; 1717 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1718 1719 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1720 val |= CHV_PCS_REQ_SOFTRESET_EN; 1721 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1722 1723 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1724 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1725 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1726 1727 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1728 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1729 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1730 1731 mutex_unlock(&dev_priv->sb_lock); 1732 } 1733 1734 static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 1735 { 1736 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1737 struct intel_hdmi *intel_hdmi = &dport->hdmi; 1738 struct drm_device *dev = encoder->base.dev; 1739 struct drm_i915_private *dev_priv = dev->dev_private; 1740 struct intel_crtc *intel_crtc = 1741 to_intel_crtc(encoder->base.crtc); 1742 struct drm_display_mode *adjusted_mode = 1743 &intel_crtc->config->base.adjusted_mode; 1744 enum dpio_channel ch = vlv_dport_to_channel(dport); 1745 int pipe = intel_crtc->pipe; 1746 int data, i, stagger; 1747 u32 val; 1748 1749 mutex_lock(&dev_priv->sb_lock); 1750 1751 /* allow hardware to manage TX FIFO reset source */ 1752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1753 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1754 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1755 1756 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1757 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 1758 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1759 1760 /* Deassert soft data lane reset*/ 1761 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1762 val |= CHV_PCS_REQ_SOFTRESET_EN; 1763 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1764 1765 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1766 val |= CHV_PCS_REQ_SOFTRESET_EN; 1767 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1768 1769 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1770 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1771 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1772 1773 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1774 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1775 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1776 1777 /* Program Tx latency optimal setting */ 1778 for (i = 0; i < 4; i++) { 1779 /* Set the upar bit */ 1780 data = (i == 1) ? 0x0 : 0x1; 1781 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 1782 data << DPIO_UPAR_SHIFT); 1783 } 1784 1785 /* Data lane stagger programming */ 1786 if (intel_crtc->config->port_clock > 270000) 1787 stagger = 0x18; 1788 else if (intel_crtc->config->port_clock > 135000) 1789 stagger = 0xd; 1790 else if (intel_crtc->config->port_clock > 67500) 1791 stagger = 0x7; 1792 else if (intel_crtc->config->port_clock > 33750) 1793 stagger = 0x4; 1794 else 1795 stagger = 0x2; 1796 1797 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 1798 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1799 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 1800 1801 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 1802 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1803 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 1804 1805 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 1806 DPIO_LANESTAGGER_STRAP(stagger) | 1807 DPIO_LANESTAGGER_STRAP_OVRD | 1808 DPIO_TX1_STAGGER_MASK(0x1f) | 1809 DPIO_TX1_STAGGER_MULT(6) | 1810 DPIO_TX2_STAGGER_MULT(0)); 1811 1812 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 1813 DPIO_LANESTAGGER_STRAP(stagger) | 1814 DPIO_LANESTAGGER_STRAP_OVRD | 1815 DPIO_TX1_STAGGER_MASK(0x1f) | 1816 DPIO_TX1_STAGGER_MULT(7) | 1817 DPIO_TX2_STAGGER_MULT(5)); 1818 1819 /* Clear calc init */ 1820 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1821 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1822 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 1823 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 1824 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1825 1826 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1827 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 1828 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 1829 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 1830 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1831 1832 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 1833 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 1834 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 1835 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 1836 1837 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 1838 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 1839 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 1840 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 1841 1842 /* FIXME: Program the support xxx V-dB */ 1843 /* Use 800mV-0dB */ 1844 for (i = 0; i < 4; i++) { 1845 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 1846 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 1847 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; 1848 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 1849 } 1850 1851 for (i = 0; i < 4; i++) { 1852 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 1853 val &= ~DPIO_SWING_MARGIN000_MASK; 1854 val |= 102 << DPIO_SWING_MARGIN000_SHIFT; 1855 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 1856 } 1857 1858 /* Disable unique transition scale */ 1859 for (i = 0; i < 4; i++) { 1860 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 1861 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 1862 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 1863 } 1864 1865 /* Additional steps for 1200mV-0dB */ 1866 #if 0 1867 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); 1868 if (ch) 1869 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; 1870 else 1871 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; 1872 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); 1873 1874 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), 1875 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | 1876 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); 1877 #endif 1878 /* Start swing calculation */ 1879 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 1880 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1881 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 1882 1883 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 1884 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 1885 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 1886 1887 /* LRC Bypass */ 1888 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1889 val |= DPIO_LRC_BYPASS; 1890 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); 1891 1892 mutex_unlock(&dev_priv->sb_lock); 1893 1894 intel_hdmi->set_infoframes(&encoder->base, 1895 intel_crtc->config->has_hdmi_sink, 1896 adjusted_mode); 1897 1898 g4x_enable_hdmi(encoder); 1899 1900 vlv_wait_port_ready(dev_priv, dport, 0x0); 1901 } 1902 1903 static void intel_hdmi_destroy(struct drm_connector *connector) 1904 { 1905 kfree(to_intel_connector(connector)->detect_edid); 1906 drm_connector_cleanup(connector); 1907 kfree(connector); 1908 } 1909 1910 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 1911 .dpms = drm_atomic_helper_connector_dpms, 1912 .detect = intel_hdmi_detect, 1913 .force = intel_hdmi_force, 1914 .fill_modes = drm_helper_probe_single_connector_modes, 1915 .set_property = intel_hdmi_set_property, 1916 .atomic_get_property = intel_connector_atomic_get_property, 1917 .destroy = intel_hdmi_destroy, 1918 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1919 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1920 }; 1921 1922 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 1923 .get_modes = intel_hdmi_get_modes, 1924 .mode_valid = intel_hdmi_mode_valid, 1925 .best_encoder = intel_best_encoder, 1926 }; 1927 1928 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 1929 .destroy = intel_encoder_destroy, 1930 }; 1931 1932 static void 1933 intel_attach_aspect_ratio_property(struct drm_connector *connector) 1934 { 1935 if (!drm_mode_create_aspect_ratio_property(connector->dev)) 1936 drm_object_attach_property(&connector->base, 1937 connector->dev->mode_config.aspect_ratio_property, 1938 DRM_MODE_PICTURE_ASPECT_NONE); 1939 } 1940 1941 static void 1942 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 1943 { 1944 intel_attach_force_audio_property(connector); 1945 intel_attach_broadcast_rgb_property(connector); 1946 intel_hdmi->color_range_auto = true; 1947 intel_attach_aspect_ratio_property(connector); 1948 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 1949 } 1950 1951 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 1952 struct intel_connector *intel_connector) 1953 { 1954 struct drm_connector *connector = &intel_connector->base; 1955 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1956 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1957 struct drm_device *dev = intel_encoder->base.dev; 1958 struct drm_i915_private *dev_priv = dev->dev_private; 1959 enum port port = intel_dig_port->port; 1960 uint8_t alternate_ddc_pin; 1961 1962 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 1963 DRM_MODE_CONNECTOR_HDMIA); 1964 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 1965 1966 connector->interlace_allowed = 1; 1967 connector->doublescan_allowed = 0; 1968 connector->stereo_allowed = 1; 1969 1970 switch (port) { 1971 case PORT_B: 1972 if (IS_BROXTON(dev_priv)) 1973 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; 1974 else 1975 intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 1976 intel_encoder->hpd_pin = HPD_PORT_B; 1977 break; 1978 case PORT_C: 1979 if (IS_BROXTON(dev_priv)) 1980 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; 1981 else 1982 intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 1983 intel_encoder->hpd_pin = HPD_PORT_C; 1984 break; 1985 case PORT_D: 1986 if (WARN_ON(IS_BROXTON(dev_priv))) 1987 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; 1988 else if (IS_CHERRYVIEW(dev_priv)) 1989 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; 1990 else 1991 intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 1992 intel_encoder->hpd_pin = HPD_PORT_D; 1993 break; 1994 case PORT_E: 1995 /* On SKL PORT E doesn't have seperate GMBUS pin 1996 * We rely on VBT to set a proper alternate GMBUS pin. */ 1997 alternate_ddc_pin = 1998 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; 1999 switch (alternate_ddc_pin) { 2000 case DDC_PIN_B: 2001 intel_hdmi->ddc_bus = GMBUS_PIN_DPB; 2002 break; 2003 case DDC_PIN_C: 2004 intel_hdmi->ddc_bus = GMBUS_PIN_DPC; 2005 break; 2006 case DDC_PIN_D: 2007 intel_hdmi->ddc_bus = GMBUS_PIN_DPD; 2008 break; 2009 default: 2010 MISSING_CASE(alternate_ddc_pin); 2011 } 2012 intel_encoder->hpd_pin = HPD_PORT_E; 2013 break; 2014 case PORT_A: 2015 intel_encoder->hpd_pin = HPD_PORT_A; 2016 /* Internal port only for eDP. */ 2017 default: 2018 BUG(); 2019 } 2020 2021 if (IS_VALLEYVIEW(dev)) { 2022 intel_hdmi->write_infoframe = vlv_write_infoframe; 2023 intel_hdmi->set_infoframes = vlv_set_infoframes; 2024 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; 2025 } else if (IS_G4X(dev)) { 2026 intel_hdmi->write_infoframe = g4x_write_infoframe; 2027 intel_hdmi->set_infoframes = g4x_set_infoframes; 2028 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; 2029 } else if (HAS_DDI(dev)) { 2030 intel_hdmi->write_infoframe = hsw_write_infoframe; 2031 intel_hdmi->set_infoframes = hsw_set_infoframes; 2032 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; 2033 } else if (HAS_PCH_IBX(dev)) { 2034 intel_hdmi->write_infoframe = ibx_write_infoframe; 2035 intel_hdmi->set_infoframes = ibx_set_infoframes; 2036 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; 2037 } else { 2038 intel_hdmi->write_infoframe = cpt_write_infoframe; 2039 intel_hdmi->set_infoframes = cpt_set_infoframes; 2040 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; 2041 } 2042 2043 if (HAS_DDI(dev)) 2044 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2045 else 2046 intel_connector->get_hw_state = intel_connector_get_hw_state; 2047 intel_connector->unregister = intel_connector_unregister; 2048 2049 intel_hdmi_add_properties(intel_hdmi, connector); 2050 2051 intel_connector_attach_encoder(intel_connector, intel_encoder); 2052 drm_connector_register(connector); 2053 2054 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2055 * 0xd. Failure to do so will result in spurious interrupts being 2056 * generated on the port when a cable is not attached. 2057 */ 2058 if (IS_G4X(dev) && !IS_GM45(dev)) { 2059 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2060 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2061 } 2062 } 2063 2064 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) 2065 { 2066 struct intel_digital_port *intel_dig_port; 2067 struct intel_encoder *intel_encoder; 2068 struct intel_connector *intel_connector; 2069 2070 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2071 if (!intel_dig_port) 2072 return; 2073 2074 intel_connector = intel_connector_alloc(); 2075 if (!intel_connector) { 2076 kfree(intel_dig_port); 2077 return; 2078 } 2079 2080 intel_encoder = &intel_dig_port->base; 2081 2082 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 2083 DRM_MODE_ENCODER_TMDS); 2084 2085 intel_encoder->compute_config = intel_hdmi_compute_config; 2086 if (HAS_PCH_SPLIT(dev)) { 2087 intel_encoder->disable = pch_disable_hdmi; 2088 intel_encoder->post_disable = pch_post_disable_hdmi; 2089 } else { 2090 intel_encoder->disable = g4x_disable_hdmi; 2091 } 2092 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 2093 intel_encoder->get_config = intel_hdmi_get_config; 2094 if (IS_CHERRYVIEW(dev)) { 2095 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 2096 intel_encoder->pre_enable = chv_hdmi_pre_enable; 2097 intel_encoder->enable = vlv_enable_hdmi; 2098 intel_encoder->post_disable = chv_hdmi_post_disable; 2099 } else if (IS_VALLEYVIEW(dev)) { 2100 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 2101 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 2102 intel_encoder->enable = vlv_enable_hdmi; 2103 intel_encoder->post_disable = vlv_hdmi_post_disable; 2104 } else { 2105 intel_encoder->pre_enable = intel_hdmi_pre_enable; 2106 if (HAS_PCH_CPT(dev)) 2107 intel_encoder->enable = cpt_enable_hdmi; 2108 else if (HAS_PCH_IBX(dev)) 2109 intel_encoder->enable = ibx_enable_hdmi; 2110 else 2111 intel_encoder->enable = g4x_enable_hdmi; 2112 } 2113 2114 intel_encoder->type = INTEL_OUTPUT_HDMI; 2115 if (IS_CHERRYVIEW(dev)) { 2116 if (port == PORT_D) 2117 intel_encoder->crtc_mask = 1 << 2; 2118 else 2119 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 2120 } else { 2121 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2122 } 2123 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 2124 /* 2125 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 2126 * to work on real hardware. And since g4x can send infoframes to 2127 * only one port anyway, nothing is lost by allowing it. 2128 */ 2129 if (IS_G4X(dev)) 2130 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 2131 2132 intel_dig_port->port = port; 2133 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 2134 intel_dig_port->dp.output_reg = 0; 2135 2136 intel_hdmi_init_connector(intel_dig_port, intel_connector); 2137 } 2138