1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 * 29 * Copyright (c) 2011 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * This software was developed by Konstantin Belousov under sponsorship from 33 * the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/mplock2.h> 58 59 #include <linux/i2c.h> 60 #include <linux/export.h> 61 #include <drm/drmP.h> 62 #include "intel_drv.h" 63 #include <drm/i915_drm.h> 64 #include "i915_drv.h" 65 66 #include <bus/iicbus/iic.h> 67 #include <bus/iicbus/iiconf.h> 68 #include <bus/iicbus/iicbus.h> 69 #include "iicbus_if.h" 70 #include "iicbb_if.h" 71 72 struct gmbus_port { 73 const char *name; 74 int reg; 75 }; 76 77 static const struct gmbus_port gmbus_ports[] = { 78 { "ssc", GPIOB }, 79 { "vga", GPIOA }, 80 { "panel", GPIOC }, 81 { "dpc", GPIOD }, 82 { "dpb", GPIOE }, 83 { "dpd", GPIOF }, 84 }; 85 86 /* Intel GPIO access functions */ 87 88 #define I2C_RISEFALL_TIME 10 89 90 void 91 intel_i2c_reset(struct drm_device *dev) 92 { 93 struct drm_i915_private *dev_priv = dev->dev_private; 94 95 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); 96 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); 97 } 98 99 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 100 { 101 u32 val; 102 103 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 104 if (!IS_PINEVIEW(dev_priv->dev)) 105 return; 106 107 val = I915_READ(DSPCLK_GATE_D); 108 if (enable) 109 val |= DPCUNIT_CLOCK_GATE_DISABLE; 110 else 111 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 112 I915_WRITE(DSPCLK_GATE_D, val); 113 } 114 115 static u32 get_reserved(device_t idev) 116 { 117 struct intel_iic_softc *sc = device_get_softc(idev); 118 struct drm_device *dev = sc->drm_dev; 119 struct drm_i915_private *dev_priv; 120 u32 reserved = 0; 121 122 dev_priv = dev->dev_private; 123 124 /* On most chips, these bits must be preserved in software. */ 125 if (!IS_I830(dev) && !IS_845G(dev)) 126 reserved = I915_READ_NOTRACE(sc->reg) & 127 (GPIO_DATA_PULLUP_DISABLE | 128 GPIO_CLOCK_PULLUP_DISABLE); 129 130 return reserved; 131 } 132 133 static int get_clock(device_t idev) 134 { 135 struct intel_iic_softc *sc; 136 struct drm_i915_private *dev_priv; 137 u32 reserved; 138 139 sc = device_get_softc(idev); 140 dev_priv = sc->drm_dev->dev_private; 141 142 reserved = get_reserved(idev); 143 144 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK); 145 I915_WRITE_NOTRACE(sc->reg, reserved); 146 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0); 147 } 148 149 static int get_data(device_t idev) 150 { 151 struct intel_iic_softc *sc; 152 struct drm_i915_private *dev_priv; 153 u32 reserved; 154 155 sc = device_get_softc(idev); 156 dev_priv = sc->drm_dev->dev_private; 157 158 reserved = get_reserved(idev); 159 160 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK); 161 I915_WRITE_NOTRACE(sc->reg, reserved); 162 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0); 163 } 164 165 static int 166 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 167 { 168 struct intel_iic_softc *sc; 169 struct drm_device *dev; 170 171 sc = device_get_softc(idev); 172 dev = sc->drm_dev; 173 174 intel_i2c_reset(dev); 175 return (0); 176 } 177 178 static void set_clock(device_t idev, int val) 179 { 180 struct intel_iic_softc *sc; 181 struct drm_i915_private *dev_priv; 182 u32 clock_bits, reserved; 183 184 sc = device_get_softc(idev); 185 dev_priv = sc->drm_dev->dev_private; 186 187 reserved = get_reserved(idev); 188 if (val) 189 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 190 else 191 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 192 GPIO_CLOCK_VAL_MASK; 193 194 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits); 195 POSTING_READ(sc->reg); 196 } 197 198 static void set_data(device_t idev, int val) 199 { 200 struct intel_iic_softc *sc; 201 struct drm_i915_private *dev_priv; 202 u32 reserved; 203 u32 data_bits; 204 205 sc = device_get_softc(idev); 206 dev_priv = sc->drm_dev->dev_private; 207 208 reserved = get_reserved(idev); 209 210 if (val) 211 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 212 else 213 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 214 GPIO_DATA_VAL_MASK; 215 216 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits); 217 POSTING_READ(sc->reg); 218 } 219 220 static const char *gpio_names[GMBUS_NUM_PORTS] = { 221 "ssc", 222 "vga", 223 "panel", 224 "dpc", 225 "dpb", 226 "dpd", 227 }; 228 229 static int 230 intel_gpio_setup(device_t idev) 231 { 232 static const int map_pin_to_reg[] = { 233 0, 234 GPIOB, 235 GPIOA, 236 GPIOC, 237 GPIOD, 238 GPIOE, 239 GPIOF, 240 0 241 }; 242 243 struct intel_iic_softc *sc; 244 struct drm_i915_private *dev_priv; 245 int pin; 246 247 sc = device_get_softc(idev); 248 sc->drm_dev = device_get_softc(device_get_parent(idev)); 249 dev_priv = sc->drm_dev->dev_private; 250 pin = device_get_unit(idev); 251 252 ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]); 253 device_set_desc(idev, sc->name); 254 255 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 256 sc->reg = dev_priv->gpio_mmio_base + map_pin_to_reg[pin + 1]; 257 258 /* add generic bit-banging code */ 259 sc->iic_dev = device_add_child(idev, "iicbb", -1); 260 if (sc->iic_dev == NULL) 261 return (ENXIO); 262 device_quiet(sc->iic_dev); 263 bus_generic_attach(idev); 264 265 return (0); 266 } 267 268 static int 269 intel_i2c_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs) 270 { 271 device_t bridge_dev; 272 struct intel_iic_softc *sc; 273 struct drm_i915_private *dev_priv; 274 int ret; 275 int i; 276 277 bridge_dev = device_get_parent(device_get_parent(idev)); 278 sc = device_get_softc(bridge_dev); 279 dev_priv = sc->drm_dev->dev_private; 280 281 intel_i2c_reset(sc->drm_dev); 282 intel_i2c_quirk_set(dev_priv, true); 283 IICBB_SETSDA(bridge_dev, 1); 284 IICBB_SETSCL(bridge_dev, 1); 285 DELAY(I2C_RISEFALL_TIME); 286 287 for (i = 0; i < nmsgs - 1; i++) { 288 /* force use of repeated start instead of default stop+start */ 289 msgs[i].flags |= IIC_M_NOSTOP; 290 } 291 ret = iicbus_transfer(idev, msgs, nmsgs); 292 IICBB_SETSDA(bridge_dev, 1); 293 IICBB_SETSCL(bridge_dev, 1); 294 intel_i2c_quirk_set(dev_priv, false); 295 296 return (ret); 297 } 298 299 static int 300 gmbus_wait_hw_status(struct drm_i915_private *dev_priv, 301 u32 gmbus2_status, 302 u32 gmbus4_irq_en) 303 { 304 int i; 305 int reg_offset = dev_priv->gpio_mmio_base; 306 u32 gmbus2 = 0; 307 DEFINE_WAIT(wait); 308 309 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 310 gmbus4_irq_en = 0; 311 312 /* Important: The hw handles only the first bit, so set only one! Since 313 * we also need to check for NAKs besides the hw ready/idle signal, we 314 * need to wake up periodically and check that ourselves. */ 315 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); 316 317 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { 318 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, 319 TASK_UNINTERRUPTIBLE); 320 321 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); 322 if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) 323 break; 324 325 schedule_timeout(1); 326 } 327 finish_wait(&dev_priv->gmbus_wait_queue, &wait); 328 329 I915_WRITE(GMBUS4 + reg_offset, 0); 330 331 if (gmbus2 & GMBUS_SATOER) 332 return -ENXIO; 333 if (gmbus2 & gmbus2_status) 334 return 0; 335 return -ETIMEDOUT; 336 } 337 338 static int 339 gmbus_wait_idle(struct drm_i915_private *dev_priv) 340 { 341 int ret; 342 int reg_offset = dev_priv->gpio_mmio_base; 343 344 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) 345 346 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 347 return wait_for(C, 10); 348 349 /* Important: The hw handles only the first bit, so set only one! */ 350 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); 351 352 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 353 msecs_to_jiffies_timeout(10)); 354 355 I915_WRITE(GMBUS4 + reg_offset, 0); 356 357 if (ret) 358 return 0; 359 else 360 return -ETIMEDOUT; 361 #undef C 362 } 363 364 static int 365 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 366 unsigned short addr, u8 *buf, unsigned int len, 367 u32 gmbus1_index) 368 { 369 int reg_offset = dev_priv->gpio_mmio_base; 370 371 I915_WRITE(GMBUS1 + reg_offset, 372 gmbus1_index | 373 GMBUS_CYCLE_WAIT | 374 (len << GMBUS_BYTE_COUNT_SHIFT) | 375 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 376 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 377 while (len) { 378 int ret; 379 u32 val, loop = 0; 380 381 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 382 GMBUS_HW_RDY_EN); 383 if (ret) 384 return ret; 385 386 val = I915_READ(GMBUS3 + reg_offset); 387 do { 388 *buf++ = val & 0xff; 389 val >>= 8; 390 } while (--len && ++loop < 4); 391 } 392 393 return 0; 394 } 395 396 static int 397 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 398 u32 gmbus1_index) 399 { 400 u8 *buf = msg->buf; 401 unsigned int rx_size = msg->len; 402 unsigned int len; 403 int ret; 404 405 do { 406 len = min(rx_size, GMBUS_BYTE_COUNT_MAX); 407 408 ret = gmbus_xfer_read_chunk(dev_priv, msg->slave >> 1, 409 buf, len, gmbus1_index); 410 if (ret) 411 return ret; 412 413 rx_size -= len; 414 buf += len; 415 } while (rx_size != 0); 416 417 return 0; 418 } 419 420 static int 421 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 422 unsigned short addr, u8 *buf, unsigned int len) 423 { 424 int reg_offset = dev_priv->gpio_mmio_base; 425 unsigned int chunk_size = len; 426 u32 val, loop; 427 428 val = loop = 0; 429 while (len && loop < 4) { 430 val |= *buf++ << (8 * loop++); 431 len -= 1; 432 } 433 434 I915_WRITE(GMBUS3 + reg_offset, val); 435 I915_WRITE(GMBUS1 + reg_offset, 436 GMBUS_CYCLE_WAIT | 437 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | 438 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 439 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 440 while (len) { 441 int ret; 442 443 val = loop = 0; 444 do { 445 val |= *buf++ << (8 * loop); 446 } while (--len && ++loop < 4); 447 448 I915_WRITE(GMBUS3 + reg_offset, val); 449 450 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 451 GMBUS_HW_RDY_EN); 452 if (ret) 453 return ret; 454 } 455 456 return 0; 457 } 458 459 static int 460 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) 461 { 462 u8 *buf = msg->buf; 463 unsigned int tx_size = msg->len; 464 unsigned int len; 465 int ret; 466 467 do { 468 len = min(tx_size, GMBUS_BYTE_COUNT_MAX); 469 470 ret = gmbus_xfer_write_chunk(dev_priv, msg->slave >> 1, buf, len); 471 if (ret) 472 return ret; 473 474 buf += len; 475 tx_size -= len; 476 } while (tx_size != 0); 477 478 return 0; 479 } 480 481 /* 482 * The gmbus controller can combine a 1 or 2 byte write with a read that 483 * immediately follows it by using an "INDEX" cycle. 484 */ 485 static bool 486 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) 487 { 488 return (i + 1 < num && 489 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 490 (msgs[i + 1].flags & I2C_M_RD)); 491 } 492 493 static int 494 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) 495 { 496 int reg_offset = dev_priv->gpio_mmio_base; 497 u32 gmbus1_index = 0; 498 u32 gmbus5 = 0; 499 int ret; 500 501 if (msgs[0].len == 2) 502 gmbus5 = GMBUS_2BYTE_INDEX_EN | 503 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 504 if (msgs[0].len == 1) 505 gmbus1_index = GMBUS_CYCLE_INDEX | 506 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 507 508 /* GMBUS5 holds 16-bit index */ 509 if (gmbus5) 510 I915_WRITE(GMBUS5 + reg_offset, gmbus5); 511 512 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 513 514 /* Clear GMBUS5 after each index transfer */ 515 if (gmbus5) 516 I915_WRITE(GMBUS5 + reg_offset, 0); 517 518 return ret; 519 } 520 521 static int 522 gmbus_xfer(struct device *adapter, 523 struct i2c_msg *msgs, 524 int num) 525 { 526 struct intel_iic_softc *sc; 527 struct drm_i915_private *dev_priv; 528 int i = 0, inc, try = 0, reg_offset; 529 int unit; 530 int ret = 0; 531 532 sc = device_get_softc(adapter); 533 dev_priv = sc->drm_dev->dev_private; 534 unit = device_get_unit(adapter); 535 536 mutex_lock(&dev_priv->gmbus_mutex); 537 538 if (sc->force_bit_dev) { 539 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 540 goto out; 541 } 542 543 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; 544 545 retry: 546 I915_WRITE(GMBUS0 + reg_offset, sc->reg0); 547 548 for (; i < num; i += inc) { 549 inc = 1; 550 if (gmbus_is_index_read(msgs, i, num)) { 551 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 552 inc = 2; /* an index read is two msgs */ 553 } else if (msgs[i].flags & I2C_M_RD) { 554 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 555 } else { 556 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 557 } 558 559 if (ret == -ETIMEDOUT) 560 goto timeout; 561 if (ret == -ENXIO) 562 goto clear_err; 563 564 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, 565 GMBUS_HW_WAIT_EN); 566 if (ret == -ENXIO) 567 goto clear_err; 568 if (ret) 569 goto timeout; 570 } 571 572 /* Generate a STOP condition on the bus. Note that gmbus can't generata 573 * a STOP on the very first cycle. To simplify the code we 574 * unconditionally generate the STOP condition with an additional gmbus 575 * cycle. */ 576 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 577 578 /* Mark the GMBUS interface as disabled after waiting for idle. 579 * We will re-enable it at the start of the next xfer, 580 * till then let it sleep. 581 */ 582 if (gmbus_wait_idle(dev_priv)) { 583 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 584 sc->name); 585 ret = -ETIMEDOUT; 586 } 587 I915_WRITE(GMBUS0 + reg_offset, 0); 588 ret = ret ?: i; 589 goto timeout; /* XXX: should be out */ 590 591 clear_err: 592 /* 593 * Wait for bus to IDLE before clearing NAK. 594 * If we clear the NAK while bus is still active, then it will stay 595 * active and the next transaction may fail. 596 * 597 * If no ACK is received during the address phase of a transaction, the 598 * adapter must report -ENXIO. It is not clear what to return if no ACK 599 * is received at other times. But we have to be careful to not return 600 * spurious -ENXIO because that will prevent i2c and drm edid functions 601 * from retrying. So return -ENXIO only when gmbus properly quiescents - 602 * timing out seems to happen when there _is_ a ddc chip present, but 603 * it's slow responding and only answers on the 2nd retry. 604 */ 605 ret = -ENXIO; 606 if (gmbus_wait_idle(dev_priv)) { 607 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 608 sc->name); 609 ret = -ETIMEDOUT; 610 } 611 612 /* Toggle the Software Clear Interrupt bit. This has the effect 613 * of resetting the GMBUS controller and so clearing the 614 * BUS_ERROR raised by the slave's NAK. 615 */ 616 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 617 I915_WRITE(GMBUS1 + reg_offset, 0); 618 I915_WRITE(GMBUS0 + reg_offset, 0); 619 620 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 621 sc->name, msgs[i].slave, 622 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 623 624 /* 625 * Passive adapters sometimes NAK the first probe. Retry the first 626 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 627 * has retries internally. See also the retry loop in 628 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 629 */ 630 if (ret == -ENXIO && i == 0 && try++ == 0) { 631 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", 632 sc->name); 633 goto retry; 634 } 635 636 goto out; 637 638 timeout: 639 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 640 sc->name, sc->reg0 & 0xff); 641 I915_WRITE(GMBUS0 + reg_offset, 0); 642 643 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 644 sc->force_bit_dev = true; 645 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 646 647 out: 648 mutex_unlock(&dev_priv->gmbus_mutex); 649 return ret; 650 } 651 652 struct device *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 653 unsigned port) 654 { 655 WARN_ON(!intel_gmbus_is_port_valid(port)); 656 /* -1 to map pin pair to gmbus index */ 657 return (intel_gmbus_is_port_valid(port)) ? 658 dev_priv->gmbus[port-1] : NULL; 659 } 660 661 void 662 intel_gmbus_set_speed(device_t idev, int speed) 663 { 664 struct intel_iic_softc *sc; 665 666 sc = device_get_softc(device_get_parent(idev)); 667 668 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed; 669 } 670 671 void 672 intel_gmbus_force_bit(device_t idev, bool force_bit) 673 { 674 struct intel_iic_softc *sc; 675 676 sc = device_get_softc(device_get_parent(idev)); 677 sc->force_bit_dev += force_bit ? 1 : -1; 678 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 679 force_bit ? "en" : "dis", sc->name, 680 sc->force_bit_dev); 681 } 682 683 static int 684 intel_gmbus_probe(device_t dev) 685 { 686 687 return (BUS_PROBE_SPECIFIC); 688 } 689 690 static int 691 intel_gmbus_attach(device_t idev) 692 { 693 struct drm_i915_private *dev_priv; 694 struct intel_iic_softc *sc; 695 int pin; 696 697 sc = device_get_softc(idev); 698 sc->drm_dev = device_get_softc(device_get_parent(idev)); 699 dev_priv = sc->drm_dev->dev_private; 700 pin = device_get_unit(idev); 701 702 ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]); 703 device_set_desc(idev, sc->name); 704 705 /* By default use a conservative clock rate */ 706 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 707 708 /* XXX force bit banging until GMBUS is fully debugged */ 709 if (IS_GEN2(sc->drm_dev)) { 710 sc->force_bit_dev = true; 711 } 712 713 /* add bus interface device */ 714 sc->iic_dev = device_add_child(idev, "iicbus", -1); 715 if (sc->iic_dev == NULL) 716 return (ENXIO); 717 device_quiet(sc->iic_dev); 718 bus_generic_attach(idev); 719 720 return (0); 721 } 722 723 static int 724 intel_gmbus_detach(device_t idev) 725 { 726 struct intel_iic_softc *sc; 727 struct drm_i915_private *dev_priv; 728 device_t child; 729 int u; 730 731 sc = device_get_softc(idev); 732 u = device_get_unit(idev); 733 dev_priv = sc->drm_dev->dev_private; 734 735 child = sc->iic_dev; 736 bus_generic_detach(idev); 737 if (child != NULL) 738 device_delete_child(idev, child); 739 740 return (0); 741 } 742 743 static int 744 intel_iicbb_probe(device_t dev) 745 { 746 747 return (BUS_PROBE_DEFAULT); 748 } 749 750 static int 751 intel_iicbb_detach(device_t idev) 752 { 753 struct intel_iic_softc *sc; 754 device_t child; 755 756 sc = device_get_softc(idev); 757 child = sc->iic_dev; 758 bus_generic_detach(idev); 759 if (child) 760 device_delete_child(idev, child); 761 return (0); 762 } 763 764 static device_method_t intel_gmbus_methods[] = { 765 DEVMETHOD(device_probe, intel_gmbus_probe), 766 DEVMETHOD(device_attach, intel_gmbus_attach), 767 DEVMETHOD(device_detach, intel_gmbus_detach), 768 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 769 DEVMETHOD(iicbus_transfer, gmbus_xfer), 770 DEVMETHOD_END 771 }; 772 static driver_t intel_gmbus_driver = { 773 "intel_gmbus", 774 intel_gmbus_methods, 775 sizeof(struct intel_iic_softc) 776 }; 777 static devclass_t intel_gmbus_devclass; 778 DRIVER_MODULE_ORDERED(intel_gmbus, drm, intel_gmbus_driver, 779 intel_gmbus_devclass, NULL, NULL, SI_ORDER_FIRST); 780 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, NULL, NULL); 781 782 static device_method_t intel_iicbb_methods[] = { 783 DEVMETHOD(device_probe, intel_iicbb_probe), 784 DEVMETHOD(device_attach, intel_gpio_setup), 785 DEVMETHOD(device_detach, intel_iicbb_detach), 786 787 DEVMETHOD(bus_add_child, bus_generic_add_child), 788 DEVMETHOD(bus_print_child, bus_generic_print_child), 789 790 DEVMETHOD(iicbb_callback, iicbus_null_callback), 791 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 792 DEVMETHOD(iicbb_setsda, set_data), 793 DEVMETHOD(iicbb_setscl, set_clock), 794 DEVMETHOD(iicbb_getsda, get_data), 795 DEVMETHOD(iicbb_getscl, get_clock), 796 DEVMETHOD_END 797 }; 798 static driver_t intel_iicbb_driver = { 799 "intel_iicbb", 800 intel_iicbb_methods, 801 sizeof(struct intel_iic_softc) 802 }; 803 static devclass_t intel_iicbb_devclass; 804 DRIVER_MODULE_ORDERED(intel_iicbb, drm, intel_iicbb_driver, 805 intel_iicbb_devclass, NULL, NULL, SI_ORDER_FIRST); 806 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL); 807 808 static void intel_teardown_gmbus_m(struct drm_device *dev, int m); 809 810 int 811 intel_setup_gmbus(struct drm_device *dev) 812 { 813 struct drm_i915_private *dev_priv = dev->dev_private; 814 device_t iic_dev; 815 int i, ret; 816 817 if (HAS_PCH_NOP(dev)) 818 return 0; 819 else if (HAS_PCH_SPLIT(dev)) 820 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; 821 else if (IS_VALLEYVIEW(dev)) 822 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 823 else 824 dev_priv->gpio_mmio_base = 0; 825 826 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE); 827 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 828 829 dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 830 M_DRM, M_WAITOK | M_ZERO); 831 dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 832 M_DRM, M_WAITOK | M_ZERO); 833 dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 834 M_DRM, M_WAITOK | M_ZERO); 835 dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 836 M_DRM, M_WAITOK | M_ZERO); 837 838 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 839 /* 840 * Initialized bbbus_bridge before gmbus_bridge, since 841 * gmbus may decide to force quirk transfer in the 842 * attachment code. 843 */ 844 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev, 845 "intel_iicbb", i); 846 if (dev_priv->bbbus_bridge[i] == NULL) { 847 DRM_ERROR("bbbus bridge %d creation failed\n", i); 848 ret = ENXIO; 849 goto err; 850 } 851 device_quiet(dev_priv->bbbus_bridge[i]); 852 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]); 853 if (ret != 0) { 854 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i, 855 ret); 856 goto err; 857 } 858 859 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb", 860 -1); 861 if (iic_dev == NULL) { 862 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 863 goto err; 864 } 865 iic_dev = device_find_child(iic_dev, "iicbus", -1); 866 if (iic_dev == NULL) { 867 DRM_ERROR( 868 "bbbus bridge doesn't have iicbus grandchild\n"); 869 goto err; 870 } 871 872 dev_priv->bbbus[i] = iic_dev; 873 874 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev, 875 "intel_gmbus", i); 876 if (dev_priv->gmbus_bridge[i] == NULL) { 877 DRM_ERROR("gmbus bridge %d creation failed\n", i); 878 ret = ENXIO; 879 goto err; 880 } 881 device_quiet(dev_priv->gmbus_bridge[i]); 882 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]); 883 if (ret != 0) { 884 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i, 885 ret); 886 ret = ENXIO; 887 goto err; 888 } 889 890 iic_dev = device_find_child(dev_priv->gmbus_bridge[i], 891 "iicbus", -1); 892 if (iic_dev == NULL) { 893 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 894 goto err; 895 } 896 dev_priv->gmbus[i] = iic_dev; 897 898 intel_i2c_reset(dev); 899 } 900 901 return (0); 902 903 err: 904 intel_teardown_gmbus_m(dev, i); 905 return (ret); 906 } 907 908 static void 909 intel_teardown_gmbus_m(struct drm_device *dev, int m) 910 { 911 struct drm_i915_private *dev_priv; 912 913 dev_priv = dev->dev_private; 914 915 drm_free(dev_priv->gmbus, M_DRM); 916 dev_priv->gmbus = NULL; 917 drm_free(dev_priv->bbbus, M_DRM); 918 dev_priv->bbbus = NULL; 919 drm_free(dev_priv->gmbus_bridge, M_DRM); 920 dev_priv->gmbus_bridge = NULL; 921 drm_free(dev_priv->bbbus_bridge, M_DRM); 922 dev_priv->bbbus_bridge = NULL; 923 lockuninit(&dev_priv->gmbus_mutex); 924 } 925 926 void 927 intel_teardown_gmbus(struct drm_device *dev) 928 { 929 930 get_mplock(); 931 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS); 932 rel_mplock(); 933 } 934