1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * Michel Thierry <michel.thierry@intel.com> 26 * Thomas Daniel <thomas.daniel@intel.com> 27 * Oscar Mateo <oscar.mateo@intel.com> 28 * 29 */ 30 31 /** 32 * DOC: Logical Rings, Logical Ring Contexts and Execlists 33 * 34 * Motivation: 35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". 36 * These expanded contexts enable a number of new abilities, especially 37 * "Execlists" (also implemented in this file). 38 * 39 * One of the main differences with the legacy HW contexts is that logical 40 * ring contexts incorporate many more things to the context's state, like 41 * PDPs or ringbuffer control registers: 42 * 43 * The reason why PDPs are included in the context is straightforward: as 44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs 45 * contained there mean you don't need to do a ppgtt->switch_mm yourself, 46 * instead, the GPU will do it for you on the context switch. 47 * 48 * But, what about the ringbuffer control registers (head, tail, etc..)? 49 * shouldn't we just need a set of those per engine command streamer? This is 50 * where the name "Logical Rings" starts to make sense: by virtualizing the 51 * rings, the engine cs shifts to a new "ring buffer" with every context 52 * switch. When you want to submit a workload to the GPU you: A) choose your 53 * context, B) find its appropriate virtualized ring, C) write commands to it 54 * and then, finally, D) tell the GPU to switch to that context. 55 * 56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch 57 * to a contexts is via a context execution list, ergo "Execlists". 58 * 59 * LRC implementation: 60 * Regarding the creation of contexts, we have: 61 * 62 * - One global default context. 63 * - One local default context for each opened fd. 64 * - One local extra context for each context create ioctl call. 65 * 66 * Now that ringbuffers belong per-context (and not per-engine, like before) 67 * and that contexts are uniquely tied to a given engine (and not reusable, 68 * like before) we need: 69 * 70 * - One ringbuffer per-engine inside each context. 71 * - One backing object per-engine inside each context. 72 * 73 * The global default context starts its life with these new objects fully 74 * allocated and populated. The local default context for each opened fd is 75 * more complex, because we don't know at creation time which engine is going 76 * to use them. To handle this, we have implemented a deferred creation of LR 77 * contexts: 78 * 79 * The local context starts its life as a hollow or blank holder, that only 80 * gets populated for a given engine once we receive an execbuffer. If later 81 * on we receive another execbuffer ioctl for the same context but a different 82 * engine, we allocate/populate a new ringbuffer and context backing object and 83 * so on. 84 * 85 * Finally, regarding local contexts created using the ioctl call: as they are 86 * only allowed with the render ring, we can allocate & populate them right 87 * away (no need to defer anything, at least for now). 88 * 89 * Execlists implementation: 90 * Execlists are the new method by which, on gen8+ hardware, workloads are 91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method). 92 * This method works as follows: 93 * 94 * When a request is committed, its commands (the BB start and any leading or 95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer 96 * for the appropriate context. The tail pointer in the hardware context is not 97 * updated at this time, but instead, kept by the driver in the ringbuffer 98 * structure. A structure representing this request is added to a request queue 99 * for the appropriate engine: this structure contains a copy of the context's 100 * tail after the request was written to the ring buffer and a pointer to the 101 * context itself. 102 * 103 * If the engine's request queue was empty before the request was added, the 104 * queue is processed immediately. Otherwise the queue will be processed during 105 * a context switch interrupt. In any case, elements on the queue will get sent 106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a 107 * globally unique 20-bits submission ID. 108 * 109 * When execution of a request completes, the GPU updates the context status 110 * buffer with a context complete event and generates a context switch interrupt. 111 * During the interrupt handling, the driver examines the events in the buffer: 112 * for each context complete event, if the announced ID matches that on the head 113 * of the request queue, then that request is retired and removed from the queue. 114 * 115 * After processing, if any requests were retired and the queue is not empty 116 * then a new execution list can be submitted. The two requests at the front of 117 * the queue are next to be submitted but since a context may not occur twice in 118 * an execution list, if subsequent requests have the same ID as the first then 119 * the two requests must be combined. This is done simply by discarding requests 120 * at the head of the queue until either only one requests is left (in which case 121 * we use a NULL second context) or the first two requests have unique IDs. 122 * 123 * By always executing the first two requests in the queue the driver ensures 124 * that the GPU is kept as busy as possible. In the case where a single context 125 * completes but a second context is still executing, the request for this second 126 * context will be at the head of the queue when we remove the first one. This 127 * request will then be resubmitted along with a new request for a different context, 128 * which will cause the hardware to continue executing the second request and queue 129 * the new request (the GPU detects the condition of a context getting preempted 130 * with the same context and optimizes the context switch flow by not doing 131 * preemption, but just sampling the new tail pointer). 132 * 133 */ 134 135 #include <drm/drmP.h> 136 #include <drm/i915_drm.h> 137 #include "i915_drv.h" 138 #include "intel_drv.h" 139 140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) 143 144 #define RING_EXECLIST_QFULL (1 << 0x2) 145 #define RING_EXECLIST1_VALID (1 << 0x3) 146 #define RING_EXECLIST0_VALID (1 << 0x4) 147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) 148 #define RING_EXECLIST1_ACTIVE (1 << 0x11) 149 #define RING_EXECLIST0_ACTIVE (1 << 0x12) 150 151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) 152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) 153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) 154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) 155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4) 156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) 157 158 #define CTX_LRI_HEADER_0 0x01 159 #define CTX_CONTEXT_CONTROL 0x02 160 #define CTX_RING_HEAD 0x04 161 #define CTX_RING_TAIL 0x06 162 #define CTX_RING_BUFFER_START 0x08 163 #define CTX_RING_BUFFER_CONTROL 0x0a 164 #define CTX_BB_HEAD_U 0x0c 165 #define CTX_BB_HEAD_L 0x0e 166 #define CTX_BB_STATE 0x10 167 #define CTX_SECOND_BB_HEAD_U 0x12 168 #define CTX_SECOND_BB_HEAD_L 0x14 169 #define CTX_SECOND_BB_STATE 0x16 170 #define CTX_BB_PER_CTX_PTR 0x18 171 #define CTX_RCS_INDIRECT_CTX 0x1a 172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c 173 #define CTX_LRI_HEADER_1 0x21 174 #define CTX_CTX_TIMESTAMP 0x22 175 #define CTX_PDP3_UDW 0x24 176 #define CTX_PDP3_LDW 0x26 177 #define CTX_PDP2_UDW 0x28 178 #define CTX_PDP2_LDW 0x2a 179 #define CTX_PDP1_UDW 0x2c 180 #define CTX_PDP1_LDW 0x2e 181 #define CTX_PDP0_UDW 0x30 182 #define CTX_PDP0_LDW 0x32 183 #define CTX_LRI_HEADER_2 0x41 184 #define CTX_R_PWR_CLK_STATE 0x42 185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 186 187 #define GEN8_CTX_VALID (1<<0) 188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) 189 #define GEN8_CTX_FORCE_RESTORE (1<<2) 190 #define GEN8_CTX_L3LLC_COHERENT (1<<5) 191 #define GEN8_CTX_PRIVILEGE (1<<8) 192 enum { 193 ADVANCED_CONTEXT = 0, 194 LEGACY_CONTEXT, 195 ADVANCED_AD_CONTEXT, 196 LEGACY_64B_CONTEXT 197 }; 198 #define GEN8_CTX_MODE_SHIFT 3 199 enum { 200 FAULT_AND_HANG = 0, 201 FAULT_AND_HALT, /* Debug only */ 202 FAULT_AND_STREAM, 203 FAULT_AND_CONTINUE /* Unsupported */ 204 }; 205 #define GEN8_CTX_ID_SHIFT 32 206 207 static int intel_lr_context_pin(struct intel_engine_cs *ring, 208 struct intel_context *ctx); 209 210 /** 211 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists 212 * @dev: DRM device. 213 * @enable_execlists: value of i915.enable_execlists module parameter. 214 * 215 * Only certain platforms support Execlists (the prerequisites being 216 * support for Logical Ring Contexts and Aliasing PPGTT or better). 217 * 218 * Return: 1 if Execlists is supported and has to be enabled. 219 */ 220 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) 221 { 222 WARN_ON(i915.enable_ppgtt == -1); 223 224 if (INTEL_INFO(dev)->gen >= 9) 225 return 1; 226 227 if (enable_execlists == 0) 228 return 0; 229 230 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && 231 i915.use_mmio_flip >= 0) 232 return 1; 233 234 return 0; 235 } 236 237 /** 238 * intel_execlists_ctx_id() - get the Execlists Context ID 239 * @ctx_obj: Logical Ring Context backing object. 240 * 241 * Do not confuse with ctx->id! Unfortunately we have a name overload 242 * here: the old context ID we pass to userspace as a handler so that 243 * they can refer to a context, and the new context ID we pass to the 244 * ELSP so that the GPU can inform us of the context status via 245 * interrupts. 246 * 247 * Return: 20-bits globally unique context ID. 248 */ 249 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) 250 { 251 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); 252 253 /* LRCA is required to be 4K aligned so the more significant 20 bits 254 * are globally unique */ 255 return lrca >> 12; 256 } 257 258 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring, 259 struct drm_i915_gem_object *ctx_obj) 260 { 261 struct drm_device *dev = ring->dev; 262 uint64_t desc; 263 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); 264 265 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); 266 267 desc = GEN8_CTX_VALID; 268 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; 269 desc |= GEN8_CTX_L3LLC_COHERENT; 270 desc |= GEN8_CTX_PRIVILEGE; 271 desc |= lrca; 272 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; 273 274 /* TODO: WaDisableLiteRestore when we start using semaphore 275 * signalling between Command Streamers */ 276 /* desc |= GEN8_CTX_FORCE_RESTORE; */ 277 278 /* WaEnableForceRestoreInCtxtDescForVCS:skl */ 279 if (IS_GEN9(dev) && 280 INTEL_REVID(dev) <= SKL_REVID_B0 && 281 (ring->id == BCS || ring->id == VCS || 282 ring->id == VECS || ring->id == VCS2)) 283 desc |= GEN8_CTX_FORCE_RESTORE; 284 285 return desc; 286 } 287 288 static void execlists_elsp_write(struct intel_engine_cs *ring, 289 struct drm_i915_gem_object *ctx_obj0, 290 struct drm_i915_gem_object *ctx_obj1) 291 { 292 struct drm_device *dev = ring->dev; 293 struct drm_i915_private *dev_priv = dev->dev_private; 294 uint64_t temp = 0; 295 uint32_t desc[4]; 296 297 /* XXX: You must always write both descriptors in the order below. */ 298 if (ctx_obj1) 299 temp = execlists_ctx_descriptor(ring, ctx_obj1); 300 else 301 temp = 0; 302 desc[1] = (u32)(temp >> 32); 303 desc[0] = (u32)temp; 304 305 temp = execlists_ctx_descriptor(ring, ctx_obj0); 306 desc[3] = (u32)(temp >> 32); 307 desc[2] = (u32)temp; 308 309 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 310 I915_WRITE(RING_ELSP(ring), desc[1]); 311 I915_WRITE(RING_ELSP(ring), desc[0]); 312 I915_WRITE(RING_ELSP(ring), desc[3]); 313 314 /* The context is automatically loaded after the following */ 315 I915_WRITE(RING_ELSP(ring), desc[2]); 316 317 /* ELSP is a wo register, so use another nearby reg for posting instead */ 318 POSTING_READ(RING_EXECLIST_STATUS(ring)); 319 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 320 } 321 322 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, 323 struct drm_i915_gem_object *ring_obj, 324 u32 tail) 325 { 326 struct vm_page *page; 327 uint32_t *reg_state; 328 329 page = i915_gem_object_get_page(ctx_obj, 1); 330 reg_state = kmap_atomic(page); 331 332 reg_state[CTX_RING_TAIL+1] = tail; 333 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); 334 335 kunmap_atomic(reg_state); 336 337 return 0; 338 } 339 340 static void execlists_submit_contexts(struct intel_engine_cs *ring, 341 struct intel_context *to0, u32 tail0, 342 struct intel_context *to1, u32 tail1) 343 { 344 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state; 345 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf; 346 struct drm_i915_gem_object *ctx_obj1 = NULL; 347 struct intel_ringbuffer *ringbuf1 = NULL; 348 349 BUG_ON(!ctx_obj0); 350 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); 351 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj)); 352 353 execlists_update_context(ctx_obj0, ringbuf0->obj, tail0); 354 355 if (to1) { 356 ringbuf1 = to1->engine[ring->id].ringbuf; 357 ctx_obj1 = to1->engine[ring->id].state; 358 BUG_ON(!ctx_obj1); 359 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); 360 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj)); 361 362 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1); 363 } 364 365 execlists_elsp_write(ring, ctx_obj0, ctx_obj1); 366 } 367 368 static void execlists_context_unqueue(struct intel_engine_cs *ring) 369 { 370 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; 371 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; 372 373 assert_spin_locked(&ring->execlist_lock); 374 375 if (list_empty(&ring->execlist_queue)) 376 return; 377 378 /* Try to read in pairs */ 379 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, 380 execlist_link) { 381 if (!req0) { 382 req0 = cursor; 383 } else if (req0->ctx == cursor->ctx) { 384 /* Same ctx: ignore first request, as second request 385 * will update tail past first request's workload */ 386 cursor->elsp_submitted = req0->elsp_submitted; 387 list_del(&req0->execlist_link); 388 list_add_tail(&req0->execlist_link, 389 &ring->execlist_retired_req_list); 390 req0 = cursor; 391 } else { 392 req1 = cursor; 393 break; 394 } 395 } 396 397 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { 398 /* 399 * WaIdleLiteRestore: make sure we never cause a lite 400 * restore with HEAD==TAIL 401 */ 402 if (req0 && req0->elsp_submitted) { 403 /* 404 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL 405 * as we resubmit the request. See gen8_emit_request() 406 * for where we prepare the padding after the end of the 407 * request. 408 */ 409 struct intel_ringbuffer *ringbuf; 410 411 ringbuf = req0->ctx->engine[ring->id].ringbuf; 412 req0->tail += 8; 413 req0->tail &= ringbuf->size - 1; 414 } 415 } 416 417 WARN_ON(req1 && req1->elsp_submitted); 418 419 execlists_submit_contexts(ring, req0->ctx, req0->tail, 420 req1 ? req1->ctx : NULL, 421 req1 ? req1->tail : 0); 422 423 req0->elsp_submitted++; 424 if (req1) 425 req1->elsp_submitted++; 426 } 427 428 static bool execlists_check_remove_request(struct intel_engine_cs *ring, 429 u32 request_id) 430 { 431 struct drm_i915_gem_request *head_req; 432 433 assert_spin_locked(&ring->execlist_lock); 434 435 head_req = list_first_entry_or_null(&ring->execlist_queue, 436 struct drm_i915_gem_request, 437 execlist_link); 438 439 if (head_req != NULL) { 440 struct drm_i915_gem_object *ctx_obj = 441 head_req->ctx->engine[ring->id].state; 442 if (intel_execlists_ctx_id(ctx_obj) == request_id) { 443 WARN(head_req->elsp_submitted == 0, 444 "Never submitted head request\n"); 445 446 if (--head_req->elsp_submitted <= 0) { 447 list_del(&head_req->execlist_link); 448 list_add_tail(&head_req->execlist_link, 449 &ring->execlist_retired_req_list); 450 return true; 451 } 452 } 453 } 454 455 return false; 456 } 457 458 /** 459 * intel_lrc_irq_handler() - handle Context Switch interrupts 460 * @ring: Engine Command Streamer to handle. 461 * 462 * Check the unread Context Status Buffers and manage the submission of new 463 * contexts to the ELSP accordingly. 464 */ 465 void intel_lrc_irq_handler(struct intel_engine_cs *ring) 466 { 467 struct drm_i915_private *dev_priv = ring->dev->dev_private; 468 u32 status_pointer; 469 u8 read_pointer; 470 u8 write_pointer; 471 u32 status; 472 u32 status_id; 473 u32 submit_contexts = 0; 474 475 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); 476 477 read_pointer = ring->next_context_status_buffer; 478 write_pointer = status_pointer & 0x07; 479 if (read_pointer > write_pointer) 480 write_pointer += 6; 481 482 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 483 484 while (read_pointer < write_pointer) { 485 read_pointer++; 486 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 487 (read_pointer % 6) * 8); 488 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 489 (read_pointer % 6) * 8 + 4); 490 491 if (status & GEN8_CTX_STATUS_PREEMPTED) { 492 if (status & GEN8_CTX_STATUS_LITE_RESTORE) { 493 if (execlists_check_remove_request(ring, status_id)) 494 WARN(1, "Lite Restored request removed from queue\n"); 495 } else 496 WARN(1, "Preemption without Lite Restore\n"); 497 } 498 499 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || 500 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { 501 if (execlists_check_remove_request(ring, status_id)) 502 submit_contexts++; 503 } 504 } 505 506 if (submit_contexts != 0) 507 execlists_context_unqueue(ring); 508 509 lockmgr(&ring->execlist_lock, LK_RELEASE); 510 511 WARN(submit_contexts > 2, "More than two context complete events?\n"); 512 ring->next_context_status_buffer = write_pointer % 6; 513 514 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), 515 ((u32)ring->next_context_status_buffer & 0x07) << 8); 516 } 517 518 static int execlists_context_queue(struct intel_engine_cs *ring, 519 struct intel_context *to, 520 u32 tail, 521 struct drm_i915_gem_request *request) 522 { 523 struct drm_i915_gem_request *cursor; 524 struct drm_i915_private *dev_priv = ring->dev->dev_private; 525 int num_elements = 0; 526 527 if (to != ring->default_context) 528 intel_lr_context_pin(ring, to); 529 530 if (!request) { 531 /* 532 * If there isn't a request associated with this submission, 533 * create one as a temporary holder. 534 */ 535 request = kzalloc(sizeof(*request), GFP_KERNEL); 536 if (request == NULL) 537 return -ENOMEM; 538 request->ring = ring; 539 request->ctx = to; 540 kref_init(&request->ref); 541 request->uniq = dev_priv->request_uniq++; 542 i915_gem_context_reference(request->ctx); 543 } else { 544 i915_gem_request_reference(request); 545 WARN_ON(to != request->ctx); 546 } 547 request->tail = tail; 548 549 intel_runtime_pm_get(dev_priv); 550 551 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 552 553 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) 554 if (++num_elements > 2) 555 break; 556 557 if (num_elements > 2) { 558 struct drm_i915_gem_request *tail_req; 559 560 tail_req = list_last_entry(&ring->execlist_queue, 561 struct drm_i915_gem_request, 562 execlist_link); 563 564 if (to == tail_req->ctx) { 565 WARN(tail_req->elsp_submitted != 0, 566 "More than 2 already-submitted reqs queued\n"); 567 list_del(&tail_req->execlist_link); 568 list_add_tail(&tail_req->execlist_link, 569 &ring->execlist_retired_req_list); 570 } 571 } 572 573 list_add_tail(&request->execlist_link, &ring->execlist_queue); 574 if (num_elements == 0) 575 execlists_context_unqueue(ring); 576 577 lockmgr(&ring->execlist_lock, LK_RELEASE); 578 579 return 0; 580 } 581 582 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf, 583 struct intel_context *ctx) 584 { 585 struct intel_engine_cs *ring = ringbuf->ring; 586 uint32_t flush_domains; 587 int ret; 588 589 flush_domains = 0; 590 if (ring->gpu_caches_dirty) 591 flush_domains = I915_GEM_GPU_DOMAINS; 592 593 ret = ring->emit_flush(ringbuf, ctx, 594 I915_GEM_GPU_DOMAINS, flush_domains); 595 if (ret) 596 return ret; 597 598 ring->gpu_caches_dirty = false; 599 return 0; 600 } 601 602 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, 603 struct intel_context *ctx, 604 struct list_head *vmas) 605 { 606 struct intel_engine_cs *ring = ringbuf->ring; 607 struct i915_vma *vma; 608 uint32_t flush_domains = 0; 609 bool flush_chipset = false; 610 int ret; 611 612 list_for_each_entry(vma, vmas, exec_list) { 613 struct drm_i915_gem_object *obj = vma->obj; 614 615 ret = i915_gem_object_sync(obj, ring); 616 if (ret) 617 return ret; 618 619 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) 620 flush_chipset |= i915_gem_clflush_object(obj, false); 621 622 flush_domains |= obj->base.write_domain; 623 } 624 625 if (flush_domains & I915_GEM_DOMAIN_GTT) 626 wmb(); 627 628 /* Unconditionally invalidate gpu caches and ensure that we do flush 629 * any residual writes from the previous batch. 630 */ 631 return logical_ring_invalidate_all_caches(ringbuf, ctx); 632 } 633 634 /** 635 * execlists_submission() - submit a batchbuffer for execution, Execlists style 636 * @dev: DRM device. 637 * @file: DRM file. 638 * @ring: Engine Command Streamer to submit to. 639 * @ctx: Context to employ for this submission. 640 * @args: execbuffer call arguments. 641 * @vmas: list of vmas. 642 * @batch_obj: the batchbuffer to submit. 643 * @exec_start: batchbuffer start virtual address pointer. 644 * @dispatch_flags: translated execbuffer call flags. 645 * 646 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts 647 * away the submission details of the execbuffer ioctl call. 648 * 649 * Return: non-zero if the submission fails. 650 */ 651 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, 652 struct intel_engine_cs *ring, 653 struct intel_context *ctx, 654 struct drm_i915_gem_execbuffer2 *args, 655 struct list_head *vmas, 656 struct drm_i915_gem_object *batch_obj, 657 u64 exec_start, u32 dispatch_flags) 658 { 659 struct drm_i915_private *dev_priv = dev->dev_private; 660 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 661 int instp_mode; 662 u32 instp_mask; 663 int ret; 664 665 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; 666 instp_mask = I915_EXEC_CONSTANTS_MASK; 667 switch (instp_mode) { 668 case I915_EXEC_CONSTANTS_REL_GENERAL: 669 case I915_EXEC_CONSTANTS_ABSOLUTE: 670 case I915_EXEC_CONSTANTS_REL_SURFACE: 671 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { 672 DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); 673 return -EINVAL; 674 } 675 676 if (instp_mode != dev_priv->relative_constants_mode) { 677 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { 678 DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); 679 return -EINVAL; 680 } 681 682 /* The HW changed the meaning on this bit on gen6 */ 683 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; 684 } 685 break; 686 default: 687 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); 688 return -EINVAL; 689 } 690 691 if (args->num_cliprects != 0) { 692 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); 693 return -EINVAL; 694 } else { 695 if (args->DR4 == 0xffffffff) { 696 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); 697 args->DR4 = 0; 698 } 699 700 if (args->DR1 || args->DR4 || args->cliprects_ptr) { 701 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); 702 return -EINVAL; 703 } 704 } 705 706 if (args->flags & I915_EXEC_GEN7_SOL_RESET) { 707 DRM_DEBUG("sol reset is gen7 only\n"); 708 return -EINVAL; 709 } 710 711 ret = execlists_move_to_gpu(ringbuf, ctx, vmas); 712 if (ret) 713 return ret; 714 715 if (ring == &dev_priv->ring[RCS] && 716 instp_mode != dev_priv->relative_constants_mode) { 717 ret = intel_logical_ring_begin(ringbuf, ctx, 4); 718 if (ret) 719 return ret; 720 721 intel_logical_ring_emit(ringbuf, MI_NOOP); 722 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); 723 intel_logical_ring_emit(ringbuf, INSTPM); 724 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); 725 intel_logical_ring_advance(ringbuf); 726 727 dev_priv->relative_constants_mode = instp_mode; 728 } 729 730 ret = ring->emit_bb_start(ringbuf, ctx, exec_start, dispatch_flags); 731 if (ret) 732 return ret; 733 734 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags); 735 736 i915_gem_execbuffer_move_to_active(vmas, ring); 737 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); 738 739 return 0; 740 } 741 742 void intel_execlists_retire_requests(struct intel_engine_cs *ring) 743 { 744 struct drm_i915_gem_request *req, *tmp; 745 struct drm_i915_private *dev_priv = ring->dev->dev_private; 746 struct list_head retired_list; 747 748 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 749 if (list_empty(&ring->execlist_retired_req_list)) 750 return; 751 752 INIT_LIST_HEAD(&retired_list); 753 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 754 list_replace_init(&ring->execlist_retired_req_list, &retired_list); 755 lockmgr(&ring->execlist_lock, LK_RELEASE); 756 757 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { 758 struct intel_context *ctx = req->ctx; 759 struct drm_i915_gem_object *ctx_obj = 760 ctx->engine[ring->id].state; 761 762 if (ctx_obj && (ctx != ring->default_context)) 763 intel_lr_context_unpin(ring, ctx); 764 intel_runtime_pm_put(dev_priv); 765 list_del(&req->execlist_link); 766 i915_gem_request_unreference(req); 767 } 768 } 769 770 void intel_logical_ring_stop(struct intel_engine_cs *ring) 771 { 772 struct drm_i915_private *dev_priv = ring->dev->dev_private; 773 int ret; 774 775 if (!intel_ring_initialized(ring)) 776 return; 777 778 ret = intel_ring_idle(ring); 779 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) 780 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", 781 ring->name, ret); 782 783 /* TODO: Is this correct with Execlists enabled? */ 784 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); 785 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { 786 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); 787 return; 788 } 789 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); 790 } 791 792 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf, 793 struct intel_context *ctx) 794 { 795 struct intel_engine_cs *ring = ringbuf->ring; 796 int ret; 797 798 if (!ring->gpu_caches_dirty) 799 return 0; 800 801 ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS); 802 if (ret) 803 return ret; 804 805 ring->gpu_caches_dirty = false; 806 return 0; 807 } 808 809 /* 810 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload 811 * @ringbuf: Logical Ringbuffer to advance. 812 * 813 * The tail is updated in our logical ringbuffer struct, not in the actual context. What 814 * really happens during submission is that the context and current tail will be placed 815 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that 816 * point, the tail *inside* the context is updated and the ELSP written to. 817 */ 818 static void 819 intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf, 820 struct intel_context *ctx, 821 struct drm_i915_gem_request *request) 822 { 823 struct intel_engine_cs *ring = ringbuf->ring; 824 825 intel_logical_ring_advance(ringbuf); 826 827 if (intel_ring_stopped(ring)) 828 return; 829 830 execlists_context_queue(ring, ctx, ringbuf->tail, request); 831 } 832 833 static int intel_lr_context_pin(struct intel_engine_cs *ring, 834 struct intel_context *ctx) 835 { 836 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; 837 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 838 int ret = 0; 839 840 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 841 if (ctx->engine[ring->id].pin_count++ == 0) { 842 ret = i915_gem_obj_ggtt_pin(ctx_obj, 843 GEN8_LR_CONTEXT_ALIGN, 0); 844 if (ret) 845 goto reset_pin_count; 846 847 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); 848 if (ret) 849 goto unpin_ctx_obj; 850 } 851 852 return ret; 853 854 unpin_ctx_obj: 855 i915_gem_object_ggtt_unpin(ctx_obj); 856 reset_pin_count: 857 ctx->engine[ring->id].pin_count = 0; 858 859 return ret; 860 } 861 862 void intel_lr_context_unpin(struct intel_engine_cs *ring, 863 struct intel_context *ctx) 864 { 865 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; 866 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 867 868 if (ctx_obj) { 869 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 870 if (--ctx->engine[ring->id].pin_count == 0) { 871 intel_unpin_ringbuffer_obj(ringbuf); 872 i915_gem_object_ggtt_unpin(ctx_obj); 873 } 874 } 875 } 876 877 static int logical_ring_alloc_request(struct intel_engine_cs *ring, 878 struct intel_context *ctx) 879 { 880 struct drm_i915_gem_request *request; 881 struct drm_i915_private *dev_private = ring->dev->dev_private; 882 int ret; 883 884 if (ring->outstanding_lazy_request) 885 return 0; 886 887 request = kzalloc(sizeof(*request), GFP_KERNEL); 888 if (request == NULL) 889 return -ENOMEM; 890 891 if (ctx != ring->default_context) { 892 ret = intel_lr_context_pin(ring, ctx); 893 if (ret) { 894 kfree(request); 895 return ret; 896 } 897 } 898 899 kref_init(&request->ref); 900 request->ring = ring; 901 request->uniq = dev_private->request_uniq++; 902 903 ret = i915_gem_get_seqno(ring->dev, &request->seqno); 904 if (ret) { 905 intel_lr_context_unpin(ring, ctx); 906 kfree(request); 907 return ret; 908 } 909 910 request->ctx = ctx; 911 i915_gem_context_reference(request->ctx); 912 request->ringbuf = ctx->engine[ring->id].ringbuf; 913 914 ring->outstanding_lazy_request = request; 915 return 0; 916 } 917 918 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, 919 int bytes) 920 { 921 struct intel_engine_cs *ring = ringbuf->ring; 922 struct drm_i915_gem_request *request; 923 int ret; 924 925 if (intel_ring_space(ringbuf) >= bytes) 926 return 0; 927 928 list_for_each_entry(request, &ring->request_list, list) { 929 /* 930 * The request queue is per-engine, so can contain requests 931 * from multiple ringbuffers. Here, we must ignore any that 932 * aren't from the ringbuffer we're considering. 933 */ 934 struct intel_context *ctx = request->ctx; 935 if (ctx->engine[ring->id].ringbuf != ringbuf) 936 continue; 937 938 /* Would completion of this request free enough space? */ 939 if (__intel_ring_space(request->tail, ringbuf->tail, 940 ringbuf->size) >= bytes) { 941 break; 942 } 943 } 944 945 if (&request->list == &ring->request_list) 946 return -ENOSPC; 947 948 ret = i915_wait_request(request); 949 if (ret) 950 return ret; 951 952 i915_gem_retire_requests_ring(ring); 953 954 return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC; 955 } 956 957 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, 958 struct intel_context *ctx, 959 int bytes) 960 { 961 struct intel_engine_cs *ring = ringbuf->ring; 962 struct drm_device *dev = ring->dev; 963 struct drm_i915_private *dev_priv = dev->dev_private; 964 unsigned long end; 965 int ret; 966 967 ret = logical_ring_wait_request(ringbuf, bytes); 968 if (ret != -ENOSPC) 969 return ret; 970 971 /* Force the context submission in case we have been skipping it */ 972 intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL); 973 974 /* With GEM the hangcheck timer should kick us out of the loop, 975 * leaving it early runs the risk of corrupting GEM state (due 976 * to running on almost untested codepaths). But on resume 977 * timers don't work yet, so prevent a complete hang in that 978 * case by choosing an insanely large timeout. */ 979 end = jiffies + 60 * HZ; 980 981 ret = 0; 982 do { 983 if (intel_ring_space(ringbuf) >= bytes) 984 break; 985 986 msleep(1); 987 988 if (dev_priv->mm.interruptible && signal_pending(curthread->td_lwp)) { 989 ret = -ERESTARTSYS; 990 break; 991 } 992 993 ret = i915_gem_check_wedge(&dev_priv->gpu_error, 994 dev_priv->mm.interruptible); 995 if (ret) 996 break; 997 998 if (time_after(jiffies, end)) { 999 ret = -EBUSY; 1000 break; 1001 } 1002 } while (1); 1003 1004 return ret; 1005 } 1006 1007 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf, 1008 struct intel_context *ctx) 1009 { 1010 uint32_t __iomem *virt; 1011 int rem = ringbuf->size - ringbuf->tail; 1012 1013 if (ringbuf->space < rem) { 1014 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem); 1015 1016 if (ret) 1017 return ret; 1018 } 1019 1020 virt = (unsigned int *)((char *)ringbuf->virtual_start + ringbuf->tail); 1021 rem /= 4; 1022 while (rem--) 1023 iowrite32(MI_NOOP, virt++); 1024 1025 ringbuf->tail = 0; 1026 intel_ring_update_space(ringbuf); 1027 1028 return 0; 1029 } 1030 1031 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, 1032 struct intel_context *ctx, int bytes) 1033 { 1034 int ret; 1035 1036 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { 1037 ret = logical_ring_wrap_buffer(ringbuf, ctx); 1038 if (unlikely(ret)) 1039 return ret; 1040 } 1041 1042 if (unlikely(ringbuf->space < bytes)) { 1043 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes); 1044 if (unlikely(ret)) 1045 return ret; 1046 } 1047 1048 return 0; 1049 } 1050 1051 /** 1052 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands 1053 * 1054 * @ringbuf: Logical ringbuffer. 1055 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. 1056 * 1057 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to 1058 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that 1059 * and also preallocates a request (every workload submission is still mediated through 1060 * requests, same as it did with legacy ringbuffer submission). 1061 * 1062 * Return: non-zero if the ringbuffer is not ready to be written to. 1063 */ 1064 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, 1065 struct intel_context *ctx, int num_dwords) 1066 { 1067 struct intel_engine_cs *ring = ringbuf->ring; 1068 struct drm_device *dev = ring->dev; 1069 struct drm_i915_private *dev_priv = dev->dev_private; 1070 int ret; 1071 1072 ret = i915_gem_check_wedge(&dev_priv->gpu_error, 1073 dev_priv->mm.interruptible); 1074 if (ret) 1075 return ret; 1076 1077 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t)); 1078 if (ret) 1079 return ret; 1080 1081 /* Preallocate the olr before touching the ring */ 1082 ret = logical_ring_alloc_request(ring, ctx); 1083 if (ret) 1084 return ret; 1085 1086 ringbuf->space -= num_dwords * sizeof(uint32_t); 1087 return 0; 1088 } 1089 1090 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring, 1091 struct intel_context *ctx) 1092 { 1093 int ret, i; 1094 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 1095 struct drm_device *dev = ring->dev; 1096 struct drm_i915_private *dev_priv = dev->dev_private; 1097 struct i915_workarounds *w = &dev_priv->workarounds; 1098 1099 if (WARN_ON_ONCE(w->count == 0)) 1100 return 0; 1101 1102 ring->gpu_caches_dirty = true; 1103 ret = logical_ring_flush_all_caches(ringbuf, ctx); 1104 if (ret) 1105 return ret; 1106 1107 ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2); 1108 if (ret) 1109 return ret; 1110 1111 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); 1112 for (i = 0; i < w->count; i++) { 1113 intel_logical_ring_emit(ringbuf, w->reg[i].addr); 1114 intel_logical_ring_emit(ringbuf, w->reg[i].value); 1115 } 1116 intel_logical_ring_emit(ringbuf, MI_NOOP); 1117 1118 intel_logical_ring_advance(ringbuf); 1119 1120 ring->gpu_caches_dirty = true; 1121 ret = logical_ring_flush_all_caches(ringbuf, ctx); 1122 if (ret) 1123 return ret; 1124 1125 return 0; 1126 } 1127 1128 static int gen8_init_common_ring(struct intel_engine_cs *ring) 1129 { 1130 struct drm_device *dev = ring->dev; 1131 struct drm_i915_private *dev_priv = dev->dev_private; 1132 1133 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); 1134 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); 1135 1136 if (ring->status_page.obj) { 1137 I915_WRITE(RING_HWS_PGA(ring->mmio_base), 1138 (u32)ring->status_page.gfx_addr); 1139 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); 1140 } 1141 1142 I915_WRITE(RING_MODE_GEN7(ring), 1143 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | 1144 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); 1145 POSTING_READ(RING_MODE_GEN7(ring)); 1146 ring->next_context_status_buffer = 0; 1147 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); 1148 1149 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); 1150 1151 return 0; 1152 } 1153 1154 static int gen8_init_render_ring(struct intel_engine_cs *ring) 1155 { 1156 struct drm_device *dev = ring->dev; 1157 struct drm_i915_private *dev_priv = dev->dev_private; 1158 int ret; 1159 1160 ret = gen8_init_common_ring(ring); 1161 if (ret) 1162 return ret; 1163 1164 /* We need to disable the AsyncFlip performance optimisations in order 1165 * to use MI_WAIT_FOR_EVENT within the CS. It should already be 1166 * programmed to '1' on all products. 1167 * 1168 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv 1169 */ 1170 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); 1171 1172 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); 1173 1174 return init_workarounds_ring(ring); 1175 } 1176 1177 static int gen9_init_render_ring(struct intel_engine_cs *ring) 1178 { 1179 int ret; 1180 1181 ret = gen8_init_common_ring(ring); 1182 if (ret) 1183 return ret; 1184 1185 return init_workarounds_ring(ring); 1186 } 1187 1188 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, 1189 struct intel_context *ctx, 1190 u64 offset, unsigned dispatch_flags) 1191 { 1192 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); 1193 int ret; 1194 1195 ret = intel_logical_ring_begin(ringbuf, ctx, 4); 1196 if (ret) 1197 return ret; 1198 1199 /* FIXME(BDW): Address space and security selectors. */ 1200 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); 1201 intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); 1202 intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); 1203 intel_logical_ring_emit(ringbuf, MI_NOOP); 1204 intel_logical_ring_advance(ringbuf); 1205 1206 return 0; 1207 } 1208 1209 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) 1210 { 1211 struct drm_device *dev = ring->dev; 1212 struct drm_i915_private *dev_priv = dev->dev_private; 1213 1214 if (WARN_ON(!intel_irqs_enabled(dev_priv))) 1215 return false; 1216 1217 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1218 if (ring->irq_refcount++ == 0) { 1219 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); 1220 POSTING_READ(RING_IMR(ring->mmio_base)); 1221 } 1222 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1223 1224 return true; 1225 } 1226 1227 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) 1228 { 1229 struct drm_device *dev = ring->dev; 1230 struct drm_i915_private *dev_priv = dev->dev_private; 1231 1232 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1233 if (--ring->irq_refcount == 0) { 1234 I915_WRITE_IMR(ring, ~ring->irq_keep_mask); 1235 POSTING_READ(RING_IMR(ring->mmio_base)); 1236 } 1237 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1238 } 1239 1240 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, 1241 struct intel_context *ctx, 1242 u32 invalidate_domains, 1243 u32 unused) 1244 { 1245 struct intel_engine_cs *ring = ringbuf->ring; 1246 struct drm_device *dev = ring->dev; 1247 struct drm_i915_private *dev_priv = dev->dev_private; 1248 uint32_t cmd; 1249 int ret; 1250 1251 ret = intel_logical_ring_begin(ringbuf, ctx, 4); 1252 if (ret) 1253 return ret; 1254 1255 cmd = MI_FLUSH_DW + 1; 1256 1257 /* We always require a command barrier so that subsequent 1258 * commands, such as breadcrumb interrupts, are strictly ordered 1259 * wrt the contents of the write cache being flushed to memory 1260 * (and thus being coherent from the CPU). 1261 */ 1262 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 1263 1264 if (invalidate_domains & I915_GEM_GPU_DOMAINS) { 1265 cmd |= MI_INVALIDATE_TLB; 1266 if (ring == &dev_priv->ring[VCS]) 1267 cmd |= MI_INVALIDATE_BSD; 1268 } 1269 1270 intel_logical_ring_emit(ringbuf, cmd); 1271 intel_logical_ring_emit(ringbuf, 1272 I915_GEM_HWS_SCRATCH_ADDR | 1273 MI_FLUSH_DW_USE_GTT); 1274 intel_logical_ring_emit(ringbuf, 0); /* upper addr */ 1275 intel_logical_ring_emit(ringbuf, 0); /* value */ 1276 intel_logical_ring_advance(ringbuf); 1277 1278 return 0; 1279 } 1280 1281 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, 1282 struct intel_context *ctx, 1283 u32 invalidate_domains, 1284 u32 flush_domains) 1285 { 1286 struct intel_engine_cs *ring = ringbuf->ring; 1287 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; 1288 u32 flags = 0; 1289 int ret; 1290 1291 flags |= PIPE_CONTROL_CS_STALL; 1292 1293 if (flush_domains) { 1294 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 1295 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 1296 } 1297 1298 if (invalidate_domains) { 1299 flags |= PIPE_CONTROL_TLB_INVALIDATE; 1300 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 1301 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 1302 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 1303 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 1304 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 1305 flags |= PIPE_CONTROL_QW_WRITE; 1306 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 1307 } 1308 1309 ret = intel_logical_ring_begin(ringbuf, ctx, 6); 1310 if (ret) 1311 return ret; 1312 1313 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); 1314 intel_logical_ring_emit(ringbuf, flags); 1315 intel_logical_ring_emit(ringbuf, scratch_addr); 1316 intel_logical_ring_emit(ringbuf, 0); 1317 intel_logical_ring_emit(ringbuf, 0); 1318 intel_logical_ring_emit(ringbuf, 0); 1319 intel_logical_ring_advance(ringbuf); 1320 1321 return 0; 1322 } 1323 1324 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) 1325 { 1326 return intel_read_status_page(ring, I915_GEM_HWS_INDEX); 1327 } 1328 1329 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) 1330 { 1331 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); 1332 } 1333 1334 static int gen8_emit_request(struct intel_ringbuffer *ringbuf, 1335 struct drm_i915_gem_request *request) 1336 { 1337 struct intel_engine_cs *ring = ringbuf->ring; 1338 u32 cmd; 1339 int ret; 1340 1341 /* 1342 * Reserve space for 2 NOOPs at the end of each request to be 1343 * used as a workaround for not being allowed to do lite 1344 * restore with HEAD==TAIL (WaIdleLiteRestore). 1345 */ 1346 ret = intel_logical_ring_begin(ringbuf, request->ctx, 8); 1347 if (ret) 1348 return ret; 1349 1350 cmd = MI_STORE_DWORD_IMM_GEN4; 1351 cmd |= MI_GLOBAL_GTT; 1352 1353 intel_logical_ring_emit(ringbuf, cmd); 1354 intel_logical_ring_emit(ringbuf, 1355 (ring->status_page.gfx_addr + 1356 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); 1357 intel_logical_ring_emit(ringbuf, 0); 1358 intel_logical_ring_emit(ringbuf, 1359 i915_gem_request_get_seqno(ring->outstanding_lazy_request)); 1360 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); 1361 intel_logical_ring_emit(ringbuf, MI_NOOP); 1362 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request); 1363 1364 /* 1365 * Here we add two extra NOOPs as padding to avoid 1366 * lite restore of a context with HEAD==TAIL. 1367 */ 1368 intel_logical_ring_emit(ringbuf, MI_NOOP); 1369 intel_logical_ring_emit(ringbuf, MI_NOOP); 1370 intel_logical_ring_advance(ringbuf); 1371 1372 return 0; 1373 } 1374 1375 static int intel_lr_context_render_state_init(struct intel_engine_cs *ring, 1376 struct intel_context *ctx) 1377 { 1378 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 1379 struct render_state so; 1380 struct drm_i915_file_private *file_priv = ctx->file_priv; 1381 struct drm_file *file = file_priv ? file_priv->file : NULL; 1382 int ret; 1383 1384 ret = i915_gem_render_state_prepare(ring, &so); 1385 if (ret) 1386 return ret; 1387 1388 if (so.rodata == NULL) 1389 return 0; 1390 1391 ret = ring->emit_bb_start(ringbuf, 1392 ctx, 1393 so.ggtt_offset, 1394 I915_DISPATCH_SECURE); 1395 if (ret) 1396 goto out; 1397 1398 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); 1399 1400 ret = __i915_add_request(ring, file, so.obj); 1401 /* intel_logical_ring_add_request moves object to inactive if it 1402 * fails */ 1403 out: 1404 i915_gem_render_state_fini(&so); 1405 return ret; 1406 } 1407 1408 static int gen8_init_rcs_context(struct intel_engine_cs *ring, 1409 struct intel_context *ctx) 1410 { 1411 int ret; 1412 1413 ret = intel_logical_ring_workarounds_emit(ring, ctx); 1414 if (ret) 1415 return ret; 1416 1417 return intel_lr_context_render_state_init(ring, ctx); 1418 } 1419 1420 /** 1421 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer 1422 * 1423 * @ring: Engine Command Streamer. 1424 * 1425 */ 1426 void intel_logical_ring_cleanup(struct intel_engine_cs *ring) 1427 { 1428 struct drm_i915_private *dev_priv; 1429 1430 if (!intel_ring_initialized(ring)) 1431 return; 1432 1433 dev_priv = ring->dev->dev_private; 1434 1435 intel_logical_ring_stop(ring); 1436 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); 1437 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); 1438 1439 if (ring->cleanup) 1440 ring->cleanup(ring); 1441 1442 i915_cmd_parser_fini_ring(ring); 1443 1444 if (ring->status_page.obj) { 1445 kunmap(ring->status_page.obj->pages[0]); 1446 ring->status_page.obj = NULL; 1447 } 1448 } 1449 1450 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) 1451 { 1452 int ret; 1453 1454 /* Intentionally left blank. */ 1455 ring->buffer = NULL; 1456 1457 ring->dev = dev; 1458 INIT_LIST_HEAD(&ring->active_list); 1459 INIT_LIST_HEAD(&ring->request_list); 1460 init_waitqueue_head(&ring->irq_queue); 1461 1462 INIT_LIST_HEAD(&ring->execlist_queue); 1463 INIT_LIST_HEAD(&ring->execlist_retired_req_list); 1464 lockinit(&ring->execlist_lock, "i915el", 0, LK_CANRECURSE); 1465 1466 ret = i915_cmd_parser_init_ring(ring); 1467 if (ret) 1468 return ret; 1469 1470 ret = intel_lr_context_deferred_create(ring->default_context, ring); 1471 1472 return ret; 1473 } 1474 1475 static int logical_render_ring_init(struct drm_device *dev) 1476 { 1477 struct drm_i915_private *dev_priv = dev->dev_private; 1478 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; 1479 int ret; 1480 1481 ring->name = "render ring"; 1482 ring->id = RCS; 1483 ring->mmio_base = RENDER_RING_BASE; 1484 ring->irq_enable_mask = 1485 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; 1486 ring->irq_keep_mask = 1487 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; 1488 if (HAS_L3_DPF(dev)) 1489 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; 1490 1491 if (INTEL_INFO(dev)->gen >= 9) 1492 ring->init_hw = gen9_init_render_ring; 1493 else 1494 ring->init_hw = gen8_init_render_ring; 1495 ring->init_context = gen8_init_rcs_context; 1496 ring->cleanup = intel_fini_pipe_control; 1497 ring->get_seqno = gen8_get_seqno; 1498 ring->set_seqno = gen8_set_seqno; 1499 ring->emit_request = gen8_emit_request; 1500 ring->emit_flush = gen8_emit_flush_render; 1501 ring->irq_get = gen8_logical_ring_get_irq; 1502 ring->irq_put = gen8_logical_ring_put_irq; 1503 ring->emit_bb_start = gen8_emit_bb_start; 1504 1505 ring->dev = dev; 1506 ret = logical_ring_init(dev, ring); 1507 if (ret) 1508 return ret; 1509 1510 return intel_init_pipe_control(ring); 1511 } 1512 1513 static int logical_bsd_ring_init(struct drm_device *dev) 1514 { 1515 struct drm_i915_private *dev_priv = dev->dev_private; 1516 struct intel_engine_cs *ring = &dev_priv->ring[VCS]; 1517 1518 ring->name = "bsd ring"; 1519 ring->id = VCS; 1520 ring->mmio_base = GEN6_BSD_RING_BASE; 1521 ring->irq_enable_mask = 1522 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; 1523 ring->irq_keep_mask = 1524 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; 1525 1526 ring->init_hw = gen8_init_common_ring; 1527 ring->get_seqno = gen8_get_seqno; 1528 ring->set_seqno = gen8_set_seqno; 1529 ring->emit_request = gen8_emit_request; 1530 ring->emit_flush = gen8_emit_flush; 1531 ring->irq_get = gen8_logical_ring_get_irq; 1532 ring->irq_put = gen8_logical_ring_put_irq; 1533 ring->emit_bb_start = gen8_emit_bb_start; 1534 1535 return logical_ring_init(dev, ring); 1536 } 1537 1538 static int logical_bsd2_ring_init(struct drm_device *dev) 1539 { 1540 struct drm_i915_private *dev_priv = dev->dev_private; 1541 struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; 1542 1543 ring->name = "bds2 ring"; 1544 ring->id = VCS2; 1545 ring->mmio_base = GEN8_BSD2_RING_BASE; 1546 ring->irq_enable_mask = 1547 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; 1548 ring->irq_keep_mask = 1549 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; 1550 1551 ring->init_hw = gen8_init_common_ring; 1552 ring->get_seqno = gen8_get_seqno; 1553 ring->set_seqno = gen8_set_seqno; 1554 ring->emit_request = gen8_emit_request; 1555 ring->emit_flush = gen8_emit_flush; 1556 ring->irq_get = gen8_logical_ring_get_irq; 1557 ring->irq_put = gen8_logical_ring_put_irq; 1558 ring->emit_bb_start = gen8_emit_bb_start; 1559 1560 return logical_ring_init(dev, ring); 1561 } 1562 1563 static int logical_blt_ring_init(struct drm_device *dev) 1564 { 1565 struct drm_i915_private *dev_priv = dev->dev_private; 1566 struct intel_engine_cs *ring = &dev_priv->ring[BCS]; 1567 1568 ring->name = "blitter ring"; 1569 ring->id = BCS; 1570 ring->mmio_base = BLT_RING_BASE; 1571 ring->irq_enable_mask = 1572 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 1573 ring->irq_keep_mask = 1574 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 1575 1576 ring->init_hw = gen8_init_common_ring; 1577 ring->get_seqno = gen8_get_seqno; 1578 ring->set_seqno = gen8_set_seqno; 1579 ring->emit_request = gen8_emit_request; 1580 ring->emit_flush = gen8_emit_flush; 1581 ring->irq_get = gen8_logical_ring_get_irq; 1582 ring->irq_put = gen8_logical_ring_put_irq; 1583 ring->emit_bb_start = gen8_emit_bb_start; 1584 1585 return logical_ring_init(dev, ring); 1586 } 1587 1588 static int logical_vebox_ring_init(struct drm_device *dev) 1589 { 1590 struct drm_i915_private *dev_priv = dev->dev_private; 1591 struct intel_engine_cs *ring = &dev_priv->ring[VECS]; 1592 1593 ring->name = "video enhancement ring"; 1594 ring->id = VECS; 1595 ring->mmio_base = VEBOX_RING_BASE; 1596 ring->irq_enable_mask = 1597 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; 1598 ring->irq_keep_mask = 1599 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; 1600 1601 ring->init_hw = gen8_init_common_ring; 1602 ring->get_seqno = gen8_get_seqno; 1603 ring->set_seqno = gen8_set_seqno; 1604 ring->emit_request = gen8_emit_request; 1605 ring->emit_flush = gen8_emit_flush; 1606 ring->irq_get = gen8_logical_ring_get_irq; 1607 ring->irq_put = gen8_logical_ring_put_irq; 1608 ring->emit_bb_start = gen8_emit_bb_start; 1609 1610 return logical_ring_init(dev, ring); 1611 } 1612 1613 /** 1614 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers 1615 * @dev: DRM device. 1616 * 1617 * This function inits the engines for an Execlists submission style (the equivalent in the 1618 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for 1619 * those engines that are present in the hardware. 1620 * 1621 * Return: non-zero if the initialization failed. 1622 */ 1623 int intel_logical_rings_init(struct drm_device *dev) 1624 { 1625 struct drm_i915_private *dev_priv = dev->dev_private; 1626 int ret; 1627 1628 ret = logical_render_ring_init(dev); 1629 if (ret) 1630 return ret; 1631 1632 if (HAS_BSD(dev)) { 1633 ret = logical_bsd_ring_init(dev); 1634 if (ret) 1635 goto cleanup_render_ring; 1636 } 1637 1638 if (HAS_BLT(dev)) { 1639 ret = logical_blt_ring_init(dev); 1640 if (ret) 1641 goto cleanup_bsd_ring; 1642 } 1643 1644 if (HAS_VEBOX(dev)) { 1645 ret = logical_vebox_ring_init(dev); 1646 if (ret) 1647 goto cleanup_blt_ring; 1648 } 1649 1650 if (HAS_BSD2(dev)) { 1651 ret = logical_bsd2_ring_init(dev); 1652 if (ret) 1653 goto cleanup_vebox_ring; 1654 } 1655 1656 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); 1657 if (ret) 1658 goto cleanup_bsd2_ring; 1659 1660 return 0; 1661 1662 cleanup_bsd2_ring: 1663 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); 1664 cleanup_vebox_ring: 1665 intel_logical_ring_cleanup(&dev_priv->ring[VECS]); 1666 cleanup_blt_ring: 1667 intel_logical_ring_cleanup(&dev_priv->ring[BCS]); 1668 cleanup_bsd_ring: 1669 intel_logical_ring_cleanup(&dev_priv->ring[VCS]); 1670 cleanup_render_ring: 1671 intel_logical_ring_cleanup(&dev_priv->ring[RCS]); 1672 1673 return ret; 1674 } 1675 1676 static u32 1677 make_rpcs(struct drm_device *dev) 1678 { 1679 u32 rpcs = 0; 1680 1681 /* 1682 * No explicit RPCS request is needed to ensure full 1683 * slice/subslice/EU enablement prior to Gen9. 1684 */ 1685 if (INTEL_INFO(dev)->gen < 9) 1686 return 0; 1687 1688 /* 1689 * Starting in Gen9, render power gating can leave 1690 * slice/subslice/EU in a partially enabled state. We 1691 * must make an explicit request through RPCS for full 1692 * enablement. 1693 */ 1694 if (INTEL_INFO(dev)->has_slice_pg) { 1695 rpcs |= GEN8_RPCS_S_CNT_ENABLE; 1696 rpcs |= INTEL_INFO(dev)->slice_total << 1697 GEN8_RPCS_S_CNT_SHIFT; 1698 rpcs |= GEN8_RPCS_ENABLE; 1699 } 1700 1701 if (INTEL_INFO(dev)->has_subslice_pg) { 1702 rpcs |= GEN8_RPCS_SS_CNT_ENABLE; 1703 rpcs |= INTEL_INFO(dev)->subslice_per_slice << 1704 GEN8_RPCS_SS_CNT_SHIFT; 1705 rpcs |= GEN8_RPCS_ENABLE; 1706 } 1707 1708 if (INTEL_INFO(dev)->has_eu_pg) { 1709 rpcs |= INTEL_INFO(dev)->eu_per_subslice << 1710 GEN8_RPCS_EU_MIN_SHIFT; 1711 rpcs |= INTEL_INFO(dev)->eu_per_subslice << 1712 GEN8_RPCS_EU_MAX_SHIFT; 1713 rpcs |= GEN8_RPCS_ENABLE; 1714 } 1715 1716 return rpcs; 1717 } 1718 1719 static int 1720 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, 1721 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) 1722 { 1723 struct drm_device *dev = ring->dev; 1724 struct drm_i915_private *dev_priv = dev->dev_private; 1725 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 1726 struct vm_page *page; 1727 uint32_t *reg_state; 1728 int ret; 1729 1730 if (!ppgtt) 1731 ppgtt = dev_priv->mm.aliasing_ppgtt; 1732 1733 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); 1734 if (ret) { 1735 DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); 1736 return ret; 1737 } 1738 1739 ret = i915_gem_object_get_pages(ctx_obj); 1740 if (ret) { 1741 DRM_DEBUG_DRIVER("Could not get object pages\n"); 1742 return ret; 1743 } 1744 1745 i915_gem_object_pin_pages(ctx_obj); 1746 1747 /* The second page of the context object contains some fields which must 1748 * be set up prior to the first execution. */ 1749 page = i915_gem_object_get_page(ctx_obj, 1); 1750 reg_state = kmap_atomic(page); 1751 1752 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM 1753 * commands followed by (reg, value) pairs. The values we are setting here are 1754 * only for the first context restore: on a subsequent save, the GPU will 1755 * recreate this batchbuffer with new values (including all the missing 1756 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ 1757 if (ring->id == RCS) 1758 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); 1759 else 1760 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); 1761 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; 1762 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); 1763 reg_state[CTX_CONTEXT_CONTROL+1] = 1764 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | 1765 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 1766 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); 1767 reg_state[CTX_RING_HEAD+1] = 0; 1768 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); 1769 reg_state[CTX_RING_TAIL+1] = 0; 1770 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); 1771 /* Ring buffer start address is not known until the buffer is pinned. 1772 * It is written to the context image in execlists_update_context() 1773 */ 1774 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); 1775 reg_state[CTX_RING_BUFFER_CONTROL+1] = 1776 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; 1777 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; 1778 reg_state[CTX_BB_HEAD_U+1] = 0; 1779 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; 1780 reg_state[CTX_BB_HEAD_L+1] = 0; 1781 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; 1782 reg_state[CTX_BB_STATE+1] = (1<<5); 1783 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; 1784 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; 1785 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; 1786 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; 1787 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; 1788 reg_state[CTX_SECOND_BB_STATE+1] = 0; 1789 if (ring->id == RCS) { 1790 /* TODO: according to BSpec, the register state context 1791 * for CHV does not have these. OTOH, these registers do 1792 * exist in CHV. I'm waiting for a clarification */ 1793 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; 1794 reg_state[CTX_BB_PER_CTX_PTR+1] = 0; 1795 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; 1796 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; 1797 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; 1798 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; 1799 } 1800 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); 1801 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; 1802 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; 1803 reg_state[CTX_CTX_TIMESTAMP+1] = 0; 1804 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); 1805 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); 1806 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); 1807 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); 1808 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); 1809 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); 1810 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); 1811 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); 1812 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[3]->daddr); 1813 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[3]->daddr); 1814 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[2]->daddr); 1815 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[2]->daddr); 1816 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[1]->daddr); 1817 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[1]->daddr); 1818 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[0]->daddr); 1819 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[0]->daddr); 1820 if (ring->id == RCS) { 1821 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); 1822 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; 1823 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); 1824 } 1825 1826 kunmap_atomic(reg_state); 1827 1828 ctx_obj->dirty = 1; 1829 set_page_dirty(page); 1830 i915_gem_object_unpin_pages(ctx_obj); 1831 1832 return 0; 1833 } 1834 1835 /** 1836 * intel_lr_context_free() - free the LRC specific bits of a context 1837 * @ctx: the LR context to free. 1838 * 1839 * The real context freeing is done in i915_gem_context_free: this only 1840 * takes care of the bits that are LRC related: the per-engine backing 1841 * objects and the logical ringbuffer. 1842 */ 1843 void intel_lr_context_free(struct intel_context *ctx) 1844 { 1845 int i; 1846 1847 for (i = 0; i < I915_NUM_RINGS; i++) { 1848 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; 1849 1850 if (ctx_obj) { 1851 struct intel_ringbuffer *ringbuf = 1852 ctx->engine[i].ringbuf; 1853 struct intel_engine_cs *ring = ringbuf->ring; 1854 1855 if (ctx == ring->default_context) { 1856 intel_unpin_ringbuffer_obj(ringbuf); 1857 i915_gem_object_ggtt_unpin(ctx_obj); 1858 } 1859 WARN_ON(ctx->engine[ring->id].pin_count); 1860 intel_destroy_ringbuffer_obj(ringbuf); 1861 kfree(ringbuf); 1862 drm_gem_object_unreference(&ctx_obj->base); 1863 } 1864 } 1865 } 1866 1867 static uint32_t get_lr_context_size(struct intel_engine_cs *ring) 1868 { 1869 int ret = 0; 1870 1871 WARN_ON(INTEL_INFO(ring->dev)->gen < 8); 1872 1873 switch (ring->id) { 1874 case RCS: 1875 if (INTEL_INFO(ring->dev)->gen >= 9) 1876 ret = GEN9_LR_CONTEXT_RENDER_SIZE; 1877 else 1878 ret = GEN8_LR_CONTEXT_RENDER_SIZE; 1879 break; 1880 case VCS: 1881 case BCS: 1882 case VECS: 1883 case VCS2: 1884 ret = GEN8_LR_CONTEXT_OTHER_SIZE; 1885 break; 1886 } 1887 1888 return ret; 1889 } 1890 1891 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, 1892 struct drm_i915_gem_object *default_ctx_obj) 1893 { 1894 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1895 1896 /* The status page is offset 0 from the default context object 1897 * in LRC mode. */ 1898 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); 1899 ring->status_page.page_addr = 1900 kmap(default_ctx_obj->pages[0]); 1901 ring->status_page.obj = default_ctx_obj; 1902 1903 I915_WRITE(RING_HWS_PGA(ring->mmio_base), 1904 (u32)ring->status_page.gfx_addr); 1905 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); 1906 } 1907 1908 /** 1909 * intel_lr_context_deferred_create() - create the LRC specific bits of a context 1910 * @ctx: LR context to create. 1911 * @ring: engine to be used with the context. 1912 * 1913 * This function can be called more than once, with different engines, if we plan 1914 * to use the context with them. The context backing objects and the ringbuffers 1915 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why 1916 * the creation is a deferred call: it's better to make sure first that we need to use 1917 * a given ring with the context. 1918 * 1919 * Return: non-zero on error. 1920 */ 1921 int intel_lr_context_deferred_create(struct intel_context *ctx, 1922 struct intel_engine_cs *ring) 1923 { 1924 const bool is_global_default_ctx = (ctx == ring->default_context); 1925 struct drm_device *dev = ring->dev; 1926 struct drm_i915_gem_object *ctx_obj; 1927 uint32_t context_size; 1928 struct intel_ringbuffer *ringbuf; 1929 int ret; 1930 1931 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); 1932 WARN_ON(ctx->engine[ring->id].state); 1933 1934 context_size = round_up(get_lr_context_size(ring), 4096); 1935 1936 ctx_obj = i915_gem_alloc_context_obj(dev, context_size); 1937 if (IS_ERR(ctx_obj)) { 1938 ret = PTR_ERR(ctx_obj); 1939 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); 1940 return ret; 1941 } 1942 1943 if (is_global_default_ctx) { 1944 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); 1945 if (ret) { 1946 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", 1947 ret); 1948 drm_gem_object_unreference(&ctx_obj->base); 1949 return ret; 1950 } 1951 } 1952 1953 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); 1954 if (!ringbuf) { 1955 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", 1956 ring->name); 1957 ret = -ENOMEM; 1958 goto error_unpin_ctx; 1959 } 1960 1961 ringbuf->ring = ring; 1962 1963 ringbuf->size = 32 * PAGE_SIZE; 1964 ringbuf->effective_size = ringbuf->size; 1965 ringbuf->head = 0; 1966 ringbuf->tail = 0; 1967 ringbuf->last_retired_head = -1; 1968 intel_ring_update_space(ringbuf); 1969 1970 if (ringbuf->obj == NULL) { 1971 ret = intel_alloc_ringbuffer_obj(dev, ringbuf); 1972 if (ret) { 1973 DRM_DEBUG_DRIVER( 1974 "Failed to allocate ringbuffer obj %s: %d\n", 1975 ring->name, ret); 1976 goto error_free_rbuf; 1977 } 1978 1979 if (is_global_default_ctx) { 1980 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); 1981 if (ret) { 1982 DRM_ERROR( 1983 "Failed to pin and map ringbuffer %s: %d\n", 1984 ring->name, ret); 1985 goto error_destroy_rbuf; 1986 } 1987 } 1988 1989 } 1990 1991 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); 1992 if (ret) { 1993 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); 1994 goto error; 1995 } 1996 1997 ctx->engine[ring->id].ringbuf = ringbuf; 1998 ctx->engine[ring->id].state = ctx_obj; 1999 2000 if (ctx == ring->default_context) 2001 lrc_setup_hardware_status_page(ring, ctx_obj); 2002 else if (ring->id == RCS && !ctx->rcs_initialized) { 2003 if (ring->init_context) { 2004 ret = ring->init_context(ring, ctx); 2005 if (ret) { 2006 DRM_ERROR("ring init context: %d\n", ret); 2007 ctx->engine[ring->id].ringbuf = NULL; 2008 ctx->engine[ring->id].state = NULL; 2009 goto error; 2010 } 2011 } 2012 2013 ctx->rcs_initialized = true; 2014 } 2015 2016 return 0; 2017 2018 error: 2019 if (is_global_default_ctx) 2020 intel_unpin_ringbuffer_obj(ringbuf); 2021 error_destroy_rbuf: 2022 intel_destroy_ringbuffer_obj(ringbuf); 2023 error_free_rbuf: 2024 kfree(ringbuf); 2025 error_unpin_ctx: 2026 if (is_global_default_ctx) 2027 i915_gem_object_ggtt_unpin(ctx_obj); 2028 drm_gem_object_unreference(&ctx_obj->base); 2029 return ret; 2030 } 2031 2032 void intel_lr_context_reset(struct drm_device *dev, 2033 struct intel_context *ctx) 2034 { 2035 struct drm_i915_private *dev_priv = dev->dev_private; 2036 struct intel_engine_cs *ring; 2037 int i; 2038 2039 for_each_ring(ring, dev_priv, i) { 2040 struct drm_i915_gem_object *ctx_obj = 2041 ctx->engine[ring->id].state; 2042 struct intel_ringbuffer *ringbuf = 2043 ctx->engine[ring->id].ringbuf; 2044 uint32_t *reg_state; 2045 struct vm_page *page; 2046 2047 if (!ctx_obj) 2048 continue; 2049 2050 if (i915_gem_object_get_pages(ctx_obj)) { 2051 WARN(1, "Failed get_pages for context obj\n"); 2052 continue; 2053 } 2054 page = i915_gem_object_get_page(ctx_obj, 1); 2055 reg_state = kmap_atomic(page); 2056 2057 reg_state[CTX_RING_HEAD+1] = 0; 2058 reg_state[CTX_RING_TAIL+1] = 0; 2059 2060 kunmap_atomic(reg_state); 2061 2062 ringbuf->head = 0; 2063 ringbuf->tail = 0; 2064 } 2065 } 2066