1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include "opt_drm.h" 31 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 #include "intel_drv.h" 41 #include <drm/i915_drm.h> 42 #include "i915_drv.h" 43 #include <linux/acpi.h> 44 45 /* Private structure for the integrated LVDS support */ 46 struct intel_lvds_connector { 47 struct intel_connector base; 48 49 struct notifier_block lid_notifier; 50 }; 51 52 struct intel_lvds_pps { 53 /* 100us units */ 54 int t1_t2; 55 int t3; 56 int t4; 57 int t5; 58 int tx; 59 60 int divider; 61 62 int port; 63 bool powerdown_on_reset; 64 }; 65 66 struct intel_lvds_encoder { 67 struct intel_encoder base; 68 69 bool is_dual_link; 70 i915_reg_t reg; 71 u32 a3_power; 72 73 struct intel_lvds_pps init_pps; 74 u32 init_lvds_val; 75 76 struct intel_lvds_connector *attached_connector; 77 }; 78 79 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 80 { 81 return container_of(encoder, struct intel_lvds_encoder, base.base); 82 } 83 84 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) 85 { 86 return container_of(connector, struct intel_lvds_connector, base.base); 87 } 88 89 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 90 enum i915_pipe *pipe) 91 { 92 struct drm_device *dev = encoder->base.dev; 93 struct drm_i915_private *dev_priv = to_i915(dev); 94 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 95 u32 tmp; 96 bool ret; 97 98 if (!intel_display_power_get_if_enabled(dev_priv, 99 encoder->power_domain)) 100 return false; 101 102 ret = false; 103 104 tmp = I915_READ(lvds_encoder->reg); 105 106 if (!(tmp & LVDS_PORT_EN)) 107 goto out; 108 109 if (HAS_PCH_CPT(dev_priv)) 110 *pipe = PORT_TO_PIPE_CPT(tmp); 111 else 112 *pipe = PORT_TO_PIPE(tmp); 113 114 ret = true; 115 116 out: 117 intel_display_power_put(dev_priv, encoder->power_domain); 118 119 return ret; 120 } 121 122 static void intel_lvds_get_config(struct intel_encoder *encoder, 123 struct intel_crtc_state *pipe_config) 124 { 125 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 126 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 127 u32 tmp, flags = 0; 128 129 tmp = I915_READ(lvds_encoder->reg); 130 if (tmp & LVDS_HSYNC_POLARITY) 131 flags |= DRM_MODE_FLAG_NHSYNC; 132 else 133 flags |= DRM_MODE_FLAG_PHSYNC; 134 if (tmp & LVDS_VSYNC_POLARITY) 135 flags |= DRM_MODE_FLAG_NVSYNC; 136 else 137 flags |= DRM_MODE_FLAG_PVSYNC; 138 139 pipe_config->base.adjusted_mode.flags |= flags; 140 141 if (INTEL_GEN(dev_priv) < 5) 142 pipe_config->gmch_pfit.lvds_border_bits = 143 tmp & LVDS_BORDER_ENABLE; 144 145 /* gen2/3 store dither state in pfit control, needs to match */ 146 if (INTEL_GEN(dev_priv) < 4) { 147 tmp = I915_READ(PFIT_CONTROL); 148 149 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 150 } 151 152 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 153 } 154 155 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 156 struct intel_lvds_pps *pps) 157 { 158 u32 val; 159 160 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; 161 162 val = I915_READ(PP_ON_DELAYS(0)); 163 pps->port = (val & PANEL_PORT_SELECT_MASK) >> 164 PANEL_PORT_SELECT_SHIFT; 165 pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >> 166 PANEL_POWER_UP_DELAY_SHIFT; 167 pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >> 168 PANEL_LIGHT_ON_DELAY_SHIFT; 169 170 val = I915_READ(PP_OFF_DELAYS(0)); 171 pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >> 172 PANEL_POWER_DOWN_DELAY_SHIFT; 173 pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >> 174 PANEL_LIGHT_OFF_DELAY_SHIFT; 175 176 val = I915_READ(PP_DIVISOR(0)); 177 pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >> 178 PP_REFERENCE_DIVIDER_SHIFT; 179 val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >> 180 PANEL_POWER_CYCLE_DELAY_SHIFT; 181 /* 182 * Remove the BSpec specified +1 (100ms) offset that accounts for a 183 * too short power-cycle delay due to the asynchronous programming of 184 * the register. 185 */ 186 if (val) 187 val--; 188 /* Convert from 100ms to 100us units */ 189 pps->t4 = val * 1000; 190 191 if (INTEL_INFO(dev_priv)->gen <= 4 && 192 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 193 DRM_DEBUG_KMS("Panel power timings uninitialized, " 194 "setting defaults\n"); 195 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 196 pps->t1_t2 = 40 * 10; 197 pps->t5 = 200 * 10; 198 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 199 pps->t3 = 35 * 10; 200 pps->tx = 200 * 10; 201 } 202 203 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 204 "divider %d port %d powerdown_on_reset %d\n", 205 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 206 pps->divider, pps->port, pps->powerdown_on_reset); 207 } 208 209 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 210 struct intel_lvds_pps *pps) 211 { 212 u32 val; 213 214 val = I915_READ(PP_CONTROL(0)); 215 WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 216 if (pps->powerdown_on_reset) 217 val |= PANEL_POWER_RESET; 218 I915_WRITE(PP_CONTROL(0), val); 219 220 I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) | 221 (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) | 222 (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT)); 223 I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) | 224 (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT)); 225 226 val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT; 227 val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) << 228 PANEL_POWER_CYCLE_DELAY_SHIFT; 229 I915_WRITE(PP_DIVISOR(0), val); 230 } 231 232 static void intel_pre_enable_lvds(struct intel_encoder *encoder, 233 struct intel_crtc_state *pipe_config, 234 struct drm_connector_state *conn_state) 235 { 236 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 237 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 238 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 239 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 240 int pipe = crtc->pipe; 241 u32 temp; 242 243 if (HAS_PCH_SPLIT(dev_priv)) { 244 assert_fdi_rx_pll_disabled(dev_priv, pipe); 245 assert_shared_dpll_disabled(dev_priv, 246 pipe_config->shared_dpll); 247 } else { 248 assert_pll_disabled(dev_priv, pipe); 249 } 250 251 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); 252 253 temp = lvds_encoder->init_lvds_val; 254 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 255 256 if (HAS_PCH_CPT(dev_priv)) { 257 temp &= ~PORT_TRANS_SEL_MASK; 258 temp |= PORT_TRANS_SEL_CPT(pipe); 259 } else { 260 if (pipe == 1) { 261 temp |= LVDS_PIPEB_SELECT; 262 } else { 263 temp &= ~LVDS_PIPEB_SELECT; 264 } 265 } 266 267 /* set the corresponsding LVDS_BORDER bit */ 268 temp &= ~LVDS_BORDER_ENABLE; 269 temp |= pipe_config->gmch_pfit.lvds_border_bits; 270 /* Set the B0-B3 data pairs corresponding to whether we're going to 271 * set the DPLLs for dual-channel mode or not. 272 */ 273 if (lvds_encoder->is_dual_link) 274 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 275 else 276 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 277 278 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 279 * appropriately here, but we need to look more thoroughly into how 280 * panels behave in the two modes. For now, let's just maintain the 281 * value we got from the BIOS. 282 */ 283 temp &= ~LVDS_A3_POWER_MASK; 284 temp |= lvds_encoder->a3_power; 285 286 /* Set the dithering flag on LVDS as needed, note that there is no 287 * special lvds dither control bit on pch-split platforms, dithering is 288 * only controlled through the PIPECONF reg. */ 289 if (IS_GEN4(dev_priv)) { 290 /* Bspec wording suggests that LVDS port dithering only exists 291 * for 18bpp panels. */ 292 if (pipe_config->dither && pipe_config->pipe_bpp == 18) 293 temp |= LVDS_ENABLE_DITHER; 294 else 295 temp &= ~LVDS_ENABLE_DITHER; 296 } 297 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 298 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 299 temp |= LVDS_HSYNC_POLARITY; 300 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 301 temp |= LVDS_VSYNC_POLARITY; 302 303 I915_WRITE(lvds_encoder->reg, temp); 304 } 305 306 /** 307 * Sets the power state for the panel. 308 */ 309 static void intel_enable_lvds(struct intel_encoder *encoder, 310 struct intel_crtc_state *pipe_config, 311 struct drm_connector_state *conn_state) 312 { 313 struct drm_device *dev = encoder->base.dev; 314 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 315 struct intel_connector *intel_connector = 316 &lvds_encoder->attached_connector->base; 317 struct drm_i915_private *dev_priv = to_i915(dev); 318 319 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); 320 321 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); 322 POSTING_READ(lvds_encoder->reg); 323 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000)) 324 DRM_ERROR("timed out waiting for panel to power on\n"); 325 326 intel_panel_enable_backlight(intel_connector); 327 } 328 329 static void intel_disable_lvds(struct intel_encoder *encoder, 330 struct intel_crtc_state *old_crtc_state, 331 struct drm_connector_state *old_conn_state) 332 { 333 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 334 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 335 336 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); 337 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000)) 338 DRM_ERROR("timed out waiting for panel to power off\n"); 339 340 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); 341 POSTING_READ(lvds_encoder->reg); 342 } 343 344 static void gmch_disable_lvds(struct intel_encoder *encoder, 345 struct intel_crtc_state *old_crtc_state, 346 struct drm_connector_state *old_conn_state) 347 348 { 349 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 350 struct intel_connector *intel_connector = 351 &lvds_encoder->attached_connector->base; 352 353 intel_panel_disable_backlight(intel_connector); 354 355 intel_disable_lvds(encoder, old_crtc_state, old_conn_state); 356 } 357 358 static void pch_disable_lvds(struct intel_encoder *encoder, 359 struct intel_crtc_state *old_crtc_state, 360 struct drm_connector_state *old_conn_state) 361 { 362 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 363 struct intel_connector *intel_connector = 364 &lvds_encoder->attached_connector->base; 365 366 intel_panel_disable_backlight(intel_connector); 367 } 368 369 static void pch_post_disable_lvds(struct intel_encoder *encoder, 370 struct intel_crtc_state *old_crtc_state, 371 struct drm_connector_state *old_conn_state) 372 { 373 intel_disable_lvds(encoder, old_crtc_state, old_conn_state); 374 } 375 376 static enum drm_mode_status 377 intel_lvds_mode_valid(struct drm_connector *connector, 378 struct drm_display_mode *mode) 379 { 380 struct intel_connector *intel_connector = to_intel_connector(connector); 381 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 382 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 383 384 if (mode->hdisplay > fixed_mode->hdisplay) 385 return MODE_PANEL; 386 if (mode->vdisplay > fixed_mode->vdisplay) 387 return MODE_PANEL; 388 if (fixed_mode->clock > max_pixclk) 389 return MODE_CLOCK_HIGH; 390 391 return MODE_OK; 392 } 393 394 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, 395 struct intel_crtc_state *pipe_config, 396 struct drm_connector_state *conn_state) 397 { 398 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 399 struct intel_lvds_encoder *lvds_encoder = 400 to_lvds_encoder(&intel_encoder->base); 401 struct intel_connector *intel_connector = 402 &lvds_encoder->attached_connector->base; 403 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 404 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 405 unsigned int lvds_bpp; 406 407 /* Should never happen!! */ 408 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { 409 DRM_ERROR("Can't support LVDS on pipe A\n"); 410 return false; 411 } 412 413 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 414 lvds_bpp = 8*3; 415 else 416 lvds_bpp = 6*3; 417 418 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 419 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", 420 pipe_config->pipe_bpp, lvds_bpp); 421 pipe_config->pipe_bpp = lvds_bpp; 422 } 423 424 /* 425 * We have timings from the BIOS for the panel, put them in 426 * to the adjusted mode. The CRTC will be set up for this mode, 427 * with the panel scaling set up to source from the H/VDisplay 428 * of the original mode. 429 */ 430 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 431 adjusted_mode); 432 433 if (HAS_PCH_SPLIT(dev_priv)) { 434 pipe_config->has_pch_encoder = true; 435 436 intel_pch_panel_fitting(intel_crtc, pipe_config, 437 intel_connector->panel.fitting_mode); 438 } else { 439 intel_gmch_panel_fitting(intel_crtc, pipe_config, 440 intel_connector->panel.fitting_mode); 441 442 } 443 444 /* 445 * XXX: It would be nice to support lower refresh rates on the 446 * panels to reduce power consumption, and perhaps match the 447 * user's requested refresh rate. 448 */ 449 450 return true; 451 } 452 453 /** 454 * Detect the LVDS connection. 455 * 456 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means 457 * connected and closed means disconnected. We also send hotplug events as 458 * needed, using lid status notification from the input layer. 459 */ 460 static enum drm_connector_status 461 intel_lvds_detect(struct drm_connector *connector, bool force) 462 { 463 struct drm_i915_private *dev_priv = to_i915(connector->dev); 464 enum drm_connector_status status; 465 466 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 467 connector->base.id, connector->name); 468 469 status = intel_panel_detect(dev_priv); 470 if (status != connector_status_unknown) 471 return status; 472 473 return connector_status_connected; 474 } 475 476 /** 477 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 478 */ 479 static int intel_lvds_get_modes(struct drm_connector *connector) 480 { 481 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); 482 struct drm_device *dev = connector->dev; 483 struct drm_display_mode *mode; 484 485 /* use cached edid if we have one */ 486 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 487 return drm_add_edid_modes(connector, lvds_connector->base.edid); 488 489 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); 490 if (mode == NULL) 491 return 0; 492 493 drm_mode_probed_add(connector, mode); 494 return 1; 495 } 496 497 #if 0 /* unused */ 498 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) 499 { 500 DRM_INFO("Skipping forced modeset for %s\n", id->ident); 501 return 1; 502 } 503 504 /* The GPU hangs up on these systems if modeset is performed on LID open */ 505 static const struct dmi_system_id intel_no_modeset_on_lid[] = { 506 { 507 .callback = intel_no_modeset_on_lid_dmi_callback, 508 .ident = "Toshiba Tecra A11", 509 .matches = { 510 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 511 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), 512 }, 513 }, 514 515 { } /* terminating entry */ 516 }; 517 518 /* 519 * Lid events. Note the use of 'modeset': 520 * - we set it to MODESET_ON_LID_OPEN on lid close, 521 * and set it to MODESET_DONE on open 522 * - we use it as a "only once" bit (ie we ignore 523 * duplicate events where it was already properly set) 524 * - the suspend/resume paths will set it to 525 * MODESET_SUSPENDED and ignore the lid open event, 526 * because they restore the mode ("lid open"). 527 */ 528 static int intel_lid_notify(struct notifier_block *nb, unsigned long val, 529 void *unused) 530 { 531 struct intel_lvds_connector *lvds_connector = 532 container_of(nb, struct intel_lvds_connector, lid_notifier); 533 struct drm_connector *connector = &lvds_connector->base.base; 534 struct drm_device *dev = connector->dev; 535 struct drm_i915_private *dev_priv = to_i915(dev); 536 537 if (dev->switch_power_state != DRM_SWITCH_POWER_ON) 538 return NOTIFY_OK; 539 540 mutex_lock(&dev_priv->modeset_restore_lock); 541 if (dev_priv->modeset_restore == MODESET_SUSPENDED) 542 goto exit; 543 /* 544 * check and update the status of LVDS connector after receiving 545 * the LID nofication event. 546 */ 547 connector->status = connector->funcs->detect(connector, false); 548 549 /* Don't force modeset on machines where it causes a GPU lockup */ 550 if (dmi_check_system(intel_no_modeset_on_lid)) 551 goto exit; 552 if (!acpi_lid_open()) { 553 /* do modeset on next lid open event */ 554 dev_priv->modeset_restore = MODESET_ON_LID_OPEN; 555 goto exit; 556 } 557 558 if (dev_priv->modeset_restore == MODESET_DONE) 559 goto exit; 560 561 /* 562 * Some old platform's BIOS love to wreak havoc while the lid is closed. 563 * We try to detect this here and undo any damage. The split for PCH 564 * platforms is rather conservative and a bit arbitrary expect that on 565 * those platforms VGA disabling requires actual legacy VGA I/O access, 566 * and as part of the cleanup in the hw state restore we also redisable 567 * the vga plane. 568 */ 569 if (!HAS_PCH_SPLIT(dev_priv)) 570 intel_display_resume(dev); 571 572 dev_priv->modeset_restore = MODESET_DONE; 573 574 exit: 575 mutex_unlock(&dev_priv->modeset_restore_lock); 576 return NOTIFY_OK; 577 } 578 #endif 579 580 /** 581 * intel_lvds_destroy - unregister and free LVDS structures 582 * @connector: connector to free 583 * 584 * Unregister the DDC bus for this connector then free the driver private 585 * structure. 586 */ 587 static void intel_lvds_destroy(struct drm_connector *connector) 588 { 589 struct intel_lvds_connector *lvds_connector = 590 to_lvds_connector(connector); 591 592 #if 0 593 if (lvds_connector->lid_notifier.notifier_call) 594 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); 595 #endif 596 597 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 598 kfree(lvds_connector->base.edid); 599 600 intel_panel_fini(&lvds_connector->base.panel); 601 602 drm_connector_cleanup(connector); 603 kfree(connector); 604 } 605 606 static int intel_lvds_set_property(struct drm_connector *connector, 607 struct drm_property *property, 608 uint64_t value) 609 { 610 struct intel_connector *intel_connector = to_intel_connector(connector); 611 struct drm_device *dev = connector->dev; 612 613 if (property == dev->mode_config.scaling_mode_property) { 614 struct drm_crtc *crtc; 615 616 if (value == DRM_MODE_SCALE_NONE) { 617 DRM_DEBUG_KMS("no scaling not supported\n"); 618 return -EINVAL; 619 } 620 621 if (intel_connector->panel.fitting_mode == value) { 622 /* the LVDS scaling property is not changed */ 623 return 0; 624 } 625 intel_connector->panel.fitting_mode = value; 626 627 crtc = intel_attached_encoder(connector)->base.crtc; 628 if (crtc && crtc->state->enable) { 629 /* 630 * If the CRTC is enabled, the display will be changed 631 * according to the new panel fitting mode. 632 */ 633 intel_crtc_restore_mode(crtc); 634 } 635 } 636 637 return 0; 638 } 639 640 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 641 .get_modes = intel_lvds_get_modes, 642 .mode_valid = intel_lvds_mode_valid, 643 }; 644 645 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 646 .dpms = drm_atomic_helper_connector_dpms, 647 .detect = intel_lvds_detect, 648 .fill_modes = drm_helper_probe_single_connector_modes, 649 .set_property = intel_lvds_set_property, 650 .atomic_get_property = intel_connector_atomic_get_property, 651 .late_register = intel_connector_register, 652 .early_unregister = intel_connector_unregister, 653 .destroy = intel_lvds_destroy, 654 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 655 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 656 }; 657 658 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 659 .destroy = intel_encoder_destroy, 660 }; 661 662 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 663 { 664 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 665 return 1; 666 } 667 668 /* These systems claim to have LVDS, but really don't */ 669 static const struct dmi_system_id intel_no_lvds[] = { 670 { 671 .callback = intel_no_lvds_dmi_callback, 672 .ident = "Apple Mac Mini (Core series)", 673 .matches = { 674 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 675 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 676 }, 677 }, 678 { 679 .callback = intel_no_lvds_dmi_callback, 680 .ident = "Apple Mac Mini (Core 2 series)", 681 .matches = { 682 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 683 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 684 }, 685 }, 686 { 687 .callback = intel_no_lvds_dmi_callback, 688 .ident = "MSI IM-945GSE-A", 689 .matches = { 690 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 691 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 692 }, 693 }, 694 { 695 .callback = intel_no_lvds_dmi_callback, 696 .ident = "Dell Studio Hybrid", 697 .matches = { 698 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 699 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 700 }, 701 }, 702 { 703 .callback = intel_no_lvds_dmi_callback, 704 .ident = "Dell OptiPlex FX170", 705 .matches = { 706 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 707 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 708 }, 709 }, 710 { 711 .callback = intel_no_lvds_dmi_callback, 712 .ident = "AOpen Mini PC", 713 .matches = { 714 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 715 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 716 }, 717 }, 718 { 719 .callback = intel_no_lvds_dmi_callback, 720 .ident = "AOpen Mini PC MP915", 721 .matches = { 722 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 723 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 724 }, 725 }, 726 { 727 .callback = intel_no_lvds_dmi_callback, 728 .ident = "AOpen i915GMm-HFS", 729 .matches = { 730 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 731 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 732 }, 733 }, 734 { 735 .callback = intel_no_lvds_dmi_callback, 736 .ident = "AOpen i45GMx-I", 737 .matches = { 738 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 739 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 740 }, 741 }, 742 { 743 .callback = intel_no_lvds_dmi_callback, 744 .ident = "Aopen i945GTt-VFA", 745 .matches = { 746 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 747 }, 748 }, 749 { 750 .callback = intel_no_lvds_dmi_callback, 751 .ident = "Clientron U800", 752 .matches = { 753 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 754 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 755 }, 756 }, 757 { 758 .callback = intel_no_lvds_dmi_callback, 759 .ident = "Clientron E830", 760 .matches = { 761 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 762 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 763 }, 764 }, 765 { 766 .callback = intel_no_lvds_dmi_callback, 767 .ident = "Asus EeeBox PC EB1007", 768 .matches = { 769 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 770 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 771 }, 772 }, 773 { 774 .callback = intel_no_lvds_dmi_callback, 775 .ident = "Asus AT5NM10T-I", 776 .matches = { 777 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 778 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 779 }, 780 }, 781 { 782 .callback = intel_no_lvds_dmi_callback, 783 .ident = "Hewlett-Packard HP t5740", 784 .matches = { 785 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 786 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 787 }, 788 }, 789 { 790 .callback = intel_no_lvds_dmi_callback, 791 .ident = "Hewlett-Packard t5745", 792 .matches = { 793 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 794 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 795 }, 796 }, 797 { 798 .callback = intel_no_lvds_dmi_callback, 799 .ident = "Hewlett-Packard st5747", 800 .matches = { 801 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 802 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 803 }, 804 }, 805 { 806 .callback = intel_no_lvds_dmi_callback, 807 .ident = "MSI Wind Box DC500", 808 .matches = { 809 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 810 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 811 }, 812 }, 813 { 814 .callback = intel_no_lvds_dmi_callback, 815 .ident = "Gigabyte GA-D525TUD", 816 .matches = { 817 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 818 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 819 }, 820 }, 821 { 822 .callback = intel_no_lvds_dmi_callback, 823 .ident = "Supermicro X7SPA-H", 824 .matches = { 825 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 826 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 827 }, 828 }, 829 { 830 .callback = intel_no_lvds_dmi_callback, 831 .ident = "Fujitsu Esprimo Q900", 832 .matches = { 833 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 834 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 835 }, 836 }, 837 { 838 .callback = intel_no_lvds_dmi_callback, 839 .ident = "Intel D410PT", 840 .matches = { 841 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 842 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 843 }, 844 }, 845 { 846 .callback = intel_no_lvds_dmi_callback, 847 .ident = "Intel D425KT", 848 .matches = { 849 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 850 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 851 }, 852 }, 853 { 854 .callback = intel_no_lvds_dmi_callback, 855 .ident = "Intel D510MO", 856 .matches = { 857 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 858 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 859 }, 860 }, 861 { 862 .callback = intel_no_lvds_dmi_callback, 863 .ident = "Intel D525MW", 864 .matches = { 865 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 866 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 867 }, 868 }, 869 870 { } /* terminating entry */ 871 }; 872 873 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 874 { 875 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 876 return 1; 877 } 878 879 static const struct dmi_system_id intel_dual_link_lvds[] = { 880 { 881 .callback = intel_dual_link_lvds_callback, 882 .ident = "Apple MacBook Pro 15\" (2010)", 883 .matches = { 884 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 885 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 886 }, 887 }, 888 { 889 .callback = intel_dual_link_lvds_callback, 890 .ident = "Apple MacBook Pro 15\" (2011)", 891 .matches = { 892 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 893 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 894 }, 895 }, 896 { 897 .callback = intel_dual_link_lvds_callback, 898 .ident = "Apple MacBook Pro 15\" (2012)", 899 .matches = { 900 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 901 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 902 }, 903 }, 904 { } /* terminating entry */ 905 }; 906 907 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev) 908 { 909 struct intel_encoder *intel_encoder; 910 911 for_each_intel_encoder(dev, intel_encoder) 912 if (intel_encoder->type == INTEL_OUTPUT_LVDS) 913 return intel_encoder; 914 915 return NULL; 916 } 917 918 bool intel_is_dual_link_lvds(struct drm_device *dev) 919 { 920 struct intel_encoder *encoder = intel_get_lvds_encoder(dev); 921 922 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; 923 } 924 925 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 926 { 927 struct drm_device *dev = lvds_encoder->base.base.dev; 928 unsigned int val; 929 struct drm_i915_private *dev_priv = to_i915(dev); 930 931 /* use the module option value if specified */ 932 if (i915.lvds_channel_mode > 0) 933 return i915.lvds_channel_mode == 2; 934 935 /* single channel LVDS is limited to 112 MHz */ 936 if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock 937 > 112999) 938 return true; 939 940 if (dmi_check_system(intel_dual_link_lvds)) 941 return true; 942 943 /* BIOS should set the proper LVDS register value at boot, but 944 * in reality, it doesn't set the value when the lid is closed; 945 * we need to check "the value to be set" in VBT when LVDS 946 * register is uninitialized. 947 */ 948 val = I915_READ(lvds_encoder->reg); 949 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) 950 val = dev_priv->vbt.bios_lvds_val; 951 952 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 953 } 954 955 static bool intel_lvds_supported(struct drm_i915_private *dev_priv) 956 { 957 /* With the introduction of the PCH we gained a dedicated 958 * LVDS presence pin, use it. */ 959 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) 960 return true; 961 962 /* Otherwise LVDS was only attached to mobile products, 963 * except for the inglorious 830gm */ 964 if (INTEL_GEN(dev_priv) <= 4 && 965 IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) 966 return true; 967 968 return false; 969 } 970 971 /** 972 * intel_lvds_init - setup LVDS connectors on this device 973 * @dev: drm device 974 * 975 * Create the connector, register the LVDS DDC bus, and try to figure out what 976 * modes we can display on the LVDS panel (if present). 977 */ 978 void intel_lvds_init(struct drm_i915_private *dev_priv) 979 { 980 struct drm_device *dev = &dev_priv->drm; 981 struct intel_lvds_encoder *lvds_encoder; 982 struct intel_encoder *intel_encoder; 983 struct intel_lvds_connector *lvds_connector; 984 struct intel_connector *intel_connector; 985 struct drm_connector *connector; 986 struct drm_encoder *encoder; 987 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 988 struct drm_display_mode *fixed_mode = NULL; 989 struct drm_display_mode *downclock_mode = NULL; 990 struct edid *edid; 991 struct intel_crtc *crtc; 992 i915_reg_t lvds_reg; 993 u32 lvds; 994 int pipe; 995 u8 pin; 996 997 if (!intel_lvds_supported(dev_priv)) 998 return; 999 1000 /* Skip init on machines we know falsely report LVDS */ 1001 if (dmi_check_system(intel_no_lvds)) 1002 return; 1003 1004 if (HAS_PCH_SPLIT(dev_priv)) 1005 lvds_reg = PCH_LVDS; 1006 else 1007 lvds_reg = LVDS; 1008 1009 lvds = I915_READ(lvds_reg); 1010 1011 if (HAS_PCH_SPLIT(dev_priv)) { 1012 if ((lvds & LVDS_DETECTED) == 0) 1013 return; 1014 if (dev_priv->vbt.edp.support) { 1015 DRM_DEBUG_KMS("disable LVDS for eDP support\n"); 1016 return; 1017 } 1018 } 1019 1020 pin = GMBUS_PIN_PANEL; 1021 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 1022 if ((lvds & LVDS_PORT_EN) == 0) { 1023 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 1024 return; 1025 } 1026 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); 1027 } 1028 1029 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 1030 if (!lvds_encoder) 1031 return; 1032 1033 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); 1034 if (!lvds_connector) { 1035 kfree(lvds_encoder); 1036 return; 1037 } 1038 1039 if (intel_connector_init(&lvds_connector->base) < 0) { 1040 kfree(lvds_connector); 1041 kfree(lvds_encoder); 1042 return; 1043 } 1044 1045 lvds_encoder->attached_connector = lvds_connector; 1046 1047 intel_encoder = &lvds_encoder->base; 1048 encoder = &intel_encoder->base; 1049 intel_connector = &lvds_connector->base; 1050 connector = &intel_connector->base; 1051 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 1052 DRM_MODE_CONNECTOR_LVDS); 1053 1054 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 1055 DRM_MODE_ENCODER_LVDS, "LVDS"); 1056 1057 intel_encoder->enable = intel_enable_lvds; 1058 intel_encoder->pre_enable = intel_pre_enable_lvds; 1059 intel_encoder->compute_config = intel_lvds_compute_config; 1060 if (HAS_PCH_SPLIT(dev_priv)) { 1061 intel_encoder->disable = pch_disable_lvds; 1062 intel_encoder->post_disable = pch_post_disable_lvds; 1063 } else { 1064 intel_encoder->disable = gmch_disable_lvds; 1065 } 1066 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 1067 intel_encoder->get_config = intel_lvds_get_config; 1068 intel_connector->get_hw_state = intel_connector_get_hw_state; 1069 1070 intel_connector_attach_encoder(intel_connector, intel_encoder); 1071 1072 intel_encoder->type = INTEL_OUTPUT_LVDS; 1073 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 1074 intel_encoder->port = PORT_NONE; 1075 intel_encoder->cloneable = 0; 1076 if (HAS_PCH_SPLIT(dev_priv)) 1077 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1078 else if (IS_GEN4(dev_priv)) 1079 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1080 else 1081 intel_encoder->crtc_mask = (1 << 1); 1082 1083 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 1084 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1085 connector->interlace_allowed = false; 1086 connector->doublescan_allowed = false; 1087 1088 lvds_encoder->reg = lvds_reg; 1089 1090 /* create the scaling mode property */ 1091 drm_mode_create_scaling_mode_property(dev); 1092 drm_object_attach_property(&connector->base, 1093 dev->mode_config.scaling_mode_property, 1094 DRM_MODE_SCALE_ASPECT); 1095 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 1096 1097 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); 1098 lvds_encoder->init_lvds_val = lvds; 1099 1100 /* 1101 * LVDS discovery: 1102 * 1) check for EDID on DDC 1103 * 2) check for VBT data 1104 * 3) check to see if LVDS is already on 1105 * if none of the above, no panel 1106 * 4) make sure lid is open 1107 * if closed, act like it's not there for now 1108 */ 1109 1110 /* 1111 * Attempt to get the fixed panel mode from DDC. Assume that the 1112 * preferred mode is the right one. 1113 */ 1114 mutex_lock(&dev->mode_config.mutex); 1115 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 1116 edid = drm_get_edid_switcheroo(connector, 1117 intel_gmbus_get_adapter(dev_priv, pin)); 1118 else 1119 edid = drm_get_edid(connector, 1120 intel_gmbus_get_adapter(dev_priv, pin)); 1121 if (edid) { 1122 if (drm_add_edid_modes(connector, edid)) { 1123 drm_mode_connector_update_edid_property(connector, 1124 edid); 1125 } else { 1126 kfree(edid); 1127 edid = ERR_PTR(-EINVAL); 1128 } 1129 } else { 1130 edid = ERR_PTR(-ENOENT); 1131 } 1132 lvds_connector->base.edid = edid; 1133 1134 list_for_each_entry(scan, &connector->probed_modes, head) { 1135 if (scan->type & DRM_MODE_TYPE_PREFERRED) { 1136 DRM_DEBUG_KMS("using preferred mode from EDID: "); 1137 drm_mode_debug_printmodeline(scan); 1138 1139 fixed_mode = drm_mode_duplicate(dev, scan); 1140 if (fixed_mode) 1141 goto out; 1142 } 1143 } 1144 1145 /* Failed to get EDID, what about VBT? */ 1146 if (dev_priv->vbt.lfp_lvds_vbt_mode) { 1147 DRM_DEBUG_KMS("using mode from VBT: "); 1148 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); 1149 1150 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); 1151 if (fixed_mode) { 1152 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1153 connector->display_info.width_mm = fixed_mode->width_mm; 1154 connector->display_info.height_mm = fixed_mode->height_mm; 1155 goto out; 1156 } 1157 } 1158 1159 /* 1160 * If we didn't get EDID, try checking if the panel is already turned 1161 * on. If so, assume that whatever is currently programmed is the 1162 * correct mode. 1163 */ 1164 1165 /* Ironlake: FIXME if still fail, not try pipe mode now */ 1166 if (HAS_PCH_SPLIT(dev_priv)) 1167 goto failed; 1168 1169 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; 1170 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1171 1172 if (crtc && (lvds & LVDS_PORT_EN)) { 1173 fixed_mode = intel_crtc_mode_get(dev, &crtc->base); 1174 if (fixed_mode) { 1175 DRM_DEBUG_KMS("using current (BIOS) mode: "); 1176 drm_mode_debug_printmodeline(fixed_mode); 1177 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1178 goto out; 1179 } 1180 } 1181 1182 /* If we still don't have a mode after all that, give up. */ 1183 if (!fixed_mode) 1184 goto failed; 1185 1186 out: 1187 mutex_unlock(&dev->mode_config.mutex); 1188 1189 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 1190 intel_panel_setup_backlight(connector, INVALID_PIPE); 1191 1192 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1193 DRM_DEBUG_KMS("detected %s-link lvds configuration\n", 1194 lvds_encoder->is_dual_link ? "dual" : "single"); 1195 1196 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1197 1198 #if 0 1199 lvds_connector->lid_notifier.notifier_call = intel_lid_notify; 1200 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { 1201 DRM_DEBUG_KMS("lid notifier registration failed\n"); 1202 lvds_connector->lid_notifier.notifier_call = NULL; 1203 } 1204 #endif 1205 1206 return; 1207 1208 failed: 1209 mutex_unlock(&dev->mode_config.mutex); 1210 1211 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1212 drm_connector_cleanup(connector); 1213 drm_encoder_cleanup(encoder); 1214 kfree(lvds_encoder); 1215 kfree(lvds_connector); 1216 return; 1217 } 1218