1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 #include <drm/drmP.h> 29 #include <drm/i915_drm.h> 30 #include "i915_drv.h" 31 #include "i915_reg.h" 32 #include "intel_drv.h" 33 #include "intel_frontbuffer.h" 34 35 /* Limits for overlay size. According to intel doc, the real limits are: 36 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 37 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 38 * the mininum of both. */ 39 #define IMAGE_MAX_WIDTH 2048 40 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 41 /* on 830 and 845 these large limits result in the card hanging */ 42 #define IMAGE_MAX_WIDTH_LEGACY 1024 43 #define IMAGE_MAX_HEIGHT_LEGACY 1088 44 45 /* overlay register definitions */ 46 /* OCMD register */ 47 #define OCMD_TILED_SURFACE (0x1<<19) 48 #define OCMD_MIRROR_MASK (0x3<<17) 49 #define OCMD_MIRROR_MODE (0x3<<17) 50 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 51 #define OCMD_MIRROR_VERTICAL (0x2<<17) 52 #define OCMD_MIRROR_BOTH (0x3<<17) 53 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 54 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 55 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 56 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 58 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 59 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 60 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 61 #define OCMD_YUV_422_PACKED (0x8<<10) 62 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 63 #define OCMD_YUV_420_PLANAR (0xc<<10) 64 #define OCMD_YUV_422_PLANAR (0xd<<10) 65 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 66 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 67 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 68 #define OCMD_BUF_TYPE_MASK (0x1<<5) 69 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 70 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 71 #define OCMD_TEST_MODE (0x1<<4) 72 #define OCMD_BUFFER_SELECT (0x3<<2) 73 #define OCMD_BUFFER0 (0x0<<2) 74 #define OCMD_BUFFER1 (0x1<<2) 75 #define OCMD_FIELD_SELECT (0x1<<2) 76 #define OCMD_FIELD0 (0x0<<1) 77 #define OCMD_FIELD1 (0x1<<1) 78 #define OCMD_ENABLE (0x1<<0) 79 80 /* OCONFIG register */ 81 #define OCONF_PIPE_MASK (0x1<<18) 82 #define OCONF_PIPE_A (0x0<<18) 83 #define OCONF_PIPE_B (0x1<<18) 84 #define OCONF_GAMMA2_ENABLE (0x1<<16) 85 #define OCONF_CSC_MODE_BT601 (0x0<<5) 86 #define OCONF_CSC_MODE_BT709 (0x1<<5) 87 #define OCONF_CSC_BYPASS (0x1<<4) 88 #define OCONF_CC_OUT_8BIT (0x1<<3) 89 #define OCONF_TEST_MODE (0x1<<2) 90 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 91 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 92 93 /* DCLRKM (dst-key) register */ 94 #define DST_KEY_ENABLE (0x1<<31) 95 #define CLK_RGB24_MASK 0x0 96 #define CLK_RGB16_MASK 0x070307 97 #define CLK_RGB15_MASK 0x070707 98 #define CLK_RGB8I_MASK 0xffffff 99 100 #define RGB16_TO_COLORKEY(c) \ 101 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 102 #define RGB15_TO_COLORKEY(c) \ 103 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 104 105 /* overlay flip addr flag */ 106 #define OFC_UPDATE 0x1 107 108 /* polyphase filter coefficients */ 109 #define N_HORIZ_Y_TAPS 5 110 #define N_VERT_Y_TAPS 3 111 #define N_HORIZ_UV_TAPS 3 112 #define N_VERT_UV_TAPS 3 113 #define N_PHASES 17 114 #define MAX_TAPS 5 115 116 /* memory bufferd overlay registers */ 117 struct overlay_registers { 118 u32 OBUF_0Y; 119 u32 OBUF_1Y; 120 u32 OBUF_0U; 121 u32 OBUF_0V; 122 u32 OBUF_1U; 123 u32 OBUF_1V; 124 u32 OSTRIDE; 125 u32 YRGB_VPH; 126 u32 UV_VPH; 127 u32 HORZ_PH; 128 u32 INIT_PHS; 129 u32 DWINPOS; 130 u32 DWINSZ; 131 u32 SWIDTH; 132 u32 SWIDTHSW; 133 u32 SHEIGHT; 134 u32 YRGBSCALE; 135 u32 UVSCALE; 136 u32 OCLRC0; 137 u32 OCLRC1; 138 u32 DCLRKV; 139 u32 DCLRKM; 140 u32 SCLRKVH; 141 u32 SCLRKVL; 142 u32 SCLRKEN; 143 u32 OCONFIG; 144 u32 OCMD; 145 u32 RESERVED1; /* 0x6C */ 146 u32 OSTART_0Y; 147 u32 OSTART_1Y; 148 u32 OSTART_0U; 149 u32 OSTART_0V; 150 u32 OSTART_1U; 151 u32 OSTART_1V; 152 u32 OTILEOFF_0Y; 153 u32 OTILEOFF_1Y; 154 u32 OTILEOFF_0U; 155 u32 OTILEOFF_0V; 156 u32 OTILEOFF_1U; 157 u32 OTILEOFF_1V; 158 u32 FASTHSCALE; /* 0xA0 */ 159 u32 UVSCALEV; /* 0xA4 */ 160 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 161 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 162 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 163 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 164 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 165 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 166 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 167 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 168 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 169 }; 170 171 struct intel_overlay { 172 struct drm_i915_private *i915; 173 struct intel_crtc *crtc; 174 struct i915_vma *vma; 175 struct i915_vma *old_vma; 176 bool active; 177 bool pfit_active; 178 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 179 u32 color_key:24; 180 u32 color_key_enabled:1; 181 u32 brightness, contrast, saturation; 182 u32 old_xscale, old_yscale; 183 /* register access */ 184 u32 flip_addr; 185 struct drm_i915_gem_object *reg_bo; 186 /* flip handling */ 187 struct i915_gem_active last_flip; 188 }; 189 190 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 191 bool enable) 192 { 193 struct pci_dev *pdev = dev_priv->drm.pdev; 194 u8 val; 195 196 /* WA_OVERLAY_CLKGATE:alm */ 197 if (enable) 198 I915_WRITE(DSPCLK_GATE_D, 0); 199 else 200 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 201 202 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 203 pci_bus_read_config_byte(pdev->bus, 204 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 205 if (enable) 206 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 207 else 208 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 209 #if 0 210 pci_bus_write_config_byte(pdev->bus, 211 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 212 #endif 213 } 214 215 static struct overlay_registers __iomem * 216 intel_overlay_map_regs(struct intel_overlay *overlay) 217 { 218 struct drm_i915_private *dev_priv = overlay->i915; 219 struct overlay_registers __iomem *regs; 220 221 if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) 222 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr; 223 else 224 regs = io_mapping_map_wc(&dev_priv->ggtt.mappable, 225 overlay->flip_addr, 226 PAGE_SIZE); 227 228 return regs; 229 } 230 231 static void intel_overlay_unmap_regs(struct intel_overlay *overlay, 232 struct overlay_registers __iomem *regs) 233 { 234 if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) 235 io_mapping_unmap(regs); 236 } 237 238 static void intel_overlay_submit_request(struct intel_overlay *overlay, 239 struct drm_i915_gem_request *req, 240 i915_gem_retire_fn retire) 241 { 242 GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip, 243 &overlay->i915->drm.struct_mutex)); 244 i915_gem_active_set_retire_fn(&overlay->last_flip, retire, 245 &overlay->i915->drm.struct_mutex); 246 i915_gem_active_set(&overlay->last_flip, req); 247 i915_add_request(req); 248 } 249 250 static int intel_overlay_do_wait_request(struct intel_overlay *overlay, 251 struct drm_i915_gem_request *req, 252 i915_gem_retire_fn retire) 253 { 254 intel_overlay_submit_request(overlay, req, retire); 255 return i915_gem_active_retire(&overlay->last_flip, 256 &overlay->i915->drm.struct_mutex); 257 } 258 259 static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay) 260 { 261 struct drm_i915_private *dev_priv = overlay->i915; 262 struct intel_engine_cs *engine = dev_priv->engine[RCS]; 263 264 return i915_gem_request_alloc(engine, dev_priv->kernel_context); 265 } 266 267 /* overlay needs to be disable in OCMD reg */ 268 static int intel_overlay_on(struct intel_overlay *overlay) 269 { 270 struct drm_i915_private *dev_priv = overlay->i915; 271 struct drm_i915_gem_request *req; 272 u32 *cs; 273 274 WARN_ON(overlay->active); 275 WARN_ON(IS_I830(dev_priv) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE)); 276 277 req = alloc_request(overlay); 278 if (IS_ERR(req)) 279 return PTR_ERR(req); 280 281 cs = intel_ring_begin(req, 4); 282 if (IS_ERR(cs)) { 283 i915_add_request(req); 284 return PTR_ERR(cs); 285 } 286 287 overlay->active = true; 288 289 if (IS_I830(dev_priv)) 290 i830_overlay_clock_gating(dev_priv, false); 291 292 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 293 *cs++ = overlay->flip_addr | OFC_UPDATE; 294 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 295 *cs++ = MI_NOOP; 296 intel_ring_advance(req, cs); 297 298 return intel_overlay_do_wait_request(overlay, req, NULL); 299 } 300 301 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 302 struct i915_vma *vma) 303 { 304 enum i915_pipe pipe = overlay->crtc->pipe; 305 306 WARN_ON(overlay->old_vma); 307 308 i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL, 309 vma ? vma->obj : NULL, 310 INTEL_FRONTBUFFER_OVERLAY(pipe)); 311 312 intel_frontbuffer_flip_prepare(overlay->i915, 313 INTEL_FRONTBUFFER_OVERLAY(pipe)); 314 315 overlay->old_vma = overlay->vma; 316 if (vma) 317 overlay->vma = i915_vma_get(vma); 318 else 319 overlay->vma = NULL; 320 } 321 322 /* overlay needs to be enabled in OCMD reg */ 323 static int intel_overlay_continue(struct intel_overlay *overlay, 324 struct i915_vma *vma, 325 bool load_polyphase_filter) 326 { 327 struct drm_i915_private *dev_priv = overlay->i915; 328 struct drm_i915_gem_request *req; 329 u32 flip_addr = overlay->flip_addr; 330 u32 tmp, *cs; 331 332 WARN_ON(!overlay->active); 333 334 if (load_polyphase_filter) 335 flip_addr |= OFC_UPDATE; 336 337 /* check for underruns */ 338 tmp = I915_READ(DOVSTA); 339 if (tmp & (1 << 17)) 340 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 341 342 req = alloc_request(overlay); 343 if (IS_ERR(req)) 344 return PTR_ERR(req); 345 346 cs = intel_ring_begin(req, 2); 347 if (IS_ERR(cs)) { 348 i915_add_request(req); 349 return PTR_ERR(cs); 350 } 351 352 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 353 *cs++ = flip_addr; 354 intel_ring_advance(req, cs); 355 356 intel_overlay_flip_prepare(overlay, vma); 357 358 intel_overlay_submit_request(overlay, req, NULL); 359 360 return 0; 361 } 362 363 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 364 { 365 struct i915_vma *vma; 366 367 vma = fetch_and_zero(&overlay->old_vma); 368 if (WARN_ON(!vma)) 369 return; 370 371 intel_frontbuffer_flip_complete(overlay->i915, 372 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 373 374 i915_gem_object_unpin_from_display_plane(vma); 375 i915_vma_put(vma); 376 } 377 378 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active, 379 struct drm_i915_gem_request *req) 380 { 381 struct intel_overlay *overlay = 382 container_of(active, typeof(*overlay), last_flip); 383 384 intel_overlay_release_old_vma(overlay); 385 } 386 387 static void intel_overlay_off_tail(struct i915_gem_active *active, 388 struct drm_i915_gem_request *req) 389 { 390 struct intel_overlay *overlay = 391 container_of(active, typeof(*overlay), last_flip); 392 struct drm_i915_private *dev_priv = overlay->i915; 393 394 intel_overlay_release_old_vma(overlay); 395 396 overlay->crtc->overlay = NULL; 397 overlay->crtc = NULL; 398 overlay->active = false; 399 400 if (IS_I830(dev_priv)) 401 i830_overlay_clock_gating(dev_priv, true); 402 } 403 404 /* overlay needs to be disabled in OCMD reg */ 405 static int intel_overlay_off(struct intel_overlay *overlay) 406 { 407 struct drm_i915_gem_request *req; 408 u32 *cs, flip_addr = overlay->flip_addr; 409 410 WARN_ON(!overlay->active); 411 412 /* According to intel docs the overlay hw may hang (when switching 413 * off) without loading the filter coeffs. It is however unclear whether 414 * this applies to the disabling of the overlay or to the switching off 415 * of the hw. Do it in both cases */ 416 flip_addr |= OFC_UPDATE; 417 418 req = alloc_request(overlay); 419 if (IS_ERR(req)) 420 return PTR_ERR(req); 421 422 cs = intel_ring_begin(req, 6); 423 if (IS_ERR(cs)) { 424 i915_add_request(req); 425 return PTR_ERR(cs); 426 } 427 428 /* wait for overlay to go idle */ 429 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 430 *cs++ = flip_addr; 431 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 432 433 /* turn overlay off */ 434 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 435 *cs++ = flip_addr; 436 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 437 438 intel_ring_advance(req, cs); 439 440 intel_overlay_flip_prepare(overlay, NULL); 441 442 return intel_overlay_do_wait_request(overlay, req, 443 intel_overlay_off_tail); 444 } 445 446 /* recover from an interruption due to a signal 447 * We have to be careful not to repeat work forever an make forward progess. */ 448 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 449 { 450 return i915_gem_active_retire(&overlay->last_flip, 451 &overlay->i915->drm.struct_mutex); 452 } 453 454 /* Wait for pending overlay flip and release old frame. 455 * Needs to be called before the overlay register are changed 456 * via intel_overlay_(un)map_regs 457 */ 458 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 459 { 460 struct drm_i915_private *dev_priv = overlay->i915; 461 u32 *cs; 462 int ret; 463 464 lockdep_assert_held(&dev_priv->drm.struct_mutex); 465 466 /* Only wait if there is actually an old frame to release to 467 * guarantee forward progress. 468 */ 469 if (!overlay->old_vma) 470 return 0; 471 472 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { 473 /* synchronous slowpath */ 474 struct drm_i915_gem_request *req; 475 476 req = alloc_request(overlay); 477 if (IS_ERR(req)) 478 return PTR_ERR(req); 479 480 cs = intel_ring_begin(req, 2); 481 if (IS_ERR(cs)) { 482 i915_add_request(req); 483 return PTR_ERR(cs); 484 } 485 486 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 487 *cs++ = MI_NOOP; 488 intel_ring_advance(req, cs); 489 490 ret = intel_overlay_do_wait_request(overlay, req, 491 intel_overlay_release_old_vid_tail); 492 if (ret) 493 return ret; 494 } else 495 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL); 496 497 return 0; 498 } 499 500 void intel_overlay_reset(struct drm_i915_private *dev_priv) 501 { 502 struct intel_overlay *overlay = dev_priv->overlay; 503 504 if (!overlay) 505 return; 506 507 intel_overlay_release_old_vid(overlay); 508 509 overlay->old_xscale = 0; 510 overlay->old_yscale = 0; 511 overlay->crtc = NULL; 512 overlay->active = false; 513 } 514 515 struct put_image_params { 516 int format; 517 short dst_x; 518 short dst_y; 519 short dst_w; 520 short dst_h; 521 short src_w; 522 short src_scan_h; 523 short src_scan_w; 524 short src_h; 525 short stride_Y; 526 short stride_UV; 527 int offset_Y; 528 int offset_U; 529 int offset_V; 530 }; 531 532 static int packed_depth_bytes(u32 format) 533 { 534 switch (format & I915_OVERLAY_DEPTH_MASK) { 535 case I915_OVERLAY_YUV422: 536 return 4; 537 case I915_OVERLAY_YUV411: 538 /* return 6; not implemented */ 539 default: 540 return -EINVAL; 541 } 542 } 543 544 static int packed_width_bytes(u32 format, short width) 545 { 546 switch (format & I915_OVERLAY_DEPTH_MASK) { 547 case I915_OVERLAY_YUV422: 548 return width << 1; 549 default: 550 return -EINVAL; 551 } 552 } 553 554 static int uv_hsubsampling(u32 format) 555 { 556 switch (format & I915_OVERLAY_DEPTH_MASK) { 557 case I915_OVERLAY_YUV422: 558 case I915_OVERLAY_YUV420: 559 return 2; 560 case I915_OVERLAY_YUV411: 561 case I915_OVERLAY_YUV410: 562 return 4; 563 default: 564 return -EINVAL; 565 } 566 } 567 568 static int uv_vsubsampling(u32 format) 569 { 570 switch (format & I915_OVERLAY_DEPTH_MASK) { 571 case I915_OVERLAY_YUV420: 572 case I915_OVERLAY_YUV410: 573 return 2; 574 case I915_OVERLAY_YUV422: 575 case I915_OVERLAY_YUV411: 576 return 1; 577 default: 578 return -EINVAL; 579 } 580 } 581 582 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 583 { 584 u32 sw; 585 586 if (IS_GEN2(dev_priv)) 587 sw = ALIGN((offset & 31) + width, 32); 588 else 589 sw = ALIGN((offset & 63) + width, 64); 590 591 if (sw == 0) 592 return 0; 593 594 return (sw - 32) >> 3; 595 } 596 597 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 598 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 599 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 600 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 601 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 602 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 603 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 604 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 605 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 606 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 607 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 608 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 609 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 610 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 611 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 612 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 613 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 614 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 615 }; 616 617 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 618 [ 0] = { 0x3000, 0x1800, 0x1800, }, 619 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 620 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 621 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 622 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 623 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 624 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 625 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 626 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 627 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 628 [10] = { 0xb100, 0x1eb8, 0x3620, }, 629 [11] = { 0xb100, 0x1f18, 0x34a0, }, 630 [12] = { 0xb100, 0x1f68, 0x3360, }, 631 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 632 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 633 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 634 [16] = { 0x3000, 0x0800, 0x3000, }, 635 }; 636 637 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 638 { 639 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 640 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 641 sizeof(uv_static_hcoeffs)); 642 } 643 644 static bool update_scaling_factors(struct intel_overlay *overlay, 645 struct overlay_registers __iomem *regs, 646 struct put_image_params *params) 647 { 648 /* fixed point with a 12 bit shift */ 649 u32 xscale, yscale, xscale_UV, yscale_UV; 650 #define FP_SHIFT 12 651 #define FRACT_MASK 0xfff 652 bool scale_changed = false; 653 int uv_hscale = uv_hsubsampling(params->format); 654 int uv_vscale = uv_vsubsampling(params->format); 655 656 if (params->dst_w > 1) 657 xscale = ((params->src_scan_w - 1) << FP_SHIFT) 658 /(params->dst_w); 659 else 660 xscale = 1 << FP_SHIFT; 661 662 if (params->dst_h > 1) 663 yscale = ((params->src_scan_h - 1) << FP_SHIFT) 664 /(params->dst_h); 665 else 666 yscale = 1 << FP_SHIFT; 667 668 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 669 xscale_UV = xscale/uv_hscale; 670 yscale_UV = yscale/uv_vscale; 671 /* make the Y scale to UV scale ratio an exact multiply */ 672 xscale = xscale_UV * uv_hscale; 673 yscale = yscale_UV * uv_vscale; 674 /*} else { 675 xscale_UV = 0; 676 yscale_UV = 0; 677 }*/ 678 679 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 680 scale_changed = true; 681 overlay->old_xscale = xscale; 682 overlay->old_yscale = yscale; 683 684 iowrite32(((yscale & FRACT_MASK) << 20) | 685 ((xscale >> FP_SHIFT) << 16) | 686 ((xscale & FRACT_MASK) << 3), 687 ®s->YRGBSCALE); 688 689 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 690 ((xscale_UV >> FP_SHIFT) << 16) | 691 ((xscale_UV & FRACT_MASK) << 3), 692 ®s->UVSCALE); 693 694 iowrite32((((yscale >> FP_SHIFT) << 16) | 695 ((yscale_UV >> FP_SHIFT) << 0)), 696 ®s->UVSCALEV); 697 698 if (scale_changed) 699 update_polyphase_filter(regs); 700 701 return scale_changed; 702 } 703 704 static void update_colorkey(struct intel_overlay *overlay, 705 struct overlay_registers __iomem *regs) 706 { 707 const struct intel_plane_state *state = 708 to_intel_plane_state(overlay->crtc->base.primary->state); 709 u32 key = overlay->color_key; 710 u32 format = 0; 711 u32 flags = 0; 712 713 if (overlay->color_key_enabled) 714 flags |= DST_KEY_ENABLE; 715 716 if (state->base.visible) 717 format = state->base.fb->format->format; 718 719 switch (format) { 720 case DRM_FORMAT_C8: 721 key = 0; 722 flags |= CLK_RGB8I_MASK; 723 break; 724 case DRM_FORMAT_XRGB1555: 725 key = RGB15_TO_COLORKEY(key); 726 flags |= CLK_RGB15_MASK; 727 break; 728 case DRM_FORMAT_RGB565: 729 key = RGB16_TO_COLORKEY(key); 730 flags |= CLK_RGB16_MASK; 731 break; 732 default: 733 flags |= CLK_RGB24_MASK; 734 break; 735 } 736 737 iowrite32(key, ®s->DCLRKV); 738 iowrite32(flags, ®s->DCLRKM); 739 } 740 741 static u32 overlay_cmd_reg(struct put_image_params *params) 742 { 743 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 744 745 if (params->format & I915_OVERLAY_YUV_PLANAR) { 746 switch (params->format & I915_OVERLAY_DEPTH_MASK) { 747 case I915_OVERLAY_YUV422: 748 cmd |= OCMD_YUV_422_PLANAR; 749 break; 750 case I915_OVERLAY_YUV420: 751 cmd |= OCMD_YUV_420_PLANAR; 752 break; 753 case I915_OVERLAY_YUV411: 754 case I915_OVERLAY_YUV410: 755 cmd |= OCMD_YUV_410_PLANAR; 756 break; 757 } 758 } else { /* YUV packed */ 759 switch (params->format & I915_OVERLAY_DEPTH_MASK) { 760 case I915_OVERLAY_YUV422: 761 cmd |= OCMD_YUV_422_PACKED; 762 break; 763 case I915_OVERLAY_YUV411: 764 cmd |= OCMD_YUV_411_PACKED; 765 break; 766 } 767 768 switch (params->format & I915_OVERLAY_SWAP_MASK) { 769 case I915_OVERLAY_NO_SWAP: 770 break; 771 case I915_OVERLAY_UV_SWAP: 772 cmd |= OCMD_UV_SWAP; 773 break; 774 case I915_OVERLAY_Y_SWAP: 775 cmd |= OCMD_Y_SWAP; 776 break; 777 case I915_OVERLAY_Y_AND_UV_SWAP: 778 cmd |= OCMD_Y_AND_UV_SWAP; 779 break; 780 } 781 } 782 783 return cmd; 784 } 785 786 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 787 struct drm_i915_gem_object *new_bo, 788 struct put_image_params *params) 789 { 790 int ret, tmp_width; 791 struct overlay_registers __iomem *regs; 792 bool scale_changed = false; 793 struct drm_i915_private *dev_priv = overlay->i915; 794 u32 swidth, swidthsw, sheight, ostride; 795 enum i915_pipe pipe = overlay->crtc->pipe; 796 struct i915_vma *vma; 797 798 lockdep_assert_held(&dev_priv->drm.struct_mutex); 799 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 800 801 ret = intel_overlay_release_old_vid(overlay); 802 if (ret != 0) 803 return ret; 804 805 vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL); 806 if (IS_ERR(vma)) 807 return PTR_ERR(vma); 808 809 ret = i915_vma_put_fence(vma); 810 if (ret) 811 goto out_unpin; 812 813 if (!overlay->active) { 814 u32 oconfig; 815 regs = intel_overlay_map_regs(overlay); 816 if (!regs) { 817 ret = -ENOMEM; 818 goto out_unpin; 819 } 820 oconfig = OCONF_CC_OUT_8BIT; 821 if (IS_GEN4(dev_priv)) 822 oconfig |= OCONF_CSC_MODE_BT709; 823 oconfig |= pipe == 0 ? 824 OCONF_PIPE_A : OCONF_PIPE_B; 825 iowrite32(oconfig, ®s->OCONFIG); 826 intel_overlay_unmap_regs(overlay, regs); 827 828 ret = intel_overlay_on(overlay); 829 if (ret != 0) 830 goto out_unpin; 831 } 832 833 regs = intel_overlay_map_regs(overlay); 834 if (!regs) { 835 ret = -ENOMEM; 836 goto out_unpin; 837 } 838 839 iowrite32((params->dst_y << 16) | params->dst_x, ®s->DWINPOS); 840 iowrite32((params->dst_h << 16) | params->dst_w, ®s->DWINSZ); 841 842 if (params->format & I915_OVERLAY_YUV_PACKED) 843 tmp_width = packed_width_bytes(params->format, params->src_w); 844 else 845 tmp_width = params->src_w; 846 847 swidth = params->src_w; 848 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 849 sheight = params->src_h; 850 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 851 ostride = params->stride_Y; 852 853 if (params->format & I915_OVERLAY_YUV_PLANAR) { 854 int uv_hscale = uv_hsubsampling(params->format); 855 int uv_vscale = uv_vsubsampling(params->format); 856 u32 tmp_U, tmp_V; 857 swidth |= (params->src_w/uv_hscale) << 16; 858 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 859 params->src_w/uv_hscale); 860 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 861 params->src_w/uv_hscale); 862 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16; 863 sheight |= (params->src_h/uv_vscale) << 16; 864 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 865 ®s->OBUF_0U); 866 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 867 ®s->OBUF_0V); 868 ostride |= params->stride_UV << 16; 869 } 870 871 iowrite32(swidth, ®s->SWIDTH); 872 iowrite32(swidthsw, ®s->SWIDTHSW); 873 iowrite32(sheight, ®s->SHEIGHT); 874 iowrite32(ostride, ®s->OSTRIDE); 875 876 scale_changed = update_scaling_factors(overlay, regs, params); 877 878 update_colorkey(overlay, regs); 879 880 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 881 882 intel_overlay_unmap_regs(overlay, regs); 883 884 ret = intel_overlay_continue(overlay, vma, scale_changed); 885 if (ret) 886 goto out_unpin; 887 888 return 0; 889 890 out_unpin: 891 i915_gem_object_unpin_from_display_plane(vma); 892 return ret; 893 } 894 895 int intel_overlay_switch_off(struct intel_overlay *overlay) 896 { 897 struct drm_i915_private *dev_priv = overlay->i915; 898 struct overlay_registers __iomem *regs; 899 int ret; 900 901 lockdep_assert_held(&dev_priv->drm.struct_mutex); 902 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 903 904 ret = intel_overlay_recover_from_interrupt(overlay); 905 if (ret != 0) 906 return ret; 907 908 if (!overlay->active) 909 return 0; 910 911 ret = intel_overlay_release_old_vid(overlay); 912 if (ret != 0) 913 return ret; 914 915 regs = intel_overlay_map_regs(overlay); 916 iowrite32(0, ®s->OCMD); 917 intel_overlay_unmap_regs(overlay, regs); 918 919 return intel_overlay_off(overlay); 920 } 921 922 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 923 struct intel_crtc *crtc) 924 { 925 if (!crtc->active) 926 return -EINVAL; 927 928 /* can't use the overlay with double wide pipe */ 929 if (crtc->config->double_wide) 930 return -EINVAL; 931 932 return 0; 933 } 934 935 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 936 { 937 struct drm_i915_private *dev_priv = overlay->i915; 938 u32 pfit_control = I915_READ(PFIT_CONTROL); 939 u32 ratio; 940 941 /* XXX: This is not the same logic as in the xorg driver, but more in 942 * line with the intel documentation for the i965 943 */ 944 if (INTEL_GEN(dev_priv) >= 4) { 945 /* on i965 use the PGM reg to read out the autoscaler values */ 946 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 947 } else { 948 if (pfit_control & VERT_AUTO_SCALE) 949 ratio = I915_READ(PFIT_AUTO_RATIOS); 950 else 951 ratio = I915_READ(PFIT_PGM_RATIOS); 952 ratio >>= PFIT_VERT_SCALE_SHIFT; 953 } 954 955 overlay->pfit_vscale_ratio = ratio; 956 } 957 958 static int check_overlay_dst(struct intel_overlay *overlay, 959 struct drm_intel_overlay_put_image *rec) 960 { 961 const struct intel_crtc_state *pipe_config = 962 overlay->crtc->config; 963 964 if (rec->dst_x < pipe_config->pipe_src_w && 965 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 966 rec->dst_y < pipe_config->pipe_src_h && 967 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 968 return 0; 969 else 970 return -EINVAL; 971 } 972 973 static int check_overlay_scaling(struct put_image_params *rec) 974 { 975 u32 tmp; 976 977 /* downscaling limit is 8.0 */ 978 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16; 979 if (tmp > 7) 980 return -EINVAL; 981 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16; 982 if (tmp > 7) 983 return -EINVAL; 984 985 return 0; 986 } 987 988 static int check_overlay_src(struct drm_i915_private *dev_priv, 989 struct drm_intel_overlay_put_image *rec, 990 struct drm_i915_gem_object *new_bo) 991 { 992 int uv_hscale = uv_hsubsampling(rec->flags); 993 int uv_vscale = uv_vsubsampling(rec->flags); 994 u32 stride_mask; 995 int depth; 996 u32 tmp; 997 998 /* check src dimensions */ 999 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 1000 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 1001 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 1002 return -EINVAL; 1003 } else { 1004 if (rec->src_height > IMAGE_MAX_HEIGHT || 1005 rec->src_width > IMAGE_MAX_WIDTH) 1006 return -EINVAL; 1007 } 1008 1009 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 1010 if (rec->src_height < N_VERT_Y_TAPS*4 || 1011 rec->src_width < N_HORIZ_Y_TAPS*4) 1012 return -EINVAL; 1013 1014 /* check alignment constraints */ 1015 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1016 case I915_OVERLAY_RGB: 1017 /* not implemented */ 1018 return -EINVAL; 1019 1020 case I915_OVERLAY_YUV_PACKED: 1021 if (uv_vscale != 1) 1022 return -EINVAL; 1023 1024 depth = packed_depth_bytes(rec->flags); 1025 if (depth < 0) 1026 return depth; 1027 1028 /* ignore UV planes */ 1029 rec->stride_UV = 0; 1030 rec->offset_U = 0; 1031 rec->offset_V = 0; 1032 /* check pixel alignment */ 1033 if (rec->offset_Y % depth) 1034 return -EINVAL; 1035 break; 1036 1037 case I915_OVERLAY_YUV_PLANAR: 1038 if (uv_vscale < 0 || uv_hscale < 0) 1039 return -EINVAL; 1040 /* no offset restrictions for planar formats */ 1041 break; 1042 1043 default: 1044 return -EINVAL; 1045 } 1046 1047 if (rec->src_width % uv_hscale) 1048 return -EINVAL; 1049 1050 /* stride checking */ 1051 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1052 stride_mask = 255; 1053 else 1054 stride_mask = 63; 1055 1056 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1057 return -EINVAL; 1058 if (IS_GEN4(dev_priv) && rec->stride_Y < 512) 1059 return -EINVAL; 1060 1061 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1062 4096 : 8192; 1063 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1064 return -EINVAL; 1065 1066 /* check buffer dimensions */ 1067 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1068 case I915_OVERLAY_RGB: 1069 case I915_OVERLAY_YUV_PACKED: 1070 /* always 4 Y values per depth pixels */ 1071 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1072 return -EINVAL; 1073 1074 tmp = rec->stride_Y*rec->src_height; 1075 if (rec->offset_Y + tmp > new_bo->base.size) 1076 return -EINVAL; 1077 break; 1078 1079 case I915_OVERLAY_YUV_PLANAR: 1080 if (rec->src_width > rec->stride_Y) 1081 return -EINVAL; 1082 if (rec->src_width/uv_hscale > rec->stride_UV) 1083 return -EINVAL; 1084 1085 tmp = rec->stride_Y * rec->src_height; 1086 if (rec->offset_Y + tmp > new_bo->base.size) 1087 return -EINVAL; 1088 1089 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1090 if (rec->offset_U + tmp > new_bo->base.size || 1091 rec->offset_V + tmp > new_bo->base.size) 1092 return -EINVAL; 1093 break; 1094 } 1095 1096 return 0; 1097 } 1098 1099 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1100 struct drm_file *file_priv) 1101 { 1102 struct drm_intel_overlay_put_image *put_image_rec = data; 1103 struct drm_i915_private *dev_priv = to_i915(dev); 1104 struct intel_overlay *overlay; 1105 struct drm_crtc *drmmode_crtc; 1106 struct intel_crtc *crtc; 1107 struct drm_i915_gem_object *new_bo; 1108 struct put_image_params *params; 1109 int ret; 1110 1111 overlay = dev_priv->overlay; 1112 if (!overlay) { 1113 DRM_DEBUG("userspace bug: no overlay\n"); 1114 return -ENODEV; 1115 } 1116 1117 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) { 1118 drm_modeset_lock_all(dev); 1119 mutex_lock(&dev->struct_mutex); 1120 1121 ret = intel_overlay_switch_off(overlay); 1122 1123 mutex_unlock(&dev->struct_mutex); 1124 drm_modeset_unlock_all(dev); 1125 1126 return ret; 1127 } 1128 1129 params = kmalloc(sizeof(*params), M_DRM, GFP_KERNEL); 1130 if (!params) 1131 return -ENOMEM; 1132 1133 drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id); 1134 if (!drmmode_crtc) { 1135 ret = -ENOENT; 1136 goto out_free; 1137 } 1138 crtc = to_intel_crtc(drmmode_crtc); 1139 1140 new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle); 1141 if (!new_bo) { 1142 ret = -ENOENT; 1143 goto out_free; 1144 } 1145 1146 drm_modeset_lock_all(dev); 1147 mutex_lock(&dev->struct_mutex); 1148 1149 if (i915_gem_object_is_tiled(new_bo)) { 1150 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); 1151 ret = -EINVAL; 1152 goto out_unlock; 1153 } 1154 1155 ret = intel_overlay_recover_from_interrupt(overlay); 1156 if (ret != 0) 1157 goto out_unlock; 1158 1159 if (overlay->crtc != crtc) { 1160 ret = intel_overlay_switch_off(overlay); 1161 if (ret != 0) 1162 goto out_unlock; 1163 1164 ret = check_overlay_possible_on_crtc(overlay, crtc); 1165 if (ret != 0) 1166 goto out_unlock; 1167 1168 overlay->crtc = crtc; 1169 crtc->overlay = overlay; 1170 1171 /* line too wide, i.e. one-line-mode */ 1172 if (crtc->config->pipe_src_w > 1024 && 1173 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1174 overlay->pfit_active = true; 1175 update_pfit_vscale_ratio(overlay); 1176 } else 1177 overlay->pfit_active = false; 1178 } 1179 1180 ret = check_overlay_dst(overlay, put_image_rec); 1181 if (ret != 0) 1182 goto out_unlock; 1183 1184 if (overlay->pfit_active) { 1185 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) / 1186 overlay->pfit_vscale_ratio); 1187 /* shifting right rounds downwards, so add 1 */ 1188 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) / 1189 overlay->pfit_vscale_ratio) + 1; 1190 } else { 1191 params->dst_y = put_image_rec->dst_y; 1192 params->dst_h = put_image_rec->dst_height; 1193 } 1194 params->dst_x = put_image_rec->dst_x; 1195 params->dst_w = put_image_rec->dst_width; 1196 1197 params->src_w = put_image_rec->src_width; 1198 params->src_h = put_image_rec->src_height; 1199 params->src_scan_w = put_image_rec->src_scan_width; 1200 params->src_scan_h = put_image_rec->src_scan_height; 1201 if (params->src_scan_h > params->src_h || 1202 params->src_scan_w > params->src_w) { 1203 ret = -EINVAL; 1204 goto out_unlock; 1205 } 1206 1207 ret = check_overlay_src(dev_priv, put_image_rec, new_bo); 1208 if (ret != 0) 1209 goto out_unlock; 1210 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK; 1211 params->stride_Y = put_image_rec->stride_Y; 1212 params->stride_UV = put_image_rec->stride_UV; 1213 params->offset_Y = put_image_rec->offset_Y; 1214 params->offset_U = put_image_rec->offset_U; 1215 params->offset_V = put_image_rec->offset_V; 1216 1217 /* Check scaling after src size to prevent a divide-by-zero. */ 1218 ret = check_overlay_scaling(params); 1219 if (ret != 0) 1220 goto out_unlock; 1221 1222 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1223 if (ret != 0) 1224 goto out_unlock; 1225 1226 mutex_unlock(&dev->struct_mutex); 1227 drm_modeset_unlock_all(dev); 1228 i915_gem_object_put(new_bo); 1229 1230 kfree(params); 1231 1232 return 0; 1233 1234 out_unlock: 1235 mutex_unlock(&dev->struct_mutex); 1236 drm_modeset_unlock_all(dev); 1237 i915_gem_object_put(new_bo); 1238 out_free: 1239 kfree(params); 1240 1241 return ret; 1242 } 1243 1244 static void update_reg_attrs(struct intel_overlay *overlay, 1245 struct overlay_registers __iomem *regs) 1246 { 1247 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1248 ®s->OCLRC0); 1249 iowrite32(overlay->saturation, ®s->OCLRC1); 1250 } 1251 1252 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1253 { 1254 int i; 1255 1256 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1257 return false; 1258 1259 for (i = 0; i < 3; i++) { 1260 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1261 return false; 1262 } 1263 1264 return true; 1265 } 1266 1267 static bool check_gamma5_errata(u32 gamma5) 1268 { 1269 int i; 1270 1271 for (i = 0; i < 3; i++) { 1272 if (((gamma5 >> i*8) & 0xff) == 0x80) 1273 return false; 1274 } 1275 1276 return true; 1277 } 1278 1279 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1280 { 1281 if (!check_gamma_bounds(0, attrs->gamma0) || 1282 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1283 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1284 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1285 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1286 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1287 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1288 return -EINVAL; 1289 1290 if (!check_gamma5_errata(attrs->gamma5)) 1291 return -EINVAL; 1292 1293 return 0; 1294 } 1295 1296 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1297 struct drm_file *file_priv) 1298 { 1299 struct drm_intel_overlay_attrs *attrs = data; 1300 struct drm_i915_private *dev_priv = to_i915(dev); 1301 struct intel_overlay *overlay; 1302 struct overlay_registers __iomem *regs; 1303 int ret; 1304 1305 overlay = dev_priv->overlay; 1306 if (!overlay) { 1307 DRM_DEBUG("userspace bug: no overlay\n"); 1308 return -ENODEV; 1309 } 1310 1311 drm_modeset_lock_all(dev); 1312 mutex_lock(&dev->struct_mutex); 1313 1314 ret = -EINVAL; 1315 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1316 attrs->color_key = overlay->color_key; 1317 attrs->brightness = overlay->brightness; 1318 attrs->contrast = overlay->contrast; 1319 attrs->saturation = overlay->saturation; 1320 1321 if (!IS_GEN2(dev_priv)) { 1322 attrs->gamma0 = I915_READ(OGAMC0); 1323 attrs->gamma1 = I915_READ(OGAMC1); 1324 attrs->gamma2 = I915_READ(OGAMC2); 1325 attrs->gamma3 = I915_READ(OGAMC3); 1326 attrs->gamma4 = I915_READ(OGAMC4); 1327 attrs->gamma5 = I915_READ(OGAMC5); 1328 } 1329 } else { 1330 if (attrs->brightness < -128 || attrs->brightness > 127) 1331 goto out_unlock; 1332 if (attrs->contrast > 255) 1333 goto out_unlock; 1334 if (attrs->saturation > 1023) 1335 goto out_unlock; 1336 1337 overlay->color_key = attrs->color_key; 1338 overlay->brightness = attrs->brightness; 1339 overlay->contrast = attrs->contrast; 1340 overlay->saturation = attrs->saturation; 1341 1342 regs = intel_overlay_map_regs(overlay); 1343 if (!regs) { 1344 ret = -ENOMEM; 1345 goto out_unlock; 1346 } 1347 1348 update_reg_attrs(overlay, regs); 1349 1350 intel_overlay_unmap_regs(overlay, regs); 1351 1352 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1353 if (IS_GEN2(dev_priv)) 1354 goto out_unlock; 1355 1356 if (overlay->active) { 1357 ret = -EBUSY; 1358 goto out_unlock; 1359 } 1360 1361 ret = check_gamma(attrs); 1362 if (ret) 1363 goto out_unlock; 1364 1365 I915_WRITE(OGAMC0, attrs->gamma0); 1366 I915_WRITE(OGAMC1, attrs->gamma1); 1367 I915_WRITE(OGAMC2, attrs->gamma2); 1368 I915_WRITE(OGAMC3, attrs->gamma3); 1369 I915_WRITE(OGAMC4, attrs->gamma4); 1370 I915_WRITE(OGAMC5, attrs->gamma5); 1371 } 1372 } 1373 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1374 1375 ret = 0; 1376 out_unlock: 1377 mutex_unlock(&dev->struct_mutex); 1378 drm_modeset_unlock_all(dev); 1379 1380 return ret; 1381 } 1382 1383 void intel_setup_overlay(struct drm_i915_private *dev_priv) 1384 { 1385 struct intel_overlay *overlay; 1386 struct drm_i915_gem_object *reg_bo; 1387 struct overlay_registers __iomem *regs; 1388 struct i915_vma *vma = NULL; 1389 int ret; 1390 1391 if (!HAS_OVERLAY(dev_priv)) 1392 return; 1393 1394 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1395 if (!overlay) 1396 return; 1397 1398 mutex_lock(&dev_priv->drm.struct_mutex); 1399 if (WARN_ON(dev_priv->overlay)) 1400 goto out_free; 1401 1402 overlay->i915 = dev_priv; 1403 1404 reg_bo = NULL; 1405 if (!OVERLAY_NEEDS_PHYSICAL(dev_priv)) 1406 reg_bo = i915_gem_object_create_stolen(dev_priv, PAGE_SIZE); 1407 if (reg_bo == NULL) 1408 reg_bo = i915_gem_object_create(dev_priv, PAGE_SIZE); 1409 if (IS_ERR(reg_bo)) 1410 goto out_free; 1411 overlay->reg_bo = reg_bo; 1412 1413 if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) { 1414 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE); 1415 if (ret) { 1416 DRM_ERROR("failed to attach phys overlay regs\n"); 1417 goto out_free_bo; 1418 } 1419 overlay->flip_addr = reg_bo->phys_handle->busaddr; 1420 } else { 1421 vma = i915_gem_object_ggtt_pin(reg_bo, NULL, 1422 0, PAGE_SIZE, PIN_MAPPABLE); 1423 if (IS_ERR(vma)) { 1424 DRM_ERROR("failed to pin overlay register bo\n"); 1425 ret = PTR_ERR(vma); 1426 goto out_free_bo; 1427 } 1428 overlay->flip_addr = i915_ggtt_offset(vma); 1429 1430 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true); 1431 if (ret) { 1432 DRM_ERROR("failed to move overlay register bo into the GTT\n"); 1433 goto out_unpin_bo; 1434 } 1435 } 1436 1437 /* init all values */ 1438 overlay->color_key = 0x0101fe; 1439 overlay->color_key_enabled = true; 1440 overlay->brightness = -19; 1441 overlay->contrast = 75; 1442 overlay->saturation = 146; 1443 1444 init_request_active(&overlay->last_flip, NULL); 1445 1446 regs = intel_overlay_map_regs(overlay); 1447 if (!regs) 1448 goto out_unpin_bo; 1449 1450 memset_io(regs, 0, sizeof(struct overlay_registers)); 1451 update_polyphase_filter(regs); 1452 update_reg_attrs(overlay, regs); 1453 1454 intel_overlay_unmap_regs(overlay, regs); 1455 1456 dev_priv->overlay = overlay; 1457 mutex_unlock(&dev_priv->drm.struct_mutex); 1458 DRM_INFO("initialized overlay support\n"); 1459 return; 1460 1461 out_unpin_bo: 1462 if (vma) 1463 i915_vma_unpin(vma); 1464 out_free_bo: 1465 i915_gem_object_put(reg_bo); 1466 out_free: 1467 mutex_unlock(&dev_priv->drm.struct_mutex); 1468 kfree(overlay); 1469 return; 1470 } 1471 1472 void intel_cleanup_overlay(struct drm_i915_private *dev_priv) 1473 { 1474 if (!dev_priv->overlay) 1475 return; 1476 1477 /* The bo's should be free'd by the generic code already. 1478 * Furthermore modesetting teardown happens beforehand so the 1479 * hardware should be off already */ 1480 WARN_ON(dev_priv->overlay->active); 1481 1482 i915_gem_object_put(dev_priv->overlay->reg_bo); 1483 kfree(dev_priv->overlay); 1484 } 1485 1486 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1487 1488 struct intel_overlay_error_state { 1489 struct overlay_registers regs; 1490 unsigned long base; 1491 u32 dovsta; 1492 u32 isr; 1493 }; 1494 1495 static struct overlay_registers __iomem * 1496 intel_overlay_map_regs_atomic(struct intel_overlay *overlay) 1497 { 1498 struct drm_i915_private *dev_priv = overlay->i915; 1499 struct overlay_registers __iomem *regs; 1500 1501 if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) 1502 /* Cast to make sparse happy, but it's wc memory anyway, so 1503 * equivalent to the wc io mapping on X86. */ 1504 regs = (struct overlay_registers __iomem *) 1505 overlay->reg_bo->phys_handle->vaddr; 1506 else 1507 regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.mappable, 1508 overlay->flip_addr); 1509 1510 return regs; 1511 } 1512 1513 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay, 1514 struct overlay_registers __iomem *regs) 1515 { 1516 if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) 1517 io_mapping_unmap_atomic(regs); 1518 } 1519 1520 struct intel_overlay_error_state * 1521 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1522 { 1523 struct intel_overlay *overlay = dev_priv->overlay; 1524 struct intel_overlay_error_state *error; 1525 struct overlay_registers __iomem *regs; 1526 1527 if (!overlay || !overlay->active) 1528 return NULL; 1529 1530 error = kmalloc(sizeof(*error), M_DRM, GFP_ATOMIC); 1531 if (error == NULL) 1532 return NULL; 1533 1534 error->dovsta = I915_READ(DOVSTA); 1535 error->isr = I915_READ(ISR); 1536 error->base = overlay->flip_addr; 1537 1538 regs = intel_overlay_map_regs_atomic(overlay); 1539 if (!regs) 1540 goto err; 1541 1542 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers)); 1543 intel_overlay_unmap_regs_atomic(overlay, regs); 1544 1545 return error; 1546 1547 err: 1548 kfree(error); 1549 return NULL; 1550 } 1551 1552 void 1553 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1554 struct intel_overlay_error_state *error) 1555 { 1556 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1557 error->dovsta, error->isr); 1558 i915_error_printf(m, " Register file at 0x%08lx:\n", 1559 error->base); 1560 1561 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1562 P(OBUF_0Y); 1563 P(OBUF_1Y); 1564 P(OBUF_0U); 1565 P(OBUF_0V); 1566 P(OBUF_1U); 1567 P(OBUF_1V); 1568 P(OSTRIDE); 1569 P(YRGB_VPH); 1570 P(UV_VPH); 1571 P(HORZ_PH); 1572 P(INIT_PHS); 1573 P(DWINPOS); 1574 P(DWINSZ); 1575 P(SWIDTH); 1576 P(SWIDTHSW); 1577 P(SHEIGHT); 1578 P(YRGBSCALE); 1579 P(UVSCALE); 1580 P(OCLRC0); 1581 P(OCLRC1); 1582 P(DCLRKV); 1583 P(DCLRKM); 1584 P(SCLRKVH); 1585 P(SCLRKVL); 1586 P(SCLRKEN); 1587 P(OCONFIG); 1588 P(OCMD); 1589 P(OSTART_0Y); 1590 P(OSTART_1Y); 1591 P(OSTART_0U); 1592 P(OSTART_0V); 1593 P(OSTART_1U); 1594 P(OSTART_1V); 1595 P(OTILEOFF_0Y); 1596 P(OTILEOFF_1Y); 1597 P(OTILEOFF_0U); 1598 P(OTILEOFF_0V); 1599 P(OTILEOFF_1U); 1600 P(OTILEOFF_1V); 1601 P(FASTHSCALE); 1602 P(UVSCALEV); 1603 #undef P 1604 } 1605 1606 #endif 1607