1 /* 2 * Copyright © 2008-2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Zou Nan hai <nanhai.zou@intel.com> 26 * Xiang Hai hao<haihao.xiang@intel.com> 27 * 28 */ 29 30 #include <drm/drmP.h> 31 #include "i915_drv.h" 32 #include <drm/i915_drm.h> 33 #include "i915_trace.h" 34 #include "intel_drv.h" 35 36 bool 37 intel_ring_initialized(struct intel_engine_cs *ring) 38 { 39 struct drm_device *dev = ring->dev; 40 41 if (!dev) 42 return false; 43 44 if (i915.enable_execlists) { 45 struct intel_context *dctx = ring->default_context; 46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; 47 48 return ringbuf->obj; 49 } else 50 return ring->buffer && ring->buffer->obj; 51 } 52 53 int __intel_ring_space(int head, int tail, int size) 54 { 55 int space = head - tail; 56 if (space <= 0) 57 space += size; 58 return space - I915_RING_FREE_SPACE; 59 } 60 61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf) 62 { 63 if (ringbuf->last_retired_head != -1) { 64 ringbuf->head = ringbuf->last_retired_head; 65 ringbuf->last_retired_head = -1; 66 } 67 68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, 69 ringbuf->tail, ringbuf->size); 70 } 71 72 int intel_ring_space(struct intel_ringbuffer *ringbuf) 73 { 74 intel_ring_update_space(ringbuf); 75 return ringbuf->space; 76 } 77 78 bool intel_ring_stopped(struct intel_engine_cs *ring) 79 { 80 struct drm_i915_private *dev_priv = ring->dev->dev_private; 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); 82 } 83 84 void __intel_ring_advance(struct intel_engine_cs *ring) 85 { 86 struct intel_ringbuffer *ringbuf = ring->buffer; 87 ringbuf->tail &= ringbuf->size - 1; 88 if (intel_ring_stopped(ring)) 89 return; 90 ring->write_tail(ring, ringbuf->tail); 91 } 92 93 static int 94 gen2_render_ring_flush(struct intel_engine_cs *ring, 95 u32 invalidate_domains, 96 u32 flush_domains) 97 { 98 u32 cmd; 99 int ret; 100 101 cmd = MI_FLUSH; 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) 103 cmd |= MI_NO_WRITE_FLUSH; 104 105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) 106 cmd |= MI_READ_FLUSH; 107 108 ret = intel_ring_begin(ring, 2); 109 if (ret) 110 return ret; 111 112 intel_ring_emit(ring, cmd); 113 intel_ring_emit(ring, MI_NOOP); 114 intel_ring_advance(ring); 115 116 return 0; 117 } 118 119 static int 120 gen4_render_ring_flush(struct intel_engine_cs *ring, 121 u32 invalidate_domains, 122 u32 flush_domains) 123 { 124 struct drm_device *dev = ring->dev; 125 u32 cmd; 126 int ret; 127 128 /* 129 * read/write caches: 130 * 131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is 132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is 133 * also flushed at 2d versus 3d pipeline switches. 134 * 135 * read-only caches: 136 * 137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if 138 * MI_READ_FLUSH is set, and is always flushed on 965. 139 * 140 * I915_GEM_DOMAIN_COMMAND may not exist? 141 * 142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is 143 * invalidated when MI_EXE_FLUSH is set. 144 * 145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is 146 * invalidated with every MI_FLUSH. 147 * 148 * TLBs: 149 * 150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND 151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and 152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER 153 * are flushed at any MI_FLUSH. 154 */ 155 156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) 158 cmd &= ~MI_NO_WRITE_FLUSH; 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) 160 cmd |= MI_EXE_FLUSH; 161 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && 163 (IS_G4X(dev) || IS_GEN5(dev))) 164 cmd |= MI_INVALIDATE_ISP; 165 166 ret = intel_ring_begin(ring, 2); 167 if (ret) 168 return ret; 169 170 intel_ring_emit(ring, cmd); 171 intel_ring_emit(ring, MI_NOOP); 172 intel_ring_advance(ring); 173 174 return 0; 175 } 176 177 /** 178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for 179 * implementing two workarounds on gen6. From section 1.4.7.1 180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: 181 * 182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those 183 * produced by non-pipelined state commands), software needs to first 184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation != 185 * 0. 186 * 187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable 188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. 189 * 190 * And the workaround for these two requires this workaround first: 191 * 192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent 193 * BEFORE the pipe-control with a post-sync op and no write-cache 194 * flushes. 195 * 196 * And this last workaround is tricky because of the requirements on 197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM 198 * volume 2 part 1: 199 * 200 * "1 of the following must also be set: 201 * - Render Target Cache Flush Enable ([12] of DW1) 202 * - Depth Cache Flush Enable ([0] of DW1) 203 * - Stall at Pixel Scoreboard ([1] of DW1) 204 * - Depth Stall ([13] of DW1) 205 * - Post-Sync Operation ([13] of DW1) 206 * - Notify Enable ([8] of DW1)" 207 * 208 * The cache flushes require the workaround flush that triggered this 209 * one, so we can't use it. Depth stall would trigger the same. 210 * Post-sync nonzero is what triggered this second workaround, so we 211 * can't use that one either. Notify enable is IRQs, which aren't 212 * really our business. That leaves only stall at scoreboard. 213 */ 214 static int 215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) 216 { 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; 218 int ret; 219 220 221 ret = intel_ring_begin(ring, 6); 222 if (ret) 223 return ret; 224 225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); 226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | 227 PIPE_CONTROL_STALL_AT_SCOREBOARD); 228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ 229 intel_ring_emit(ring, 0); /* low dword */ 230 intel_ring_emit(ring, 0); /* high dword */ 231 intel_ring_emit(ring, MI_NOOP); 232 intel_ring_advance(ring); 233 234 ret = intel_ring_begin(ring, 6); 235 if (ret) 236 return ret; 237 238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); 239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); 240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ 241 intel_ring_emit(ring, 0); 242 intel_ring_emit(ring, 0); 243 intel_ring_emit(ring, MI_NOOP); 244 intel_ring_advance(ring); 245 246 return 0; 247 } 248 249 static int 250 gen6_render_ring_flush(struct intel_engine_cs *ring, 251 u32 invalidate_domains, u32 flush_domains) 252 { 253 u32 flags = 0; 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; 255 int ret; 256 257 /* Force SNB workarounds for PIPE_CONTROL flushes */ 258 ret = intel_emit_post_sync_nonzero_flush(ring); 259 if (ret) 260 return ret; 261 262 /* Just flush everything. Experiments have shown that reducing the 263 * number of bits based on the write domains has little performance 264 * impact. 265 */ 266 if (flush_domains) { 267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 269 /* 270 * Ensure that any following seqno writes only happen 271 * when the render cache is indeed flushed. 272 */ 273 flags |= PIPE_CONTROL_CS_STALL; 274 } 275 if (invalidate_domains) { 276 flags |= PIPE_CONTROL_TLB_INVALIDATE; 277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 282 /* 283 * TLB invalidate requires a post-sync write. 284 */ 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; 286 } 287 288 ret = intel_ring_begin(ring, 4); 289 if (ret) 290 return ret; 291 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); 293 intel_ring_emit(ring, flags); 294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); 295 intel_ring_emit(ring, 0); 296 intel_ring_advance(ring); 297 298 return 0; 299 } 300 301 static int 302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) 303 { 304 int ret; 305 306 ret = intel_ring_begin(ring, 4); 307 if (ret) 308 return ret; 309 310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); 311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | 312 PIPE_CONTROL_STALL_AT_SCOREBOARD); 313 intel_ring_emit(ring, 0); 314 intel_ring_emit(ring, 0); 315 intel_ring_advance(ring); 316 317 return 0; 318 } 319 320 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) 321 { 322 int ret; 323 324 if (!ring->fbc_dirty) 325 return 0; 326 327 ret = intel_ring_begin(ring, 6); 328 if (ret) 329 return ret; 330 /* WaFbcNukeOn3DBlt:ivb/hsw */ 331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 332 intel_ring_emit(ring, MSG_FBC_REND_STATE); 333 intel_ring_emit(ring, value); 334 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); 335 intel_ring_emit(ring, MSG_FBC_REND_STATE); 336 intel_ring_emit(ring, ring->scratch.gtt_offset + 256); 337 intel_ring_advance(ring); 338 339 ring->fbc_dirty = false; 340 return 0; 341 } 342 343 static int 344 gen7_render_ring_flush(struct intel_engine_cs *ring, 345 u32 invalidate_domains, u32 flush_domains) 346 { 347 u32 flags = 0; 348 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; 349 int ret; 350 351 /* 352 * Ensure that any following seqno writes only happen when the render 353 * cache is indeed flushed. 354 * 355 * Workaround: 4th PIPE_CONTROL command (except the ones with only 356 * read-cache invalidate bits set) must have the CS_STALL bit set. We 357 * don't try to be clever and just set it unconditionally. 358 */ 359 flags |= PIPE_CONTROL_CS_STALL; 360 361 /* Just flush everything. Experiments have shown that reducing the 362 * number of bits based on the write domains has little performance 363 * impact. 364 */ 365 if (flush_domains) { 366 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 367 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 368 } 369 if (invalidate_domains) { 370 flags |= PIPE_CONTROL_TLB_INVALIDATE; 371 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 372 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 373 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 374 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 375 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 376 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; 377 /* 378 * TLB invalidate requires a post-sync write. 379 */ 380 flags |= PIPE_CONTROL_QW_WRITE; 381 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 382 383 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; 384 385 /* Workaround: we must issue a pipe_control with CS-stall bit 386 * set before a pipe_control command that has the state cache 387 * invalidate bit set. */ 388 gen7_render_ring_cs_stall_wa(ring); 389 } 390 391 ret = intel_ring_begin(ring, 4); 392 if (ret) 393 return ret; 394 395 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); 396 intel_ring_emit(ring, flags); 397 intel_ring_emit(ring, scratch_addr); 398 intel_ring_emit(ring, 0); 399 intel_ring_advance(ring); 400 401 if (!invalidate_domains && flush_domains) 402 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); 403 404 return 0; 405 } 406 407 static int 408 gen8_emit_pipe_control(struct intel_engine_cs *ring, 409 u32 flags, u32 scratch_addr) 410 { 411 int ret; 412 413 ret = intel_ring_begin(ring, 6); 414 if (ret) 415 return ret; 416 417 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); 418 intel_ring_emit(ring, flags); 419 intel_ring_emit(ring, scratch_addr); 420 intel_ring_emit(ring, 0); 421 intel_ring_emit(ring, 0); 422 intel_ring_emit(ring, 0); 423 intel_ring_advance(ring); 424 425 return 0; 426 } 427 428 static int 429 gen8_render_ring_flush(struct intel_engine_cs *ring, 430 u32 invalidate_domains, u32 flush_domains) 431 { 432 u32 flags = 0; 433 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; 434 int ret; 435 436 flags |= PIPE_CONTROL_CS_STALL; 437 438 if (flush_domains) { 439 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 440 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 441 } 442 if (invalidate_domains) { 443 flags |= PIPE_CONTROL_TLB_INVALIDATE; 444 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 445 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 446 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 447 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 448 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 449 flags |= PIPE_CONTROL_QW_WRITE; 450 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 451 452 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ 453 ret = gen8_emit_pipe_control(ring, 454 PIPE_CONTROL_CS_STALL | 455 PIPE_CONTROL_STALL_AT_SCOREBOARD, 456 0); 457 if (ret) 458 return ret; 459 } 460 461 ret = gen8_emit_pipe_control(ring, flags, scratch_addr); 462 if (ret) 463 return ret; 464 465 if (!invalidate_domains && flush_domains) 466 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); 467 468 return 0; 469 } 470 471 static void ring_write_tail(struct intel_engine_cs *ring, 472 u32 value) 473 { 474 struct drm_i915_private *dev_priv = ring->dev->dev_private; 475 I915_WRITE_TAIL(ring, value); 476 } 477 478 u64 intel_ring_get_active_head(struct intel_engine_cs *ring) 479 { 480 struct drm_i915_private *dev_priv = ring->dev->dev_private; 481 u64 acthd; 482 483 if (INTEL_INFO(ring->dev)->gen >= 8) 484 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), 485 RING_ACTHD_UDW(ring->mmio_base)); 486 else if (INTEL_INFO(ring->dev)->gen >= 4) 487 acthd = I915_READ(RING_ACTHD(ring->mmio_base)); 488 else 489 acthd = I915_READ(ACTHD); 490 491 return acthd; 492 } 493 494 static void ring_setup_phys_status_page(struct intel_engine_cs *ring) 495 { 496 struct drm_i915_private *dev_priv = ring->dev->dev_private; 497 u32 addr; 498 499 addr = dev_priv->status_page_dmah->busaddr; 500 if (INTEL_INFO(ring->dev)->gen >= 4) 501 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; 502 I915_WRITE(HWS_PGA, addr); 503 } 504 505 static bool stop_ring(struct intel_engine_cs *ring) 506 { 507 struct drm_i915_private *dev_priv = to_i915(ring->dev); 508 509 if (!IS_GEN2(ring->dev)) { 510 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); 511 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { 512 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); 513 /* Sometimes we observe that the idle flag is not 514 * set even though the ring is empty. So double 515 * check before giving up. 516 */ 517 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) 518 return false; 519 } 520 } 521 522 I915_WRITE_CTL(ring, 0); 523 I915_WRITE_HEAD(ring, 0); 524 ring->write_tail(ring, 0); 525 526 if (!IS_GEN2(ring->dev)) { 527 (void)I915_READ_CTL(ring); 528 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); 529 } 530 531 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; 532 } 533 534 static int init_ring_common(struct intel_engine_cs *ring) 535 { 536 struct drm_device *dev = ring->dev; 537 struct drm_i915_private *dev_priv = dev->dev_private; 538 struct intel_ringbuffer *ringbuf = ring->buffer; 539 struct drm_i915_gem_object *obj = ringbuf->obj; 540 int ret = 0; 541 542 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 543 544 if (!stop_ring(ring)) { 545 /* G45 ring initialization often fails to reset head to zero */ 546 DRM_DEBUG_KMS("%s head not reset to zero " 547 "ctl %08x head %08x tail %08x start %08x\n", 548 ring->name, 549 I915_READ_CTL(ring), 550 I915_READ_HEAD(ring), 551 I915_READ_TAIL(ring), 552 I915_READ_START(ring)); 553 554 if (!stop_ring(ring)) { 555 DRM_ERROR("failed to set %s head to zero " 556 "ctl %08x head %08x tail %08x start %08x\n", 557 ring->name, 558 I915_READ_CTL(ring), 559 I915_READ_HEAD(ring), 560 I915_READ_TAIL(ring), 561 I915_READ_START(ring)); 562 ret = -EIO; 563 goto out; 564 } 565 } 566 567 if (I915_NEED_GFX_HWS(dev)) 568 intel_ring_setup_status_page(ring); 569 else 570 ring_setup_phys_status_page(ring); 571 572 /* Enforce ordering by reading HEAD register back */ 573 I915_READ_HEAD(ring); 574 575 /* Initialize the ring. This must happen _after_ we've cleared the ring 576 * registers with the above sequence (the readback of the HEAD registers 577 * also enforces ordering), otherwise the hw might lose the new ring 578 * register values. */ 579 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); 580 581 /* WaClearRingBufHeadRegAtInit:ctg,elk */ 582 if (I915_READ_HEAD(ring)) 583 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", 584 ring->name, I915_READ_HEAD(ring)); 585 I915_WRITE_HEAD(ring, 0); 586 (void)I915_READ_HEAD(ring); 587 588 I915_WRITE_CTL(ring, 589 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) 590 | RING_VALID); 591 592 /* If the head is still not zero, the ring is dead */ 593 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && 594 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && 595 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { 596 DRM_ERROR("%s initialization failed " 597 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", 598 ring->name, 599 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, 600 I915_READ_HEAD(ring), I915_READ_TAIL(ring), 601 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); 602 ret = -EIO; 603 goto out; 604 } 605 606 ringbuf->last_retired_head = -1; 607 ringbuf->head = I915_READ_HEAD(ring); 608 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; 609 intel_ring_update_space(ringbuf); 610 611 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); 612 613 out: 614 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 615 616 return ret; 617 } 618 619 void 620 intel_fini_pipe_control(struct intel_engine_cs *ring) 621 { 622 struct drm_device *dev = ring->dev; 623 624 if (ring->scratch.obj == NULL) 625 return; 626 627 if (INTEL_INFO(dev)->gen >= 5) { 628 kunmap(ring->scratch.obj->pages[0]); 629 i915_gem_object_ggtt_unpin(ring->scratch.obj); 630 } 631 632 drm_gem_object_unreference(&ring->scratch.obj->base); 633 ring->scratch.obj = NULL; 634 } 635 636 int 637 intel_init_pipe_control(struct intel_engine_cs *ring) 638 { 639 int ret; 640 641 WARN_ON(ring->scratch.obj); 642 643 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); 644 if (ring->scratch.obj == NULL) { 645 DRM_ERROR("Failed to allocate seqno page\n"); 646 ret = -ENOMEM; 647 goto err; 648 } 649 650 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); 651 if (ret) 652 goto err_unref; 653 654 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); 655 if (ret) 656 goto err_unref; 657 658 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); 659 ring->scratch.cpu_page = kmap(ring->scratch.obj->pages[0]); 660 if (ring->scratch.cpu_page == NULL) { 661 ret = -ENOMEM; 662 goto err_unpin; 663 } 664 665 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", 666 ring->name, ring->scratch.gtt_offset); 667 return 0; 668 669 err_unpin: 670 i915_gem_object_ggtt_unpin(ring->scratch.obj); 671 err_unref: 672 drm_gem_object_unreference(&ring->scratch.obj->base); 673 err: 674 return ret; 675 } 676 677 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring, 678 struct intel_context *ctx) 679 { 680 int ret, i; 681 struct drm_device *dev = ring->dev; 682 struct drm_i915_private *dev_priv = dev->dev_private; 683 struct i915_workarounds *w = &dev_priv->workarounds; 684 685 if (WARN_ON_ONCE(w->count == 0)) 686 return 0; 687 688 ring->gpu_caches_dirty = true; 689 ret = intel_ring_flush_all_caches(ring); 690 if (ret) 691 return ret; 692 693 ret = intel_ring_begin(ring, (w->count * 2 + 2)); 694 if (ret) 695 return ret; 696 697 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); 698 for (i = 0; i < w->count; i++) { 699 intel_ring_emit(ring, w->reg[i].addr); 700 intel_ring_emit(ring, w->reg[i].value); 701 } 702 intel_ring_emit(ring, MI_NOOP); 703 704 intel_ring_advance(ring); 705 706 ring->gpu_caches_dirty = true; 707 ret = intel_ring_flush_all_caches(ring); 708 if (ret) 709 return ret; 710 711 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); 712 713 return 0; 714 } 715 716 static int intel_rcs_ctx_init(struct intel_engine_cs *ring, 717 struct intel_context *ctx) 718 { 719 int ret; 720 721 ret = intel_ring_workarounds_emit(ring, ctx); 722 if (ret != 0) 723 return ret; 724 725 ret = i915_gem_render_state_init(ring); 726 if (ret) 727 DRM_ERROR("init render state: %d\n", ret); 728 729 return ret; 730 } 731 732 static int wa_add(struct drm_i915_private *dev_priv, 733 const u32 addr, const u32 mask, const u32 val) 734 { 735 const u32 idx = dev_priv->workarounds.count; 736 737 if (WARN_ON(idx >= I915_MAX_WA_REGS)) 738 return -ENOSPC; 739 740 dev_priv->workarounds.reg[idx].addr = addr; 741 dev_priv->workarounds.reg[idx].value = val; 742 dev_priv->workarounds.reg[idx].mask = mask; 743 744 dev_priv->workarounds.count++; 745 746 return 0; 747 } 748 749 #define WA_REG(addr, mask, val) { \ 750 const int r = wa_add(dev_priv, (addr), (mask), (val)); \ 751 if (r) \ 752 return r; \ 753 } 754 755 #define WA_SET_BIT_MASKED(addr, mask) \ 756 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) 757 758 #define WA_CLR_BIT_MASKED(addr, mask) \ 759 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) 760 761 #define WA_SET_FIELD_MASKED(addr, mask, value) \ 762 WA_REG(addr, mask, _MASKED_FIELD(mask, value)) 763 764 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) 765 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) 766 767 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) 768 769 static int bdw_init_workarounds(struct intel_engine_cs *ring) 770 { 771 struct drm_device *dev = ring->dev; 772 struct drm_i915_private *dev_priv = dev->dev_private; 773 774 /* WaDisablePartialInstShootdown:bdw */ 775 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 776 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 777 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | 778 STALL_DOP_GATING_DISABLE); 779 780 /* WaDisableDopClockGating:bdw */ 781 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 782 DOP_CLOCK_GATING_DISABLE); 783 784 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 785 GEN8_SAMPLER_POWER_BYPASS_DIS); 786 787 /* Use Force Non-Coherent whenever executing a 3D context. This is a 788 * workaround for for a possible hang in the unlikely event a TLB 789 * invalidation occurs during a PSD flush. 790 */ 791 /* WaForceEnableNonCoherent:bdw */ 792 /* WaHdcDisableFetchWhenMasked:bdw */ 793 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ 794 WA_SET_BIT_MASKED(HDC_CHICKEN0, 795 HDC_FORCE_NON_COHERENT | 796 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 797 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 798 799 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 800 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 801 * polygons in the same 8x4 pixel/sample area to be processed without 802 * stalling waiting for the earlier ones to write to Hierarchical Z 803 * buffer." 804 * 805 * This optimization is off by default for Broadwell; turn it on. 806 */ 807 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 808 809 /* Wa4x4STCOptimizationDisable:bdw */ 810 WA_SET_BIT_MASKED(CACHE_MODE_1, 811 GEN8_4x4_STC_OPTIMIZATION_DISABLE); 812 813 /* 814 * BSpec recommends 8x4 when MSAA is used, 815 * however in practice 16x4 seems fastest. 816 * 817 * Note that PS/WM thread counts depend on the WIZ hashing 818 * disable bit, which we don't touch here, but it's good 819 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 820 */ 821 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 822 GEN6_WIZ_HASHING_MASK, 823 GEN6_WIZ_HASHING_16x4); 824 825 return 0; 826 } 827 828 static int chv_init_workarounds(struct intel_engine_cs *ring) 829 { 830 struct drm_device *dev = ring->dev; 831 struct drm_i915_private *dev_priv = dev->dev_private; 832 833 /* WaDisablePartialInstShootdown:chv */ 834 /* WaDisableThreadStallDopClockGating:chv */ 835 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 836 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | 837 STALL_DOP_GATING_DISABLE); 838 839 /* Use Force Non-Coherent whenever executing a 3D context. This is a 840 * workaround for a possible hang in the unlikely event a TLB 841 * invalidation occurs during a PSD flush. 842 */ 843 /* WaForceEnableNonCoherent:chv */ 844 /* WaHdcDisableFetchWhenMasked:chv */ 845 WA_SET_BIT_MASKED(HDC_CHICKEN0, 846 HDC_FORCE_NON_COHERENT | 847 HDC_DONOT_FETCH_MEM_WHEN_MASKED); 848 849 /* According to the CACHE_MODE_0 default value documentation, some 850 * CHV platforms disable this optimization by default. Turn it on. 851 */ 852 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 853 854 /* Wa4x4STCOptimizationDisable:chv */ 855 WA_SET_BIT_MASKED(CACHE_MODE_1, 856 GEN8_4x4_STC_OPTIMIZATION_DISABLE); 857 858 /* Improve HiZ throughput on CHV. */ 859 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 860 861 /* 862 * BSpec recommends 8x4 when MSAA is used, 863 * however in practice 16x4 seems fastest. 864 * 865 * Note that PS/WM thread counts depend on the WIZ hashing 866 * disable bit, which we don't touch here, but it's good 867 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 868 */ 869 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 870 GEN6_WIZ_HASHING_MASK, 871 GEN6_WIZ_HASHING_16x4); 872 873 return 0; 874 } 875 876 int init_workarounds_ring(struct intel_engine_cs *ring) 877 { 878 struct drm_device *dev = ring->dev; 879 struct drm_i915_private *dev_priv = dev->dev_private; 880 881 WARN_ON(ring->id != RCS); 882 883 dev_priv->workarounds.count = 0; 884 885 if (IS_BROADWELL(dev)) 886 return bdw_init_workarounds(ring); 887 888 if (IS_CHERRYVIEW(dev)) 889 return chv_init_workarounds(ring); 890 891 return 0; 892 } 893 894 static int init_render_ring(struct intel_engine_cs *ring) 895 { 896 struct drm_device *dev = ring->dev; 897 struct drm_i915_private *dev_priv = dev->dev_private; 898 int ret = init_ring_common(ring); 899 if (ret) 900 return ret; 901 902 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 903 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) 904 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); 905 906 /* We need to disable the AsyncFlip performance optimisations in order 907 * to use MI_WAIT_FOR_EVENT within the CS. It should already be 908 * programmed to '1' on all products. 909 * 910 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv 911 */ 912 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) 913 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); 914 915 /* Required for the hardware to program scanline values for waiting */ 916 /* WaEnableFlushTlbInvalidationMode:snb */ 917 if (INTEL_INFO(dev)->gen == 6) 918 I915_WRITE(GFX_MODE, 919 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); 920 921 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 922 if (IS_GEN7(dev)) 923 I915_WRITE(GFX_MODE_GEN7, 924 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | 925 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); 926 927 if (IS_GEN6(dev)) { 928 /* From the Sandybridge PRM, volume 1 part 3, page 24: 929 * "If this bit is set, STCunit will have LRA as replacement 930 * policy. [...] This bit must be reset. LRA replacement 931 * policy is not supported." 932 */ 933 I915_WRITE(CACHE_MODE_0, 934 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 935 } 936 937 if (INTEL_INFO(dev)->gen >= 6) 938 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); 939 940 if (HAS_L3_DPF(dev)) 941 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); 942 943 return init_workarounds_ring(ring); 944 } 945 946 static void render_ring_cleanup(struct intel_engine_cs *ring) 947 { 948 struct drm_device *dev = ring->dev; 949 struct drm_i915_private *dev_priv = dev->dev_private; 950 951 if (dev_priv->semaphore_obj) { 952 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); 953 drm_gem_object_unreference(&dev_priv->semaphore_obj->base); 954 dev_priv->semaphore_obj = NULL; 955 } 956 957 intel_fini_pipe_control(ring); 958 } 959 960 static int gen8_rcs_signal(struct intel_engine_cs *signaller, 961 unsigned int num_dwords) 962 { 963 #define MBOX_UPDATE_DWORDS 8 964 struct drm_device *dev = signaller->dev; 965 struct drm_i915_private *dev_priv = dev->dev_private; 966 struct intel_engine_cs *waiter; 967 int i, ret, num_rings; 968 969 num_rings = hweight32(INTEL_INFO(dev)->ring_mask); 970 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; 971 #undef MBOX_UPDATE_DWORDS 972 973 ret = intel_ring_begin(signaller, num_dwords); 974 if (ret) 975 return ret; 976 977 for_each_ring(waiter, dev_priv, i) { 978 u32 seqno; 979 u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; 980 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) 981 continue; 982 983 seqno = i915_gem_request_get_seqno( 984 signaller->outstanding_lazy_request); 985 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); 986 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | 987 PIPE_CONTROL_QW_WRITE | 988 PIPE_CONTROL_FLUSH_ENABLE); 989 intel_ring_emit(signaller, lower_32_bits(gtt_offset)); 990 intel_ring_emit(signaller, upper_32_bits(gtt_offset)); 991 intel_ring_emit(signaller, seqno); 992 intel_ring_emit(signaller, 0); 993 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | 994 MI_SEMAPHORE_TARGET(waiter->id)); 995 intel_ring_emit(signaller, 0); 996 } 997 998 return 0; 999 } 1000 1001 static int gen8_xcs_signal(struct intel_engine_cs *signaller, 1002 unsigned int num_dwords) 1003 { 1004 #define MBOX_UPDATE_DWORDS 6 1005 struct drm_device *dev = signaller->dev; 1006 struct drm_i915_private *dev_priv = dev->dev_private; 1007 struct intel_engine_cs *waiter; 1008 int i, ret, num_rings; 1009 1010 num_rings = hweight32(INTEL_INFO(dev)->ring_mask); 1011 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; 1012 #undef MBOX_UPDATE_DWORDS 1013 1014 ret = intel_ring_begin(signaller, num_dwords); 1015 if (ret) 1016 return ret; 1017 1018 for_each_ring(waiter, dev_priv, i) { 1019 u32 seqno; 1020 u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; 1021 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) 1022 continue; 1023 1024 seqno = i915_gem_request_get_seqno( 1025 signaller->outstanding_lazy_request); 1026 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | 1027 MI_FLUSH_DW_OP_STOREDW); 1028 intel_ring_emit(signaller, lower_32_bits(gtt_offset) | 1029 MI_FLUSH_DW_USE_GTT); 1030 intel_ring_emit(signaller, upper_32_bits(gtt_offset)); 1031 intel_ring_emit(signaller, seqno); 1032 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | 1033 MI_SEMAPHORE_TARGET(waiter->id)); 1034 intel_ring_emit(signaller, 0); 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int gen6_signal(struct intel_engine_cs *signaller, 1041 unsigned int num_dwords) 1042 { 1043 struct drm_device *dev = signaller->dev; 1044 struct drm_i915_private *dev_priv = dev->dev_private; 1045 struct intel_engine_cs *useless; 1046 int i, ret, num_rings; 1047 1048 #define MBOX_UPDATE_DWORDS 3 1049 num_rings = hweight32(INTEL_INFO(dev)->ring_mask); 1050 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); 1051 #undef MBOX_UPDATE_DWORDS 1052 1053 ret = intel_ring_begin(signaller, num_dwords); 1054 if (ret) 1055 return ret; 1056 1057 for_each_ring(useless, dev_priv, i) { 1058 u32 mbox_reg = signaller->semaphore.mbox.signal[i]; 1059 if (mbox_reg != GEN6_NOSYNC) { 1060 u32 seqno = i915_gem_request_get_seqno( 1061 signaller->outstanding_lazy_request); 1062 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); 1063 intel_ring_emit(signaller, mbox_reg); 1064 intel_ring_emit(signaller, seqno); 1065 } 1066 } 1067 1068 /* If num_dwords was rounded, make sure the tail pointer is correct */ 1069 if (num_rings % 2 == 0) 1070 intel_ring_emit(signaller, MI_NOOP); 1071 1072 return 0; 1073 } 1074 1075 /** 1076 * gen6_add_request - Update the semaphore mailbox registers 1077 * 1078 * @ring - ring that is adding a request 1079 * @seqno - return seqno stuck into the ring 1080 * 1081 * Update the mailbox registers in the *other* rings with the current seqno. 1082 * This acts like a signal in the canonical semaphore. 1083 */ 1084 static int 1085 gen6_add_request(struct intel_engine_cs *ring) 1086 { 1087 int ret; 1088 1089 if (ring->semaphore.signal) 1090 ret = ring->semaphore.signal(ring, 4); 1091 else 1092 ret = intel_ring_begin(ring, 4); 1093 1094 if (ret) 1095 return ret; 1096 1097 intel_ring_emit(ring, MI_STORE_DWORD_INDEX); 1098 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 1099 intel_ring_emit(ring, 1100 i915_gem_request_get_seqno(ring->outstanding_lazy_request)); 1101 intel_ring_emit(ring, MI_USER_INTERRUPT); 1102 __intel_ring_advance(ring); 1103 1104 return 0; 1105 } 1106 1107 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, 1108 u32 seqno) 1109 { 1110 struct drm_i915_private *dev_priv = dev->dev_private; 1111 return dev_priv->last_seqno < seqno; 1112 } 1113 1114 /** 1115 * intel_ring_sync - sync the waiter to the signaller on seqno 1116 * 1117 * @waiter - ring that is waiting 1118 * @signaller - ring which has, or will signal 1119 * @seqno - seqno which the waiter will block on 1120 */ 1121 1122 static int 1123 gen8_ring_sync(struct intel_engine_cs *waiter, 1124 struct intel_engine_cs *signaller, 1125 u32 seqno) 1126 { 1127 struct drm_i915_private *dev_priv = waiter->dev->dev_private; 1128 int ret; 1129 1130 ret = intel_ring_begin(waiter, 4); 1131 if (ret) 1132 return ret; 1133 1134 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | 1135 MI_SEMAPHORE_GLOBAL_GTT | 1136 MI_SEMAPHORE_POLL | 1137 MI_SEMAPHORE_SAD_GTE_SDD); 1138 intel_ring_emit(waiter, seqno); 1139 intel_ring_emit(waiter, 1140 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); 1141 intel_ring_emit(waiter, 1142 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); 1143 intel_ring_advance(waiter); 1144 return 0; 1145 } 1146 1147 static int 1148 gen6_ring_sync(struct intel_engine_cs *waiter, 1149 struct intel_engine_cs *signaller, 1150 u32 seqno) 1151 { 1152 u32 dw1 = MI_SEMAPHORE_MBOX | 1153 MI_SEMAPHORE_COMPARE | 1154 MI_SEMAPHORE_REGISTER; 1155 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; 1156 int ret; 1157 1158 /* Throughout all of the GEM code, seqno passed implies our current 1159 * seqno is >= the last seqno executed. However for hardware the 1160 * comparison is strictly greater than. 1161 */ 1162 seqno -= 1; 1163 1164 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); 1165 1166 ret = intel_ring_begin(waiter, 4); 1167 if (ret) 1168 return ret; 1169 1170 /* If seqno wrap happened, omit the wait with no-ops */ 1171 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { 1172 intel_ring_emit(waiter, dw1 | wait_mbox); 1173 intel_ring_emit(waiter, seqno); 1174 intel_ring_emit(waiter, 0); 1175 intel_ring_emit(waiter, MI_NOOP); 1176 } else { 1177 intel_ring_emit(waiter, MI_NOOP); 1178 intel_ring_emit(waiter, MI_NOOP); 1179 intel_ring_emit(waiter, MI_NOOP); 1180 intel_ring_emit(waiter, MI_NOOP); 1181 } 1182 intel_ring_advance(waiter); 1183 1184 return 0; 1185 } 1186 1187 #define PIPE_CONTROL_FLUSH(ring__, addr__) \ 1188 do { \ 1189 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ 1190 PIPE_CONTROL_DEPTH_STALL); \ 1191 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ 1192 intel_ring_emit(ring__, 0); \ 1193 intel_ring_emit(ring__, 0); \ 1194 } while (0) 1195 1196 static int 1197 pc_render_add_request(struct intel_engine_cs *ring) 1198 { 1199 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; 1200 int ret; 1201 1202 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently 1203 * incoherent with writes to memory, i.e. completely fubar, 1204 * so we need to use PIPE_NOTIFY instead. 1205 * 1206 * However, we also need to workaround the qword write 1207 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to 1208 * memory before requesting an interrupt. 1209 */ 1210 ret = intel_ring_begin(ring, 32); 1211 if (ret) 1212 return ret; 1213 1214 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | 1215 PIPE_CONTROL_WRITE_FLUSH | 1216 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); 1217 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); 1218 intel_ring_emit(ring, 1219 i915_gem_request_get_seqno(ring->outstanding_lazy_request)); 1220 intel_ring_emit(ring, 0); 1221 PIPE_CONTROL_FLUSH(ring, scratch_addr); 1222 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ 1223 PIPE_CONTROL_FLUSH(ring, scratch_addr); 1224 scratch_addr += 2 * CACHELINE_BYTES; 1225 PIPE_CONTROL_FLUSH(ring, scratch_addr); 1226 scratch_addr += 2 * CACHELINE_BYTES; 1227 PIPE_CONTROL_FLUSH(ring, scratch_addr); 1228 scratch_addr += 2 * CACHELINE_BYTES; 1229 PIPE_CONTROL_FLUSH(ring, scratch_addr); 1230 scratch_addr += 2 * CACHELINE_BYTES; 1231 PIPE_CONTROL_FLUSH(ring, scratch_addr); 1232 1233 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | 1234 PIPE_CONTROL_WRITE_FLUSH | 1235 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | 1236 PIPE_CONTROL_NOTIFY); 1237 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); 1238 intel_ring_emit(ring, 1239 i915_gem_request_get_seqno(ring->outstanding_lazy_request)); 1240 intel_ring_emit(ring, 0); 1241 __intel_ring_advance(ring); 1242 1243 return 0; 1244 } 1245 1246 static u32 1247 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) 1248 { 1249 /* Workaround to force correct ordering between irq and seqno writes on 1250 * ivb (and maybe also on snb) by reading from a CS register (like 1251 * ACTHD) before reading the status page. */ 1252 if (!lazy_coherency) { 1253 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1254 POSTING_READ(RING_ACTHD(ring->mmio_base)); 1255 } 1256 1257 return intel_read_status_page(ring, I915_GEM_HWS_INDEX); 1258 } 1259 1260 static u32 1261 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) 1262 { 1263 return intel_read_status_page(ring, I915_GEM_HWS_INDEX); 1264 } 1265 1266 static void 1267 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) 1268 { 1269 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); 1270 } 1271 1272 static u32 1273 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) 1274 { 1275 return ring->scratch.cpu_page[0]; 1276 } 1277 1278 static void 1279 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) 1280 { 1281 ring->scratch.cpu_page[0] = seqno; 1282 } 1283 1284 static bool 1285 gen5_ring_get_irq(struct intel_engine_cs *ring) 1286 { 1287 struct drm_device *dev = ring->dev; 1288 struct drm_i915_private *dev_priv = dev->dev_private; 1289 1290 if (WARN_ON(!intel_irqs_enabled(dev_priv))) 1291 return false; 1292 1293 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1294 if (ring->irq_refcount++ == 0) 1295 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); 1296 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1297 1298 return true; 1299 } 1300 1301 static void 1302 gen5_ring_put_irq(struct intel_engine_cs *ring) 1303 { 1304 struct drm_device *dev = ring->dev; 1305 struct drm_i915_private *dev_priv = dev->dev_private; 1306 1307 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1308 if (--ring->irq_refcount == 0) 1309 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); 1310 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1311 } 1312 1313 static bool 1314 i9xx_ring_get_irq(struct intel_engine_cs *ring) 1315 { 1316 struct drm_device *dev = ring->dev; 1317 struct drm_i915_private *dev_priv = dev->dev_private; 1318 1319 if (!intel_irqs_enabled(dev_priv)) 1320 return false; 1321 1322 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1323 if (ring->irq_refcount++ == 0) { 1324 dev_priv->irq_mask &= ~ring->irq_enable_mask; 1325 I915_WRITE(IMR, dev_priv->irq_mask); 1326 POSTING_READ(IMR); 1327 } 1328 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1329 1330 return true; 1331 } 1332 1333 static void 1334 i9xx_ring_put_irq(struct intel_engine_cs *ring) 1335 { 1336 struct drm_device *dev = ring->dev; 1337 struct drm_i915_private *dev_priv = dev->dev_private; 1338 1339 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1340 if (--ring->irq_refcount == 0) { 1341 dev_priv->irq_mask |= ring->irq_enable_mask; 1342 I915_WRITE(IMR, dev_priv->irq_mask); 1343 POSTING_READ(IMR); 1344 } 1345 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1346 } 1347 1348 static bool 1349 i8xx_ring_get_irq(struct intel_engine_cs *ring) 1350 { 1351 struct drm_device *dev = ring->dev; 1352 struct drm_i915_private *dev_priv = dev->dev_private; 1353 1354 if (!intel_irqs_enabled(dev_priv)) 1355 return false; 1356 1357 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1358 if (ring->irq_refcount++ == 0) { 1359 dev_priv->irq_mask &= ~ring->irq_enable_mask; 1360 I915_WRITE16(IMR, dev_priv->irq_mask); 1361 POSTING_READ16(IMR); 1362 } 1363 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1364 1365 return true; 1366 } 1367 1368 static void 1369 i8xx_ring_put_irq(struct intel_engine_cs *ring) 1370 { 1371 struct drm_device *dev = ring->dev; 1372 struct drm_i915_private *dev_priv = dev->dev_private; 1373 1374 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1375 if (--ring->irq_refcount == 0) { 1376 dev_priv->irq_mask |= ring->irq_enable_mask; 1377 I915_WRITE16(IMR, dev_priv->irq_mask); 1378 POSTING_READ16(IMR); 1379 } 1380 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1381 } 1382 1383 void intel_ring_setup_status_page(struct intel_engine_cs *ring) 1384 { 1385 struct drm_device *dev = ring->dev; 1386 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1387 u32 mmio = 0; 1388 1389 /* The ring status page addresses are no longer next to the rest of 1390 * the ring registers as of gen7. 1391 */ 1392 if (IS_GEN7(dev)) { 1393 switch (ring->id) { 1394 case RCS: 1395 mmio = RENDER_HWS_PGA_GEN7; 1396 break; 1397 case BCS: 1398 mmio = BLT_HWS_PGA_GEN7; 1399 break; 1400 /* 1401 * VCS2 actually doesn't exist on Gen7. Only shut up 1402 * gcc switch check warning 1403 */ 1404 case VCS2: 1405 case VCS: 1406 mmio = BSD_HWS_PGA_GEN7; 1407 break; 1408 case VECS: 1409 mmio = VEBOX_HWS_PGA_GEN7; 1410 break; 1411 } 1412 } else if (IS_GEN6(ring->dev)) { 1413 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 1414 } else { 1415 /* XXX: gen8 returns to sanity */ 1416 mmio = RING_HWS_PGA(ring->mmio_base); 1417 } 1418 1419 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); 1420 POSTING_READ(mmio); 1421 1422 /* 1423 * Flush the TLB for this page 1424 * 1425 * FIXME: These two bits have disappeared on gen8, so a question 1426 * arises: do we still need this and if so how should we go about 1427 * invalidating the TLB? 1428 */ 1429 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { 1430 u32 reg = RING_INSTPM(ring->mmio_base); 1431 1432 /* ring should be idle before issuing a sync flush*/ 1433 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); 1434 1435 I915_WRITE(reg, 1436 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | 1437 INSTPM_SYNC_FLUSH)); 1438 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, 1439 1000)) 1440 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", 1441 ring->name); 1442 } 1443 } 1444 1445 static int 1446 bsd_ring_flush(struct intel_engine_cs *ring, 1447 u32 invalidate_domains, 1448 u32 flush_domains) 1449 { 1450 int ret; 1451 1452 ret = intel_ring_begin(ring, 2); 1453 if (ret) 1454 return ret; 1455 1456 intel_ring_emit(ring, MI_FLUSH); 1457 intel_ring_emit(ring, MI_NOOP); 1458 intel_ring_advance(ring); 1459 return 0; 1460 } 1461 1462 static int 1463 i9xx_add_request(struct intel_engine_cs *ring) 1464 { 1465 int ret; 1466 1467 ret = intel_ring_begin(ring, 4); 1468 if (ret) 1469 return ret; 1470 1471 intel_ring_emit(ring, MI_STORE_DWORD_INDEX); 1472 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 1473 intel_ring_emit(ring, 1474 i915_gem_request_get_seqno(ring->outstanding_lazy_request)); 1475 intel_ring_emit(ring, MI_USER_INTERRUPT); 1476 __intel_ring_advance(ring); 1477 1478 return 0; 1479 } 1480 1481 static bool 1482 gen6_ring_get_irq(struct intel_engine_cs *ring) 1483 { 1484 struct drm_device *dev = ring->dev; 1485 struct drm_i915_private *dev_priv = dev->dev_private; 1486 1487 if (WARN_ON(!intel_irqs_enabled(dev_priv))) 1488 return false; 1489 1490 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1491 if (ring->irq_refcount++ == 0) { 1492 if (HAS_L3_DPF(dev) && ring->id == RCS) 1493 I915_WRITE_IMR(ring, 1494 ~(ring->irq_enable_mask | 1495 GT_PARITY_ERROR(dev))); 1496 else 1497 I915_WRITE_IMR(ring, ~ring->irq_enable_mask); 1498 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); 1499 } 1500 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1501 1502 return true; 1503 } 1504 1505 static void 1506 gen6_ring_put_irq(struct intel_engine_cs *ring) 1507 { 1508 struct drm_device *dev = ring->dev; 1509 struct drm_i915_private *dev_priv = dev->dev_private; 1510 1511 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1512 if (--ring->irq_refcount == 0) { 1513 if (HAS_L3_DPF(dev) && ring->id == RCS) 1514 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); 1515 else 1516 I915_WRITE_IMR(ring, ~0); 1517 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); 1518 } 1519 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1520 } 1521 1522 static bool 1523 hsw_vebox_get_irq(struct intel_engine_cs *ring) 1524 { 1525 struct drm_device *dev = ring->dev; 1526 struct drm_i915_private *dev_priv = dev->dev_private; 1527 1528 if (WARN_ON(!intel_irqs_enabled(dev_priv))) 1529 return false; 1530 1531 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1532 if (ring->irq_refcount++ == 0) { 1533 I915_WRITE_IMR(ring, ~ring->irq_enable_mask); 1534 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); 1535 } 1536 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1537 1538 return true; 1539 } 1540 1541 static void 1542 hsw_vebox_put_irq(struct intel_engine_cs *ring) 1543 { 1544 struct drm_device *dev = ring->dev; 1545 struct drm_i915_private *dev_priv = dev->dev_private; 1546 1547 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1548 if (--ring->irq_refcount == 0) { 1549 I915_WRITE_IMR(ring, ~0); 1550 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); 1551 } 1552 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1553 } 1554 1555 static bool 1556 gen8_ring_get_irq(struct intel_engine_cs *ring) 1557 { 1558 struct drm_device *dev = ring->dev; 1559 struct drm_i915_private *dev_priv = dev->dev_private; 1560 1561 if (WARN_ON(!intel_irqs_enabled(dev_priv))) 1562 return false; 1563 1564 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1565 if (ring->irq_refcount++ == 0) { 1566 if (HAS_L3_DPF(dev) && ring->id == RCS) { 1567 I915_WRITE_IMR(ring, 1568 ~(ring->irq_enable_mask | 1569 GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); 1570 } else { 1571 I915_WRITE_IMR(ring, ~ring->irq_enable_mask); 1572 } 1573 POSTING_READ(RING_IMR(ring->mmio_base)); 1574 } 1575 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1576 1577 return true; 1578 } 1579 1580 static void 1581 gen8_ring_put_irq(struct intel_engine_cs *ring) 1582 { 1583 struct drm_device *dev = ring->dev; 1584 struct drm_i915_private *dev_priv = dev->dev_private; 1585 1586 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1587 if (--ring->irq_refcount == 0) { 1588 if (HAS_L3_DPF(dev) && ring->id == RCS) { 1589 I915_WRITE_IMR(ring, 1590 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); 1591 } else { 1592 I915_WRITE_IMR(ring, ~0); 1593 } 1594 POSTING_READ(RING_IMR(ring->mmio_base)); 1595 } 1596 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1597 } 1598 1599 static int 1600 i965_dispatch_execbuffer(struct intel_engine_cs *ring, 1601 u64 offset, u32 length, 1602 unsigned flags) 1603 { 1604 int ret; 1605 1606 ret = intel_ring_begin(ring, 2); 1607 if (ret) 1608 return ret; 1609 1610 intel_ring_emit(ring, 1611 MI_BATCH_BUFFER_START | 1612 MI_BATCH_GTT | 1613 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); 1614 intel_ring_emit(ring, offset); 1615 intel_ring_advance(ring); 1616 1617 return 0; 1618 } 1619 1620 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ 1621 #define I830_BATCH_LIMIT (256*1024) 1622 #define I830_TLB_ENTRIES (2) 1623 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) 1624 static int 1625 i830_dispatch_execbuffer(struct intel_engine_cs *ring, 1626 u64 offset, u32 len, 1627 unsigned flags) 1628 { 1629 u32 cs_offset = ring->scratch.gtt_offset; 1630 int ret; 1631 1632 ret = intel_ring_begin(ring, 6); 1633 if (ret) 1634 return ret; 1635 1636 /* Evict the invalid PTE TLBs */ 1637 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); 1638 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); 1639 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ 1640 intel_ring_emit(ring, cs_offset); 1641 intel_ring_emit(ring, 0xdeadbeef); 1642 intel_ring_emit(ring, MI_NOOP); 1643 intel_ring_advance(ring); 1644 1645 if ((flags & I915_DISPATCH_PINNED) == 0) { 1646 if (len > I830_BATCH_LIMIT) 1647 return -ENOSPC; 1648 1649 ret = intel_ring_begin(ring, 6 + 2); 1650 if (ret) 1651 return ret; 1652 1653 /* Blit the batch (which has now all relocs applied) to the 1654 * stable batch scratch bo area (so that the CS never 1655 * stumbles over its tlb invalidation bug) ... 1656 */ 1657 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); 1658 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); 1659 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); 1660 intel_ring_emit(ring, cs_offset); 1661 intel_ring_emit(ring, 4096); 1662 intel_ring_emit(ring, offset); 1663 1664 intel_ring_emit(ring, MI_FLUSH); 1665 intel_ring_emit(ring, MI_NOOP); 1666 intel_ring_advance(ring); 1667 1668 /* ... and execute it. */ 1669 offset = cs_offset; 1670 } 1671 1672 ret = intel_ring_begin(ring, 4); 1673 if (ret) 1674 return ret; 1675 1676 intel_ring_emit(ring, MI_BATCH_BUFFER); 1677 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); 1678 intel_ring_emit(ring, offset + len - 8); 1679 intel_ring_emit(ring, MI_NOOP); 1680 intel_ring_advance(ring); 1681 1682 return 0; 1683 } 1684 1685 static int 1686 i915_dispatch_execbuffer(struct intel_engine_cs *ring, 1687 u64 offset, u32 len, 1688 unsigned flags) 1689 { 1690 int ret; 1691 1692 ret = intel_ring_begin(ring, 2); 1693 if (ret) 1694 return ret; 1695 1696 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); 1697 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); 1698 intel_ring_advance(ring); 1699 1700 return 0; 1701 } 1702 1703 static void cleanup_status_page(struct intel_engine_cs *ring) 1704 { 1705 struct drm_i915_gem_object *obj; 1706 1707 obj = ring->status_page.obj; 1708 if (obj == NULL) 1709 return; 1710 1711 kunmap(obj->pages[0]); 1712 i915_gem_object_ggtt_unpin(obj); 1713 drm_gem_object_unreference(&obj->base); 1714 ring->status_page.obj = NULL; 1715 } 1716 1717 static int init_status_page(struct intel_engine_cs *ring) 1718 { 1719 struct drm_i915_gem_object *obj; 1720 1721 if ((obj = ring->status_page.obj) == NULL) { 1722 unsigned flags; 1723 int ret; 1724 1725 obj = i915_gem_alloc_object(ring->dev, 4096); 1726 if (obj == NULL) { 1727 DRM_ERROR("Failed to allocate status page\n"); 1728 return -ENOMEM; 1729 } 1730 1731 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); 1732 if (ret) 1733 goto err_unref; 1734 1735 flags = 0; 1736 if (!HAS_LLC(ring->dev)) 1737 /* On g33, we cannot place HWS above 256MiB, so 1738 * restrict its pinning to the low mappable arena. 1739 * Though this restriction is not documented for 1740 * gen4, gen5, or byt, they also behave similarly 1741 * and hang if the HWS is placed at the top of the 1742 * GTT. To generalise, it appears that all !llc 1743 * platforms have issues with us placing the HWS 1744 * above the mappable region (even though we never 1745 * actualy map it). 1746 */ 1747 flags |= PIN_MAPPABLE; 1748 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); 1749 if (ret) { 1750 err_unref: 1751 drm_gem_object_unreference(&obj->base); 1752 return ret; 1753 } 1754 1755 ring->status_page.obj = obj; 1756 } 1757 1758 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); 1759 ring->status_page.page_addr = kmap(obj->pages[0]); 1760 memset(ring->status_page.page_addr, 0, PAGE_SIZE); 1761 1762 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", 1763 ring->name, ring->status_page.gfx_addr); 1764 1765 return 0; 1766 } 1767 1768 static int init_phys_status_page(struct intel_engine_cs *ring) 1769 { 1770 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1771 1772 if (!dev_priv->status_page_dmah) { 1773 dev_priv->status_page_dmah = 1774 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); 1775 if (!dev_priv->status_page_dmah) 1776 return -ENOMEM; 1777 } 1778 1779 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; 1780 memset(ring->status_page.page_addr, 0, PAGE_SIZE); 1781 1782 return 0; 1783 } 1784 1785 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) 1786 { 1787 iounmap(ringbuf->virtual_start, ringbuf->size); 1788 ringbuf->virtual_start = NULL; 1789 i915_gem_object_ggtt_unpin(ringbuf->obj); 1790 } 1791 1792 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, 1793 struct intel_ringbuffer *ringbuf) 1794 { 1795 struct drm_i915_private *dev_priv = to_i915(dev); 1796 struct drm_i915_gem_object *obj = ringbuf->obj; 1797 int ret; 1798 1799 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); 1800 if (ret) 1801 return ret; 1802 1803 ret = i915_gem_object_set_to_gtt_domain(obj, true); 1804 if (ret) { 1805 i915_gem_object_ggtt_unpin(obj); 1806 return ret; 1807 } 1808 1809 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + 1810 i915_gem_obj_ggtt_offset(obj), ringbuf->size); 1811 if (ringbuf->virtual_start == NULL) { 1812 i915_gem_object_ggtt_unpin(obj); 1813 return -EINVAL; 1814 } 1815 1816 return 0; 1817 } 1818 1819 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) 1820 { 1821 drm_gem_object_unreference(&ringbuf->obj->base); 1822 ringbuf->obj = NULL; 1823 } 1824 1825 int intel_alloc_ringbuffer_obj(struct drm_device *dev, 1826 struct intel_ringbuffer *ringbuf) 1827 { 1828 struct drm_i915_gem_object *obj; 1829 1830 obj = NULL; 1831 if (!HAS_LLC(dev)) 1832 obj = i915_gem_object_create_stolen(dev, ringbuf->size); 1833 if (obj == NULL) 1834 obj = i915_gem_alloc_object(dev, ringbuf->size); 1835 if (obj == NULL) 1836 return -ENOMEM; 1837 1838 /* mark ring buffers as read-only from GPU side by default */ 1839 obj->gt_ro = 1; 1840 1841 ringbuf->obj = obj; 1842 1843 return 0; 1844 } 1845 1846 static int intel_init_ring_buffer(struct drm_device *dev, 1847 struct intel_engine_cs *ring) 1848 { 1849 struct intel_ringbuffer *ringbuf; 1850 int ret; 1851 1852 WARN_ON(ring->buffer); 1853 1854 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); 1855 if (!ringbuf) 1856 return -ENOMEM; 1857 ring->buffer = ringbuf; 1858 1859 ring->dev = dev; 1860 INIT_LIST_HEAD(&ring->active_list); 1861 INIT_LIST_HEAD(&ring->request_list); 1862 INIT_LIST_HEAD(&ring->execlist_queue); 1863 ringbuf->size = 32 * PAGE_SIZE; 1864 ringbuf->ring = ring; 1865 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); 1866 1867 init_waitqueue_head(&ring->irq_queue); 1868 1869 if (I915_NEED_GFX_HWS(dev)) { 1870 ret = init_status_page(ring); 1871 if (ret) 1872 goto error; 1873 } else { 1874 BUG_ON(ring->id != RCS); 1875 ret = init_phys_status_page(ring); 1876 if (ret) 1877 goto error; 1878 } 1879 1880 WARN_ON(ringbuf->obj); 1881 1882 ret = intel_alloc_ringbuffer_obj(dev, ringbuf); 1883 if (ret) { 1884 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", 1885 ring->name, ret); 1886 goto error; 1887 } 1888 1889 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); 1890 if (ret) { 1891 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", 1892 ring->name, ret); 1893 intel_destroy_ringbuffer_obj(ringbuf); 1894 goto error; 1895 } 1896 1897 /* Workaround an erratum on the i830 which causes a hang if 1898 * the TAIL pointer points to within the last 2 cachelines 1899 * of the buffer. 1900 */ 1901 ringbuf->effective_size = ringbuf->size; 1902 if (IS_I830(dev) || IS_845G(dev)) 1903 ringbuf->effective_size -= 2 * CACHELINE_BYTES; 1904 1905 ret = i915_cmd_parser_init_ring(ring); 1906 if (ret) 1907 goto error; 1908 1909 return 0; 1910 1911 error: 1912 kfree(ringbuf); 1913 ring->buffer = NULL; 1914 return ret; 1915 } 1916 1917 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) 1918 { 1919 struct drm_i915_private *dev_priv; 1920 struct intel_ringbuffer *ringbuf; 1921 1922 if (!intel_ring_initialized(ring)) 1923 return; 1924 1925 dev_priv = to_i915(ring->dev); 1926 ringbuf = ring->buffer; 1927 1928 intel_stop_ring_buffer(ring); 1929 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); 1930 1931 intel_unpin_ringbuffer_obj(ringbuf); 1932 intel_destroy_ringbuffer_obj(ringbuf); 1933 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); 1934 1935 if (ring->cleanup) 1936 ring->cleanup(ring); 1937 1938 cleanup_status_page(ring); 1939 1940 i915_cmd_parser_fini_ring(ring); 1941 1942 kfree(ringbuf); 1943 ring->buffer = NULL; 1944 } 1945 1946 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) 1947 { 1948 struct intel_ringbuffer *ringbuf = ring->buffer; 1949 struct drm_i915_gem_request *request; 1950 int ret; 1951 1952 if (intel_ring_space(ringbuf) >= n) 1953 return 0; 1954 1955 list_for_each_entry(request, &ring->request_list, list) { 1956 if (__intel_ring_space(request->postfix, ringbuf->tail, 1957 ringbuf->size) >= n) { 1958 break; 1959 } 1960 } 1961 1962 if (&request->list == &ring->request_list) 1963 return -ENOSPC; 1964 1965 ret = i915_wait_request(request); 1966 if (ret) 1967 return ret; 1968 1969 i915_gem_retire_requests_ring(ring); 1970 1971 return 0; 1972 } 1973 1974 static int ring_wait_for_space(struct intel_engine_cs *ring, int n) 1975 { 1976 struct drm_device *dev = ring->dev; 1977 struct drm_i915_private *dev_priv = dev->dev_private; 1978 struct intel_ringbuffer *ringbuf = ring->buffer; 1979 unsigned long end; 1980 int ret; 1981 1982 ret = intel_ring_wait_request(ring, n); 1983 if (ret != -ENOSPC) 1984 return ret; 1985 1986 /* force the tail write in case we have been skipping them */ 1987 __intel_ring_advance(ring); 1988 1989 /* With GEM the hangcheck timer should kick us out of the loop, 1990 * leaving it early runs the risk of corrupting GEM state (due 1991 * to running on almost untested codepaths). But on resume 1992 * timers don't work yet, so prevent a complete hang in that 1993 * case by choosing an insanely large timeout. */ 1994 end = jiffies + 60 * HZ; 1995 1996 ret = 0; 1997 trace_i915_ring_wait_begin(ring); 1998 do { 1999 if (intel_ring_space(ringbuf) >= n) 2000 break; 2001 ringbuf->head = I915_READ_HEAD(ring); 2002 if (intel_ring_space(ringbuf) >= n) 2003 break; 2004 2005 msleep(1); 2006 2007 if (dev_priv->mm.interruptible && signal_pending(curthread->td_lwp)) { 2008 ret = -ERESTARTSYS; 2009 break; 2010 } 2011 2012 ret = i915_gem_check_wedge(&dev_priv->gpu_error, 2013 dev_priv->mm.interruptible); 2014 if (ret) 2015 break; 2016 2017 if (time_after(jiffies, end)) { 2018 ret = -EBUSY; 2019 break; 2020 } 2021 } while (1); 2022 trace_i915_ring_wait_end(ring); 2023 return ret; 2024 } 2025 2026 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) 2027 { 2028 uint32_t __iomem *virt; 2029 struct intel_ringbuffer *ringbuf = ring->buffer; 2030 int rem = ringbuf->size - ringbuf->tail; 2031 2032 if (ringbuf->space < rem) { 2033 int ret = ring_wait_for_space(ring, rem); 2034 if (ret) 2035 return ret; 2036 } 2037 2038 virt = (unsigned int *)((char *)ringbuf->virtual_start + ringbuf->tail); 2039 rem /= 4; 2040 while (rem--) 2041 iowrite32(MI_NOOP, virt++); 2042 2043 ringbuf->tail = 0; 2044 intel_ring_update_space(ringbuf); 2045 2046 return 0; 2047 } 2048 2049 int intel_ring_idle(struct intel_engine_cs *ring) 2050 { 2051 struct drm_i915_gem_request *req; 2052 int ret; 2053 2054 /* We need to add any requests required to flush the objects and ring */ 2055 if (ring->outstanding_lazy_request) { 2056 ret = i915_add_request(ring); 2057 if (ret) 2058 return ret; 2059 } 2060 2061 /* Wait upon the last request to be completed */ 2062 if (list_empty(&ring->request_list)) 2063 return 0; 2064 2065 req = list_entry(ring->request_list.prev, 2066 struct drm_i915_gem_request, 2067 list); 2068 2069 return i915_wait_request(req); 2070 } 2071 2072 static int 2073 intel_ring_alloc_request(struct intel_engine_cs *ring) 2074 { 2075 int ret; 2076 struct drm_i915_gem_request *request; 2077 struct drm_i915_private *dev_private = ring->dev->dev_private; 2078 2079 if (ring->outstanding_lazy_request) 2080 return 0; 2081 2082 request = kzalloc(sizeof(*request), GFP_KERNEL); 2083 if (request == NULL) 2084 return -ENOMEM; 2085 2086 kref_init(&request->ref); 2087 request->ring = ring; 2088 request->uniq = dev_private->request_uniq++; 2089 2090 ret = i915_gem_get_seqno(ring->dev, &request->seqno); 2091 if (ret) { 2092 kfree(request); 2093 return ret; 2094 } 2095 2096 ring->outstanding_lazy_request = request; 2097 return 0; 2098 } 2099 2100 static int __intel_ring_prepare(struct intel_engine_cs *ring, 2101 int bytes) 2102 { 2103 struct intel_ringbuffer *ringbuf = ring->buffer; 2104 int ret; 2105 2106 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { 2107 ret = intel_wrap_ring_buffer(ring); 2108 if (unlikely(ret)) 2109 return ret; 2110 } 2111 2112 if (unlikely(ringbuf->space < bytes)) { 2113 ret = ring_wait_for_space(ring, bytes); 2114 if (unlikely(ret)) 2115 return ret; 2116 } 2117 2118 return 0; 2119 } 2120 2121 int intel_ring_begin(struct intel_engine_cs *ring, 2122 int num_dwords) 2123 { 2124 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2125 int ret; 2126 2127 ret = i915_gem_check_wedge(&dev_priv->gpu_error, 2128 dev_priv->mm.interruptible); 2129 if (ret) 2130 return ret; 2131 2132 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); 2133 if (ret) 2134 return ret; 2135 2136 /* Preallocate the olr before touching the ring */ 2137 ret = intel_ring_alloc_request(ring); 2138 if (ret) 2139 return ret; 2140 2141 ring->buffer->space -= num_dwords * sizeof(uint32_t); 2142 return 0; 2143 } 2144 2145 /* Align the ring tail to a cacheline boundary */ 2146 int intel_ring_cacheline_align(struct intel_engine_cs *ring) 2147 { 2148 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); 2149 int ret; 2150 2151 if (num_dwords == 0) 2152 return 0; 2153 2154 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; 2155 ret = intel_ring_begin(ring, num_dwords); 2156 if (ret) 2157 return ret; 2158 2159 while (num_dwords--) 2160 intel_ring_emit(ring, MI_NOOP); 2161 2162 intel_ring_advance(ring); 2163 2164 return 0; 2165 } 2166 2167 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) 2168 { 2169 struct drm_device *dev = ring->dev; 2170 struct drm_i915_private *dev_priv = dev->dev_private; 2171 2172 BUG_ON(ring->outstanding_lazy_request); 2173 2174 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { 2175 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); 2176 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); 2177 if (HAS_VEBOX(dev)) 2178 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); 2179 } 2180 2181 ring->set_seqno(ring, seqno); 2182 ring->hangcheck.seqno = seqno; 2183 } 2184 2185 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, 2186 u32 value) 2187 { 2188 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2189 2190 /* Every tail move must follow the sequence below */ 2191 2192 /* Disable notification that the ring is IDLE. The GT 2193 * will then assume that it is busy and bring it out of rc6. 2194 */ 2195 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, 2196 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 2197 2198 /* Clear the context id. Here be magic! */ 2199 I915_WRITE64(GEN6_BSD_RNCID, 0x0); 2200 2201 /* Wait for the ring not to be idle, i.e. for it to wake up. */ 2202 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & 2203 GEN6_BSD_SLEEP_INDICATOR) == 0, 2204 50)) 2205 DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); 2206 2207 /* Now that the ring is fully powered up, update the tail */ 2208 I915_WRITE_TAIL(ring, value); 2209 POSTING_READ(RING_TAIL(ring->mmio_base)); 2210 2211 /* Let the ring send IDLE messages to the GT again, 2212 * and so let it sleep to conserve power when idle. 2213 */ 2214 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, 2215 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 2216 } 2217 2218 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, 2219 u32 invalidate, u32 flush) 2220 { 2221 uint32_t cmd; 2222 int ret; 2223 2224 ret = intel_ring_begin(ring, 4); 2225 if (ret) 2226 return ret; 2227 2228 cmd = MI_FLUSH_DW; 2229 if (INTEL_INFO(ring->dev)->gen >= 8) 2230 cmd += 1; 2231 2232 /* We always require a command barrier so that subsequent 2233 * commands, such as breadcrumb interrupts, are strictly ordered 2234 * wrt the contents of the write cache being flushed to memory 2235 * (and thus being coherent from the CPU). 2236 */ 2237 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 2238 2239 /* 2240 * Bspec vol 1c.5 - video engine command streamer: 2241 * "If ENABLED, all TLBs will be invalidated once the flush 2242 * operation is complete. This bit is only valid when the 2243 * Post-Sync Operation field is a value of 1h or 3h." 2244 */ 2245 if (invalidate & I915_GEM_GPU_DOMAINS) 2246 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; 2247 2248 intel_ring_emit(ring, cmd); 2249 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); 2250 if (INTEL_INFO(ring->dev)->gen >= 8) { 2251 intel_ring_emit(ring, 0); /* upper addr */ 2252 intel_ring_emit(ring, 0); /* value */ 2253 } else { 2254 intel_ring_emit(ring, 0); 2255 intel_ring_emit(ring, MI_NOOP); 2256 } 2257 intel_ring_advance(ring); 2258 return 0; 2259 } 2260 2261 static int 2262 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, 2263 u64 offset, u32 len, 2264 unsigned flags) 2265 { 2266 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE); 2267 int ret; 2268 2269 ret = intel_ring_begin(ring, 4); 2270 if (ret) 2271 return ret; 2272 2273 /* FIXME(BDW): Address space and security selectors. */ 2274 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); 2275 intel_ring_emit(ring, lower_32_bits(offset)); 2276 intel_ring_emit(ring, upper_32_bits(offset)); 2277 intel_ring_emit(ring, MI_NOOP); 2278 intel_ring_advance(ring); 2279 2280 return 0; 2281 } 2282 2283 static int 2284 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, 2285 u64 offset, u32 len, 2286 unsigned flags) 2287 { 2288 int ret; 2289 2290 ret = intel_ring_begin(ring, 2); 2291 if (ret) 2292 return ret; 2293 2294 intel_ring_emit(ring, 2295 MI_BATCH_BUFFER_START | 2296 (flags & I915_DISPATCH_SECURE ? 2297 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW)); 2298 /* bit0-7 is the length on GEN6+ */ 2299 intel_ring_emit(ring, offset); 2300 intel_ring_advance(ring); 2301 2302 return 0; 2303 } 2304 2305 static int 2306 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, 2307 u64 offset, u32 len, 2308 unsigned flags) 2309 { 2310 int ret; 2311 2312 ret = intel_ring_begin(ring, 2); 2313 if (ret) 2314 return ret; 2315 2316 intel_ring_emit(ring, 2317 MI_BATCH_BUFFER_START | 2318 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); 2319 /* bit0-7 is the length on GEN6+ */ 2320 intel_ring_emit(ring, offset); 2321 intel_ring_advance(ring); 2322 2323 return 0; 2324 } 2325 2326 /* Blitter support (SandyBridge+) */ 2327 2328 static int gen6_ring_flush(struct intel_engine_cs *ring, 2329 u32 invalidate, u32 flush) 2330 { 2331 struct drm_device *dev = ring->dev; 2332 struct drm_i915_private *dev_priv = dev->dev_private; 2333 uint32_t cmd; 2334 int ret; 2335 2336 ret = intel_ring_begin(ring, 4); 2337 if (ret) 2338 return ret; 2339 2340 cmd = MI_FLUSH_DW; 2341 if (INTEL_INFO(ring->dev)->gen >= 8) 2342 cmd += 1; 2343 2344 /* We always require a command barrier so that subsequent 2345 * commands, such as breadcrumb interrupts, are strictly ordered 2346 * wrt the contents of the write cache being flushed to memory 2347 * (and thus being coherent from the CPU). 2348 */ 2349 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 2350 2351 /* 2352 * Bspec vol 1c.3 - blitter engine command streamer: 2353 * "If ENABLED, all TLBs will be invalidated once the flush 2354 * operation is complete. This bit is only valid when the 2355 * Post-Sync Operation field is a value of 1h or 3h." 2356 */ 2357 if (invalidate & I915_GEM_DOMAIN_RENDER) 2358 cmd |= MI_INVALIDATE_TLB; 2359 intel_ring_emit(ring, cmd); 2360 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); 2361 if (INTEL_INFO(ring->dev)->gen >= 8) { 2362 intel_ring_emit(ring, 0); /* upper addr */ 2363 intel_ring_emit(ring, 0); /* value */ 2364 } else { 2365 intel_ring_emit(ring, 0); 2366 intel_ring_emit(ring, MI_NOOP); 2367 } 2368 intel_ring_advance(ring); 2369 2370 if (!invalidate && flush) { 2371 if (IS_GEN7(dev)) 2372 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); 2373 else if (IS_BROADWELL(dev)) 2374 dev_priv->fbc.need_sw_cache_clean = true; 2375 } 2376 2377 return 0; 2378 } 2379 2380 int intel_init_render_ring_buffer(struct drm_device *dev) 2381 { 2382 struct drm_i915_private *dev_priv = dev->dev_private; 2383 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; 2384 struct drm_i915_gem_object *obj; 2385 int ret; 2386 2387 ring->name = "render ring"; 2388 ring->id = RCS; 2389 ring->mmio_base = RENDER_RING_BASE; 2390 2391 if (INTEL_INFO(dev)->gen >= 8) { 2392 if (i915_semaphore_is_enabled(dev)) { 2393 obj = i915_gem_alloc_object(dev, 4096); 2394 if (obj == NULL) { 2395 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); 2396 i915.semaphores = 0; 2397 } else { 2398 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); 2399 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); 2400 if (ret != 0) { 2401 drm_gem_object_unreference(&obj->base); 2402 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); 2403 i915.semaphores = 0; 2404 } else 2405 dev_priv->semaphore_obj = obj; 2406 } 2407 } 2408 2409 ring->init_context = intel_rcs_ctx_init; 2410 ring->add_request = gen6_add_request; 2411 ring->flush = gen8_render_ring_flush; 2412 ring->irq_get = gen8_ring_get_irq; 2413 ring->irq_put = gen8_ring_put_irq; 2414 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; 2415 ring->get_seqno = gen6_ring_get_seqno; 2416 ring->set_seqno = ring_set_seqno; 2417 if (i915_semaphore_is_enabled(dev)) { 2418 WARN_ON(!dev_priv->semaphore_obj); 2419 ring->semaphore.sync_to = gen8_ring_sync; 2420 ring->semaphore.signal = gen8_rcs_signal; 2421 GEN8_RING_SEMAPHORE_INIT; 2422 } 2423 } else if (INTEL_INFO(dev)->gen >= 6) { 2424 ring->add_request = gen6_add_request; 2425 ring->flush = gen7_render_ring_flush; 2426 if (INTEL_INFO(dev)->gen == 6) 2427 ring->flush = gen6_render_ring_flush; 2428 ring->irq_get = gen6_ring_get_irq; 2429 ring->irq_put = gen6_ring_put_irq; 2430 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; 2431 ring->get_seqno = gen6_ring_get_seqno; 2432 ring->set_seqno = ring_set_seqno; 2433 if (i915_semaphore_is_enabled(dev)) { 2434 ring->semaphore.sync_to = gen6_ring_sync; 2435 ring->semaphore.signal = gen6_signal; 2436 /* 2437 * The current semaphore is only applied on pre-gen8 2438 * platform. And there is no VCS2 ring on the pre-gen8 2439 * platform. So the semaphore between RCS and VCS2 is 2440 * initialized as INVALID. Gen8 will initialize the 2441 * sema between VCS2 and RCS later. 2442 */ 2443 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; 2444 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; 2445 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; 2446 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; 2447 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; 2448 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; 2449 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; 2450 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; 2451 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; 2452 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; 2453 } 2454 } else if (IS_GEN5(dev)) { 2455 ring->add_request = pc_render_add_request; 2456 ring->flush = gen4_render_ring_flush; 2457 ring->get_seqno = pc_render_get_seqno; 2458 ring->set_seqno = pc_render_set_seqno; 2459 ring->irq_get = gen5_ring_get_irq; 2460 ring->irq_put = gen5_ring_put_irq; 2461 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | 2462 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; 2463 } else { 2464 ring->add_request = i9xx_add_request; 2465 if (INTEL_INFO(dev)->gen < 4) 2466 ring->flush = gen2_render_ring_flush; 2467 else 2468 ring->flush = gen4_render_ring_flush; 2469 ring->get_seqno = ring_get_seqno; 2470 ring->set_seqno = ring_set_seqno; 2471 if (IS_GEN2(dev)) { 2472 ring->irq_get = i8xx_ring_get_irq; 2473 ring->irq_put = i8xx_ring_put_irq; 2474 } else { 2475 ring->irq_get = i9xx_ring_get_irq; 2476 ring->irq_put = i9xx_ring_put_irq; 2477 } 2478 ring->irq_enable_mask = I915_USER_INTERRUPT; 2479 } 2480 ring->write_tail = ring_write_tail; 2481 2482 if (IS_HASWELL(dev)) 2483 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; 2484 else if (IS_GEN8(dev)) 2485 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; 2486 else if (INTEL_INFO(dev)->gen >= 6) 2487 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; 2488 else if (INTEL_INFO(dev)->gen >= 4) 2489 ring->dispatch_execbuffer = i965_dispatch_execbuffer; 2490 else if (IS_I830(dev) || IS_845G(dev)) 2491 ring->dispatch_execbuffer = i830_dispatch_execbuffer; 2492 else 2493 ring->dispatch_execbuffer = i915_dispatch_execbuffer; 2494 ring->init_hw = init_render_ring; 2495 ring->cleanup = render_ring_cleanup; 2496 2497 /* Workaround batchbuffer to combat CS tlb bug. */ 2498 if (HAS_BROKEN_CS_TLB(dev)) { 2499 obj = i915_gem_alloc_object(dev, I830_WA_SIZE); 2500 if (obj == NULL) { 2501 DRM_ERROR("Failed to allocate batch bo\n"); 2502 return -ENOMEM; 2503 } 2504 2505 ret = i915_gem_obj_ggtt_pin(obj, 0, 0); 2506 if (ret != 0) { 2507 drm_gem_object_unreference(&obj->base); 2508 DRM_ERROR("Failed to ping batch bo\n"); 2509 return ret; 2510 } 2511 2512 ring->scratch.obj = obj; 2513 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); 2514 } 2515 2516 ret = intel_init_ring_buffer(dev, ring); 2517 if (ret) 2518 return ret; 2519 2520 if (INTEL_INFO(dev)->gen >= 5) { 2521 ret = intel_init_pipe_control(ring); 2522 if (ret) 2523 return ret; 2524 } 2525 2526 return 0; 2527 } 2528 2529 int intel_init_bsd_ring_buffer(struct drm_device *dev) 2530 { 2531 struct drm_i915_private *dev_priv = dev->dev_private; 2532 struct intel_engine_cs *ring = &dev_priv->ring[VCS]; 2533 2534 ring->name = "bsd ring"; 2535 ring->id = VCS; 2536 2537 ring->write_tail = ring_write_tail; 2538 if (INTEL_INFO(dev)->gen >= 6) { 2539 ring->mmio_base = GEN6_BSD_RING_BASE; 2540 /* gen6 bsd needs a special wa for tail updates */ 2541 if (IS_GEN6(dev)) 2542 ring->write_tail = gen6_bsd_ring_write_tail; 2543 ring->flush = gen6_bsd_ring_flush; 2544 ring->add_request = gen6_add_request; 2545 ring->get_seqno = gen6_ring_get_seqno; 2546 ring->set_seqno = ring_set_seqno; 2547 if (INTEL_INFO(dev)->gen >= 8) { 2548 ring->irq_enable_mask = 2549 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; 2550 ring->irq_get = gen8_ring_get_irq; 2551 ring->irq_put = gen8_ring_put_irq; 2552 ring->dispatch_execbuffer = 2553 gen8_ring_dispatch_execbuffer; 2554 if (i915_semaphore_is_enabled(dev)) { 2555 ring->semaphore.sync_to = gen8_ring_sync; 2556 ring->semaphore.signal = gen8_xcs_signal; 2557 GEN8_RING_SEMAPHORE_INIT; 2558 } 2559 } else { 2560 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; 2561 ring->irq_get = gen6_ring_get_irq; 2562 ring->irq_put = gen6_ring_put_irq; 2563 ring->dispatch_execbuffer = 2564 gen6_ring_dispatch_execbuffer; 2565 if (i915_semaphore_is_enabled(dev)) { 2566 ring->semaphore.sync_to = gen6_ring_sync; 2567 ring->semaphore.signal = gen6_signal; 2568 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; 2569 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; 2570 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; 2571 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; 2572 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; 2573 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; 2574 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; 2575 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; 2576 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; 2577 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; 2578 } 2579 } 2580 } else { 2581 ring->mmio_base = BSD_RING_BASE; 2582 ring->flush = bsd_ring_flush; 2583 ring->add_request = i9xx_add_request; 2584 ring->get_seqno = ring_get_seqno; 2585 ring->set_seqno = ring_set_seqno; 2586 if (IS_GEN5(dev)) { 2587 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; 2588 ring->irq_get = gen5_ring_get_irq; 2589 ring->irq_put = gen5_ring_put_irq; 2590 } else { 2591 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; 2592 ring->irq_get = i9xx_ring_get_irq; 2593 ring->irq_put = i9xx_ring_put_irq; 2594 } 2595 ring->dispatch_execbuffer = i965_dispatch_execbuffer; 2596 } 2597 ring->init_hw = init_ring_common; 2598 2599 return intel_init_ring_buffer(dev, ring); 2600 } 2601 2602 /** 2603 * Initialize the second BSD ring for Broadwell GT3. 2604 * It is noted that this only exists on Broadwell GT3. 2605 */ 2606 int intel_init_bsd2_ring_buffer(struct drm_device *dev) 2607 { 2608 struct drm_i915_private *dev_priv = dev->dev_private; 2609 struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; 2610 2611 if ((INTEL_INFO(dev)->gen != 8)) { 2612 DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); 2613 return -EINVAL; 2614 } 2615 2616 ring->name = "bsd2 ring"; 2617 ring->id = VCS2; 2618 2619 ring->write_tail = ring_write_tail; 2620 ring->mmio_base = GEN8_BSD2_RING_BASE; 2621 ring->flush = gen6_bsd_ring_flush; 2622 ring->add_request = gen6_add_request; 2623 ring->get_seqno = gen6_ring_get_seqno; 2624 ring->set_seqno = ring_set_seqno; 2625 ring->irq_enable_mask = 2626 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; 2627 ring->irq_get = gen8_ring_get_irq; 2628 ring->irq_put = gen8_ring_put_irq; 2629 ring->dispatch_execbuffer = 2630 gen8_ring_dispatch_execbuffer; 2631 if (i915_semaphore_is_enabled(dev)) { 2632 ring->semaphore.sync_to = gen8_ring_sync; 2633 ring->semaphore.signal = gen8_xcs_signal; 2634 GEN8_RING_SEMAPHORE_INIT; 2635 } 2636 ring->init_hw = init_ring_common; 2637 2638 return intel_init_ring_buffer(dev, ring); 2639 } 2640 2641 int intel_init_blt_ring_buffer(struct drm_device *dev) 2642 { 2643 struct drm_i915_private *dev_priv = dev->dev_private; 2644 struct intel_engine_cs *ring = &dev_priv->ring[BCS]; 2645 2646 ring->name = "blitter ring"; 2647 ring->id = BCS; 2648 2649 ring->mmio_base = BLT_RING_BASE; 2650 ring->write_tail = ring_write_tail; 2651 ring->flush = gen6_ring_flush; 2652 ring->add_request = gen6_add_request; 2653 ring->get_seqno = gen6_ring_get_seqno; 2654 ring->set_seqno = ring_set_seqno; 2655 if (INTEL_INFO(dev)->gen >= 8) { 2656 ring->irq_enable_mask = 2657 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 2658 ring->irq_get = gen8_ring_get_irq; 2659 ring->irq_put = gen8_ring_put_irq; 2660 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; 2661 if (i915_semaphore_is_enabled(dev)) { 2662 ring->semaphore.sync_to = gen8_ring_sync; 2663 ring->semaphore.signal = gen8_xcs_signal; 2664 GEN8_RING_SEMAPHORE_INIT; 2665 } 2666 } else { 2667 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; 2668 ring->irq_get = gen6_ring_get_irq; 2669 ring->irq_put = gen6_ring_put_irq; 2670 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; 2671 if (i915_semaphore_is_enabled(dev)) { 2672 ring->semaphore.signal = gen6_signal; 2673 ring->semaphore.sync_to = gen6_ring_sync; 2674 /* 2675 * The current semaphore is only applied on pre-gen8 2676 * platform. And there is no VCS2 ring on the pre-gen8 2677 * platform. So the semaphore between BCS and VCS2 is 2678 * initialized as INVALID. Gen8 will initialize the 2679 * sema between BCS and VCS2 later. 2680 */ 2681 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; 2682 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; 2683 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; 2684 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; 2685 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; 2686 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; 2687 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; 2688 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; 2689 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; 2690 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; 2691 } 2692 } 2693 ring->init_hw = init_ring_common; 2694 2695 return intel_init_ring_buffer(dev, ring); 2696 } 2697 2698 int intel_init_vebox_ring_buffer(struct drm_device *dev) 2699 { 2700 struct drm_i915_private *dev_priv = dev->dev_private; 2701 struct intel_engine_cs *ring = &dev_priv->ring[VECS]; 2702 2703 ring->name = "video enhancement ring"; 2704 ring->id = VECS; 2705 2706 ring->mmio_base = VEBOX_RING_BASE; 2707 ring->write_tail = ring_write_tail; 2708 ring->flush = gen6_ring_flush; 2709 ring->add_request = gen6_add_request; 2710 ring->get_seqno = gen6_ring_get_seqno; 2711 ring->set_seqno = ring_set_seqno; 2712 2713 if (INTEL_INFO(dev)->gen >= 8) { 2714 ring->irq_enable_mask = 2715 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; 2716 ring->irq_get = gen8_ring_get_irq; 2717 ring->irq_put = gen8_ring_put_irq; 2718 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; 2719 if (i915_semaphore_is_enabled(dev)) { 2720 ring->semaphore.sync_to = gen8_ring_sync; 2721 ring->semaphore.signal = gen8_xcs_signal; 2722 GEN8_RING_SEMAPHORE_INIT; 2723 } 2724 } else { 2725 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; 2726 ring->irq_get = hsw_vebox_get_irq; 2727 ring->irq_put = hsw_vebox_put_irq; 2728 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; 2729 if (i915_semaphore_is_enabled(dev)) { 2730 ring->semaphore.sync_to = gen6_ring_sync; 2731 ring->semaphore.signal = gen6_signal; 2732 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; 2733 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; 2734 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; 2735 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; 2736 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; 2737 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; 2738 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; 2739 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; 2740 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; 2741 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; 2742 } 2743 } 2744 ring->init_hw = init_ring_common; 2745 2746 return intel_init_ring_buffer(dev, ring); 2747 } 2748 2749 int 2750 intel_ring_flush_all_caches(struct intel_engine_cs *ring) 2751 { 2752 int ret; 2753 2754 if (!ring->gpu_caches_dirty) 2755 return 0; 2756 2757 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); 2758 if (ret) 2759 return ret; 2760 2761 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); 2762 2763 ring->gpu_caches_dirty = false; 2764 return 0; 2765 } 2766 2767 int 2768 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) 2769 { 2770 uint32_t flush_domains; 2771 int ret; 2772 2773 flush_domains = 0; 2774 if (ring->gpu_caches_dirty) 2775 flush_domains = I915_GEM_GPU_DOMAINS; 2776 2777 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); 2778 if (ret) 2779 return ret; 2780 2781 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); 2782 2783 ring->gpu_caches_dirty = false; 2784 return 0; 2785 } 2786 2787 void 2788 intel_stop_ring_buffer(struct intel_engine_cs *ring) 2789 { 2790 int ret; 2791 2792 if (!intel_ring_initialized(ring)) 2793 return; 2794 2795 ret = intel_ring_idle(ring); 2796 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) 2797 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", 2798 ring->name, ret); 2799 2800 stop_ring(ring); 2801 } 2802