1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include "i915_drv.h" 30 #include "intel_drv.h" 31 32 /** 33 * DOC: runtime pm 34 * 35 * The i915 driver supports dynamic enabling and disabling of entire hardware 36 * blocks at runtime. This is especially important on the display side where 37 * software is supposed to control many power gates manually on recent hardware, 38 * since on the GT side a lot of the power management is done by the hardware. 39 * But even there some manual control at the device level is required. 40 * 41 * Since i915 supports a diverse set of platforms with a unified codebase and 42 * hardware engineers just love to shuffle functionality around between power 43 * domains there's a sizeable amount of indirection required. This file provides 44 * generic functions to the driver for grabbing and releasing references for 45 * abstract power domains. It then maps those to the actual power wells 46 * present for a given platform. 47 */ 48 49 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 50 for (i = 0; \ 51 i < (power_domains)->power_well_count && \ 52 ((power_well) = &(power_domains)->power_wells[i]); \ 53 i++) \ 54 if ((power_well)->domains & (domain_mask)) 55 56 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 57 for (i = (power_domains)->power_well_count - 1; \ 58 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 59 i--) \ 60 if ((power_well)->domains & (domain_mask)) 61 62 /* 63 * We should only use the power well if we explicitly asked the hardware to 64 * enable it, so check if it's enabled and also check if we've requested it to 65 * be enabled. 66 */ 67 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 68 struct i915_power_well *power_well) 69 { 70 return I915_READ(HSW_PWR_WELL_DRIVER) == 71 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 72 } 73 74 /** 75 * __intel_display_power_is_enabled - unlocked check for a power domain 76 * @dev_priv: i915 device instance 77 * @domain: power domain to check 78 * 79 * This is the unlocked version of intel_display_power_is_enabled() and should 80 * only be used from error capture and recovery code where deadlocks are 81 * possible. 82 * 83 * Returns: 84 * True when the power domain is enabled, false otherwise. 85 */ 86 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 87 enum intel_display_power_domain domain) 88 { 89 struct i915_power_domains *power_domains; 90 struct i915_power_well *power_well; 91 bool is_enabled; 92 int i; 93 94 if (dev_priv->pm.suspended) 95 return false; 96 97 power_domains = &dev_priv->power_domains; 98 99 is_enabled = true; 100 101 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 102 if (power_well->always_on) 103 continue; 104 105 if (!power_well->hw_enabled) { 106 is_enabled = false; 107 break; 108 } 109 } 110 111 return is_enabled; 112 } 113 114 /** 115 * intel_display_power_is_enabled - check for a power domain 116 * @dev_priv: i915 device instance 117 * @domain: power domain to check 118 * 119 * This function can be used to check the hw power domain state. It is mostly 120 * used in hardware state readout functions. Everywhere else code should rely 121 * upon explicit power domain reference counting to ensure that the hardware 122 * block is powered up before accessing it. 123 * 124 * Callers must hold the relevant modesetting locks to ensure that concurrent 125 * threads can't disable the power well while the caller tries to read a few 126 * registers. 127 * 128 * Returns: 129 * True when the power domain is enabled, false otherwise. 130 */ 131 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 132 enum intel_display_power_domain domain) 133 { 134 struct i915_power_domains *power_domains; 135 bool ret; 136 137 power_domains = &dev_priv->power_domains; 138 139 mutex_lock(&power_domains->lock); 140 ret = __intel_display_power_is_enabled(dev_priv, domain); 141 mutex_unlock(&power_domains->lock); 142 143 return ret; 144 } 145 146 /** 147 * intel_display_set_init_power - set the initial power domain state 148 * @dev_priv: i915 device instance 149 * @enable: whether to enable or disable the initial power domain state 150 * 151 * For simplicity our driver load/unload and system suspend/resume code assumes 152 * that all power domains are always enabled. This functions controls the state 153 * of this little hack. While the initial power domain state is enabled runtime 154 * pm is effectively disabled. 155 */ 156 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 157 bool enable) 158 { 159 if (dev_priv->power_domains.init_power_on == enable) 160 return; 161 162 if (enable) 163 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 164 else 165 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 166 167 dev_priv->power_domains.init_power_on = enable; 168 } 169 170 /* 171 * Starting with Haswell, we have a "Power Down Well" that can be turned off 172 * when not needed anymore. We have 4 registers that can request the power well 173 * to be enabled, and it will only be disabled if none of the registers is 174 * requesting it to be enabled. 175 */ 176 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 177 { 178 struct drm_device *dev = dev_priv->dev; 179 180 /* 181 * After we re-enable the power well, if we touch VGA register 0x3d5 182 * we'll get unclaimed register interrupts. This stops after we write 183 * anything to the VGA MSR register. The vgacon module uses this 184 * register all the time, so if we unbind our driver and, as a 185 * consequence, bind vgacon, we'll get stuck in an infinite loop at 186 * console_unlock(). So make here we touch the VGA MSR register, making 187 * sure vgacon can keep working normally without triggering interrupts 188 * and error messages. 189 */ 190 #if 0 191 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 192 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 193 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 194 #endif 195 196 if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) 197 gen8_irq_power_well_post_enable(dev_priv); 198 } 199 200 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 201 struct i915_power_well *power_well, bool enable) 202 { 203 bool is_enabled, enable_requested; 204 uint32_t tmp; 205 206 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 207 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 208 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 209 210 if (enable) { 211 if (!enable_requested) 212 I915_WRITE(HSW_PWR_WELL_DRIVER, 213 HSW_PWR_WELL_ENABLE_REQUEST); 214 215 if (!is_enabled) { 216 DRM_DEBUG_KMS("Enabling power well\n"); 217 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 218 HSW_PWR_WELL_STATE_ENABLED), 20)) 219 DRM_ERROR("Timeout enabling power well\n"); 220 hsw_power_well_post_enable(dev_priv); 221 } 222 223 } else { 224 if (enable_requested) { 225 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 226 POSTING_READ(HSW_PWR_WELL_DRIVER); 227 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 228 } 229 } 230 } 231 232 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 233 struct i915_power_well *power_well) 234 { 235 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 236 237 /* 238 * We're taking over the BIOS, so clear any requests made by it since 239 * the driver is in charge now. 240 */ 241 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 242 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 243 } 244 245 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 246 struct i915_power_well *power_well) 247 { 248 hsw_set_power_well(dev_priv, power_well, true); 249 } 250 251 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 252 struct i915_power_well *power_well) 253 { 254 hsw_set_power_well(dev_priv, power_well, false); 255 } 256 257 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 258 struct i915_power_well *power_well) 259 { 260 } 261 262 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 263 struct i915_power_well *power_well) 264 { 265 return true; 266 } 267 268 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 269 struct i915_power_well *power_well, bool enable) 270 { 271 enum punit_power_well power_well_id = power_well->data; 272 u32 mask; 273 u32 state; 274 u32 ctrl; 275 276 mask = PUNIT_PWRGT_MASK(power_well_id); 277 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 278 PUNIT_PWRGT_PWR_GATE(power_well_id); 279 280 mutex_lock(&dev_priv->rps.hw_lock); 281 282 #define COND \ 283 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 284 285 if (COND) 286 goto out; 287 288 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 289 ctrl &= ~mask; 290 ctrl |= state; 291 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 292 293 if (wait_for(COND, 100)) 294 DRM_ERROR("timout setting power well state %08x (%08x)\n", 295 state, 296 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 297 298 #undef COND 299 300 out: 301 mutex_unlock(&dev_priv->rps.hw_lock); 302 } 303 304 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 305 struct i915_power_well *power_well) 306 { 307 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 308 } 309 310 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 311 struct i915_power_well *power_well) 312 { 313 vlv_set_power_well(dev_priv, power_well, true); 314 } 315 316 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 317 struct i915_power_well *power_well) 318 { 319 vlv_set_power_well(dev_priv, power_well, false); 320 } 321 322 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 323 struct i915_power_well *power_well) 324 { 325 int power_well_id = power_well->data; 326 bool enabled = false; 327 u32 mask; 328 u32 state; 329 u32 ctrl; 330 331 mask = PUNIT_PWRGT_MASK(power_well_id); 332 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 333 334 mutex_lock(&dev_priv->rps.hw_lock); 335 336 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 337 /* 338 * We only ever set the power-on and power-gate states, anything 339 * else is unexpected. 340 */ 341 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 342 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 343 if (state == ctrl) 344 enabled = true; 345 346 /* 347 * A transient state at this point would mean some unexpected party 348 * is poking at the power controls too. 349 */ 350 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 351 WARN_ON(ctrl != state); 352 353 mutex_unlock(&dev_priv->rps.hw_lock); 354 355 return enabled; 356 } 357 358 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 359 struct i915_power_well *power_well) 360 { 361 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 362 363 vlv_set_power_well(dev_priv, power_well, true); 364 365 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 366 valleyview_enable_display_irqs(dev_priv); 367 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 368 369 /* 370 * During driver initialization/resume we can avoid restoring the 371 * part of the HW/SW state that will be inited anyway explicitly. 372 */ 373 if (dev_priv->power_domains.initializing) 374 return; 375 376 intel_hpd_init(dev_priv); 377 378 i915_redisable_vga_power_on(dev_priv->dev); 379 } 380 381 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 382 struct i915_power_well *power_well) 383 { 384 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 385 386 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 387 valleyview_disable_display_irqs(dev_priv); 388 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 389 390 vlv_set_power_well(dev_priv, power_well, false); 391 392 vlv_power_sequencer_reset(dev_priv); 393 } 394 395 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 396 struct i915_power_well *power_well) 397 { 398 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 399 400 /* 401 * Enable the CRI clock source so we can get at the 402 * display and the reference clock for VGA 403 * hotplug / manual detection. 404 */ 405 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | 406 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); 407 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 408 409 vlv_set_power_well(dev_priv, power_well, true); 410 411 /* 412 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 413 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 414 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 415 * b. The other bits such as sfr settings / modesel may all 416 * be set to 0. 417 * 418 * This should only be done on init and resume from S3 with 419 * both PLLs disabled, or we risk losing DPIO and PLL 420 * synchronization. 421 */ 422 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 423 } 424 425 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 426 struct i915_power_well *power_well) 427 { 428 enum i915_pipe pipe; 429 430 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 431 432 for_each_pipe(dev_priv, pipe) 433 assert_pll_disabled(dev_priv, pipe); 434 435 /* Assert common reset */ 436 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 437 438 vlv_set_power_well(dev_priv, power_well, false); 439 } 440 441 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 442 struct i915_power_well *power_well) 443 { 444 enum dpio_phy phy; 445 446 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 447 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 448 449 /* 450 * Enable the CRI clock source so we can get at the 451 * display and the reference clock for VGA 452 * hotplug / manual detection. 453 */ 454 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 455 phy = DPIO_PHY0; 456 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | 457 DPLL_REFA_CLK_ENABLE_VLV); 458 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | 459 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); 460 } else { 461 phy = DPIO_PHY1; 462 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | 463 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); 464 } 465 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 466 vlv_set_power_well(dev_priv, power_well, true); 467 468 /* Poll for phypwrgood signal */ 469 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) 470 DRM_ERROR("Display PHY %d is not power up\n", phy); 471 472 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) | 473 PHY_COM_LANE_RESET_DEASSERT(phy)); 474 } 475 476 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 477 struct i915_power_well *power_well) 478 { 479 enum dpio_phy phy; 480 481 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 482 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 483 484 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 485 phy = DPIO_PHY0; 486 assert_pll_disabled(dev_priv, PIPE_A); 487 assert_pll_disabled(dev_priv, PIPE_B); 488 } else { 489 phy = DPIO_PHY1; 490 assert_pll_disabled(dev_priv, PIPE_C); 491 } 492 493 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) & 494 ~PHY_COM_LANE_RESET_DEASSERT(phy)); 495 496 vlv_set_power_well(dev_priv, power_well, false); 497 } 498 499 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 500 struct i915_power_well *power_well) 501 { 502 enum i915_pipe pipe = power_well->data; 503 bool enabled; 504 u32 state, ctrl; 505 506 mutex_lock(&dev_priv->rps.hw_lock); 507 508 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 509 /* 510 * We only ever set the power-on and power-gate states, anything 511 * else is unexpected. 512 */ 513 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 514 enabled = state == DP_SSS_PWR_ON(pipe); 515 516 /* 517 * A transient state at this point would mean some unexpected party 518 * is poking at the power controls too. 519 */ 520 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 521 WARN_ON(ctrl << 16 != state); 522 523 mutex_unlock(&dev_priv->rps.hw_lock); 524 525 return enabled; 526 } 527 528 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 529 struct i915_power_well *power_well, 530 bool enable) 531 { 532 enum i915_pipe pipe = power_well->data; 533 u32 state; 534 u32 ctrl; 535 536 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 537 538 mutex_lock(&dev_priv->rps.hw_lock); 539 540 #define COND \ 541 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 542 543 if (COND) 544 goto out; 545 546 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 547 ctrl &= ~DP_SSC_MASK(pipe); 548 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 549 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 550 551 if (wait_for(COND, 100)) 552 DRM_ERROR("timout setting power well state %08x (%08x)\n", 553 state, 554 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 555 556 #undef COND 557 558 out: 559 mutex_unlock(&dev_priv->rps.hw_lock); 560 } 561 562 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 563 struct i915_power_well *power_well) 564 { 565 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 566 } 567 568 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 569 struct i915_power_well *power_well) 570 { 571 WARN_ON_ONCE(power_well->data != PIPE_A && 572 power_well->data != PIPE_B && 573 power_well->data != PIPE_C); 574 575 chv_set_pipe_power_well(dev_priv, power_well, true); 576 577 if (power_well->data == PIPE_A) { 578 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 579 valleyview_enable_display_irqs(dev_priv); 580 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 581 582 /* 583 * During driver initialization/resume we can avoid restoring the 584 * part of the HW/SW state that will be inited anyway explicitly. 585 */ 586 if (dev_priv->power_domains.initializing) 587 return; 588 589 intel_hpd_init(dev_priv); 590 591 i915_redisable_vga_power_on(dev_priv->dev); 592 } 593 } 594 595 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 596 struct i915_power_well *power_well) 597 { 598 WARN_ON_ONCE(power_well->data != PIPE_A && 599 power_well->data != PIPE_B && 600 power_well->data != PIPE_C); 601 602 if (power_well->data == PIPE_A) { 603 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 604 valleyview_disable_display_irqs(dev_priv); 605 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 606 } 607 608 chv_set_pipe_power_well(dev_priv, power_well, false); 609 610 if (power_well->data == PIPE_A) 611 vlv_power_sequencer_reset(dev_priv); 612 } 613 614 /** 615 * intel_display_power_get - grab a power domain reference 616 * @dev_priv: i915 device instance 617 * @domain: power domain to reference 618 * 619 * This function grabs a power domain reference for @domain and ensures that the 620 * power domain and all its parents are powered up. Therefore users should only 621 * grab a reference to the innermost power domain they need. 622 * 623 * Any power domain reference obtained by this function must have a symmetric 624 * call to intel_display_power_put() to release the reference again. 625 */ 626 void intel_display_power_get(struct drm_i915_private *dev_priv, 627 enum intel_display_power_domain domain) 628 { 629 struct i915_power_domains *power_domains; 630 struct i915_power_well *power_well; 631 int i; 632 633 intel_runtime_pm_get(dev_priv); 634 635 power_domains = &dev_priv->power_domains; 636 637 mutex_lock(&power_domains->lock); 638 639 for_each_power_well(i, power_well, BIT(domain), power_domains) { 640 if (!power_well->count++) { 641 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 642 power_well->ops->enable(dev_priv, power_well); 643 power_well->hw_enabled = true; 644 } 645 } 646 647 power_domains->domain_use_count[domain]++; 648 649 mutex_unlock(&power_domains->lock); 650 } 651 652 /** 653 * intel_display_power_put - release a power domain reference 654 * @dev_priv: i915 device instance 655 * @domain: power domain to reference 656 * 657 * This function drops the power domain reference obtained by 658 * intel_display_power_get() and might power down the corresponding hardware 659 * block right away if this is the last reference. 660 */ 661 void intel_display_power_put(struct drm_i915_private *dev_priv, 662 enum intel_display_power_domain domain) 663 { 664 struct i915_power_domains *power_domains; 665 struct i915_power_well *power_well; 666 int i; 667 668 power_domains = &dev_priv->power_domains; 669 670 mutex_lock(&power_domains->lock); 671 672 WARN_ON(!power_domains->domain_use_count[domain]); 673 power_domains->domain_use_count[domain]--; 674 675 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 676 WARN_ON(!power_well->count); 677 678 if (!--power_well->count && i915.disable_power_well) { 679 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 680 power_well->hw_enabled = false; 681 power_well->ops->disable(dev_priv, power_well); 682 } 683 } 684 685 mutex_unlock(&power_domains->lock); 686 687 intel_runtime_pm_put(dev_priv); 688 } 689 690 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 691 692 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 693 BIT(POWER_DOMAIN_PIPE_A) | \ 694 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 695 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ 696 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ 697 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 698 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 699 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 700 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 701 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 702 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 703 BIT(POWER_DOMAIN_PORT_CRT) | \ 704 BIT(POWER_DOMAIN_PLLS) | \ 705 BIT(POWER_DOMAIN_AUX_A) | \ 706 BIT(POWER_DOMAIN_AUX_B) | \ 707 BIT(POWER_DOMAIN_AUX_C) | \ 708 BIT(POWER_DOMAIN_AUX_D) | \ 709 BIT(POWER_DOMAIN_INIT)) 710 #define HSW_DISPLAY_POWER_DOMAINS ( \ 711 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 712 BIT(POWER_DOMAIN_INIT)) 713 714 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 715 HSW_ALWAYS_ON_POWER_DOMAINS | \ 716 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 717 #define BDW_DISPLAY_POWER_DOMAINS ( \ 718 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 719 BIT(POWER_DOMAIN_INIT)) 720 721 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) 722 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK 723 724 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 725 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 726 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 727 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 728 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 729 BIT(POWER_DOMAIN_PORT_CRT) | \ 730 BIT(POWER_DOMAIN_AUX_B) | \ 731 BIT(POWER_DOMAIN_AUX_C) | \ 732 BIT(POWER_DOMAIN_INIT)) 733 734 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 735 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 736 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 737 BIT(POWER_DOMAIN_AUX_B) | \ 738 BIT(POWER_DOMAIN_INIT)) 739 740 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 741 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 742 BIT(POWER_DOMAIN_AUX_B) | \ 743 BIT(POWER_DOMAIN_INIT)) 744 745 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 746 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 747 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 748 BIT(POWER_DOMAIN_AUX_C) | \ 749 BIT(POWER_DOMAIN_INIT)) 750 751 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 752 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 753 BIT(POWER_DOMAIN_AUX_C) | \ 754 BIT(POWER_DOMAIN_INIT)) 755 756 #define CHV_PIPE_A_POWER_DOMAINS ( \ 757 BIT(POWER_DOMAIN_PIPE_A) | \ 758 BIT(POWER_DOMAIN_INIT)) 759 760 #define CHV_PIPE_B_POWER_DOMAINS ( \ 761 BIT(POWER_DOMAIN_PIPE_B) | \ 762 BIT(POWER_DOMAIN_INIT)) 763 764 #define CHV_PIPE_C_POWER_DOMAINS ( \ 765 BIT(POWER_DOMAIN_PIPE_C) | \ 766 BIT(POWER_DOMAIN_INIT)) 767 768 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 769 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 770 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 771 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 772 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 773 BIT(POWER_DOMAIN_AUX_B) | \ 774 BIT(POWER_DOMAIN_AUX_C) | \ 775 BIT(POWER_DOMAIN_INIT)) 776 777 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 778 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 779 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 780 BIT(POWER_DOMAIN_AUX_D) | \ 781 BIT(POWER_DOMAIN_INIT)) 782 783 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ 784 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 785 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 786 BIT(POWER_DOMAIN_AUX_D) | \ 787 BIT(POWER_DOMAIN_INIT)) 788 789 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ 790 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 791 BIT(POWER_DOMAIN_AUX_D) | \ 792 BIT(POWER_DOMAIN_INIT)) 793 794 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 795 .sync_hw = i9xx_always_on_power_well_noop, 796 .enable = i9xx_always_on_power_well_noop, 797 .disable = i9xx_always_on_power_well_noop, 798 .is_enabled = i9xx_always_on_power_well_enabled, 799 }; 800 801 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 802 .sync_hw = chv_pipe_power_well_sync_hw, 803 .enable = chv_pipe_power_well_enable, 804 .disable = chv_pipe_power_well_disable, 805 .is_enabled = chv_pipe_power_well_enabled, 806 }; 807 808 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 809 .sync_hw = vlv_power_well_sync_hw, 810 .enable = chv_dpio_cmn_power_well_enable, 811 .disable = chv_dpio_cmn_power_well_disable, 812 .is_enabled = vlv_power_well_enabled, 813 }; 814 815 static struct i915_power_well i9xx_always_on_power_well[] = { 816 { 817 .name = "always-on", 818 .always_on = 1, 819 .domains = POWER_DOMAIN_MASK, 820 .ops = &i9xx_always_on_power_well_ops, 821 }, 822 }; 823 824 static const struct i915_power_well_ops hsw_power_well_ops = { 825 .sync_hw = hsw_power_well_sync_hw, 826 .enable = hsw_power_well_enable, 827 .disable = hsw_power_well_disable, 828 .is_enabled = hsw_power_well_enabled, 829 }; 830 831 static struct i915_power_well hsw_power_wells[] = { 832 { 833 .name = "always-on", 834 .always_on = 1, 835 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 836 .ops = &i9xx_always_on_power_well_ops, 837 }, 838 { 839 .name = "display", 840 .domains = HSW_DISPLAY_POWER_DOMAINS, 841 .ops = &hsw_power_well_ops, 842 }, 843 }; 844 845 static struct i915_power_well bdw_power_wells[] = { 846 { 847 .name = "always-on", 848 .always_on = 1, 849 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 850 .ops = &i9xx_always_on_power_well_ops, 851 }, 852 { 853 .name = "display", 854 .domains = BDW_DISPLAY_POWER_DOMAINS, 855 .ops = &hsw_power_well_ops, 856 }, 857 }; 858 859 static const struct i915_power_well_ops vlv_display_power_well_ops = { 860 .sync_hw = vlv_power_well_sync_hw, 861 .enable = vlv_display_power_well_enable, 862 .disable = vlv_display_power_well_disable, 863 .is_enabled = vlv_power_well_enabled, 864 }; 865 866 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 867 .sync_hw = vlv_power_well_sync_hw, 868 .enable = vlv_dpio_cmn_power_well_enable, 869 .disable = vlv_dpio_cmn_power_well_disable, 870 .is_enabled = vlv_power_well_enabled, 871 }; 872 873 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 874 .sync_hw = vlv_power_well_sync_hw, 875 .enable = vlv_power_well_enable, 876 .disable = vlv_power_well_disable, 877 .is_enabled = vlv_power_well_enabled, 878 }; 879 880 static struct i915_power_well vlv_power_wells[] = { 881 { 882 .name = "always-on", 883 .always_on = 1, 884 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 885 .ops = &i9xx_always_on_power_well_ops, 886 }, 887 { 888 .name = "display", 889 .domains = VLV_DISPLAY_POWER_DOMAINS, 890 .data = PUNIT_POWER_WELL_DISP2D, 891 .ops = &vlv_display_power_well_ops, 892 }, 893 { 894 .name = "dpio-tx-b-01", 895 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 896 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 897 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 898 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 899 .ops = &vlv_dpio_power_well_ops, 900 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 901 }, 902 { 903 .name = "dpio-tx-b-23", 904 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 905 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 906 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 907 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 908 .ops = &vlv_dpio_power_well_ops, 909 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 910 }, 911 { 912 .name = "dpio-tx-c-01", 913 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 914 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 915 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 916 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 917 .ops = &vlv_dpio_power_well_ops, 918 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 919 }, 920 { 921 .name = "dpio-tx-c-23", 922 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 923 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 924 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 925 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 926 .ops = &vlv_dpio_power_well_ops, 927 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 928 }, 929 { 930 .name = "dpio-common", 931 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 932 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 933 .ops = &vlv_dpio_cmn_power_well_ops, 934 }, 935 }; 936 937 static struct i915_power_well chv_power_wells[] = { 938 { 939 .name = "always-on", 940 .always_on = 1, 941 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 942 .ops = &i9xx_always_on_power_well_ops, 943 }, 944 #if 0 945 { 946 .name = "display", 947 .domains = VLV_DISPLAY_POWER_DOMAINS, 948 .data = PUNIT_POWER_WELL_DISP2D, 949 .ops = &vlv_display_power_well_ops, 950 }, 951 #endif 952 { 953 .name = "pipe-a", 954 /* 955 * FIXME: pipe A power well seems to be the new disp2d well. 956 * At least all registers seem to be housed there. Figure 957 * out if this a a temporary situation in pre-production 958 * hardware or a permanent state of affairs. 959 */ 960 .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, 961 .data = PIPE_A, 962 .ops = &chv_pipe_power_well_ops, 963 }, 964 #if 0 965 { 966 .name = "pipe-b", 967 .domains = CHV_PIPE_B_POWER_DOMAINS, 968 .data = PIPE_B, 969 .ops = &chv_pipe_power_well_ops, 970 }, 971 { 972 .name = "pipe-c", 973 .domains = CHV_PIPE_C_POWER_DOMAINS, 974 .data = PIPE_C, 975 .ops = &chv_pipe_power_well_ops, 976 }, 977 #endif 978 { 979 .name = "dpio-common-bc", 980 /* 981 * XXX: cmnreset for one PHY seems to disturb the other. 982 * As a workaround keep both powered on at the same 983 * time for now. 984 */ 985 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, 986 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 987 .ops = &chv_dpio_cmn_power_well_ops, 988 }, 989 { 990 .name = "dpio-common-d", 991 /* 992 * XXX: cmnreset for one PHY seems to disturb the other. 993 * As a workaround keep both powered on at the same 994 * time for now. 995 */ 996 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, 997 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 998 .ops = &chv_dpio_cmn_power_well_ops, 999 }, 1000 #if 0 1001 { 1002 .name = "dpio-tx-b-01", 1003 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1004 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, 1005 .ops = &vlv_dpio_power_well_ops, 1006 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 1007 }, 1008 { 1009 .name = "dpio-tx-b-23", 1010 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1011 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, 1012 .ops = &vlv_dpio_power_well_ops, 1013 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 1014 }, 1015 { 1016 .name = "dpio-tx-c-01", 1017 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1018 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1019 .ops = &vlv_dpio_power_well_ops, 1020 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 1021 }, 1022 { 1023 .name = "dpio-tx-c-23", 1024 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1025 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1026 .ops = &vlv_dpio_power_well_ops, 1027 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 1028 }, 1029 { 1030 .name = "dpio-tx-d-01", 1031 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | 1032 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, 1033 .ops = &vlv_dpio_power_well_ops, 1034 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, 1035 }, 1036 { 1037 .name = "dpio-tx-d-23", 1038 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | 1039 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, 1040 .ops = &vlv_dpio_power_well_ops, 1041 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, 1042 }, 1043 #endif 1044 }; 1045 1046 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1047 enum punit_power_well power_well_id) 1048 { 1049 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1050 struct i915_power_well *power_well; 1051 int i; 1052 1053 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 1054 if (power_well->data == power_well_id) 1055 return power_well; 1056 } 1057 1058 return NULL; 1059 } 1060 1061 #define set_power_wells(power_domains, __power_wells) ({ \ 1062 (power_domains)->power_wells = (__power_wells); \ 1063 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 1064 }) 1065 1066 /** 1067 * intel_power_domains_init - initializes the power domain structures 1068 * @dev_priv: i915 device instance 1069 * 1070 * Initializes the power domain structures for @dev_priv depending upon the 1071 * supported platform. 1072 */ 1073 int intel_power_domains_init(struct drm_i915_private *dev_priv) 1074 { 1075 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1076 1077 lockinit(&power_domains->lock, "i915pl", 0, LK_CANRECURSE); 1078 1079 /* 1080 * The enabling order will be from lower to higher indexed wells, 1081 * the disabling order is reversed. 1082 */ 1083 if (IS_HASWELL(dev_priv->dev)) { 1084 set_power_wells(power_domains, hsw_power_wells); 1085 } else if (IS_BROADWELL(dev_priv->dev)) { 1086 set_power_wells(power_domains, bdw_power_wells); 1087 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 1088 set_power_wells(power_domains, chv_power_wells); 1089 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 1090 set_power_wells(power_domains, vlv_power_wells); 1091 } else { 1092 set_power_wells(power_domains, i9xx_always_on_power_well); 1093 } 1094 1095 return 0; 1096 } 1097 1098 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) 1099 { 1100 #if 0 1101 struct drm_device *dev = dev_priv->dev; 1102 struct device *device = &dev->pdev->dev; 1103 1104 if (!HAS_RUNTIME_PM(dev)) 1105 return; 1106 1107 if (!intel_enable_rc6(dev)) 1108 return; 1109 1110 /* Make sure we're not suspended first. */ 1111 pm_runtime_get_sync(device); 1112 pm_runtime_disable(device); 1113 #endif 1114 } 1115 1116 /** 1117 * intel_power_domains_fini - finalizes the power domain structures 1118 * @dev_priv: i915 device instance 1119 * 1120 * Finalizes the power domain structures for @dev_priv depending upon the 1121 * supported platform. This function also disables runtime pm and ensures that 1122 * the device stays powered up so that the driver can be reloaded. 1123 */ 1124 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 1125 { 1126 intel_runtime_pm_disable(dev_priv); 1127 1128 /* The i915.ko module is still not prepared to be loaded when 1129 * the power well is not enabled, so just enable it in case 1130 * we're going to unload/reload. */ 1131 intel_display_set_init_power(dev_priv, true); 1132 } 1133 1134 static void intel_power_domains_resume(struct drm_i915_private *dev_priv) 1135 { 1136 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1137 struct i915_power_well *power_well; 1138 int i; 1139 1140 mutex_lock(&power_domains->lock); 1141 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 1142 power_well->ops->sync_hw(dev_priv, power_well); 1143 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 1144 power_well); 1145 } 1146 mutex_unlock(&power_domains->lock); 1147 } 1148 1149 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 1150 { 1151 struct i915_power_well *cmn = 1152 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1153 struct i915_power_well *disp2d = 1154 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 1155 1156 /* If the display might be already active skip this */ 1157 if (cmn->ops->is_enabled(dev_priv, cmn) && 1158 disp2d->ops->is_enabled(dev_priv, disp2d) && 1159 I915_READ(DPIO_CTL) & DPIO_CMNRST) 1160 return; 1161 1162 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 1163 1164 /* cmnlane needs DPLL registers */ 1165 disp2d->ops->enable(dev_priv, disp2d); 1166 1167 /* 1168 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 1169 * Need to assert and de-assert PHY SB reset by gating the 1170 * common lane power, then un-gating it. 1171 * Simply ungating isn't enough to reset the PHY enough to get 1172 * ports and lanes running. 1173 */ 1174 cmn->ops->disable(dev_priv, cmn); 1175 } 1176 1177 /** 1178 * intel_power_domains_init_hw - initialize hardware power domain state 1179 * @dev_priv: i915 device instance 1180 * 1181 * This function initializes the hardware power domain state and enables all 1182 * power domains using intel_display_set_init_power(). 1183 */ 1184 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) 1185 { 1186 struct drm_device *dev = dev_priv->dev; 1187 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1188 1189 power_domains->initializing = true; 1190 1191 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { 1192 mutex_lock(&power_domains->lock); 1193 vlv_cmnlane_wa(dev_priv); 1194 mutex_unlock(&power_domains->lock); 1195 } 1196 1197 /* For now, we need the power well to be always enabled. */ 1198 intel_display_set_init_power(dev_priv, true); 1199 intel_power_domains_resume(dev_priv); 1200 power_domains->initializing = false; 1201 } 1202 1203 /** 1204 * intel_aux_display_runtime_get - grab an auxilliary power domain reference 1205 * @dev_priv: i915 device instance 1206 * 1207 * This function grabs a power domain reference for the auxiliary power domain 1208 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its 1209 * parents are powered up. Therefore users should only grab a reference to the 1210 * innermost power domain they need. 1211 * 1212 * Any power domain reference obtained by this function must have a symmetric 1213 * call to intel_aux_display_runtime_put() to release the reference again. 1214 */ 1215 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) 1216 { 1217 intel_runtime_pm_get(dev_priv); 1218 } 1219 1220 /** 1221 * intel_aux_display_runtime_put - release an auxilliary power domain reference 1222 * @dev_priv: i915 device instance 1223 * 1224 * This function drops the auxilliary power domain reference obtained by 1225 * intel_aux_display_runtime_get() and might power down the corresponding 1226 * hardware block right away if this is the last reference. 1227 */ 1228 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) 1229 { 1230 intel_runtime_pm_put(dev_priv); 1231 } 1232 1233 /** 1234 * intel_runtime_pm_get - grab a runtime pm reference 1235 * @dev_priv: i915 device instance 1236 * 1237 * This function grabs a device-level runtime pm reference (mostly used for GEM 1238 * code to ensure the GTT or GT is on) and ensures that it is powered up. 1239 * 1240 * Any runtime pm reference obtained by this function must have a symmetric 1241 * call to intel_runtime_pm_put() to release the reference again. 1242 */ 1243 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 1244 { 1245 struct drm_device *dev = dev_priv->dev; 1246 #if 0 1247 struct device *device = &dev->pdev->dev; 1248 #endif 1249 1250 if (!HAS_RUNTIME_PM(dev)) 1251 return; 1252 1253 #if 0 1254 pm_runtime_get_sync(device); 1255 #endif 1256 WARN(dev_priv->pm.suspended, "Device still suspended.\n"); 1257 } 1258 1259 /** 1260 * intel_runtime_pm_get_noresume - grab a runtime pm reference 1261 * @dev_priv: i915 device instance 1262 * 1263 * This function grabs a device-level runtime pm reference (mostly used for GEM 1264 * code to ensure the GTT or GT is on). 1265 * 1266 * It will _not_ power up the device but instead only check that it's powered 1267 * on. Therefore it is only valid to call this functions from contexts where 1268 * the device is known to be powered up and where trying to power it up would 1269 * result in hilarity and deadlocks. That pretty much means only the system 1270 * suspend/resume code where this is used to grab runtime pm references for 1271 * delayed setup down in work items. 1272 * 1273 * Any runtime pm reference obtained by this function must have a symmetric 1274 * call to intel_runtime_pm_put() to release the reference again. 1275 */ 1276 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 1277 { 1278 struct drm_device *dev = dev_priv->dev; 1279 #if 0 1280 struct device *device = &dev->pdev->dev; 1281 #endif 1282 1283 if (!HAS_RUNTIME_PM(dev)) 1284 return; 1285 1286 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); 1287 #if 0 1288 pm_runtime_get_noresume(device); 1289 #endif 1290 } 1291 1292 /** 1293 * intel_runtime_pm_put - release a runtime pm reference 1294 * @dev_priv: i915 device instance 1295 * 1296 * This function drops the device-level runtime pm reference obtained by 1297 * intel_runtime_pm_get() and might power down the corresponding 1298 * hardware block right away if this is the last reference. 1299 */ 1300 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 1301 { 1302 #if 0 1303 struct drm_device *dev = dev_priv->dev; 1304 struct device *device = &dev->pdev->dev; 1305 1306 if (!HAS_RUNTIME_PM(dev)) 1307 return; 1308 1309 pm_runtime_mark_last_busy(device); 1310 pm_runtime_put_autosuspend(device); 1311 #endif 1312 } 1313 1314 /** 1315 * intel_runtime_pm_enable - enable runtime pm 1316 * @dev_priv: i915 device instance 1317 * 1318 * This function enables runtime pm at the end of the driver load sequence. 1319 * 1320 * Note that this function does currently not enable runtime pm for the 1321 * subordinate display power domains. That is only done on the first modeset 1322 * using intel_display_set_init_power(). 1323 */ 1324 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 1325 { 1326 struct drm_device *dev = dev_priv->dev; 1327 #if 0 1328 struct device *device = &dev->pdev->dev; 1329 #endif 1330 1331 if (!HAS_RUNTIME_PM(dev)) 1332 return; 1333 1334 #if 0 1335 pm_runtime_set_active(device); 1336 #endif 1337 1338 /* 1339 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a 1340 * requirement. 1341 */ 1342 if (!intel_enable_rc6(dev)) { 1343 DRM_INFO("RC6 disabled, disabling runtime PM support\n"); 1344 return; 1345 } 1346 1347 #if 0 1348 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 1349 pm_runtime_mark_last_busy(device); 1350 pm_runtime_use_autosuspend(device); 1351 1352 pm_runtime_put_autosuspend(device); 1353 #endif 1354 } 1355 1356