1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 #include <linux/i2c.h> 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_atomic_helper.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 #include "intel_sdvo_regs.h" 39 40 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 41 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 42 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 43 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 44 45 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 46 SDVO_TV_MASK) 47 48 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 49 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 50 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 51 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 52 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 53 54 55 static const char * const tv_format_names[] = { 56 "NTSC_M" , "NTSC_J" , "NTSC_443", 57 "PAL_B" , "PAL_D" , "PAL_G" , 58 "PAL_H" , "PAL_I" , "PAL_M" , 59 "PAL_N" , "PAL_NC" , "PAL_60" , 60 "SECAM_B" , "SECAM_D" , "SECAM_G" , 61 "SECAM_K" , "SECAM_K1", "SECAM_L" , 62 "SECAM_60" 63 }; 64 65 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 66 67 struct intel_sdvo { 68 struct intel_encoder base; 69 70 struct i2c_adapter *i2c; 71 u8 slave_addr; 72 73 struct i2c_adapter ddc; 74 75 /* Register for the SDVO device: SDVOB or SDVOC */ 76 uint32_t sdvo_reg; 77 78 /* Active outputs controlled by this SDVO output */ 79 uint16_t controlled_output; 80 81 /* 82 * Capabilities of the SDVO device returned by 83 * intel_sdvo_get_capabilities() 84 */ 85 struct intel_sdvo_caps caps; 86 87 /* Pixel clock limitations reported by the SDVO device, in kHz */ 88 int pixel_clock_min, pixel_clock_max; 89 90 /* 91 * For multiple function SDVO device, 92 * this is for current attached outputs. 93 */ 94 uint16_t attached_output; 95 96 /* 97 * Hotplug activation bits for this device 98 */ 99 uint16_t hotplug_active; 100 101 /** 102 * This is used to select the color range of RBG outputs in HDMI mode. 103 * It is only valid when using TMDS encoding and 8 bit per color mode. 104 */ 105 uint32_t color_range; 106 bool color_range_auto; 107 108 /** 109 * HDMI user specified aspect ratio 110 */ 111 enum hdmi_picture_aspect aspect_ratio; 112 113 /** 114 * This is set if we're going to treat the device as TV-out. 115 * 116 * While we have these nice friendly flags for output types that ought 117 * to decide this for us, the S-Video output on our HDMI+S-Video card 118 * shows up as RGB1 (VGA). 119 */ 120 bool is_tv; 121 122 /* On different gens SDVOB is at different places. */ 123 bool is_sdvob; 124 125 /* This is for current tv format name */ 126 int tv_format_index; 127 128 /** 129 * This is set if we treat the device as HDMI, instead of DVI. 130 */ 131 bool is_hdmi; 132 bool has_hdmi_monitor; 133 bool has_hdmi_audio; 134 bool rgb_quant_range_selectable; 135 136 /** 137 * This is set if we detect output of sdvo device as LVDS and 138 * have a valid fixed mode to use with the panel. 139 */ 140 bool is_lvds; 141 142 /** 143 * This is sdvo fixed pannel mode pointer 144 */ 145 struct drm_display_mode *sdvo_lvds_fixed_mode; 146 147 /* DDC bus used by this SDVO encoder */ 148 uint8_t ddc_bus; 149 150 /* 151 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 152 */ 153 uint8_t dtd_sdvo_flags; 154 }; 155 156 struct intel_sdvo_connector { 157 struct intel_connector base; 158 159 /* Mark the type of connector */ 160 uint16_t output_flag; 161 162 enum hdmi_force_audio force_audio; 163 164 /* This contains all current supported TV format */ 165 u8 tv_format_supported[TV_FORMAT_NUM]; 166 int format_supported_num; 167 struct drm_property *tv_format; 168 169 /* add the property for the SDVO-TV */ 170 struct drm_property *left; 171 struct drm_property *right; 172 struct drm_property *top; 173 struct drm_property *bottom; 174 struct drm_property *hpos; 175 struct drm_property *vpos; 176 struct drm_property *contrast; 177 struct drm_property *saturation; 178 struct drm_property *hue; 179 struct drm_property *sharpness; 180 struct drm_property *flicker_filter; 181 struct drm_property *flicker_filter_adaptive; 182 struct drm_property *flicker_filter_2d; 183 struct drm_property *tv_chroma_filter; 184 struct drm_property *tv_luma_filter; 185 struct drm_property *dot_crawl; 186 187 /* add the property for the SDVO-TV/LVDS */ 188 struct drm_property *brightness; 189 190 /* Add variable to record current setting for the above property */ 191 u32 left_margin, right_margin, top_margin, bottom_margin; 192 193 /* this is to get the range of margin.*/ 194 u32 max_hscan, max_vscan; 195 u32 max_hpos, cur_hpos; 196 u32 max_vpos, cur_vpos; 197 u32 cur_brightness, max_brightness; 198 u32 cur_contrast, max_contrast; 199 u32 cur_saturation, max_saturation; 200 u32 cur_hue, max_hue; 201 u32 cur_sharpness, max_sharpness; 202 u32 cur_flicker_filter, max_flicker_filter; 203 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 204 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 205 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 206 u32 cur_tv_luma_filter, max_tv_luma_filter; 207 u32 cur_dot_crawl, max_dot_crawl; 208 }; 209 210 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 211 { 212 return container_of(encoder, struct intel_sdvo, base); 213 } 214 215 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 216 { 217 return to_sdvo(intel_attached_encoder(connector)); 218 } 219 220 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 221 { 222 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 223 } 224 225 static bool 226 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 227 static bool 228 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 229 struct intel_sdvo_connector *intel_sdvo_connector, 230 int type); 231 static bool 232 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 233 struct intel_sdvo_connector *intel_sdvo_connector); 234 235 /** 236 * Writes the SDVOB or SDVOC with the given value, but always writes both 237 * SDVOB and SDVOC to work around apparent hardware issues (according to 238 * comments in the BIOS). 239 */ 240 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 241 { 242 struct drm_device *dev = intel_sdvo->base.base.dev; 243 struct drm_i915_private *dev_priv = dev->dev_private; 244 u32 bval = val, cval = val; 245 int i; 246 247 if (intel_sdvo->sdvo_reg == PCH_SDVOB) { 248 I915_WRITE(intel_sdvo->sdvo_reg, val); 249 POSTING_READ(intel_sdvo->sdvo_reg); 250 /* 251 * HW workaround, need to write this twice for issue 252 * that may result in first write getting masked. 253 */ 254 if (HAS_PCH_IBX(dev)) { 255 I915_WRITE(intel_sdvo->sdvo_reg, val); 256 POSTING_READ(intel_sdvo->sdvo_reg); 257 } 258 return; 259 } 260 261 if (intel_sdvo->sdvo_reg == GEN3_SDVOB) 262 cval = I915_READ(GEN3_SDVOC); 263 else 264 bval = I915_READ(GEN3_SDVOB); 265 266 /* 267 * Write the registers twice for luck. Sometimes, 268 * writing them only once doesn't appear to 'stick'. 269 * The BIOS does this too. Yay, magic 270 */ 271 for (i = 0; i < 2; i++) 272 { 273 I915_WRITE(GEN3_SDVOB, bval); 274 POSTING_READ(GEN3_SDVOB); 275 I915_WRITE(GEN3_SDVOC, cval); 276 POSTING_READ(GEN3_SDVOC); 277 } 278 } 279 280 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 281 { 282 struct i2c_msg msgs[] = { 283 { 284 .addr = intel_sdvo->slave_addr, 285 .flags = 0, 286 .len = 1, 287 .buf = &addr, 288 }, 289 { 290 .addr = intel_sdvo->slave_addr, 291 .flags = I2C_M_RD, 292 .len = 1, 293 .buf = ch, 294 } 295 }; 296 int ret; 297 298 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 299 return true; 300 301 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 302 return false; 303 } 304 305 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 306 /** Mapping of command numbers to names, for debug output */ 307 static const struct _sdvo_cmd_name { 308 u8 cmd; 309 const char *name; 310 } sdvo_cmd_names[] = { 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 354 355 /* Add the op code for SDVO enhancements */ 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 400 401 /* HDMI op code */ 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 413 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 414 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 415 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 416 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 417 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 418 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 419 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 420 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 421 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 422 }; 423 424 #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") 425 426 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 427 const void *args, int args_len) 428 { 429 int i, pos = 0; 430 #define BUF_LEN 256 431 char buffer[BUF_LEN]; 432 433 #define BUF_PRINT(args...) \ 434 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 435 436 437 for (i = 0; i < args_len; i++) { 438 BUF_PRINT("%02X ", ((const u8 *)args)[i]); 439 } 440 for (; i < 8; i++) { 441 BUF_PRINT(" "); 442 } 443 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 444 if (cmd == sdvo_cmd_names[i].cmd) { 445 BUF_PRINT("(%s)", sdvo_cmd_names[i].name); 446 break; 447 } 448 } 449 if (i == ARRAY_SIZE(sdvo_cmd_names)) { 450 BUF_PRINT("(%02X)", cmd); 451 } 452 BUG_ON(pos >= BUF_LEN - 1); 453 #undef BUF_PRINT 454 #undef BUF_LEN 455 456 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 457 } 458 459 static const char * const cmd_status_names[] = { 460 "Power on", 461 "Success", 462 "Not supported", 463 "Invalid arg", 464 "Pending", 465 "Target not specified", 466 "Scaling not supported" 467 }; 468 469 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 470 const void *args, int args_len) 471 { 472 u8 *buf, status; 473 struct i2c_msg *msgs; 474 int i, ret = true; 475 476 /* Would be simpler to allocate both in one go ? */ 477 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 478 if (!buf) 479 return false; 480 481 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 482 if (!msgs) { 483 kfree(buf); 484 return false; 485 } 486 487 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 488 489 for (i = 0; i < args_len; i++) { 490 msgs[i].addr = intel_sdvo->slave_addr; 491 msgs[i].flags = 0; 492 msgs[i].len = 2; 493 msgs[i].buf = buf + 2 *i; 494 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 495 buf[2*i + 1] = ((const u8*)args)[i]; 496 } 497 msgs[i].addr = intel_sdvo->slave_addr; 498 msgs[i].flags = 0; 499 msgs[i].len = 2; 500 msgs[i].buf = buf + 2*i; 501 buf[2*i + 0] = SDVO_I2C_OPCODE; 502 buf[2*i + 1] = cmd; 503 504 /* the following two are to read the response */ 505 status = SDVO_I2C_CMD_STATUS; 506 msgs[i+1].addr = intel_sdvo->slave_addr; 507 msgs[i+1].flags = 0; 508 msgs[i+1].len = 1; 509 msgs[i+1].buf = &status; 510 511 msgs[i+2].addr = intel_sdvo->slave_addr; 512 msgs[i+2].flags = I2C_M_RD; 513 msgs[i+2].len = 1; 514 msgs[i+2].buf = &status; 515 516 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 517 if (ret < 0) { 518 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 519 ret = false; 520 goto out; 521 } 522 if (ret != i+3) { 523 /* failure in I2C transfer */ 524 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 525 ret = false; 526 } 527 528 out: 529 kfree(msgs); 530 kfree(buf); 531 return ret; 532 } 533 534 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 535 void *response, int response_len) 536 { 537 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 538 u8 status; 539 int i, pos = 0; 540 #define BUF_LEN 256 541 char buffer[BUF_LEN]; 542 543 544 /* 545 * The documentation states that all commands will be 546 * processed within 15µs, and that we need only poll 547 * the status byte a maximum of 3 times in order for the 548 * command to be complete. 549 * 550 * Check 5 times in case the hardware failed to read the docs. 551 * 552 * Also beware that the first response by many devices is to 553 * reply PENDING and stall for time. TVs are notorious for 554 * requiring longer than specified to complete their replies. 555 * Originally (in the DDX long ago), the delay was only ever 15ms 556 * with an additional delay of 30ms applied for TVs added later after 557 * many experiments. To accommodate both sets of delays, we do a 558 * sequence of slow checks if the device is falling behind and fails 559 * to reply within 5*15µs. 560 */ 561 if (!intel_sdvo_read_byte(intel_sdvo, 562 SDVO_I2C_CMD_STATUS, 563 &status)) 564 goto log_fail; 565 566 while ((status == SDVO_CMD_STATUS_PENDING || 567 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 568 if (retry < 10) 569 msleep(15); 570 else 571 udelay(15); 572 573 if (!intel_sdvo_read_byte(intel_sdvo, 574 SDVO_I2C_CMD_STATUS, 575 &status)) 576 goto log_fail; 577 } 578 579 #define BUF_PRINT(args...) \ 580 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 581 582 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 583 BUF_PRINT("(%s)", cmd_status_names[status]); 584 else 585 BUF_PRINT("(??? %d)", status); 586 587 if (status != SDVO_CMD_STATUS_SUCCESS) 588 goto log_fail; 589 590 /* Read the command response */ 591 for (i = 0; i < response_len; i++) { 592 if (!intel_sdvo_read_byte(intel_sdvo, 593 SDVO_I2C_RETURN_0 + i, 594 &((u8 *)response)[i])) 595 goto log_fail; 596 BUF_PRINT(" %02X", ((u8 *)response)[i]); 597 } 598 BUG_ON(pos >= BUF_LEN - 1); 599 #undef BUF_PRINT 600 #undef BUF_LEN 601 602 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 603 return true; 604 605 log_fail: 606 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); 607 return false; 608 } 609 610 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 611 { 612 if (adjusted_mode->crtc_clock >= 100000) 613 return 1; 614 else if (adjusted_mode->crtc_clock >= 50000) 615 return 2; 616 else 617 return 4; 618 } 619 620 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 621 u8 ddc_bus) 622 { 623 /* This must be the immediately preceding write before the i2c xfer */ 624 return intel_sdvo_write_cmd(intel_sdvo, 625 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 626 &ddc_bus, 1); 627 } 628 629 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 630 { 631 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 632 return false; 633 634 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 635 } 636 637 static bool 638 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 639 { 640 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 641 return false; 642 643 return intel_sdvo_read_response(intel_sdvo, value, len); 644 } 645 646 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 647 { 648 struct intel_sdvo_set_target_input_args targets = {0}; 649 return intel_sdvo_set_value(intel_sdvo, 650 SDVO_CMD_SET_TARGET_INPUT, 651 &targets, sizeof(targets)); 652 } 653 654 /** 655 * Return whether each input is trained. 656 * 657 * This function is making an assumption about the layout of the response, 658 * which should be checked against the docs. 659 */ 660 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 661 { 662 struct intel_sdvo_get_trained_inputs_response response; 663 664 BUILD_BUG_ON(sizeof(response) != 1); 665 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 666 &response, sizeof(response))) 667 return false; 668 669 *input_1 = response.input0_trained; 670 *input_2 = response.input1_trained; 671 return true; 672 } 673 674 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 675 u16 outputs) 676 { 677 return intel_sdvo_set_value(intel_sdvo, 678 SDVO_CMD_SET_ACTIVE_OUTPUTS, 679 &outputs, sizeof(outputs)); 680 } 681 682 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 683 u16 *outputs) 684 { 685 return intel_sdvo_get_value(intel_sdvo, 686 SDVO_CMD_GET_ACTIVE_OUTPUTS, 687 outputs, sizeof(*outputs)); 688 } 689 690 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 691 int mode) 692 { 693 u8 state = SDVO_ENCODER_STATE_ON; 694 695 switch (mode) { 696 case DRM_MODE_DPMS_ON: 697 state = SDVO_ENCODER_STATE_ON; 698 break; 699 case DRM_MODE_DPMS_STANDBY: 700 state = SDVO_ENCODER_STATE_STANDBY; 701 break; 702 case DRM_MODE_DPMS_SUSPEND: 703 state = SDVO_ENCODER_STATE_SUSPEND; 704 break; 705 case DRM_MODE_DPMS_OFF: 706 state = SDVO_ENCODER_STATE_OFF; 707 break; 708 } 709 710 return intel_sdvo_set_value(intel_sdvo, 711 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 712 } 713 714 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 715 int *clock_min, 716 int *clock_max) 717 { 718 struct intel_sdvo_pixel_clock_range clocks; 719 720 BUILD_BUG_ON(sizeof(clocks) != 4); 721 if (!intel_sdvo_get_value(intel_sdvo, 722 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 723 &clocks, sizeof(clocks))) 724 return false; 725 726 /* Convert the values from units of 10 kHz to kHz. */ 727 *clock_min = clocks.min * 10; 728 *clock_max = clocks.max * 10; 729 return true; 730 } 731 732 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 733 u16 outputs) 734 { 735 return intel_sdvo_set_value(intel_sdvo, 736 SDVO_CMD_SET_TARGET_OUTPUT, 737 &outputs, sizeof(outputs)); 738 } 739 740 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 741 struct intel_sdvo_dtd *dtd) 742 { 743 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 744 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 745 } 746 747 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 748 struct intel_sdvo_dtd *dtd) 749 { 750 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 751 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 752 } 753 754 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 755 struct intel_sdvo_dtd *dtd) 756 { 757 return intel_sdvo_set_timing(intel_sdvo, 758 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 759 } 760 761 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 762 struct intel_sdvo_dtd *dtd) 763 { 764 return intel_sdvo_set_timing(intel_sdvo, 765 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 766 } 767 768 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 769 struct intel_sdvo_dtd *dtd) 770 { 771 return intel_sdvo_get_timing(intel_sdvo, 772 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 773 } 774 775 static bool 776 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 777 uint16_t clock, 778 uint16_t width, 779 uint16_t height) 780 { 781 struct intel_sdvo_preferred_input_timing_args args; 782 783 memset(&args, 0, sizeof(args)); 784 args.clock = clock; 785 args.width = width; 786 args.height = height; 787 args.interlace = 0; 788 789 if (intel_sdvo->is_lvds && 790 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 791 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 792 args.scaled = 1; 793 794 return intel_sdvo_set_value(intel_sdvo, 795 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 796 &args, sizeof(args)); 797 } 798 799 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 800 struct intel_sdvo_dtd *dtd) 801 { 802 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 803 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 804 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 805 &dtd->part1, sizeof(dtd->part1)) && 806 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 807 &dtd->part2, sizeof(dtd->part2)); 808 } 809 810 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 811 { 812 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 813 } 814 815 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 816 const struct drm_display_mode *mode) 817 { 818 uint16_t width, height; 819 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 820 uint16_t h_sync_offset, v_sync_offset; 821 int mode_clock; 822 823 memset(dtd, 0, sizeof(*dtd)); 824 825 width = mode->hdisplay; 826 height = mode->vdisplay; 827 828 /* do some mode translations */ 829 h_blank_len = mode->htotal - mode->hdisplay; 830 h_sync_len = mode->hsync_end - mode->hsync_start; 831 832 v_blank_len = mode->vtotal - mode->vdisplay; 833 v_sync_len = mode->vsync_end - mode->vsync_start; 834 835 h_sync_offset = mode->hsync_start - mode->hdisplay; 836 v_sync_offset = mode->vsync_start - mode->vdisplay; 837 838 mode_clock = mode->clock; 839 mode_clock /= 10; 840 dtd->part1.clock = mode_clock; 841 842 dtd->part1.h_active = width & 0xff; 843 dtd->part1.h_blank = h_blank_len & 0xff; 844 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 845 ((h_blank_len >> 8) & 0xf); 846 dtd->part1.v_active = height & 0xff; 847 dtd->part1.v_blank = v_blank_len & 0xff; 848 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 849 ((v_blank_len >> 8) & 0xf); 850 851 dtd->part2.h_sync_off = h_sync_offset & 0xff; 852 dtd->part2.h_sync_width = h_sync_len & 0xff; 853 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 854 (v_sync_len & 0xf); 855 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 856 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 857 ((v_sync_len & 0x30) >> 4); 858 859 dtd->part2.dtd_flags = 0x18; 860 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 861 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 862 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 863 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 864 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 865 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 866 867 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 868 } 869 870 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 871 const struct intel_sdvo_dtd *dtd) 872 { 873 struct drm_display_mode mode = {}; 874 875 mode.hdisplay = dtd->part1.h_active; 876 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 877 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 878 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 879 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 880 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 881 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 882 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 883 884 mode.vdisplay = dtd->part1.v_active; 885 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 886 mode.vsync_start = mode.vdisplay; 887 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 888 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 889 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 890 mode.vsync_end = mode.vsync_start + 891 (dtd->part2.v_sync_off_width & 0xf); 892 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 893 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 894 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 895 896 mode.clock = dtd->part1.clock * 10; 897 898 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 899 mode.flags |= DRM_MODE_FLAG_INTERLACE; 900 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 901 mode.flags |= DRM_MODE_FLAG_PHSYNC; 902 else 903 mode.flags |= DRM_MODE_FLAG_NHSYNC; 904 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 905 mode.flags |= DRM_MODE_FLAG_PVSYNC; 906 else 907 mode.flags |= DRM_MODE_FLAG_NVSYNC; 908 909 drm_mode_set_crtcinfo(&mode, 0); 910 911 drm_mode_copy(pmode, &mode); 912 } 913 914 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 915 { 916 struct intel_sdvo_encode encode; 917 918 BUILD_BUG_ON(sizeof(encode) != 2); 919 return intel_sdvo_get_value(intel_sdvo, 920 SDVO_CMD_GET_SUPP_ENCODE, 921 &encode, sizeof(encode)); 922 } 923 924 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 925 uint8_t mode) 926 { 927 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 928 } 929 930 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 931 uint8_t mode) 932 { 933 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 934 } 935 936 #if 0 937 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 938 { 939 int i, j; 940 uint8_t set_buf_index[2]; 941 uint8_t av_split; 942 uint8_t buf_size; 943 uint8_t buf[48]; 944 uint8_t *pos; 945 946 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 947 948 for (i = 0; i <= av_split; i++) { 949 set_buf_index[0] = i; set_buf_index[1] = 0; 950 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 951 set_buf_index, 2); 952 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 953 intel_sdvo_read_response(encoder, &buf_size, 1); 954 955 pos = buf; 956 for (j = 0; j <= buf_size; j += 8) { 957 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 958 NULL, 0); 959 intel_sdvo_read_response(encoder, pos, 8); 960 pos += 8; 961 } 962 } 963 } 964 #endif 965 966 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 967 unsigned if_index, uint8_t tx_rate, 968 const uint8_t *data, unsigned length) 969 { 970 uint8_t set_buf_index[2] = { if_index, 0 }; 971 uint8_t hbuf_size, tmp[8]; 972 int i; 973 974 if (!intel_sdvo_set_value(intel_sdvo, 975 SDVO_CMD_SET_HBUF_INDEX, 976 set_buf_index, 2)) 977 return false; 978 979 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 980 &hbuf_size, 1)) 981 return false; 982 983 /* Buffer size is 0 based, hooray! */ 984 hbuf_size++; 985 986 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", 987 if_index, length, hbuf_size); 988 989 for (i = 0; i < hbuf_size; i += 8) { 990 memset(tmp, 0, 8); 991 if (i < length) 992 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 993 994 if (!intel_sdvo_set_value(intel_sdvo, 995 SDVO_CMD_SET_HBUF_DATA, 996 tmp, 8)) 997 return false; 998 } 999 1000 return intel_sdvo_set_value(intel_sdvo, 1001 SDVO_CMD_SET_HBUF_TXRATE, 1002 &tx_rate, 1); 1003 } 1004 1005 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1006 const struct drm_display_mode *adjusted_mode) 1007 { 1008 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1009 struct drm_crtc *crtc = intel_sdvo->base.base.crtc; 1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1011 union hdmi_infoframe frame; 1012 int ret; 1013 ssize_t len; 1014 1015 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 1016 adjusted_mode); 1017 if (ret < 0) { 1018 DRM_ERROR("couldn't fill AVI infoframe\n"); 1019 return false; 1020 } 1021 1022 if (intel_sdvo->rgb_quant_range_selectable) { 1023 if (intel_crtc->config->limited_color_range) 1024 frame.avi.quantization_range = 1025 HDMI_QUANTIZATION_RANGE_LIMITED; 1026 else 1027 frame.avi.quantization_range = 1028 HDMI_QUANTIZATION_RANGE_FULL; 1029 } 1030 1031 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); 1032 if (len < 0) 1033 return false; 1034 1035 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1036 SDVO_HBUF_TX_VSYNC, 1037 sdvo_data, sizeof(sdvo_data)); 1038 } 1039 1040 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 1041 { 1042 struct intel_sdvo_tv_format format; 1043 uint32_t format_map; 1044 1045 format_map = 1 << intel_sdvo->tv_format_index; 1046 memset(&format, 0, sizeof(format)); 1047 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1048 1049 BUILD_BUG_ON(sizeof(format) != 6); 1050 return intel_sdvo_set_value(intel_sdvo, 1051 SDVO_CMD_SET_TV_FORMAT, 1052 &format, sizeof(format)); 1053 } 1054 1055 static bool 1056 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1057 const struct drm_display_mode *mode) 1058 { 1059 struct intel_sdvo_dtd output_dtd; 1060 1061 if (!intel_sdvo_set_target_output(intel_sdvo, 1062 intel_sdvo->attached_output)) 1063 return false; 1064 1065 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1066 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1067 return false; 1068 1069 return true; 1070 } 1071 1072 /* Asks the sdvo controller for the preferred input mode given the output mode. 1073 * Unfortunately we have to set up the full output mode to do that. */ 1074 static bool 1075 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1076 const struct drm_display_mode *mode, 1077 struct drm_display_mode *adjusted_mode) 1078 { 1079 struct intel_sdvo_dtd input_dtd; 1080 1081 /* Reset the input timing to the screen. Assume always input 0. */ 1082 if (!intel_sdvo_set_target_input(intel_sdvo)) 1083 return false; 1084 1085 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1086 mode->clock / 10, 1087 mode->hdisplay, 1088 mode->vdisplay)) 1089 return false; 1090 1091 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1092 &input_dtd)) 1093 return false; 1094 1095 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1096 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1097 1098 return true; 1099 } 1100 1101 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1102 { 1103 unsigned dotclock = pipe_config->port_clock; 1104 struct dpll *clock = &pipe_config->dpll; 1105 1106 /* SDVO TV has fixed PLL values depend on its clock range, 1107 this mirrors vbios setting. */ 1108 if (dotclock >= 100000 && dotclock < 140500) { 1109 clock->p1 = 2; 1110 clock->p2 = 10; 1111 clock->n = 3; 1112 clock->m1 = 16; 1113 clock->m2 = 8; 1114 } else if (dotclock >= 140500 && dotclock <= 200000) { 1115 clock->p1 = 1; 1116 clock->p2 = 10; 1117 clock->n = 6; 1118 clock->m1 = 12; 1119 clock->m2 = 8; 1120 } else { 1121 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1122 } 1123 1124 pipe_config->clock_set = true; 1125 } 1126 1127 static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1128 struct intel_crtc_state *pipe_config) 1129 { 1130 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1131 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1132 struct drm_display_mode *mode = &pipe_config->base.mode; 1133 1134 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1135 pipe_config->pipe_bpp = 8*3; 1136 1137 if (HAS_PCH_SPLIT(encoder->base.dev)) 1138 pipe_config->has_pch_encoder = true; 1139 1140 /* We need to construct preferred input timings based on our 1141 * output timings. To do that, we have to set the output 1142 * timings, even though this isn't really the right place in 1143 * the sequence to do it. Oh well. 1144 */ 1145 if (intel_sdvo->is_tv) { 1146 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1147 return false; 1148 1149 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1150 mode, 1151 adjusted_mode); 1152 pipe_config->sdvo_tv_clock = true; 1153 } else if (intel_sdvo->is_lvds) { 1154 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1155 intel_sdvo->sdvo_lvds_fixed_mode)) 1156 return false; 1157 1158 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1159 mode, 1160 adjusted_mode); 1161 } 1162 1163 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1164 * SDVO device will factor out the multiplier during mode_set. 1165 */ 1166 pipe_config->pixel_multiplier = 1167 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1168 1169 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; 1170 1171 if (intel_sdvo->color_range_auto) { 1172 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1173 /* FIXME: This bit is only valid when using TMDS encoding and 8 1174 * bit per color mode. */ 1175 if (pipe_config->has_hdmi_sink && 1176 drm_match_cea_mode(adjusted_mode) > 1) 1177 pipe_config->limited_color_range = true; 1178 } else { 1179 if (pipe_config->has_hdmi_sink && 1180 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) 1181 pipe_config->limited_color_range = true; 1182 } 1183 1184 /* Clock computation needs to happen after pixel multiplier. */ 1185 if (intel_sdvo->is_tv) 1186 i9xx_adjust_sdvo_tv_clock(pipe_config); 1187 1188 /* Set user selected PAR to incoming mode's member */ 1189 if (intel_sdvo->is_hdmi) 1190 adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio; 1191 1192 return true; 1193 } 1194 1195 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) 1196 { 1197 struct drm_device *dev = intel_encoder->base.dev; 1198 struct drm_i915_private *dev_priv = dev->dev_private; 1199 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); 1200 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 1201 struct drm_display_mode *mode = &crtc->config->base.mode; 1202 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1203 u32 sdvox; 1204 struct intel_sdvo_in_out_map in_out; 1205 struct intel_sdvo_dtd input_dtd, output_dtd; 1206 int rate; 1207 1208 if (!mode) 1209 return; 1210 1211 /* First, set the input mapping for the first input to our controlled 1212 * output. This is only correct if we're a single-input device, in 1213 * which case the first input is the output from the appropriate SDVO 1214 * channel on the motherboard. In a two-input device, the first input 1215 * will be SDVOB and the second SDVOC. 1216 */ 1217 in_out.in0 = intel_sdvo->attached_output; 1218 in_out.in1 = 0; 1219 1220 intel_sdvo_set_value(intel_sdvo, 1221 SDVO_CMD_SET_IN_OUT_MAP, 1222 &in_out, sizeof(in_out)); 1223 1224 /* Set the output timings to the screen */ 1225 if (!intel_sdvo_set_target_output(intel_sdvo, 1226 intel_sdvo->attached_output)) 1227 return; 1228 1229 /* lvds has a special fixed output timing. */ 1230 if (intel_sdvo->is_lvds) 1231 intel_sdvo_get_dtd_from_mode(&output_dtd, 1232 intel_sdvo->sdvo_lvds_fixed_mode); 1233 else 1234 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1235 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1236 DRM_INFO("Setting output timings on %s failed\n", 1237 SDVO_NAME(intel_sdvo)); 1238 1239 /* Set the input timing to the screen. Assume always input 0. */ 1240 if (!intel_sdvo_set_target_input(intel_sdvo)) 1241 return; 1242 1243 if (crtc->config->has_hdmi_sink) { 1244 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1245 intel_sdvo_set_colorimetry(intel_sdvo, 1246 SDVO_COLORIMETRY_RGB256); 1247 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); 1248 } else 1249 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1250 1251 if (intel_sdvo->is_tv && 1252 !intel_sdvo_set_tv_format(intel_sdvo)) 1253 return; 1254 1255 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1256 1257 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1258 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1259 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1260 DRM_INFO("Setting input timings on %s failed\n", 1261 SDVO_NAME(intel_sdvo)); 1262 1263 switch (crtc->config->pixel_multiplier) { 1264 default: 1265 WARN(1, "unknown pixel multiplier specified\n"); 1266 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1267 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1268 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1269 } 1270 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1271 return; 1272 1273 /* Set the SDVO control regs. */ 1274 if (INTEL_INFO(dev)->gen >= 4) { 1275 /* The real mode polarity is set by the SDVO commands, using 1276 * struct intel_sdvo_dtd. */ 1277 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1278 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 1279 sdvox |= HDMI_COLOR_RANGE_16_235; 1280 if (INTEL_INFO(dev)->gen < 5) 1281 sdvox |= SDVO_BORDER_ENABLE; 1282 } else { 1283 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1284 switch (intel_sdvo->sdvo_reg) { 1285 case GEN3_SDVOB: 1286 sdvox &= SDVOB_PRESERVE_MASK; 1287 break; 1288 case GEN3_SDVOC: 1289 sdvox &= SDVOC_PRESERVE_MASK; 1290 break; 1291 } 1292 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1293 } 1294 1295 if (INTEL_PCH_TYPE(dev) >= PCH_CPT) 1296 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1297 else 1298 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1299 1300 if (intel_sdvo->has_hdmi_audio) 1301 sdvox |= SDVO_AUDIO_ENABLE; 1302 1303 if (INTEL_INFO(dev)->gen >= 4) { 1304 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1305 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1306 /* done in crtc_mode_set as it lives inside the dpll register */ 1307 } else { 1308 sdvox |= (crtc->config->pixel_multiplier - 1) 1309 << SDVO_PORT_MULTIPLY_SHIFT; 1310 } 1311 1312 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1313 INTEL_INFO(dev)->gen < 5) 1314 sdvox |= SDVO_STALL_SELECT; 1315 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1316 } 1317 1318 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1319 { 1320 struct intel_sdvo_connector *intel_sdvo_connector = 1321 to_intel_sdvo_connector(&connector->base); 1322 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1323 u16 active_outputs = 0; 1324 1325 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1326 1327 if (active_outputs & intel_sdvo_connector->output_flag) 1328 return true; 1329 else 1330 return false; 1331 } 1332 1333 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1334 enum i915_pipe *pipe) 1335 { 1336 struct drm_device *dev = encoder->base.dev; 1337 struct drm_i915_private *dev_priv = dev->dev_private; 1338 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1339 u16 active_outputs = 0; 1340 u32 tmp; 1341 1342 tmp = I915_READ(intel_sdvo->sdvo_reg); 1343 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1344 1345 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) 1346 return false; 1347 1348 if (HAS_PCH_CPT(dev)) 1349 *pipe = PORT_TO_PIPE_CPT(tmp); 1350 else 1351 *pipe = PORT_TO_PIPE(tmp); 1352 1353 return true; 1354 } 1355 1356 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1357 struct intel_crtc_state *pipe_config) 1358 { 1359 struct drm_device *dev = encoder->base.dev; 1360 struct drm_i915_private *dev_priv = dev->dev_private; 1361 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1362 struct intel_sdvo_dtd dtd; 1363 int encoder_pixel_multiplier = 0; 1364 int dotclock; 1365 u32 flags = 0, sdvox; 1366 u8 val; 1367 bool ret; 1368 1369 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1370 1371 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1372 if (!ret) { 1373 /* Some sdvo encoders are not spec compliant and don't 1374 * implement the mandatory get_timings function. */ 1375 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1376 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1377 } else { 1378 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1379 flags |= DRM_MODE_FLAG_PHSYNC; 1380 else 1381 flags |= DRM_MODE_FLAG_NHSYNC; 1382 1383 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1384 flags |= DRM_MODE_FLAG_PVSYNC; 1385 else 1386 flags |= DRM_MODE_FLAG_NVSYNC; 1387 } 1388 1389 pipe_config->base.adjusted_mode.flags |= flags; 1390 1391 /* 1392 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1393 * the sdvo port register, on all other platforms it is part of the dpll 1394 * state. Since the general pipe state readout happens before the 1395 * encoder->get_config we so already have a valid pixel multplier on all 1396 * other platfroms. 1397 */ 1398 if (IS_I915G(dev) || IS_I915GM(dev)) { 1399 pipe_config->pixel_multiplier = 1400 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1401 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1402 } 1403 1404 dotclock = pipe_config->port_clock; 1405 if (pipe_config->pixel_multiplier) 1406 dotclock /= pipe_config->pixel_multiplier; 1407 1408 if (HAS_PCH_SPLIT(dev)) 1409 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1410 1411 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1412 1413 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1414 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1415 &val, 1)) { 1416 switch (val) { 1417 case SDVO_CLOCK_RATE_MULT_1X: 1418 encoder_pixel_multiplier = 1; 1419 break; 1420 case SDVO_CLOCK_RATE_MULT_2X: 1421 encoder_pixel_multiplier = 2; 1422 break; 1423 case SDVO_CLOCK_RATE_MULT_4X: 1424 encoder_pixel_multiplier = 4; 1425 break; 1426 } 1427 } 1428 1429 if (sdvox & HDMI_COLOR_RANGE_16_235) 1430 pipe_config->limited_color_range = true; 1431 1432 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1433 &val, 1)) { 1434 if (val == SDVO_ENCODE_HDMI) 1435 pipe_config->has_hdmi_sink = true; 1436 } 1437 1438 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1439 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1440 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1441 } 1442 1443 static void intel_disable_sdvo(struct intel_encoder *encoder) 1444 { 1445 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1446 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1447 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1448 u32 temp; 1449 1450 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1451 if (0) 1452 intel_sdvo_set_encoder_power_state(intel_sdvo, 1453 DRM_MODE_DPMS_OFF); 1454 1455 temp = I915_READ(intel_sdvo->sdvo_reg); 1456 1457 temp &= ~SDVO_ENABLE; 1458 intel_sdvo_write_sdvox(intel_sdvo, temp); 1459 1460 /* 1461 * HW workaround for IBX, we need to move the port 1462 * to transcoder A after disabling it to allow the 1463 * matching DP port to be enabled on transcoder A. 1464 */ 1465 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1466 temp &= ~SDVO_PIPE_B_SELECT; 1467 temp |= SDVO_ENABLE; 1468 intel_sdvo_write_sdvox(intel_sdvo, temp); 1469 1470 temp &= ~SDVO_ENABLE; 1471 intel_sdvo_write_sdvox(intel_sdvo, temp); 1472 } 1473 } 1474 1475 static void pch_disable_sdvo(struct intel_encoder *encoder) 1476 { 1477 } 1478 1479 static void pch_post_disable_sdvo(struct intel_encoder *encoder) 1480 { 1481 intel_disable_sdvo(encoder); 1482 } 1483 1484 static void intel_enable_sdvo(struct intel_encoder *encoder) 1485 { 1486 struct drm_device *dev = encoder->base.dev; 1487 struct drm_i915_private *dev_priv = dev->dev_private; 1488 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1489 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1490 u32 temp; 1491 bool input1, input2; 1492 int i; 1493 bool success; 1494 1495 temp = I915_READ(intel_sdvo->sdvo_reg); 1496 temp |= SDVO_ENABLE; 1497 intel_sdvo_write_sdvox(intel_sdvo, temp); 1498 1499 for (i = 0; i < 2; i++) 1500 intel_wait_for_vblank(dev, intel_crtc->pipe); 1501 1502 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1503 /* Warn if the device reported failure to sync. 1504 * A lot of SDVO devices fail to notify of sync, but it's 1505 * a given it the status is a success, we succeeded. 1506 */ 1507 if (success && !input1) { 1508 DRM_DEBUG_KMS("First %s output reported failure to " 1509 "sync\n", SDVO_NAME(intel_sdvo)); 1510 } 1511 1512 if (0) 1513 intel_sdvo_set_encoder_power_state(intel_sdvo, 1514 DRM_MODE_DPMS_ON); 1515 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1516 } 1517 1518 static enum drm_mode_status 1519 intel_sdvo_mode_valid(struct drm_connector *connector, 1520 struct drm_display_mode *mode) 1521 { 1522 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1523 1524 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1525 return MODE_NO_DBLESCAN; 1526 1527 if (intel_sdvo->pixel_clock_min > mode->clock) 1528 return MODE_CLOCK_LOW; 1529 1530 if (intel_sdvo->pixel_clock_max < mode->clock) 1531 return MODE_CLOCK_HIGH; 1532 1533 if (intel_sdvo->is_lvds) { 1534 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1535 return MODE_PANEL; 1536 1537 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1538 return MODE_PANEL; 1539 } 1540 1541 return MODE_OK; 1542 } 1543 1544 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1545 { 1546 BUILD_BUG_ON(sizeof(*caps) != 8); 1547 if (!intel_sdvo_get_value(intel_sdvo, 1548 SDVO_CMD_GET_DEVICE_CAPS, 1549 caps, sizeof(*caps))) 1550 return false; 1551 1552 DRM_DEBUG_KMS("SDVO capabilities:\n" 1553 " vendor_id: %d\n" 1554 " device_id: %d\n" 1555 " device_rev_id: %d\n" 1556 " sdvo_version_major: %d\n" 1557 " sdvo_version_minor: %d\n" 1558 " sdvo_inputs_mask: %d\n" 1559 " smooth_scaling: %d\n" 1560 " sharp_scaling: %d\n" 1561 " up_scaling: %d\n" 1562 " down_scaling: %d\n" 1563 " stall_support: %d\n" 1564 " output_flags: %d\n", 1565 caps->vendor_id, 1566 caps->device_id, 1567 caps->device_rev_id, 1568 caps->sdvo_version_major, 1569 caps->sdvo_version_minor, 1570 caps->sdvo_inputs_mask, 1571 caps->smooth_scaling, 1572 caps->sharp_scaling, 1573 caps->up_scaling, 1574 caps->down_scaling, 1575 caps->stall_support, 1576 caps->output_flags); 1577 1578 return true; 1579 } 1580 1581 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1582 { 1583 struct drm_device *dev = intel_sdvo->base.base.dev; 1584 uint16_t hotplug; 1585 1586 if (!I915_HAS_HOTPLUG(dev)) 1587 return 0; 1588 1589 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1590 * on the line. */ 1591 if (IS_I945G(dev) || IS_I945GM(dev)) 1592 return 0; 1593 1594 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1595 &hotplug, sizeof(hotplug))) 1596 return 0; 1597 1598 return hotplug; 1599 } 1600 1601 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1602 { 1603 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1604 1605 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1606 &intel_sdvo->hotplug_active, 2); 1607 } 1608 1609 static bool 1610 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1611 { 1612 /* Is there more than one type of output? */ 1613 return hweight16(intel_sdvo->caps.output_flags) > 1; 1614 } 1615 1616 static struct edid * 1617 intel_sdvo_get_edid(struct drm_connector *connector) 1618 { 1619 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1620 return drm_get_edid(connector, &sdvo->ddc); 1621 } 1622 1623 /* Mac mini hack -- use the same DDC as the analog connector */ 1624 static struct edid * 1625 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1626 { 1627 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1628 1629 return drm_get_edid(connector, 1630 intel_gmbus_get_adapter(dev_priv, 1631 dev_priv->vbt.crt_ddc_pin)); 1632 } 1633 1634 static enum drm_connector_status 1635 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1636 { 1637 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1638 enum drm_connector_status status; 1639 struct edid *edid; 1640 1641 edid = intel_sdvo_get_edid(connector); 1642 1643 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1644 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1645 1646 /* 1647 * Don't use the 1 as the argument of DDC bus switch to get 1648 * the EDID. It is used for SDVO SPD ROM. 1649 */ 1650 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1651 intel_sdvo->ddc_bus = ddc; 1652 edid = intel_sdvo_get_edid(connector); 1653 if (edid) 1654 break; 1655 } 1656 /* 1657 * If we found the EDID on the other bus, 1658 * assume that is the correct DDC bus. 1659 */ 1660 if (edid == NULL) 1661 intel_sdvo->ddc_bus = saved_ddc; 1662 } 1663 1664 /* 1665 * When there is no edid and no monitor is connected with VGA 1666 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1667 */ 1668 if (edid == NULL) 1669 edid = intel_sdvo_get_analog_edid(connector); 1670 1671 status = connector_status_unknown; 1672 if (edid != NULL) { 1673 /* DDC bus is shared, match EDID to connector type */ 1674 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1675 status = connector_status_connected; 1676 if (intel_sdvo->is_hdmi) { 1677 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1678 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1679 intel_sdvo->rgb_quant_range_selectable = 1680 drm_rgb_quant_range_selectable(edid); 1681 } 1682 } else 1683 status = connector_status_disconnected; 1684 kfree(edid); 1685 } 1686 1687 if (status == connector_status_connected) { 1688 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1689 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) 1690 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); 1691 } 1692 1693 return status; 1694 } 1695 1696 static bool 1697 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 1698 struct edid *edid) 1699 { 1700 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1701 bool connector_is_digital = !!IS_DIGITAL(sdvo); 1702 1703 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 1704 connector_is_digital, monitor_is_digital); 1705 return connector_is_digital == monitor_is_digital; 1706 } 1707 1708 static enum drm_connector_status 1709 intel_sdvo_detect(struct drm_connector *connector, bool force) 1710 { 1711 uint16_t response; 1712 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1713 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1714 enum drm_connector_status ret; 1715 1716 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1717 connector->base.id, connector->name); 1718 1719 if (!intel_sdvo_get_value(intel_sdvo, 1720 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1721 &response, 2)) 1722 return connector_status_unknown; 1723 1724 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1725 response & 0xff, response >> 8, 1726 intel_sdvo_connector->output_flag); 1727 1728 if (response == 0) 1729 return connector_status_disconnected; 1730 1731 intel_sdvo->attached_output = response; 1732 1733 intel_sdvo->has_hdmi_monitor = false; 1734 intel_sdvo->has_hdmi_audio = false; 1735 intel_sdvo->rgb_quant_range_selectable = false; 1736 1737 if ((intel_sdvo_connector->output_flag & response) == 0) 1738 ret = connector_status_disconnected; 1739 else if (IS_TMDS(intel_sdvo_connector)) 1740 ret = intel_sdvo_tmds_sink_detect(connector); 1741 else { 1742 struct edid *edid; 1743 1744 /* if we have an edid check it matches the connection */ 1745 edid = intel_sdvo_get_edid(connector); 1746 if (edid == NULL) 1747 edid = intel_sdvo_get_analog_edid(connector); 1748 if (edid != NULL) { 1749 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 1750 edid)) 1751 ret = connector_status_connected; 1752 else 1753 ret = connector_status_disconnected; 1754 1755 kfree(edid); 1756 } else 1757 ret = connector_status_connected; 1758 } 1759 1760 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1761 if (ret == connector_status_connected) { 1762 intel_sdvo->is_tv = false; 1763 intel_sdvo->is_lvds = false; 1764 1765 if (response & SDVO_TV_MASK) 1766 intel_sdvo->is_tv = true; 1767 if (response & SDVO_LVDS_MASK) 1768 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1769 } 1770 1771 return ret; 1772 } 1773 1774 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1775 { 1776 struct edid *edid; 1777 1778 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1779 connector->base.id, connector->name); 1780 1781 /* set the bus switch and get the modes */ 1782 edid = intel_sdvo_get_edid(connector); 1783 1784 /* 1785 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1786 * link between analog and digital outputs. So, if the regular SDVO 1787 * DDC fails, check to see if the analog output is disconnected, in 1788 * which case we'll look there for the digital DDC data. 1789 */ 1790 if (edid == NULL) 1791 edid = intel_sdvo_get_analog_edid(connector); 1792 1793 if (edid != NULL) { 1794 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1795 edid)) { 1796 drm_mode_connector_update_edid_property(connector, edid); 1797 drm_add_edid_modes(connector, edid); 1798 } 1799 1800 kfree(edid); 1801 } 1802 } 1803 1804 /* 1805 * Set of SDVO TV modes. 1806 * Note! This is in reply order (see loop in get_tv_modes). 1807 * XXX: all 60Hz refresh? 1808 */ 1809 static const struct drm_display_mode sdvo_tv_modes[] = { 1810 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1811 416, 0, 200, 201, 232, 233, 0, 1812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1813 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1814 416, 0, 240, 241, 272, 273, 0, 1815 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1816 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1817 496, 0, 300, 301, 332, 333, 0, 1818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1819 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1820 736, 0, 350, 351, 382, 383, 0, 1821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1822 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1823 736, 0, 400, 401, 432, 433, 0, 1824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1825 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1826 736, 0, 480, 481, 512, 513, 0, 1827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1828 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1829 800, 0, 480, 481, 512, 513, 0, 1830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1831 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1832 800, 0, 576, 577, 608, 609, 0, 1833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1834 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1835 816, 0, 350, 351, 382, 383, 0, 1836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1837 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1838 816, 0, 400, 401, 432, 433, 0, 1839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1840 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1841 816, 0, 480, 481, 512, 513, 0, 1842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1843 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1844 816, 0, 540, 541, 572, 573, 0, 1845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1846 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1847 816, 0, 576, 577, 608, 609, 0, 1848 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1849 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1850 864, 0, 576, 577, 608, 609, 0, 1851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1852 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1853 896, 0, 600, 601, 632, 633, 0, 1854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1855 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1856 928, 0, 624, 625, 656, 657, 0, 1857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1858 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1859 1016, 0, 766, 767, 798, 799, 0, 1860 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1861 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1862 1120, 0, 768, 769, 800, 801, 0, 1863 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1864 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1865 1376, 0, 1024, 1025, 1056, 1057, 0, 1866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1867 }; 1868 1869 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1870 { 1871 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1872 struct intel_sdvo_sdtv_resolution_request tv_res; 1873 uint32_t reply = 0, format_map = 0; 1874 int i; 1875 1876 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1877 connector->base.id, connector->name); 1878 1879 /* Read the list of supported input resolutions for the selected TV 1880 * format. 1881 */ 1882 format_map = 1 << intel_sdvo->tv_format_index; 1883 memcpy(&tv_res, &format_map, 1884 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1885 1886 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1887 return; 1888 1889 BUILD_BUG_ON(sizeof(tv_res) != 3); 1890 if (!intel_sdvo_write_cmd(intel_sdvo, 1891 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1892 &tv_res, sizeof(tv_res))) 1893 return; 1894 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1895 return; 1896 1897 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1898 if (reply & (1 << i)) { 1899 struct drm_display_mode *nmode; 1900 nmode = drm_mode_duplicate(connector->dev, 1901 &sdvo_tv_modes[i]); 1902 if (nmode) 1903 drm_mode_probed_add(connector, nmode); 1904 } 1905 } 1906 1907 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1908 { 1909 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1910 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1911 struct drm_display_mode *newmode; 1912 1913 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1914 connector->base.id, connector->name); 1915 1916 /* 1917 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 1918 * SDVO->LVDS transcoders can't cope with the EDID mode. 1919 */ 1920 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 1921 newmode = drm_mode_duplicate(connector->dev, 1922 dev_priv->vbt.sdvo_lvds_vbt_mode); 1923 if (newmode != NULL) { 1924 /* Guarantee the mode is preferred */ 1925 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1926 DRM_MODE_TYPE_DRIVER); 1927 drm_mode_probed_add(connector, newmode); 1928 } 1929 } 1930 1931 /* 1932 * Attempt to get the mode list from DDC. 1933 * Assume that the preferred modes are 1934 * arranged in priority order. 1935 */ 1936 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 1937 1938 list_for_each_entry(newmode, &connector->probed_modes, head) { 1939 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1940 intel_sdvo->sdvo_lvds_fixed_mode = 1941 drm_mode_duplicate(connector->dev, newmode); 1942 1943 intel_sdvo->is_lvds = true; 1944 break; 1945 } 1946 } 1947 } 1948 1949 static int intel_sdvo_get_modes(struct drm_connector *connector) 1950 { 1951 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1952 1953 if (IS_TV(intel_sdvo_connector)) 1954 intel_sdvo_get_tv_modes(connector); 1955 else if (IS_LVDS(intel_sdvo_connector)) 1956 intel_sdvo_get_lvds_modes(connector); 1957 else 1958 intel_sdvo_get_ddc_modes(connector); 1959 1960 return !list_empty(&connector->probed_modes); 1961 } 1962 1963 static void intel_sdvo_destroy(struct drm_connector *connector) 1964 { 1965 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1966 1967 drm_connector_cleanup(connector); 1968 kfree(intel_sdvo_connector); 1969 } 1970 1971 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 1972 { 1973 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1974 struct edid *edid; 1975 bool has_audio = false; 1976 1977 if (!intel_sdvo->is_hdmi) 1978 return false; 1979 1980 edid = intel_sdvo_get_edid(connector); 1981 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 1982 has_audio = drm_detect_monitor_audio(edid); 1983 kfree(edid); 1984 1985 return has_audio; 1986 } 1987 1988 static int 1989 intel_sdvo_set_property(struct drm_connector *connector, 1990 struct drm_property *property, 1991 uint64_t val) 1992 { 1993 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1994 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1995 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1996 uint16_t temp_value; 1997 uint8_t cmd; 1998 int ret; 1999 2000 ret = drm_object_property_set_value(&connector->base, property, val); 2001 if (ret) 2002 return ret; 2003 2004 if (property == dev_priv->force_audio_property) { 2005 int i = val; 2006 bool has_audio; 2007 2008 if (i == intel_sdvo_connector->force_audio) 2009 return 0; 2010 2011 intel_sdvo_connector->force_audio = i; 2012 2013 if (i == HDMI_AUDIO_AUTO) 2014 has_audio = intel_sdvo_detect_hdmi_audio(connector); 2015 else 2016 has_audio = (i == HDMI_AUDIO_ON); 2017 2018 if (has_audio == intel_sdvo->has_hdmi_audio) 2019 return 0; 2020 2021 intel_sdvo->has_hdmi_audio = has_audio; 2022 goto done; 2023 } 2024 2025 if (property == dev_priv->broadcast_rgb_property) { 2026 bool old_auto = intel_sdvo->color_range_auto; 2027 uint32_t old_range = intel_sdvo->color_range; 2028 2029 switch (val) { 2030 case INTEL_BROADCAST_RGB_AUTO: 2031 intel_sdvo->color_range_auto = true; 2032 break; 2033 case INTEL_BROADCAST_RGB_FULL: 2034 intel_sdvo->color_range_auto = false; 2035 intel_sdvo->color_range = 0; 2036 break; 2037 case INTEL_BROADCAST_RGB_LIMITED: 2038 intel_sdvo->color_range_auto = false; 2039 /* FIXME: this bit is only valid when using TMDS 2040 * encoding and 8 bit per color mode. */ 2041 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 2042 break; 2043 default: 2044 return -EINVAL; 2045 } 2046 2047 if (old_auto == intel_sdvo->color_range_auto && 2048 old_range == intel_sdvo->color_range) 2049 return 0; 2050 2051 goto done; 2052 } 2053 2054 if (property == connector->dev->mode_config.aspect_ratio_property) { 2055 switch (val) { 2056 case DRM_MODE_PICTURE_ASPECT_NONE: 2057 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2058 break; 2059 case DRM_MODE_PICTURE_ASPECT_4_3: 2060 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 2061 break; 2062 case DRM_MODE_PICTURE_ASPECT_16_9: 2063 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 2064 break; 2065 default: 2066 return -EINVAL; 2067 } 2068 goto done; 2069 } 2070 2071 #define CHECK_PROPERTY(name, NAME) \ 2072 if (intel_sdvo_connector->name == property) { \ 2073 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 2074 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 2075 cmd = SDVO_CMD_SET_##NAME; \ 2076 intel_sdvo_connector->cur_##name = temp_value; \ 2077 goto set_value; \ 2078 } 2079 2080 if (property == intel_sdvo_connector->tv_format) { 2081 if (val >= TV_FORMAT_NUM) 2082 return -EINVAL; 2083 2084 if (intel_sdvo->tv_format_index == 2085 intel_sdvo_connector->tv_format_supported[val]) 2086 return 0; 2087 2088 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 2089 goto done; 2090 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 2091 temp_value = val; 2092 if (intel_sdvo_connector->left == property) { 2093 drm_object_property_set_value(&connector->base, 2094 intel_sdvo_connector->right, val); 2095 if (intel_sdvo_connector->left_margin == temp_value) 2096 return 0; 2097 2098 intel_sdvo_connector->left_margin = temp_value; 2099 intel_sdvo_connector->right_margin = temp_value; 2100 temp_value = intel_sdvo_connector->max_hscan - 2101 intel_sdvo_connector->left_margin; 2102 cmd = SDVO_CMD_SET_OVERSCAN_H; 2103 goto set_value; 2104 } else if (intel_sdvo_connector->right == property) { 2105 drm_object_property_set_value(&connector->base, 2106 intel_sdvo_connector->left, val); 2107 if (intel_sdvo_connector->right_margin == temp_value) 2108 return 0; 2109 2110 intel_sdvo_connector->left_margin = temp_value; 2111 intel_sdvo_connector->right_margin = temp_value; 2112 temp_value = intel_sdvo_connector->max_hscan - 2113 intel_sdvo_connector->left_margin; 2114 cmd = SDVO_CMD_SET_OVERSCAN_H; 2115 goto set_value; 2116 } else if (intel_sdvo_connector->top == property) { 2117 drm_object_property_set_value(&connector->base, 2118 intel_sdvo_connector->bottom, val); 2119 if (intel_sdvo_connector->top_margin == temp_value) 2120 return 0; 2121 2122 intel_sdvo_connector->top_margin = temp_value; 2123 intel_sdvo_connector->bottom_margin = temp_value; 2124 temp_value = intel_sdvo_connector->max_vscan - 2125 intel_sdvo_connector->top_margin; 2126 cmd = SDVO_CMD_SET_OVERSCAN_V; 2127 goto set_value; 2128 } else if (intel_sdvo_connector->bottom == property) { 2129 drm_object_property_set_value(&connector->base, 2130 intel_sdvo_connector->top, val); 2131 if (intel_sdvo_connector->bottom_margin == temp_value) 2132 return 0; 2133 2134 intel_sdvo_connector->top_margin = temp_value; 2135 intel_sdvo_connector->bottom_margin = temp_value; 2136 temp_value = intel_sdvo_connector->max_vscan - 2137 intel_sdvo_connector->top_margin; 2138 cmd = SDVO_CMD_SET_OVERSCAN_V; 2139 goto set_value; 2140 } 2141 CHECK_PROPERTY(hpos, HPOS) 2142 CHECK_PROPERTY(vpos, VPOS) 2143 CHECK_PROPERTY(saturation, SATURATION) 2144 CHECK_PROPERTY(contrast, CONTRAST) 2145 CHECK_PROPERTY(hue, HUE) 2146 CHECK_PROPERTY(brightness, BRIGHTNESS) 2147 CHECK_PROPERTY(sharpness, SHARPNESS) 2148 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 2149 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 2150 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 2151 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 2152 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 2153 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 2154 } 2155 2156 return -EINVAL; /* unknown property */ 2157 2158 set_value: 2159 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 2160 return -EIO; 2161 2162 2163 done: 2164 if (intel_sdvo->base.base.crtc) 2165 intel_crtc_restore_mode(intel_sdvo->base.base.crtc); 2166 2167 return 0; 2168 #undef CHECK_PROPERTY 2169 } 2170 2171 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2172 .dpms = drm_atomic_helper_connector_dpms, 2173 .detect = intel_sdvo_detect, 2174 .fill_modes = drm_helper_probe_single_connector_modes, 2175 .set_property = intel_sdvo_set_property, 2176 .atomic_get_property = intel_connector_atomic_get_property, 2177 .destroy = intel_sdvo_destroy, 2178 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2179 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2180 }; 2181 2182 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2183 .get_modes = intel_sdvo_get_modes, 2184 .mode_valid = intel_sdvo_mode_valid, 2185 .best_encoder = intel_best_encoder, 2186 }; 2187 2188 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2189 { 2190 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2191 2192 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 2193 drm_mode_destroy(encoder->dev, 2194 intel_sdvo->sdvo_lvds_fixed_mode); 2195 2196 i2c_del_adapter(&intel_sdvo->ddc); 2197 intel_encoder_destroy(encoder); 2198 } 2199 2200 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2201 .destroy = intel_sdvo_enc_destroy, 2202 }; 2203 2204 static void 2205 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2206 { 2207 uint16_t mask = 0; 2208 unsigned int num_bits; 2209 2210 /* Make a mask of outputs less than or equal to our own priority in the 2211 * list. 2212 */ 2213 switch (sdvo->controlled_output) { 2214 case SDVO_OUTPUT_LVDS1: 2215 mask |= SDVO_OUTPUT_LVDS1; 2216 case SDVO_OUTPUT_LVDS0: 2217 mask |= SDVO_OUTPUT_LVDS0; 2218 case SDVO_OUTPUT_TMDS1: 2219 mask |= SDVO_OUTPUT_TMDS1; 2220 case SDVO_OUTPUT_TMDS0: 2221 mask |= SDVO_OUTPUT_TMDS0; 2222 case SDVO_OUTPUT_RGB1: 2223 mask |= SDVO_OUTPUT_RGB1; 2224 case SDVO_OUTPUT_RGB0: 2225 mask |= SDVO_OUTPUT_RGB0; 2226 break; 2227 } 2228 2229 /* Count bits to find what number we are in the priority list. */ 2230 mask &= sdvo->caps.output_flags; 2231 num_bits = hweight16(mask); 2232 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2233 if (num_bits > 3) 2234 num_bits = 3; 2235 2236 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2237 sdvo->ddc_bus = 1 << num_bits; 2238 } 2239 2240 /** 2241 * Choose the appropriate DDC bus for control bus switch command for this 2242 * SDVO output based on the controlled output. 2243 * 2244 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2245 * outputs, then LVDS outputs. 2246 */ 2247 static void 2248 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2249 struct intel_sdvo *sdvo) 2250 { 2251 struct sdvo_device_mapping *mapping; 2252 2253 if (sdvo->is_sdvob) 2254 mapping = &(dev_priv->sdvo_mappings[0]); 2255 else 2256 mapping = &(dev_priv->sdvo_mappings[1]); 2257 2258 if (mapping->initialized) 2259 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2260 else 2261 intel_sdvo_guess_ddc_bus(sdvo); 2262 } 2263 2264 static void 2265 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2266 struct intel_sdvo *sdvo) 2267 { 2268 struct sdvo_device_mapping *mapping; 2269 u8 pin; 2270 2271 if (sdvo->is_sdvob) 2272 mapping = &dev_priv->sdvo_mappings[0]; 2273 else 2274 mapping = &dev_priv->sdvo_mappings[1]; 2275 2276 if (mapping->initialized && 2277 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2278 pin = mapping->i2c_pin; 2279 else 2280 pin = GMBUS_PIN_DPB; 2281 2282 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2283 2284 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2285 * our code totally fails once we start using gmbus. Hence fall back to 2286 * bit banging for now. */ 2287 intel_gmbus_force_bit(sdvo->i2c, true); 2288 } 2289 2290 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2291 static void 2292 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2293 { 2294 intel_gmbus_force_bit(sdvo->i2c, false); 2295 } 2296 2297 static bool 2298 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2299 { 2300 return intel_sdvo_check_supp_encode(intel_sdvo); 2301 } 2302 2303 static u8 2304 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) 2305 { 2306 struct drm_i915_private *dev_priv = dev->dev_private; 2307 struct sdvo_device_mapping *my_mapping, *other_mapping; 2308 2309 if (sdvo->is_sdvob) { 2310 my_mapping = &dev_priv->sdvo_mappings[0]; 2311 other_mapping = &dev_priv->sdvo_mappings[1]; 2312 } else { 2313 my_mapping = &dev_priv->sdvo_mappings[1]; 2314 other_mapping = &dev_priv->sdvo_mappings[0]; 2315 } 2316 2317 /* If the BIOS described our SDVO device, take advantage of it. */ 2318 if (my_mapping->slave_addr) 2319 return my_mapping->slave_addr; 2320 2321 /* If the BIOS only described a different SDVO device, use the 2322 * address that it isn't using. 2323 */ 2324 if (other_mapping->slave_addr) { 2325 if (other_mapping->slave_addr == 0x70) 2326 return 0x72; 2327 else 2328 return 0x70; 2329 } 2330 2331 /* No SDVO device info is found for another DVO port, 2332 * so use mapping assumption we had before BIOS parsing. 2333 */ 2334 if (sdvo->is_sdvob) 2335 return 0x70; 2336 else 2337 return 0x72; 2338 } 2339 2340 static void 2341 intel_sdvo_connector_unregister(struct intel_connector *intel_connector) 2342 { 2343 struct drm_connector *drm_connector; 2344 struct intel_sdvo *sdvo_encoder; 2345 2346 drm_connector = &intel_connector->base; 2347 sdvo_encoder = intel_attached_sdvo(&intel_connector->base); 2348 2349 #if 0 2350 sysfs_remove_link(&drm_connector->kdev->kobj, 2351 sdvo_encoder->ddc.dev.kobj.name); 2352 #endif 2353 intel_connector_unregister(intel_connector); 2354 } 2355 2356 static int 2357 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2358 struct intel_sdvo *encoder) 2359 { 2360 struct drm_connector *drm_connector; 2361 int ret; 2362 2363 drm_connector = &connector->base.base; 2364 ret = drm_connector_init(encoder->base.base.dev, 2365 drm_connector, 2366 &intel_sdvo_connector_funcs, 2367 connector->base.base.connector_type); 2368 if (ret < 0) 2369 return ret; 2370 2371 drm_connector_helper_add(drm_connector, 2372 &intel_sdvo_connector_helper_funcs); 2373 2374 connector->base.base.interlace_allowed = 1; 2375 connector->base.base.doublescan_allowed = 0; 2376 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2377 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2378 connector->base.unregister = intel_sdvo_connector_unregister; 2379 2380 intel_connector_attach_encoder(&connector->base, &encoder->base); 2381 ret = drm_connector_register(drm_connector); 2382 if (ret < 0) 2383 goto err1; 2384 2385 #if 0 2386 ret = sysfs_create_link(&drm_connector->kdev->kobj, 2387 &encoder->ddc.dev.kobj, 2388 encoder->ddc.dev.kobj.name); 2389 if (ret < 0) 2390 goto err2; 2391 2392 return 0; 2393 2394 err2: 2395 #endif 2396 drm_connector_unregister(drm_connector); 2397 err1: 2398 drm_connector_cleanup(drm_connector); 2399 2400 return ret; 2401 } 2402 2403 static void 2404 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2405 struct intel_sdvo_connector *connector) 2406 { 2407 struct drm_device *dev = connector->base.base.dev; 2408 2409 intel_attach_force_audio_property(&connector->base.base); 2410 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { 2411 intel_attach_broadcast_rgb_property(&connector->base.base); 2412 intel_sdvo->color_range_auto = true; 2413 } 2414 intel_attach_aspect_ratio_property(&connector->base.base); 2415 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2416 } 2417 2418 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2419 { 2420 struct intel_sdvo_connector *sdvo_connector; 2421 2422 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2423 if (!sdvo_connector) 2424 return NULL; 2425 2426 if (intel_connector_init(&sdvo_connector->base) < 0) { 2427 kfree(sdvo_connector); 2428 return NULL; 2429 } 2430 2431 return sdvo_connector; 2432 } 2433 2434 static bool 2435 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2436 { 2437 struct drm_encoder *encoder = &intel_sdvo->base.base; 2438 struct drm_connector *connector; 2439 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2440 struct intel_connector *intel_connector; 2441 struct intel_sdvo_connector *intel_sdvo_connector; 2442 2443 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2444 2445 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2446 if (!intel_sdvo_connector) 2447 return false; 2448 2449 if (device == 0) { 2450 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2451 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2452 } else if (device == 1) { 2453 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2454 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2455 } 2456 2457 intel_connector = &intel_sdvo_connector->base; 2458 connector = &intel_connector->base; 2459 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2460 intel_sdvo_connector->output_flag) { 2461 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2462 /* Some SDVO devices have one-shot hotplug interrupts. 2463 * Ensure that they get re-enabled when an interrupt happens. 2464 */ 2465 intel_encoder->hot_plug = intel_sdvo_enable_hotplug; 2466 intel_sdvo_enable_hotplug(intel_encoder); 2467 } else { 2468 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2469 } 2470 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2471 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2472 2473 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2474 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2475 intel_sdvo->is_hdmi = true; 2476 } 2477 2478 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2479 kfree(intel_sdvo_connector); 2480 return false; 2481 } 2482 2483 if (intel_sdvo->is_hdmi) 2484 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2485 2486 return true; 2487 } 2488 2489 static bool 2490 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2491 { 2492 struct drm_encoder *encoder = &intel_sdvo->base.base; 2493 struct drm_connector *connector; 2494 struct intel_connector *intel_connector; 2495 struct intel_sdvo_connector *intel_sdvo_connector; 2496 2497 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2498 2499 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2500 if (!intel_sdvo_connector) 2501 return false; 2502 2503 intel_connector = &intel_sdvo_connector->base; 2504 connector = &intel_connector->base; 2505 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2506 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2507 2508 intel_sdvo->controlled_output |= type; 2509 intel_sdvo_connector->output_flag = type; 2510 2511 intel_sdvo->is_tv = true; 2512 2513 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2514 kfree(intel_sdvo_connector); 2515 return false; 2516 } 2517 2518 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2519 goto err; 2520 2521 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2522 goto err; 2523 2524 return true; 2525 2526 err: 2527 drm_connector_unregister(connector); 2528 intel_sdvo_destroy(connector); 2529 return false; 2530 } 2531 2532 static bool 2533 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2534 { 2535 struct drm_encoder *encoder = &intel_sdvo->base.base; 2536 struct drm_connector *connector; 2537 struct intel_connector *intel_connector; 2538 struct intel_sdvo_connector *intel_sdvo_connector; 2539 2540 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2541 2542 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2543 if (!intel_sdvo_connector) 2544 return false; 2545 2546 intel_connector = &intel_sdvo_connector->base; 2547 connector = &intel_connector->base; 2548 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2549 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2550 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2551 2552 if (device == 0) { 2553 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2554 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2555 } else if (device == 1) { 2556 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2557 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2558 } 2559 2560 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2561 kfree(intel_sdvo_connector); 2562 return false; 2563 } 2564 2565 return true; 2566 } 2567 2568 static bool 2569 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2570 { 2571 struct drm_encoder *encoder = &intel_sdvo->base.base; 2572 struct drm_connector *connector; 2573 struct intel_connector *intel_connector; 2574 struct intel_sdvo_connector *intel_sdvo_connector; 2575 2576 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2577 2578 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2579 if (!intel_sdvo_connector) 2580 return false; 2581 2582 intel_connector = &intel_sdvo_connector->base; 2583 connector = &intel_connector->base; 2584 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2585 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2586 2587 if (device == 0) { 2588 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2589 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2590 } else if (device == 1) { 2591 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2592 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2593 } 2594 2595 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2596 kfree(intel_sdvo_connector); 2597 return false; 2598 } 2599 2600 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2601 goto err; 2602 2603 return true; 2604 2605 err: 2606 drm_connector_unregister(connector); 2607 intel_sdvo_destroy(connector); 2608 return false; 2609 } 2610 2611 static bool 2612 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2613 { 2614 intel_sdvo->is_tv = false; 2615 intel_sdvo->is_lvds = false; 2616 2617 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2618 2619 if (flags & SDVO_OUTPUT_TMDS0) 2620 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2621 return false; 2622 2623 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2624 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2625 return false; 2626 2627 /* TV has no XXX1 function block */ 2628 if (flags & SDVO_OUTPUT_SVID0) 2629 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2630 return false; 2631 2632 if (flags & SDVO_OUTPUT_CVBS0) 2633 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2634 return false; 2635 2636 if (flags & SDVO_OUTPUT_YPRPB0) 2637 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2638 return false; 2639 2640 if (flags & SDVO_OUTPUT_RGB0) 2641 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2642 return false; 2643 2644 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2645 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2646 return false; 2647 2648 if (flags & SDVO_OUTPUT_LVDS0) 2649 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2650 return false; 2651 2652 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2653 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2654 return false; 2655 2656 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2657 unsigned char bytes[2]; 2658 2659 intel_sdvo->controlled_output = 0; 2660 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2661 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2662 SDVO_NAME(intel_sdvo), 2663 bytes[0], bytes[1]); 2664 return false; 2665 } 2666 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2667 2668 return true; 2669 } 2670 2671 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2672 { 2673 struct drm_device *dev = intel_sdvo->base.base.dev; 2674 struct drm_connector *connector, *tmp; 2675 2676 list_for_each_entry_safe(connector, tmp, 2677 &dev->mode_config.connector_list, head) { 2678 if (intel_attached_encoder(connector) == &intel_sdvo->base) { 2679 drm_connector_unregister(connector); 2680 intel_sdvo_destroy(connector); 2681 } 2682 } 2683 } 2684 2685 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2686 struct intel_sdvo_connector *intel_sdvo_connector, 2687 int type) 2688 { 2689 struct drm_device *dev = intel_sdvo->base.base.dev; 2690 struct intel_sdvo_tv_format format; 2691 uint32_t format_map, i; 2692 2693 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2694 return false; 2695 2696 BUILD_BUG_ON(sizeof(format) != 6); 2697 if (!intel_sdvo_get_value(intel_sdvo, 2698 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2699 &format, sizeof(format))) 2700 return false; 2701 2702 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2703 2704 if (format_map == 0) 2705 return false; 2706 2707 intel_sdvo_connector->format_supported_num = 0; 2708 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2709 if (format_map & (1 << i)) 2710 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2711 2712 2713 intel_sdvo_connector->tv_format = 2714 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2715 "mode", intel_sdvo_connector->format_supported_num); 2716 if (!intel_sdvo_connector->tv_format) 2717 return false; 2718 2719 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2720 drm_property_add_enum( 2721 intel_sdvo_connector->tv_format, i, 2722 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2723 2724 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2725 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2726 intel_sdvo_connector->tv_format, 0); 2727 return true; 2728 2729 } 2730 2731 #define ENHANCEMENT(name, NAME) do { \ 2732 if (enhancements.name) { \ 2733 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2734 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2735 return false; \ 2736 intel_sdvo_connector->max_##name = data_value[0]; \ 2737 intel_sdvo_connector->cur_##name = response; \ 2738 intel_sdvo_connector->name = \ 2739 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2740 if (!intel_sdvo_connector->name) return false; \ 2741 drm_object_attach_property(&connector->base, \ 2742 intel_sdvo_connector->name, \ 2743 intel_sdvo_connector->cur_##name); \ 2744 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2745 data_value[0], data_value[1], response); \ 2746 } \ 2747 } while (0) 2748 2749 static bool 2750 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2751 struct intel_sdvo_connector *intel_sdvo_connector, 2752 struct intel_sdvo_enhancements_reply enhancements) 2753 { 2754 struct drm_device *dev = intel_sdvo->base.base.dev; 2755 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2756 uint16_t response, data_value[2]; 2757 2758 /* when horizontal overscan is supported, Add the left/right property */ 2759 if (enhancements.overscan_h) { 2760 if (!intel_sdvo_get_value(intel_sdvo, 2761 SDVO_CMD_GET_MAX_OVERSCAN_H, 2762 &data_value, 4)) 2763 return false; 2764 2765 if (!intel_sdvo_get_value(intel_sdvo, 2766 SDVO_CMD_GET_OVERSCAN_H, 2767 &response, 2)) 2768 return false; 2769 2770 intel_sdvo_connector->max_hscan = data_value[0]; 2771 intel_sdvo_connector->left_margin = data_value[0] - response; 2772 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2773 intel_sdvo_connector->left = 2774 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2775 if (!intel_sdvo_connector->left) 2776 return false; 2777 2778 drm_object_attach_property(&connector->base, 2779 intel_sdvo_connector->left, 2780 intel_sdvo_connector->left_margin); 2781 2782 intel_sdvo_connector->right = 2783 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2784 if (!intel_sdvo_connector->right) 2785 return false; 2786 2787 drm_object_attach_property(&connector->base, 2788 intel_sdvo_connector->right, 2789 intel_sdvo_connector->right_margin); 2790 DRM_DEBUG_KMS("h_overscan: max %d, " 2791 "default %d, current %d\n", 2792 data_value[0], data_value[1], response); 2793 } 2794 2795 if (enhancements.overscan_v) { 2796 if (!intel_sdvo_get_value(intel_sdvo, 2797 SDVO_CMD_GET_MAX_OVERSCAN_V, 2798 &data_value, 4)) 2799 return false; 2800 2801 if (!intel_sdvo_get_value(intel_sdvo, 2802 SDVO_CMD_GET_OVERSCAN_V, 2803 &response, 2)) 2804 return false; 2805 2806 intel_sdvo_connector->max_vscan = data_value[0]; 2807 intel_sdvo_connector->top_margin = data_value[0] - response; 2808 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2809 intel_sdvo_connector->top = 2810 drm_property_create_range(dev, 0, 2811 "top_margin", 0, data_value[0]); 2812 if (!intel_sdvo_connector->top) 2813 return false; 2814 2815 drm_object_attach_property(&connector->base, 2816 intel_sdvo_connector->top, 2817 intel_sdvo_connector->top_margin); 2818 2819 intel_sdvo_connector->bottom = 2820 drm_property_create_range(dev, 0, 2821 "bottom_margin", 0, data_value[0]); 2822 if (!intel_sdvo_connector->bottom) 2823 return false; 2824 2825 drm_object_attach_property(&connector->base, 2826 intel_sdvo_connector->bottom, 2827 intel_sdvo_connector->bottom_margin); 2828 DRM_DEBUG_KMS("v_overscan: max %d, " 2829 "default %d, current %d\n", 2830 data_value[0], data_value[1], response); 2831 } 2832 2833 ENHANCEMENT(hpos, HPOS); 2834 ENHANCEMENT(vpos, VPOS); 2835 ENHANCEMENT(saturation, SATURATION); 2836 ENHANCEMENT(contrast, CONTRAST); 2837 ENHANCEMENT(hue, HUE); 2838 ENHANCEMENT(sharpness, SHARPNESS); 2839 ENHANCEMENT(brightness, BRIGHTNESS); 2840 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2841 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2842 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2843 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2844 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2845 2846 if (enhancements.dot_crawl) { 2847 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2848 return false; 2849 2850 intel_sdvo_connector->max_dot_crawl = 1; 2851 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2852 intel_sdvo_connector->dot_crawl = 2853 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2854 if (!intel_sdvo_connector->dot_crawl) 2855 return false; 2856 2857 drm_object_attach_property(&connector->base, 2858 intel_sdvo_connector->dot_crawl, 2859 intel_sdvo_connector->cur_dot_crawl); 2860 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2861 } 2862 2863 return true; 2864 } 2865 2866 static bool 2867 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2868 struct intel_sdvo_connector *intel_sdvo_connector, 2869 struct intel_sdvo_enhancements_reply enhancements) 2870 { 2871 struct drm_device *dev = intel_sdvo->base.base.dev; 2872 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2873 uint16_t response, data_value[2]; 2874 2875 ENHANCEMENT(brightness, BRIGHTNESS); 2876 2877 return true; 2878 } 2879 #undef ENHANCEMENT 2880 2881 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2882 struct intel_sdvo_connector *intel_sdvo_connector) 2883 { 2884 union { 2885 struct intel_sdvo_enhancements_reply reply; 2886 uint16_t response; 2887 } enhancements; 2888 2889 BUILD_BUG_ON(sizeof(enhancements) != 2); 2890 2891 enhancements.response = 0; 2892 intel_sdvo_get_value(intel_sdvo, 2893 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2894 &enhancements, sizeof(enhancements)); 2895 if (enhancements.response == 0) { 2896 DRM_DEBUG_KMS("No enhancement is supported\n"); 2897 return true; 2898 } 2899 2900 if (IS_TV(intel_sdvo_connector)) 2901 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2902 else if (IS_LVDS(intel_sdvo_connector)) 2903 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2904 else 2905 return true; 2906 } 2907 2908 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 2909 struct i2c_msg *msgs, 2910 int num) 2911 { 2912 struct intel_sdvo *sdvo = adapter->algo_data; 2913 2914 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2915 return -EIO; 2916 2917 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 2918 } 2919 2920 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 2921 { 2922 struct intel_sdvo *sdvo = adapter->algo_data; 2923 return sdvo->i2c->algo->functionality(sdvo->i2c); 2924 } 2925 2926 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 2927 .master_xfer = intel_sdvo_ddc_proxy_xfer, 2928 .functionality = intel_sdvo_ddc_proxy_func 2929 }; 2930 2931 static bool 2932 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 2933 struct drm_device *dev) 2934 { 2935 #if 0 2936 sdvo->ddc.owner = THIS_MODULE; 2937 sdvo->ddc.class = I2C_CLASS_DDC; 2938 #endif 2939 ksnprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 2940 sdvo->ddc.dev.parent = &dev->pdev->dev; 2941 sdvo->ddc.algo_data = sdvo; 2942 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 2943 2944 return i2c_add_adapter(&sdvo->ddc) == 0; 2945 } 2946 2947 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) 2948 { 2949 struct drm_i915_private *dev_priv = dev->dev_private; 2950 struct intel_encoder *intel_encoder; 2951 struct intel_sdvo *intel_sdvo; 2952 int i; 2953 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 2954 if (!intel_sdvo) 2955 return false; 2956 2957 intel_sdvo->sdvo_reg = sdvo_reg; 2958 intel_sdvo->is_sdvob = is_sdvob; 2959 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; 2960 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 2961 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) 2962 goto err_i2c_bus; 2963 2964 /* encoder type will be decided later */ 2965 intel_encoder = &intel_sdvo->base; 2966 intel_encoder->type = INTEL_OUTPUT_SDVO; 2967 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); 2968 2969 /* Read the regs to test if we can talk to the device */ 2970 for (i = 0; i < 0x40; i++) { 2971 u8 byte; 2972 2973 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 2974 DRM_DEBUG_KMS("No SDVO device found on %s\n", 2975 SDVO_NAME(intel_sdvo)); 2976 goto err; 2977 } 2978 } 2979 2980 intel_encoder->compute_config = intel_sdvo_compute_config; 2981 if (HAS_PCH_SPLIT(dev)) { 2982 intel_encoder->disable = pch_disable_sdvo; 2983 intel_encoder->post_disable = pch_post_disable_sdvo; 2984 } else { 2985 intel_encoder->disable = intel_disable_sdvo; 2986 } 2987 intel_encoder->pre_enable = intel_sdvo_pre_enable; 2988 intel_encoder->enable = intel_enable_sdvo; 2989 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 2990 intel_encoder->get_config = intel_sdvo_get_config; 2991 2992 /* In default case sdvo lvds is false */ 2993 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 2994 goto err; 2995 2996 if (intel_sdvo_output_setup(intel_sdvo, 2997 intel_sdvo->caps.output_flags) != true) { 2998 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 2999 SDVO_NAME(intel_sdvo)); 3000 /* Output_setup can leave behind connectors! */ 3001 goto err_output; 3002 } 3003 3004 /* Only enable the hotplug irq if we need it, to work around noisy 3005 * hotplug lines. 3006 */ 3007 if (intel_sdvo->hotplug_active) { 3008 intel_encoder->hpd_pin = 3009 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; 3010 } 3011 3012 /* 3013 * Cloning SDVO with anything is often impossible, since the SDVO 3014 * encoder can request a special input timing mode. And even if that's 3015 * not the case we have evidence that cloning a plain unscaled mode with 3016 * VGA doesn't really work. Furthermore the cloning flags are way too 3017 * simplistic anyway to express such constraints, so just give up on 3018 * cloning for SDVO encoders. 3019 */ 3020 intel_sdvo->base.cloneable = 0; 3021 3022 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); 3023 3024 /* Set the input timing to the screen. Assume always input 0. */ 3025 if (!intel_sdvo_set_target_input(intel_sdvo)) 3026 goto err_output; 3027 3028 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3029 &intel_sdvo->pixel_clock_min, 3030 &intel_sdvo->pixel_clock_max)) 3031 goto err_output; 3032 3033 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3034 "clock range %dMHz - %dMHz, " 3035 "input 1: %c, input 2: %c, " 3036 "output 1: %c, output 2: %c\n", 3037 SDVO_NAME(intel_sdvo), 3038 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3039 intel_sdvo->caps.device_rev_id, 3040 intel_sdvo->pixel_clock_min / 1000, 3041 intel_sdvo->pixel_clock_max / 1000, 3042 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3043 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3044 /* check currently supported outputs */ 3045 intel_sdvo->caps.output_flags & 3046 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3047 intel_sdvo->caps.output_flags & 3048 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3049 return true; 3050 3051 err_output: 3052 intel_sdvo_output_cleanup(intel_sdvo); 3053 3054 err: 3055 drm_encoder_cleanup(&intel_encoder->base); 3056 i2c_del_adapter(&intel_sdvo->ddc); 3057 err_i2c_bus: 3058 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3059 kfree(intel_sdvo); 3060 3061 return false; 3062 } 3063