1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 #include <linux/i2c.h> 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_atomic_helper.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 #include "intel_sdvo_regs.h" 39 40 #include <bus/iicbus/iic.h> 41 #include <bus/iicbus/iiconf.h> 42 #include "iicbus_if.h" 43 44 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 45 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 46 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 47 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 48 49 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 50 SDVO_TV_MASK) 51 52 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 53 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 54 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 55 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 56 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 57 58 59 static const char *tv_format_names[] = { 60 "NTSC_M" , "NTSC_J" , "NTSC_443", 61 "PAL_B" , "PAL_D" , "PAL_G" , 62 "PAL_H" , "PAL_I" , "PAL_M" , 63 "PAL_N" , "PAL_NC" , "PAL_60" , 64 "SECAM_B" , "SECAM_D" , "SECAM_G" , 65 "SECAM_K" , "SECAM_K1", "SECAM_L" , 66 "SECAM_60" 67 }; 68 69 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) 70 71 struct intel_sdvo { 72 struct intel_encoder base; 73 74 struct device *i2c; 75 u8 slave_addr; 76 77 device_t ddc_iic_bus, ddc; 78 79 /* Register for the SDVO device: SDVOB or SDVOC */ 80 uint32_t sdvo_reg; 81 82 /* Active outputs controlled by this SDVO output */ 83 uint16_t controlled_output; 84 85 /* 86 * Capabilities of the SDVO device returned by 87 * intel_sdvo_get_capabilities() 88 */ 89 struct intel_sdvo_caps caps; 90 91 /* Pixel clock limitations reported by the SDVO device, in kHz */ 92 int pixel_clock_min, pixel_clock_max; 93 94 /* 95 * For multiple function SDVO device, 96 * this is for current attached outputs. 97 */ 98 uint16_t attached_output; 99 100 /* 101 * Hotplug activation bits for this device 102 */ 103 uint16_t hotplug_active; 104 105 /** 106 * This is used to select the color range of RBG outputs in HDMI mode. 107 * It is only valid when using TMDS encoding and 8 bit per color mode. 108 */ 109 uint32_t color_range; 110 bool color_range_auto; 111 112 /** 113 * This is set if we're going to treat the device as TV-out. 114 * 115 * While we have these nice friendly flags for output types that ought 116 * to decide this for us, the S-Video output on our HDMI+S-Video card 117 * shows up as RGB1 (VGA). 118 */ 119 bool is_tv; 120 121 /* On different gens SDVOB is at different places. */ 122 bool is_sdvob; 123 124 /* This is for current tv format name */ 125 int tv_format_index; 126 127 /** 128 * This is set if we treat the device as HDMI, instead of DVI. 129 */ 130 bool is_hdmi; 131 bool has_hdmi_monitor; 132 bool has_hdmi_audio; 133 bool rgb_quant_range_selectable; 134 135 /** 136 * This is set if we detect output of sdvo device as LVDS and 137 * have a valid fixed mode to use with the panel. 138 */ 139 bool is_lvds; 140 141 /** 142 * This is sdvo fixed pannel mode pointer 143 */ 144 struct drm_display_mode *sdvo_lvds_fixed_mode; 145 146 /* DDC bus used by this SDVO encoder */ 147 uint8_t ddc_bus; 148 149 /* 150 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 151 */ 152 uint8_t dtd_sdvo_flags; 153 }; 154 155 struct intel_sdvo_connector { 156 struct intel_connector base; 157 158 /* Mark the type of connector */ 159 uint16_t output_flag; 160 161 enum hdmi_force_audio force_audio; 162 163 /* This contains all current supported TV format */ 164 u8 tv_format_supported[TV_FORMAT_NUM]; 165 int format_supported_num; 166 struct drm_property *tv_format; 167 168 /* add the property for the SDVO-TV */ 169 struct drm_property *left; 170 struct drm_property *right; 171 struct drm_property *top; 172 struct drm_property *bottom; 173 struct drm_property *hpos; 174 struct drm_property *vpos; 175 struct drm_property *contrast; 176 struct drm_property *saturation; 177 struct drm_property *hue; 178 struct drm_property *sharpness; 179 struct drm_property *flicker_filter; 180 struct drm_property *flicker_filter_adaptive; 181 struct drm_property *flicker_filter_2d; 182 struct drm_property *tv_chroma_filter; 183 struct drm_property *tv_luma_filter; 184 struct drm_property *dot_crawl; 185 186 /* add the property for the SDVO-TV/LVDS */ 187 struct drm_property *brightness; 188 189 /* Add variable to record current setting for the above property */ 190 u32 left_margin, right_margin, top_margin, bottom_margin; 191 192 /* this is to get the range of margin.*/ 193 u32 max_hscan, max_vscan; 194 u32 max_hpos, cur_hpos; 195 u32 max_vpos, cur_vpos; 196 u32 cur_brightness, max_brightness; 197 u32 cur_contrast, max_contrast; 198 u32 cur_saturation, max_saturation; 199 u32 cur_hue, max_hue; 200 u32 cur_sharpness, max_sharpness; 201 u32 cur_flicker_filter, max_flicker_filter; 202 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 203 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 204 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 205 u32 cur_tv_luma_filter, max_tv_luma_filter; 206 u32 cur_dot_crawl, max_dot_crawl; 207 }; 208 209 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 210 { 211 return container_of(encoder, struct intel_sdvo, base); 212 } 213 214 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 215 { 216 return to_sdvo(intel_attached_encoder(connector)); 217 } 218 219 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 220 { 221 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 222 } 223 224 static bool 225 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 226 static bool 227 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 228 struct intel_sdvo_connector *intel_sdvo_connector, 229 int type); 230 static bool 231 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 232 struct intel_sdvo_connector *intel_sdvo_connector); 233 234 /** 235 * Writes the SDVOB or SDVOC with the given value, but always writes both 236 * SDVOB and SDVOC to work around apparent hardware issues (according to 237 * comments in the BIOS). 238 */ 239 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 240 { 241 struct drm_device *dev = intel_sdvo->base.base.dev; 242 struct drm_i915_private *dev_priv = dev->dev_private; 243 u32 bval = val, cval = val; 244 int i; 245 246 if (intel_sdvo->sdvo_reg == PCH_SDVOB) { 247 I915_WRITE(intel_sdvo->sdvo_reg, val); 248 I915_READ(intel_sdvo->sdvo_reg); 249 return; 250 } 251 252 if (intel_sdvo->sdvo_reg == GEN3_SDVOB) 253 cval = I915_READ(GEN3_SDVOC); 254 else 255 bval = I915_READ(GEN3_SDVOB); 256 257 /* 258 * Write the registers twice for luck. Sometimes, 259 * writing them only once doesn't appear to 'stick'. 260 * The BIOS does this too. Yay, magic 261 */ 262 for (i = 0; i < 2; i++) 263 { 264 I915_WRITE(GEN3_SDVOB, bval); 265 I915_READ(GEN3_SDVOB); 266 I915_WRITE(GEN3_SDVOC, cval); 267 I915_READ(GEN3_SDVOC); 268 } 269 } 270 271 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 272 { 273 struct i2c_msg msgs[] = { 274 { 275 .slave = intel_sdvo->slave_addr << 1, 276 .flags = 0, 277 .len = 1, 278 .buf = &addr, 279 }, 280 { 281 .slave = intel_sdvo->slave_addr << 1, 282 .flags = I2C_M_RD, 283 .len = 1, 284 .buf = ch, 285 } 286 }; 287 int ret; 288 289 if ((ret = iicbus_transfer(intel_sdvo->i2c, msgs, 2)) == 0) 290 return true; 291 292 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 293 return false; 294 } 295 296 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 297 /** Mapping of command numbers to names, for debug output */ 298 static const struct _sdvo_cmd_name { 299 u8 cmd; 300 const char *name; 301 } sdvo_cmd_names[] = { 302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 345 346 /* Add the op code for SDVO enhancements */ 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 391 392 /* HDMI op code */ 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 413 }; 414 415 #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") 416 417 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 418 const void *args, int args_len) 419 { 420 int i, pos = 0; 421 #define BUF_LEN 256 422 char buffer[BUF_LEN]; 423 424 #define BUF_PRINT(args...) \ 425 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 426 427 428 for (i = 0; i < args_len; i++) { 429 BUF_PRINT("%02X ", ((const u8 *)args)[i]); 430 } 431 for (; i < 8; i++) { 432 BUF_PRINT(" "); 433 } 434 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 435 if (cmd == sdvo_cmd_names[i].cmd) { 436 BUF_PRINT("(%s)", sdvo_cmd_names[i].name); 437 break; 438 } 439 } 440 if (i == ARRAY_SIZE(sdvo_cmd_names)) { 441 BUF_PRINT("(%02X)", cmd); 442 } 443 BUG_ON(pos >= BUF_LEN - 1); 444 #undef BUF_PRINT 445 #undef BUF_LEN 446 447 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 448 } 449 450 static const char *cmd_status_names[] = { 451 "Power on", 452 "Success", 453 "Not supported", 454 "Invalid arg", 455 "Pending", 456 "Target not specified", 457 "Scaling not supported" 458 }; 459 460 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 461 const void *args, int args_len) 462 { 463 u8 *buf, status; 464 struct i2c_msg *msgs; 465 int i, ret = true; 466 467 /* Would be simpler to allocate both in one go ? */ 468 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 469 if (!buf) 470 return false; 471 472 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 473 if (!msgs) { 474 kfree(buf); 475 return false; 476 } 477 478 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 479 480 for (i = 0; i < args_len; i++) { 481 msgs[i].slave = intel_sdvo->slave_addr << 1; 482 msgs[i].flags = 0; 483 msgs[i].len = 2; 484 msgs[i].buf = buf + 2 *i; 485 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 486 buf[2*i + 1] = ((const u8*)args)[i]; 487 } 488 msgs[i].slave = intel_sdvo->slave_addr << 1; 489 msgs[i].flags = 0; 490 msgs[i].len = 2; 491 msgs[i].buf = buf + 2*i; 492 buf[2*i + 0] = SDVO_I2C_OPCODE; 493 buf[2*i + 1] = cmd; 494 495 /* the following two are to read the response */ 496 status = SDVO_I2C_CMD_STATUS; 497 msgs[i+1].slave = intel_sdvo->slave_addr << 1; 498 msgs[i+1].flags = 0; 499 msgs[i+1].len = 1; 500 msgs[i+1].buf = &status; 501 502 msgs[i+2].slave = intel_sdvo->slave_addr << 1; 503 msgs[i+2].flags = I2C_M_RD; 504 msgs[i+2].len = 1; 505 msgs[i+2].buf = &status; 506 507 ret = iicbus_transfer(intel_sdvo->i2c, msgs, i+3); 508 if (ret != 0) { 509 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 510 ret = false; 511 goto out; 512 } 513 #if 0 514 if (ret != i+3) { 515 /* failure in I2C transfer */ 516 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 517 ret = false; 518 } 519 #endif 520 521 out: 522 kfree(msgs); 523 kfree(buf); 524 return ret; 525 } 526 527 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 528 void *response, int response_len) 529 { 530 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 531 u8 status; 532 int i, pos = 0; 533 #define BUF_LEN 256 534 char buffer[BUF_LEN]; 535 536 537 /* 538 * The documentation states that all commands will be 539 * processed within 15µs, and that we need only poll 540 * the status byte a maximum of 3 times in order for the 541 * command to be complete. 542 * 543 * Check 5 times in case the hardware failed to read the docs. 544 * 545 * Also beware that the first response by many devices is to 546 * reply PENDING and stall for time. TVs are notorious for 547 * requiring longer than specified to complete their replies. 548 * Originally (in the DDX long ago), the delay was only ever 15ms 549 * with an additional delay of 30ms applied for TVs added later after 550 * many experiments. To accommodate both sets of delays, we do a 551 * sequence of slow checks if the device is falling behind and fails 552 * to reply within 5*15µs. 553 */ 554 if (!intel_sdvo_read_byte(intel_sdvo, 555 SDVO_I2C_CMD_STATUS, 556 &status)) 557 goto log_fail; 558 559 while ((status == SDVO_CMD_STATUS_PENDING || 560 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 561 if (retry < 10) 562 msleep(15); 563 else 564 udelay(15); 565 566 if (!intel_sdvo_read_byte(intel_sdvo, 567 SDVO_I2C_CMD_STATUS, 568 &status)) 569 goto log_fail; 570 } 571 572 #define BUF_PRINT(args...) \ 573 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 574 575 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 576 BUF_PRINT("(%s)", cmd_status_names[status]); 577 else 578 BUF_PRINT("(??? %d)", status); 579 580 if (status != SDVO_CMD_STATUS_SUCCESS) 581 goto log_fail; 582 583 /* Read the command response */ 584 for (i = 0; i < response_len; i++) { 585 if (!intel_sdvo_read_byte(intel_sdvo, 586 SDVO_I2C_RETURN_0 + i, 587 &((u8 *)response)[i])) 588 goto log_fail; 589 BUF_PRINT(" %02X", ((u8 *)response)[i]); 590 } 591 BUG_ON(pos >= BUF_LEN - 1); 592 #undef BUF_PRINT 593 #undef BUF_LEN 594 595 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 596 return true; 597 598 log_fail: 599 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); 600 return false; 601 } 602 603 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 604 { 605 if (mode->clock >= 100000) 606 return 1; 607 else if (mode->clock >= 50000) 608 return 2; 609 else 610 return 4; 611 } 612 613 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 614 u8 ddc_bus) 615 { 616 /* This must be the immediately preceding write before the i2c xfer */ 617 return intel_sdvo_write_cmd(intel_sdvo, 618 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 619 &ddc_bus, 1); 620 } 621 622 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 623 { 624 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 625 return false; 626 627 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 628 } 629 630 static bool 631 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 632 { 633 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 634 return false; 635 636 return intel_sdvo_read_response(intel_sdvo, value, len); 637 } 638 639 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 640 { 641 struct intel_sdvo_set_target_input_args targets = {0}; 642 return intel_sdvo_set_value(intel_sdvo, 643 SDVO_CMD_SET_TARGET_INPUT, 644 &targets, sizeof(targets)); 645 } 646 647 /** 648 * Return whether each input is trained. 649 * 650 * This function is making an assumption about the layout of the response, 651 * which should be checked against the docs. 652 */ 653 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 654 { 655 struct intel_sdvo_get_trained_inputs_response response; 656 657 BUILD_BUG_ON(sizeof(response) != 1); 658 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 659 &response, sizeof(response))) 660 return false; 661 662 *input_1 = response.input0_trained; 663 *input_2 = response.input1_trained; 664 return true; 665 } 666 667 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 668 u16 outputs) 669 { 670 return intel_sdvo_set_value(intel_sdvo, 671 SDVO_CMD_SET_ACTIVE_OUTPUTS, 672 &outputs, sizeof(outputs)); 673 } 674 675 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 676 u16 *outputs) 677 { 678 return intel_sdvo_get_value(intel_sdvo, 679 SDVO_CMD_GET_ACTIVE_OUTPUTS, 680 outputs, sizeof(*outputs)); 681 } 682 683 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 684 int mode) 685 { 686 u8 state = SDVO_ENCODER_STATE_ON; 687 688 switch (mode) { 689 case DRM_MODE_DPMS_ON: 690 state = SDVO_ENCODER_STATE_ON; 691 break; 692 case DRM_MODE_DPMS_STANDBY: 693 state = SDVO_ENCODER_STATE_STANDBY; 694 break; 695 case DRM_MODE_DPMS_SUSPEND: 696 state = SDVO_ENCODER_STATE_SUSPEND; 697 break; 698 case DRM_MODE_DPMS_OFF: 699 state = SDVO_ENCODER_STATE_OFF; 700 break; 701 } 702 703 return intel_sdvo_set_value(intel_sdvo, 704 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 705 } 706 707 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 708 int *clock_min, 709 int *clock_max) 710 { 711 struct intel_sdvo_pixel_clock_range clocks; 712 713 BUILD_BUG_ON(sizeof(clocks) != 4); 714 if (!intel_sdvo_get_value(intel_sdvo, 715 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 716 &clocks, sizeof(clocks))) 717 return false; 718 719 /* Convert the values from units of 10 kHz to kHz. */ 720 *clock_min = clocks.min * 10; 721 *clock_max = clocks.max * 10; 722 return true; 723 } 724 725 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 726 u16 outputs) 727 { 728 return intel_sdvo_set_value(intel_sdvo, 729 SDVO_CMD_SET_TARGET_OUTPUT, 730 &outputs, sizeof(outputs)); 731 } 732 733 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 734 struct intel_sdvo_dtd *dtd) 735 { 736 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 737 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 738 } 739 740 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 741 struct intel_sdvo_dtd *dtd) 742 { 743 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 744 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 745 } 746 747 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 748 struct intel_sdvo_dtd *dtd) 749 { 750 return intel_sdvo_set_timing(intel_sdvo, 751 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 752 } 753 754 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 755 struct intel_sdvo_dtd *dtd) 756 { 757 return intel_sdvo_set_timing(intel_sdvo, 758 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 759 } 760 761 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 762 struct intel_sdvo_dtd *dtd) 763 { 764 return intel_sdvo_get_timing(intel_sdvo, 765 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 766 } 767 768 static bool 769 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 770 uint16_t clock, 771 uint16_t width, 772 uint16_t height) 773 { 774 struct intel_sdvo_preferred_input_timing_args args; 775 776 memset(&args, 0, sizeof(args)); 777 args.clock = clock; 778 args.width = width; 779 args.height = height; 780 args.interlace = 0; 781 782 if (intel_sdvo->is_lvds && 783 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 784 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 785 args.scaled = 1; 786 787 return intel_sdvo_set_value(intel_sdvo, 788 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 789 &args, sizeof(args)); 790 } 791 792 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 793 struct intel_sdvo_dtd *dtd) 794 { 795 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 796 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 797 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 798 &dtd->part1, sizeof(dtd->part1)) && 799 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 800 &dtd->part2, sizeof(dtd->part2)); 801 } 802 803 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 804 { 805 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 806 } 807 808 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 809 const struct drm_display_mode *mode) 810 { 811 uint16_t width, height; 812 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 813 uint16_t h_sync_offset, v_sync_offset; 814 int mode_clock; 815 816 memset(dtd, 0, sizeof(*dtd)); 817 818 width = mode->hdisplay; 819 height = mode->vdisplay; 820 821 /* do some mode translations */ 822 h_blank_len = mode->htotal - mode->hdisplay; 823 h_sync_len = mode->hsync_end - mode->hsync_start; 824 825 v_blank_len = mode->vtotal - mode->vdisplay; 826 v_sync_len = mode->vsync_end - mode->vsync_start; 827 828 h_sync_offset = mode->hsync_start - mode->hdisplay; 829 v_sync_offset = mode->vsync_start - mode->vdisplay; 830 831 mode_clock = mode->clock; 832 mode_clock /= 10; 833 dtd->part1.clock = mode_clock; 834 835 dtd->part1.h_active = width & 0xff; 836 dtd->part1.h_blank = h_blank_len & 0xff; 837 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 838 ((h_blank_len >> 8) & 0xf); 839 dtd->part1.v_active = height & 0xff; 840 dtd->part1.v_blank = v_blank_len & 0xff; 841 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 842 ((v_blank_len >> 8) & 0xf); 843 844 dtd->part2.h_sync_off = h_sync_offset & 0xff; 845 dtd->part2.h_sync_width = h_sync_len & 0xff; 846 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 847 (v_sync_len & 0xf); 848 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 849 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 850 ((v_sync_len & 0x30) >> 4); 851 852 dtd->part2.dtd_flags = 0x18; 853 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 854 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 855 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 856 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 857 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 858 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 859 860 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 861 } 862 863 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 864 const struct intel_sdvo_dtd *dtd) 865 { 866 struct drm_display_mode mode = {}; 867 868 mode.hdisplay = dtd->part1.h_active; 869 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 870 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 871 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 872 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 873 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 874 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 875 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 876 877 mode.vdisplay = dtd->part1.v_active; 878 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 879 mode.vsync_start = mode.vdisplay; 880 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 881 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 882 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 883 mode.vsync_end = mode.vsync_start + 884 (dtd->part2.v_sync_off_width & 0xf); 885 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 886 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 887 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 888 889 mode.clock = dtd->part1.clock * 10; 890 891 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 892 mode.flags |= DRM_MODE_FLAG_INTERLACE; 893 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 894 mode.flags |= DRM_MODE_FLAG_PHSYNC; 895 else 896 mode.flags |= DRM_MODE_FLAG_NHSYNC; 897 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 898 mode.flags |= DRM_MODE_FLAG_PVSYNC; 899 else 900 mode.flags |= DRM_MODE_FLAG_NVSYNC; 901 902 drm_mode_set_crtcinfo(&mode, 0); 903 904 drm_mode_copy(pmode, &mode); 905 } 906 907 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 908 { 909 struct intel_sdvo_encode encode; 910 911 BUILD_BUG_ON(sizeof(encode) != 2); 912 return intel_sdvo_get_value(intel_sdvo, 913 SDVO_CMD_GET_SUPP_ENCODE, 914 &encode, sizeof(encode)); 915 } 916 917 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 918 uint8_t mode) 919 { 920 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 921 } 922 923 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 924 uint8_t mode) 925 { 926 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 927 } 928 929 #if 0 930 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 931 { 932 int i, j; 933 uint8_t set_buf_index[2]; 934 uint8_t av_split; 935 uint8_t buf_size; 936 uint8_t buf[48]; 937 uint8_t *pos; 938 939 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 940 941 for (i = 0; i <= av_split; i++) { 942 set_buf_index[0] = i; set_buf_index[1] = 0; 943 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 944 set_buf_index, 2); 945 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 946 intel_sdvo_read_response(encoder, &buf_size, 1); 947 948 pos = buf; 949 for (j = 0; j <= buf_size; j += 8) { 950 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 951 NULL, 0); 952 intel_sdvo_read_response(encoder, pos, 8); 953 pos += 8; 954 } 955 } 956 } 957 #endif 958 959 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 960 unsigned if_index, uint8_t tx_rate, 961 const uint8_t *data, unsigned length) 962 { 963 uint8_t set_buf_index[2] = { if_index, 0 }; 964 uint8_t hbuf_size, tmp[8]; 965 int i; 966 967 if (!intel_sdvo_set_value(intel_sdvo, 968 SDVO_CMD_SET_HBUF_INDEX, 969 set_buf_index, 2)) 970 return false; 971 972 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 973 &hbuf_size, 1)) 974 return false; 975 976 /* Buffer size is 0 based, hooray! */ 977 hbuf_size++; 978 979 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", 980 if_index, length, hbuf_size); 981 982 for (i = 0; i < hbuf_size; i += 8) { 983 memset(tmp, 0, 8); 984 if (i < length) 985 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 986 987 if (!intel_sdvo_set_value(intel_sdvo, 988 SDVO_CMD_SET_HBUF_DATA, 989 tmp, 8)) 990 return false; 991 } 992 993 return intel_sdvo_set_value(intel_sdvo, 994 SDVO_CMD_SET_HBUF_TXRATE, 995 &tx_rate, 1); 996 } 997 998 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 999 const struct drm_display_mode *adjusted_mode) 1000 { 1001 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1002 struct drm_crtc *crtc = intel_sdvo->base.base.crtc; 1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1004 union hdmi_infoframe frame; 1005 int ret; 1006 ssize_t len; 1007 1008 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 1009 adjusted_mode); 1010 if (ret < 0) { 1011 DRM_ERROR("couldn't fill AVI infoframe\n"); 1012 return false; 1013 } 1014 1015 if (intel_sdvo->rgb_quant_range_selectable) { 1016 if (intel_crtc->config->limited_color_range) 1017 frame.avi.quantization_range = 1018 HDMI_QUANTIZATION_RANGE_LIMITED; 1019 else 1020 frame.avi.quantization_range = 1021 HDMI_QUANTIZATION_RANGE_FULL; 1022 } 1023 1024 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); 1025 if (len < 0) 1026 return false; 1027 1028 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1029 SDVO_HBUF_TX_VSYNC, 1030 sdvo_data, sizeof(sdvo_data)); 1031 } 1032 1033 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 1034 { 1035 struct intel_sdvo_tv_format format; 1036 uint32_t format_map; 1037 1038 format_map = 1 << intel_sdvo->tv_format_index; 1039 memset(&format, 0, sizeof(format)); 1040 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1041 1042 BUILD_BUG_ON(sizeof(format) != 6); 1043 return intel_sdvo_set_value(intel_sdvo, 1044 SDVO_CMD_SET_TV_FORMAT, 1045 &format, sizeof(format)); 1046 } 1047 1048 static bool 1049 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1050 const struct drm_display_mode *mode) 1051 { 1052 struct intel_sdvo_dtd output_dtd; 1053 1054 if (!intel_sdvo_set_target_output(intel_sdvo, 1055 intel_sdvo->attached_output)) 1056 return false; 1057 1058 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1059 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1060 return false; 1061 1062 return true; 1063 } 1064 1065 /* Asks the sdvo controller for the preferred input mode given the output mode. 1066 * Unfortunately we have to set up the full output mode to do that. */ 1067 static bool 1068 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1069 const struct drm_display_mode *mode, 1070 struct drm_display_mode *adjusted_mode) 1071 { 1072 struct intel_sdvo_dtd input_dtd; 1073 1074 /* Reset the input timing to the screen. Assume always input 0. */ 1075 if (!intel_sdvo_set_target_input(intel_sdvo)) 1076 return false; 1077 1078 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1079 mode->clock / 10, 1080 mode->hdisplay, 1081 mode->vdisplay)) 1082 return false; 1083 1084 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1085 &input_dtd)) 1086 return false; 1087 1088 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1089 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1090 1091 return true; 1092 } 1093 1094 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1095 { 1096 unsigned dotclock = pipe_config->port_clock; 1097 struct dpll *clock = &pipe_config->dpll; 1098 1099 /* SDVO TV has fixed PLL values depend on its clock range, 1100 this mirrors vbios setting. */ 1101 if (dotclock >= 100000 && dotclock < 140500) { 1102 clock->p1 = 2; 1103 clock->p2 = 10; 1104 clock->n = 3; 1105 clock->m1 = 16; 1106 clock->m2 = 8; 1107 } else if (dotclock >= 140500 && dotclock <= 200000) { 1108 clock->p1 = 1; 1109 clock->p2 = 10; 1110 clock->n = 6; 1111 clock->m1 = 12; 1112 clock->m2 = 8; 1113 } else { 1114 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1115 } 1116 1117 pipe_config->clock_set = true; 1118 } 1119 1120 static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1121 struct intel_crtc_state *pipe_config) 1122 { 1123 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1124 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1125 struct drm_display_mode *mode = &pipe_config->base.mode; 1126 1127 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1128 pipe_config->pipe_bpp = 8*3; 1129 1130 if (HAS_PCH_SPLIT(encoder->base.dev)) 1131 pipe_config->has_pch_encoder = true; 1132 1133 /* We need to construct preferred input timings based on our 1134 * output timings. To do that, we have to set the output 1135 * timings, even though this isn't really the right place in 1136 * the sequence to do it. Oh well. 1137 */ 1138 if (intel_sdvo->is_tv) { 1139 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1140 return false; 1141 1142 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1143 mode, 1144 adjusted_mode); 1145 pipe_config->sdvo_tv_clock = true; 1146 } else if (intel_sdvo->is_lvds) { 1147 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1148 intel_sdvo->sdvo_lvds_fixed_mode)) 1149 return false; 1150 1151 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1152 mode, 1153 adjusted_mode); 1154 } 1155 1156 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1157 * SDVO device will factor out the multiplier during mode_set. 1158 */ 1159 pipe_config->pixel_multiplier = 1160 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1161 1162 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; 1163 1164 if (intel_sdvo->color_range_auto) { 1165 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1166 /* FIXME: This bit is only valid when using TMDS encoding and 8 1167 * bit per color mode. */ 1168 if (pipe_config->has_hdmi_sink && 1169 drm_match_cea_mode(adjusted_mode) > 1) 1170 pipe_config->limited_color_range = true; 1171 } else { 1172 if (pipe_config->has_hdmi_sink && 1173 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) 1174 pipe_config->limited_color_range = true; 1175 } 1176 1177 /* Clock computation needs to happen after pixel multiplier. */ 1178 if (intel_sdvo->is_tv) 1179 i9xx_adjust_sdvo_tv_clock(pipe_config); 1180 1181 return true; 1182 } 1183 1184 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) 1185 { 1186 struct drm_device *dev = intel_encoder->base.dev; 1187 struct drm_i915_private *dev_priv = dev->dev_private; 1188 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); 1189 struct drm_display_mode *adjusted_mode = 1190 &crtc->config->base.adjusted_mode; 1191 struct drm_display_mode *mode = &crtc->config->base.mode; 1192 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1193 u32 sdvox; 1194 struct intel_sdvo_in_out_map in_out; 1195 struct intel_sdvo_dtd input_dtd, output_dtd; 1196 int rate; 1197 1198 if (!mode) 1199 return; 1200 1201 /* First, set the input mapping for the first input to our controlled 1202 * output. This is only correct if we're a single-input device, in 1203 * which case the first input is the output from the appropriate SDVO 1204 * channel on the motherboard. In a two-input device, the first input 1205 * will be SDVOB and the second SDVOC. 1206 */ 1207 in_out.in0 = intel_sdvo->attached_output; 1208 in_out.in1 = 0; 1209 1210 intel_sdvo_set_value(intel_sdvo, 1211 SDVO_CMD_SET_IN_OUT_MAP, 1212 &in_out, sizeof(in_out)); 1213 1214 /* Set the output timings to the screen */ 1215 if (!intel_sdvo_set_target_output(intel_sdvo, 1216 intel_sdvo->attached_output)) 1217 return; 1218 1219 /* lvds has a special fixed output timing. */ 1220 if (intel_sdvo->is_lvds) 1221 intel_sdvo_get_dtd_from_mode(&output_dtd, 1222 intel_sdvo->sdvo_lvds_fixed_mode); 1223 else 1224 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1225 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1226 DRM_INFO("Setting output timings on %s failed\n", 1227 SDVO_NAME(intel_sdvo)); 1228 1229 /* Set the input timing to the screen. Assume always input 0. */ 1230 if (!intel_sdvo_set_target_input(intel_sdvo)) 1231 return; 1232 1233 if (crtc->config->has_hdmi_sink) { 1234 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1235 intel_sdvo_set_colorimetry(intel_sdvo, 1236 SDVO_COLORIMETRY_RGB256); 1237 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); 1238 } else 1239 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1240 1241 if (intel_sdvo->is_tv && 1242 !intel_sdvo_set_tv_format(intel_sdvo)) 1243 return; 1244 1245 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1246 1247 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1248 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1249 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1250 DRM_INFO("Setting input timings on %s failed\n", 1251 SDVO_NAME(intel_sdvo)); 1252 1253 switch (crtc->config->pixel_multiplier) { 1254 default: 1255 WARN(1, "unknown pixel mutlipler specified\n"); 1256 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1257 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1258 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1259 } 1260 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1261 return; 1262 1263 /* Set the SDVO control regs. */ 1264 if (INTEL_INFO(dev)->gen >= 4) { 1265 /* The real mode polarity is set by the SDVO commands, using 1266 * struct intel_sdvo_dtd. */ 1267 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1268 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 1269 sdvox |= HDMI_COLOR_RANGE_16_235; 1270 if (INTEL_INFO(dev)->gen < 5) 1271 sdvox |= SDVO_BORDER_ENABLE; 1272 } else { 1273 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1274 switch (intel_sdvo->sdvo_reg) { 1275 case GEN3_SDVOB: 1276 sdvox &= SDVOB_PRESERVE_MASK; 1277 break; 1278 case GEN3_SDVOC: 1279 sdvox &= SDVOC_PRESERVE_MASK; 1280 break; 1281 } 1282 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1283 } 1284 1285 if (INTEL_PCH_TYPE(dev) >= PCH_CPT) 1286 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1287 else 1288 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1289 1290 if (intel_sdvo->has_hdmi_audio) 1291 sdvox |= SDVO_AUDIO_ENABLE; 1292 1293 if (INTEL_INFO(dev)->gen >= 4) { 1294 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1295 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1296 /* done in crtc_mode_set as it lives inside the dpll register */ 1297 } else { 1298 sdvox |= (crtc->config->pixel_multiplier - 1) 1299 << SDVO_PORT_MULTIPLY_SHIFT; 1300 } 1301 1302 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1303 INTEL_INFO(dev)->gen < 5) 1304 sdvox |= SDVO_STALL_SELECT; 1305 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1306 } 1307 1308 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1309 { 1310 struct intel_sdvo_connector *intel_sdvo_connector = 1311 to_intel_sdvo_connector(&connector->base); 1312 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1313 u16 active_outputs = 0; 1314 1315 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1316 1317 if (active_outputs & intel_sdvo_connector->output_flag) 1318 return true; 1319 else 1320 return false; 1321 } 1322 1323 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1324 enum i915_pipe *pipe) 1325 { 1326 struct drm_device *dev = encoder->base.dev; 1327 struct drm_i915_private *dev_priv = dev->dev_private; 1328 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1329 u16 active_outputs = 0; 1330 u32 tmp; 1331 1332 tmp = I915_READ(intel_sdvo->sdvo_reg); 1333 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1334 1335 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) 1336 return false; 1337 1338 if (HAS_PCH_CPT(dev)) 1339 *pipe = PORT_TO_PIPE_CPT(tmp); 1340 else 1341 *pipe = PORT_TO_PIPE(tmp); 1342 1343 return true; 1344 } 1345 1346 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1347 struct intel_crtc_state *pipe_config) 1348 { 1349 struct drm_device *dev = encoder->base.dev; 1350 struct drm_i915_private *dev_priv = dev->dev_private; 1351 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1352 struct intel_sdvo_dtd dtd; 1353 int encoder_pixel_multiplier = 0; 1354 int dotclock; 1355 u32 flags = 0, sdvox; 1356 u8 val; 1357 bool ret; 1358 1359 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1360 1361 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1362 if (!ret) { 1363 /* Some sdvo encoders are not spec compliant and don't 1364 * implement the mandatory get_timings function. */ 1365 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1366 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1367 } else { 1368 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1369 flags |= DRM_MODE_FLAG_PHSYNC; 1370 else 1371 flags |= DRM_MODE_FLAG_NHSYNC; 1372 1373 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1374 flags |= DRM_MODE_FLAG_PVSYNC; 1375 else 1376 flags |= DRM_MODE_FLAG_NVSYNC; 1377 } 1378 1379 pipe_config->base.adjusted_mode.flags |= flags; 1380 1381 /* 1382 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1383 * the sdvo port register, on all other platforms it is part of the dpll 1384 * state. Since the general pipe state readout happens before the 1385 * encoder->get_config we so already have a valid pixel multplier on all 1386 * other platfroms. 1387 */ 1388 if (IS_I915G(dev) || IS_I915GM(dev)) { 1389 pipe_config->pixel_multiplier = 1390 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1391 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1392 } 1393 1394 dotclock = pipe_config->port_clock; 1395 if (pipe_config->pixel_multiplier) 1396 dotclock /= pipe_config->pixel_multiplier; 1397 1398 if (HAS_PCH_SPLIT(dev)) 1399 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1400 1401 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1402 1403 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1404 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1405 &val, 1)) { 1406 switch (val) { 1407 case SDVO_CLOCK_RATE_MULT_1X: 1408 encoder_pixel_multiplier = 1; 1409 break; 1410 case SDVO_CLOCK_RATE_MULT_2X: 1411 encoder_pixel_multiplier = 2; 1412 break; 1413 case SDVO_CLOCK_RATE_MULT_4X: 1414 encoder_pixel_multiplier = 4; 1415 break; 1416 } 1417 } 1418 1419 if (sdvox & HDMI_COLOR_RANGE_16_235) 1420 pipe_config->limited_color_range = true; 1421 1422 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1423 &val, 1)) { 1424 if (val == SDVO_ENCODE_HDMI) 1425 pipe_config->has_hdmi_sink = true; 1426 } 1427 1428 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1429 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1430 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1431 } 1432 1433 static void intel_disable_sdvo(struct intel_encoder *encoder) 1434 { 1435 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1436 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1437 u32 temp; 1438 1439 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1440 if (0) 1441 intel_sdvo_set_encoder_power_state(intel_sdvo, 1442 DRM_MODE_DPMS_OFF); 1443 1444 temp = I915_READ(intel_sdvo->sdvo_reg); 1445 if ((temp & SDVO_ENABLE) != 0) { 1446 /* HW workaround for IBX, we need to move the port to 1447 * transcoder A before disabling it. */ 1448 if (HAS_PCH_IBX(encoder->base.dev)) { 1449 struct drm_crtc *crtc = encoder->base.crtc; 1450 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 1451 1452 if (temp & SDVO_PIPE_B_SELECT) { 1453 temp &= ~SDVO_PIPE_B_SELECT; 1454 I915_WRITE(intel_sdvo->sdvo_reg, temp); 1455 POSTING_READ(intel_sdvo->sdvo_reg); 1456 1457 /* Again we need to write this twice. */ 1458 I915_WRITE(intel_sdvo->sdvo_reg, temp); 1459 POSTING_READ(intel_sdvo->sdvo_reg); 1460 1461 /* Transcoder selection bits only update 1462 * effectively on vblank. */ 1463 if (crtc) 1464 intel_wait_for_vblank(encoder->base.dev, pipe); 1465 else 1466 msleep(50); 1467 } 1468 } 1469 1470 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); 1471 } 1472 } 1473 1474 static void intel_enable_sdvo(struct intel_encoder *encoder) 1475 { 1476 struct drm_device *dev = encoder->base.dev; 1477 struct drm_i915_private *dev_priv = dev->dev_private; 1478 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1479 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1480 u32 temp; 1481 bool input1, input2; 1482 int i; 1483 bool success; 1484 1485 temp = I915_READ(intel_sdvo->sdvo_reg); 1486 if ((temp & SDVO_ENABLE) == 0) { 1487 /* HW workaround for IBX, we need to move the port 1488 * to transcoder A before disabling it, so restore it here. */ 1489 if (HAS_PCH_IBX(dev)) 1490 temp |= SDVO_PIPE_SEL(intel_crtc->pipe); 1491 1492 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); 1493 } 1494 for (i = 0; i < 2; i++) 1495 intel_wait_for_vblank(dev, intel_crtc->pipe); 1496 1497 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1498 /* Warn if the device reported failure to sync. 1499 * A lot of SDVO devices fail to notify of sync, but it's 1500 * a given it the status is a success, we succeeded. 1501 */ 1502 if (success && !input1) { 1503 DRM_DEBUG_KMS("First %s output reported failure to " 1504 "sync\n", SDVO_NAME(intel_sdvo)); 1505 } 1506 1507 if (0) 1508 intel_sdvo_set_encoder_power_state(intel_sdvo, 1509 DRM_MODE_DPMS_ON); 1510 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1511 } 1512 1513 /* Special dpms function to support cloning between dvo/sdvo/crt. */ 1514 static void intel_sdvo_dpms(struct drm_connector *connector, int mode) 1515 { 1516 struct drm_crtc *crtc; 1517 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1518 1519 /* dvo supports only 2 dpms states. */ 1520 if (mode != DRM_MODE_DPMS_ON) 1521 mode = DRM_MODE_DPMS_OFF; 1522 1523 if (mode == connector->dpms) 1524 return; 1525 1526 connector->dpms = mode; 1527 1528 /* Only need to change hw state when actually enabled */ 1529 crtc = intel_sdvo->base.base.crtc; 1530 if (!crtc) { 1531 intel_sdvo->base.connectors_active = false; 1532 return; 1533 } 1534 1535 /* We set active outputs manually below in case pipe dpms doesn't change 1536 * due to cloning. */ 1537 if (mode != DRM_MODE_DPMS_ON) { 1538 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1539 if (0) 1540 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1541 1542 intel_sdvo->base.connectors_active = false; 1543 1544 intel_crtc_update_dpms(crtc); 1545 } else { 1546 intel_sdvo->base.connectors_active = true; 1547 1548 intel_crtc_update_dpms(crtc); 1549 1550 if (0) 1551 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1552 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1553 } 1554 1555 intel_modeset_check_state(connector->dev); 1556 } 1557 1558 static enum drm_mode_status 1559 intel_sdvo_mode_valid(struct drm_connector *connector, 1560 struct drm_display_mode *mode) 1561 { 1562 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1563 1564 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1565 return MODE_NO_DBLESCAN; 1566 1567 if (intel_sdvo->pixel_clock_min > mode->clock) 1568 return MODE_CLOCK_LOW; 1569 1570 if (intel_sdvo->pixel_clock_max < mode->clock) 1571 return MODE_CLOCK_HIGH; 1572 1573 if (intel_sdvo->is_lvds) { 1574 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1575 return MODE_PANEL; 1576 1577 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1578 return MODE_PANEL; 1579 } 1580 1581 return MODE_OK; 1582 } 1583 1584 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1585 { 1586 BUILD_BUG_ON(sizeof(*caps) != 8); 1587 if (!intel_sdvo_get_value(intel_sdvo, 1588 SDVO_CMD_GET_DEVICE_CAPS, 1589 caps, sizeof(*caps))) 1590 return false; 1591 1592 DRM_DEBUG_KMS("SDVO capabilities:\n" 1593 " vendor_id: %d\n" 1594 " device_id: %d\n" 1595 " device_rev_id: %d\n" 1596 " sdvo_version_major: %d\n" 1597 " sdvo_version_minor: %d\n" 1598 " sdvo_inputs_mask: %d\n" 1599 " smooth_scaling: %d\n" 1600 " sharp_scaling: %d\n" 1601 " up_scaling: %d\n" 1602 " down_scaling: %d\n" 1603 " stall_support: %d\n" 1604 " output_flags: %d\n", 1605 caps->vendor_id, 1606 caps->device_id, 1607 caps->device_rev_id, 1608 caps->sdvo_version_major, 1609 caps->sdvo_version_minor, 1610 caps->sdvo_inputs_mask, 1611 caps->smooth_scaling, 1612 caps->sharp_scaling, 1613 caps->up_scaling, 1614 caps->down_scaling, 1615 caps->stall_support, 1616 caps->output_flags); 1617 1618 return true; 1619 } 1620 1621 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1622 { 1623 struct drm_device *dev = intel_sdvo->base.base.dev; 1624 uint16_t hotplug; 1625 1626 if (!I915_HAS_HOTPLUG(dev)) 1627 return 0; 1628 1629 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1630 * on the line. */ 1631 if (IS_I945G(dev) || IS_I945GM(dev)) 1632 return 0; 1633 1634 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1635 &hotplug, sizeof(hotplug))) 1636 return 0; 1637 1638 return hotplug; 1639 } 1640 1641 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1642 { 1643 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1644 1645 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1646 &intel_sdvo->hotplug_active, 2); 1647 } 1648 1649 static bool 1650 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1651 { 1652 /* Is there more than one type of output? */ 1653 return hweight16(intel_sdvo->caps.output_flags) > 1; 1654 } 1655 1656 static struct edid * 1657 intel_sdvo_get_edid(struct drm_connector *connector) 1658 { 1659 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1660 return drm_get_edid(connector, sdvo->ddc); 1661 } 1662 1663 /* Mac mini hack -- use the same DDC as the analog connector */ 1664 static struct edid * 1665 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1666 { 1667 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1668 1669 return drm_get_edid(connector, 1670 intel_gmbus_get_adapter(dev_priv, 1671 dev_priv->vbt.crt_ddc_pin)); 1672 } 1673 1674 static enum drm_connector_status 1675 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1676 { 1677 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1678 enum drm_connector_status status; 1679 struct edid *edid; 1680 1681 edid = intel_sdvo_get_edid(connector); 1682 1683 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1684 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1685 1686 /* 1687 * Don't use the 1 as the argument of DDC bus switch to get 1688 * the EDID. It is used for SDVO SPD ROM. 1689 */ 1690 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1691 intel_sdvo->ddc_bus = ddc; 1692 edid = intel_sdvo_get_edid(connector); 1693 if (edid) 1694 break; 1695 } 1696 /* 1697 * If we found the EDID on the other bus, 1698 * assume that is the correct DDC bus. 1699 */ 1700 if (edid == NULL) 1701 intel_sdvo->ddc_bus = saved_ddc; 1702 } 1703 1704 /* 1705 * When there is no edid and no monitor is connected with VGA 1706 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1707 */ 1708 if (edid == NULL) 1709 edid = intel_sdvo_get_analog_edid(connector); 1710 1711 status = connector_status_unknown; 1712 if (edid != NULL) { 1713 /* DDC bus is shared, match EDID to connector type */ 1714 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1715 status = connector_status_connected; 1716 if (intel_sdvo->is_hdmi) { 1717 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1718 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1719 intel_sdvo->rgb_quant_range_selectable = 1720 drm_rgb_quant_range_selectable(edid); 1721 } 1722 } else 1723 status = connector_status_disconnected; 1724 kfree(edid); 1725 } 1726 1727 if (status == connector_status_connected) { 1728 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1729 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) 1730 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); 1731 } 1732 1733 return status; 1734 } 1735 1736 static bool 1737 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 1738 struct edid *edid) 1739 { 1740 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1741 bool connector_is_digital = !!IS_DIGITAL(sdvo); 1742 1743 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 1744 connector_is_digital, monitor_is_digital); 1745 return connector_is_digital == monitor_is_digital; 1746 } 1747 1748 static enum drm_connector_status 1749 intel_sdvo_detect(struct drm_connector *connector, bool force) 1750 { 1751 uint16_t response; 1752 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1753 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1754 enum drm_connector_status ret; 1755 1756 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1757 connector->base.id, connector->name); 1758 1759 if (!intel_sdvo_get_value(intel_sdvo, 1760 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1761 &response, 2)) 1762 return connector_status_unknown; 1763 1764 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1765 response & 0xff, response >> 8, 1766 intel_sdvo_connector->output_flag); 1767 1768 if (response == 0) 1769 return connector_status_disconnected; 1770 1771 intel_sdvo->attached_output = response; 1772 1773 intel_sdvo->has_hdmi_monitor = false; 1774 intel_sdvo->has_hdmi_audio = false; 1775 intel_sdvo->rgb_quant_range_selectable = false; 1776 1777 if ((intel_sdvo_connector->output_flag & response) == 0) 1778 ret = connector_status_disconnected; 1779 else if (IS_TMDS(intel_sdvo_connector)) 1780 ret = intel_sdvo_tmds_sink_detect(connector); 1781 else { 1782 struct edid *edid; 1783 1784 /* if we have an edid check it matches the connection */ 1785 edid = intel_sdvo_get_edid(connector); 1786 if (edid == NULL) 1787 edid = intel_sdvo_get_analog_edid(connector); 1788 if (edid != NULL) { 1789 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 1790 edid)) 1791 ret = connector_status_connected; 1792 else 1793 ret = connector_status_disconnected; 1794 1795 kfree(edid); 1796 } else 1797 ret = connector_status_connected; 1798 } 1799 1800 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1801 if (ret == connector_status_connected) { 1802 intel_sdvo->is_tv = false; 1803 intel_sdvo->is_lvds = false; 1804 1805 if (response & SDVO_TV_MASK) 1806 intel_sdvo->is_tv = true; 1807 if (response & SDVO_LVDS_MASK) 1808 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1809 } 1810 1811 return ret; 1812 } 1813 1814 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1815 { 1816 struct edid *edid; 1817 1818 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1819 connector->base.id, connector->name); 1820 1821 /* set the bus switch and get the modes */ 1822 edid = intel_sdvo_get_edid(connector); 1823 1824 /* 1825 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1826 * link between analog and digital outputs. So, if the regular SDVO 1827 * DDC fails, check to see if the analog output is disconnected, in 1828 * which case we'll look there for the digital DDC data. 1829 */ 1830 if (edid == NULL) 1831 edid = intel_sdvo_get_analog_edid(connector); 1832 1833 if (edid != NULL) { 1834 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1835 edid)) { 1836 drm_mode_connector_update_edid_property(connector, edid); 1837 drm_add_edid_modes(connector, edid); 1838 } 1839 1840 kfree(edid); 1841 } 1842 } 1843 1844 /* 1845 * Set of SDVO TV modes. 1846 * Note! This is in reply order (see loop in get_tv_modes). 1847 * XXX: all 60Hz refresh? 1848 */ 1849 static const struct drm_display_mode sdvo_tv_modes[] = { 1850 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1851 416, 0, 200, 201, 232, 233, 0, 1852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1853 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1854 416, 0, 240, 241, 272, 273, 0, 1855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1856 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1857 496, 0, 300, 301, 332, 333, 0, 1858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1859 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1860 736, 0, 350, 351, 382, 383, 0, 1861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1862 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1863 736, 0, 400, 401, 432, 433, 0, 1864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1865 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1866 736, 0, 480, 481, 512, 513, 0, 1867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1868 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1869 800, 0, 480, 481, 512, 513, 0, 1870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1871 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1872 800, 0, 576, 577, 608, 609, 0, 1873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1874 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1875 816, 0, 350, 351, 382, 383, 0, 1876 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1877 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1878 816, 0, 400, 401, 432, 433, 0, 1879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1880 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1881 816, 0, 480, 481, 512, 513, 0, 1882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1883 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1884 816, 0, 540, 541, 572, 573, 0, 1885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1887 816, 0, 576, 577, 608, 609, 0, 1888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1889 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1890 864, 0, 576, 577, 608, 609, 0, 1891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1892 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1893 896, 0, 600, 601, 632, 633, 0, 1894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1895 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1896 928, 0, 624, 625, 656, 657, 0, 1897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1898 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1899 1016, 0, 766, 767, 798, 799, 0, 1900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1901 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1902 1120, 0, 768, 769, 800, 801, 0, 1903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1904 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1905 1376, 0, 1024, 1025, 1056, 1057, 0, 1906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1907 }; 1908 1909 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1910 { 1911 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1912 struct intel_sdvo_sdtv_resolution_request tv_res; 1913 uint32_t reply = 0, format_map = 0; 1914 int i; 1915 1916 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1917 connector->base.id, connector->name); 1918 1919 /* Read the list of supported input resolutions for the selected TV 1920 * format. 1921 */ 1922 format_map = 1 << intel_sdvo->tv_format_index; 1923 memcpy(&tv_res, &format_map, 1924 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1925 1926 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1927 return; 1928 1929 BUILD_BUG_ON(sizeof(tv_res) != 3); 1930 if (!intel_sdvo_write_cmd(intel_sdvo, 1931 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1932 &tv_res, sizeof(tv_res))) 1933 return; 1934 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1935 return; 1936 1937 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1938 if (reply & (1 << i)) { 1939 struct drm_display_mode *nmode; 1940 nmode = drm_mode_duplicate(connector->dev, 1941 &sdvo_tv_modes[i]); 1942 if (nmode) 1943 drm_mode_probed_add(connector, nmode); 1944 } 1945 } 1946 1947 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1948 { 1949 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1950 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1951 struct drm_display_mode *newmode; 1952 1953 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1954 connector->base.id, connector->name); 1955 1956 /* 1957 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 1958 * SDVO->LVDS transcoders can't cope with the EDID mode. 1959 */ 1960 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 1961 newmode = drm_mode_duplicate(connector->dev, 1962 dev_priv->vbt.sdvo_lvds_vbt_mode); 1963 if (newmode != NULL) { 1964 /* Guarantee the mode is preferred */ 1965 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1966 DRM_MODE_TYPE_DRIVER); 1967 drm_mode_probed_add(connector, newmode); 1968 } 1969 } 1970 1971 /* 1972 * Attempt to get the mode list from DDC. 1973 * Assume that the preferred modes are 1974 * arranged in priority order. 1975 */ 1976 intel_ddc_get_modes(connector, intel_sdvo->ddc); 1977 1978 list_for_each_entry(newmode, &connector->probed_modes, head) { 1979 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1980 intel_sdvo->sdvo_lvds_fixed_mode = 1981 drm_mode_duplicate(connector->dev, newmode); 1982 1983 intel_sdvo->is_lvds = true; 1984 break; 1985 } 1986 } 1987 } 1988 1989 static int intel_sdvo_get_modes(struct drm_connector *connector) 1990 { 1991 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1992 1993 if (IS_TV(intel_sdvo_connector)) 1994 intel_sdvo_get_tv_modes(connector); 1995 else if (IS_LVDS(intel_sdvo_connector)) 1996 intel_sdvo_get_lvds_modes(connector); 1997 else 1998 intel_sdvo_get_ddc_modes(connector); 1999 2000 return !list_empty(&connector->probed_modes); 2001 } 2002 2003 static void intel_sdvo_destroy(struct drm_connector *connector) 2004 { 2005 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2006 2007 drm_connector_cleanup(connector); 2008 kfree(intel_sdvo_connector); 2009 } 2010 2011 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 2012 { 2013 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2014 struct edid *edid; 2015 bool has_audio = false; 2016 2017 if (!intel_sdvo->is_hdmi) 2018 return false; 2019 2020 edid = intel_sdvo_get_edid(connector); 2021 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 2022 has_audio = drm_detect_monitor_audio(edid); 2023 kfree(edid); 2024 2025 return has_audio; 2026 } 2027 2028 static int 2029 intel_sdvo_set_property(struct drm_connector *connector, 2030 struct drm_property *property, 2031 uint64_t val) 2032 { 2033 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2034 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2035 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2036 uint16_t temp_value; 2037 uint8_t cmd; 2038 int ret; 2039 2040 ret = drm_object_property_set_value(&connector->base, property, val); 2041 if (ret) 2042 return ret; 2043 2044 if (property == dev_priv->force_audio_property) { 2045 int i = val; 2046 bool has_audio; 2047 2048 if (i == intel_sdvo_connector->force_audio) 2049 return 0; 2050 2051 intel_sdvo_connector->force_audio = i; 2052 2053 if (i == HDMI_AUDIO_AUTO) 2054 has_audio = intel_sdvo_detect_hdmi_audio(connector); 2055 else 2056 has_audio = (i == HDMI_AUDIO_ON); 2057 2058 if (has_audio == intel_sdvo->has_hdmi_audio) 2059 return 0; 2060 2061 intel_sdvo->has_hdmi_audio = has_audio; 2062 goto done; 2063 } 2064 2065 if (property == dev_priv->broadcast_rgb_property) { 2066 bool old_auto = intel_sdvo->color_range_auto; 2067 uint32_t old_range = intel_sdvo->color_range; 2068 2069 switch (val) { 2070 case INTEL_BROADCAST_RGB_AUTO: 2071 intel_sdvo->color_range_auto = true; 2072 break; 2073 case INTEL_BROADCAST_RGB_FULL: 2074 intel_sdvo->color_range_auto = false; 2075 intel_sdvo->color_range = 0; 2076 break; 2077 case INTEL_BROADCAST_RGB_LIMITED: 2078 intel_sdvo->color_range_auto = false; 2079 /* FIXME: this bit is only valid when using TMDS 2080 * encoding and 8 bit per color mode. */ 2081 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 2082 break; 2083 default: 2084 return -EINVAL; 2085 } 2086 2087 if (old_auto == intel_sdvo->color_range_auto && 2088 old_range == intel_sdvo->color_range) 2089 return 0; 2090 2091 goto done; 2092 } 2093 2094 #define CHECK_PROPERTY(name, NAME) \ 2095 if (intel_sdvo_connector->name == property) { \ 2096 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 2097 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 2098 cmd = SDVO_CMD_SET_##NAME; \ 2099 intel_sdvo_connector->cur_##name = temp_value; \ 2100 goto set_value; \ 2101 } 2102 2103 if (property == intel_sdvo_connector->tv_format) { 2104 if (val >= TV_FORMAT_NUM) 2105 return -EINVAL; 2106 2107 if (intel_sdvo->tv_format_index == 2108 intel_sdvo_connector->tv_format_supported[val]) 2109 return 0; 2110 2111 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 2112 goto done; 2113 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 2114 temp_value = val; 2115 if (intel_sdvo_connector->left == property) { 2116 drm_object_property_set_value(&connector->base, 2117 intel_sdvo_connector->right, val); 2118 if (intel_sdvo_connector->left_margin == temp_value) 2119 return 0; 2120 2121 intel_sdvo_connector->left_margin = temp_value; 2122 intel_sdvo_connector->right_margin = temp_value; 2123 temp_value = intel_sdvo_connector->max_hscan - 2124 intel_sdvo_connector->left_margin; 2125 cmd = SDVO_CMD_SET_OVERSCAN_H; 2126 goto set_value; 2127 } else if (intel_sdvo_connector->right == property) { 2128 drm_object_property_set_value(&connector->base, 2129 intel_sdvo_connector->left, val); 2130 if (intel_sdvo_connector->right_margin == temp_value) 2131 return 0; 2132 2133 intel_sdvo_connector->left_margin = temp_value; 2134 intel_sdvo_connector->right_margin = temp_value; 2135 temp_value = intel_sdvo_connector->max_hscan - 2136 intel_sdvo_connector->left_margin; 2137 cmd = SDVO_CMD_SET_OVERSCAN_H; 2138 goto set_value; 2139 } else if (intel_sdvo_connector->top == property) { 2140 drm_object_property_set_value(&connector->base, 2141 intel_sdvo_connector->bottom, val); 2142 if (intel_sdvo_connector->top_margin == temp_value) 2143 return 0; 2144 2145 intel_sdvo_connector->top_margin = temp_value; 2146 intel_sdvo_connector->bottom_margin = temp_value; 2147 temp_value = intel_sdvo_connector->max_vscan - 2148 intel_sdvo_connector->top_margin; 2149 cmd = SDVO_CMD_SET_OVERSCAN_V; 2150 goto set_value; 2151 } else if (intel_sdvo_connector->bottom == property) { 2152 drm_object_property_set_value(&connector->base, 2153 intel_sdvo_connector->top, val); 2154 if (intel_sdvo_connector->bottom_margin == temp_value) 2155 return 0; 2156 2157 intel_sdvo_connector->top_margin = temp_value; 2158 intel_sdvo_connector->bottom_margin = temp_value; 2159 temp_value = intel_sdvo_connector->max_vscan - 2160 intel_sdvo_connector->top_margin; 2161 cmd = SDVO_CMD_SET_OVERSCAN_V; 2162 goto set_value; 2163 } 2164 CHECK_PROPERTY(hpos, HPOS) 2165 CHECK_PROPERTY(vpos, VPOS) 2166 CHECK_PROPERTY(saturation, SATURATION) 2167 CHECK_PROPERTY(contrast, CONTRAST) 2168 CHECK_PROPERTY(hue, HUE) 2169 CHECK_PROPERTY(brightness, BRIGHTNESS) 2170 CHECK_PROPERTY(sharpness, SHARPNESS) 2171 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 2172 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 2173 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 2174 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 2175 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 2176 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 2177 } 2178 2179 return -EINVAL; /* unknown property */ 2180 2181 set_value: 2182 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 2183 return -EIO; 2184 2185 2186 done: 2187 if (intel_sdvo->base.base.crtc) 2188 intel_crtc_restore_mode(intel_sdvo->base.base.crtc); 2189 2190 return 0; 2191 #undef CHECK_PROPERTY 2192 } 2193 2194 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2195 .dpms = intel_sdvo_dpms, 2196 .detect = intel_sdvo_detect, 2197 .fill_modes = drm_helper_probe_single_connector_modes, 2198 .set_property = intel_sdvo_set_property, 2199 .atomic_get_property = intel_connector_atomic_get_property, 2200 .destroy = intel_sdvo_destroy, 2201 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2202 }; 2203 2204 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2205 .get_modes = intel_sdvo_get_modes, 2206 .mode_valid = intel_sdvo_mode_valid, 2207 .best_encoder = intel_best_encoder, 2208 }; 2209 2210 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2211 { 2212 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2213 2214 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 2215 drm_mode_destroy(encoder->dev, 2216 intel_sdvo->sdvo_lvds_fixed_mode); 2217 2218 device_delete_child(intel_sdvo->base.base.dev->dev, 2219 intel_sdvo->ddc_iic_bus); 2220 intel_encoder_destroy(encoder); 2221 } 2222 2223 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2224 .destroy = intel_sdvo_enc_destroy, 2225 }; 2226 2227 static void 2228 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2229 { 2230 uint16_t mask = 0; 2231 unsigned int num_bits; 2232 2233 /* Make a mask of outputs less than or equal to our own priority in the 2234 * list. 2235 */ 2236 switch (sdvo->controlled_output) { 2237 case SDVO_OUTPUT_LVDS1: 2238 mask |= SDVO_OUTPUT_LVDS1; 2239 case SDVO_OUTPUT_LVDS0: 2240 mask |= SDVO_OUTPUT_LVDS0; 2241 case SDVO_OUTPUT_TMDS1: 2242 mask |= SDVO_OUTPUT_TMDS1; 2243 case SDVO_OUTPUT_TMDS0: 2244 mask |= SDVO_OUTPUT_TMDS0; 2245 case SDVO_OUTPUT_RGB1: 2246 mask |= SDVO_OUTPUT_RGB1; 2247 case SDVO_OUTPUT_RGB0: 2248 mask |= SDVO_OUTPUT_RGB0; 2249 break; 2250 } 2251 2252 /* Count bits to find what number we are in the priority list. */ 2253 mask &= sdvo->caps.output_flags; 2254 num_bits = hweight16(mask); 2255 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2256 if (num_bits > 3) 2257 num_bits = 3; 2258 2259 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2260 sdvo->ddc_bus = 1 << num_bits; 2261 } 2262 2263 /** 2264 * Choose the appropriate DDC bus for control bus switch command for this 2265 * SDVO output based on the controlled output. 2266 * 2267 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2268 * outputs, then LVDS outputs. 2269 */ 2270 static void 2271 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2272 struct intel_sdvo *sdvo, u32 reg) 2273 { 2274 struct sdvo_device_mapping *mapping; 2275 2276 if (sdvo->is_sdvob) 2277 mapping = &(dev_priv->sdvo_mappings[0]); 2278 else 2279 mapping = &(dev_priv->sdvo_mappings[1]); 2280 2281 if (mapping->initialized) 2282 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2283 else 2284 intel_sdvo_guess_ddc_bus(sdvo); 2285 } 2286 2287 static void 2288 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2289 struct intel_sdvo *sdvo, u32 reg) 2290 { 2291 struct sdvo_device_mapping *mapping; 2292 u8 pin; 2293 2294 if (sdvo->is_sdvob) 2295 mapping = &dev_priv->sdvo_mappings[0]; 2296 else 2297 mapping = &dev_priv->sdvo_mappings[1]; 2298 2299 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) 2300 pin = mapping->i2c_pin; 2301 else 2302 pin = GMBUS_PORT_DPB; 2303 2304 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2305 2306 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2307 * our code totally fails once we start using gmbus. Hence fall back to 2308 * bit banging for now. */ 2309 intel_gmbus_force_bit(sdvo->i2c, true); 2310 } 2311 2312 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2313 static void 2314 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2315 { 2316 intel_gmbus_force_bit(sdvo->i2c, false); 2317 } 2318 2319 static bool 2320 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2321 { 2322 return intel_sdvo_check_supp_encode(intel_sdvo); 2323 } 2324 2325 static u8 2326 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) 2327 { 2328 struct drm_i915_private *dev_priv = dev->dev_private; 2329 struct sdvo_device_mapping *my_mapping, *other_mapping; 2330 2331 if (sdvo->is_sdvob) { 2332 my_mapping = &dev_priv->sdvo_mappings[0]; 2333 other_mapping = &dev_priv->sdvo_mappings[1]; 2334 } else { 2335 my_mapping = &dev_priv->sdvo_mappings[1]; 2336 other_mapping = &dev_priv->sdvo_mappings[0]; 2337 } 2338 2339 /* If the BIOS described our SDVO device, take advantage of it. */ 2340 if (my_mapping->slave_addr) 2341 return my_mapping->slave_addr; 2342 2343 /* If the BIOS only described a different SDVO device, use the 2344 * address that it isn't using. 2345 */ 2346 if (other_mapping->slave_addr) { 2347 if (other_mapping->slave_addr == 0x70) 2348 return 0x72; 2349 else 2350 return 0x70; 2351 } 2352 2353 /* No SDVO device info is found for another DVO port, 2354 * so use mapping assumption we had before BIOS parsing. 2355 */ 2356 if (sdvo->is_sdvob) 2357 return 0x70; 2358 else 2359 return 0x72; 2360 } 2361 2362 static void 2363 intel_sdvo_connector_unregister(struct intel_connector *intel_connector) 2364 { 2365 struct drm_connector *drm_connector; 2366 struct intel_sdvo *sdvo_encoder; 2367 2368 drm_connector = &intel_connector->base; 2369 sdvo_encoder = intel_attached_sdvo(&intel_connector->base); 2370 2371 intel_connector_unregister(intel_connector); 2372 } 2373 2374 static int 2375 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2376 struct intel_sdvo *encoder) 2377 { 2378 struct drm_connector *drm_connector; 2379 int ret; 2380 2381 drm_connector = &connector->base.base; 2382 ret = drm_connector_init(encoder->base.base.dev, 2383 drm_connector, 2384 &intel_sdvo_connector_funcs, 2385 connector->base.base.connector_type); 2386 if (ret < 0) 2387 return ret; 2388 2389 drm_connector_helper_add(drm_connector, 2390 &intel_sdvo_connector_helper_funcs); 2391 2392 connector->base.base.interlace_allowed = 1; 2393 connector->base.base.doublescan_allowed = 0; 2394 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2395 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2396 connector->base.unregister = intel_sdvo_connector_unregister; 2397 2398 intel_connector_attach_encoder(&connector->base, &encoder->base); 2399 ret = drm_connector_register(drm_connector); 2400 if (ret < 0) 2401 goto err1; 2402 2403 #if 0 2404 ret = sysfs_create_link(&encoder->ddc.dev.kobj, 2405 &drm_connector->kdev->kobj, 2406 encoder->ddc.dev.kobj.name); 2407 if (ret < 0) 2408 goto err2; 2409 2410 return 0; 2411 2412 err2: 2413 #endif 2414 drm_connector_unregister(drm_connector); 2415 err1: 2416 drm_connector_cleanup(drm_connector); 2417 2418 return ret; 2419 } 2420 2421 static void 2422 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2423 struct intel_sdvo_connector *connector) 2424 { 2425 struct drm_device *dev = connector->base.base.dev; 2426 2427 intel_attach_force_audio_property(&connector->base.base); 2428 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { 2429 intel_attach_broadcast_rgb_property(&connector->base.base); 2430 intel_sdvo->color_range_auto = true; 2431 } 2432 } 2433 2434 static bool 2435 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2436 { 2437 struct drm_encoder *encoder = &intel_sdvo->base.base; 2438 struct drm_connector *connector; 2439 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2440 struct intel_connector *intel_connector; 2441 struct intel_sdvo_connector *intel_sdvo_connector; 2442 2443 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2444 2445 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); 2446 if (!intel_sdvo_connector) 2447 return false; 2448 2449 if (device == 0) { 2450 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2451 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2452 } else if (device == 1) { 2453 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2454 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2455 } 2456 2457 intel_connector = &intel_sdvo_connector->base; 2458 connector = &intel_connector->base; 2459 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2460 intel_sdvo_connector->output_flag) { 2461 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2462 /* Some SDVO devices have one-shot hotplug interrupts. 2463 * Ensure that they get re-enabled when an interrupt happens. 2464 */ 2465 intel_encoder->hot_plug = intel_sdvo_enable_hotplug; 2466 intel_sdvo_enable_hotplug(intel_encoder); 2467 } else { 2468 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2469 } 2470 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2471 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2472 2473 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2474 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2475 intel_sdvo->is_hdmi = true; 2476 } 2477 2478 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2479 kfree(intel_sdvo_connector); 2480 return false; 2481 } 2482 2483 if (intel_sdvo->is_hdmi) 2484 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2485 2486 return true; 2487 } 2488 2489 static bool 2490 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2491 { 2492 struct drm_encoder *encoder = &intel_sdvo->base.base; 2493 struct drm_connector *connector; 2494 struct intel_connector *intel_connector; 2495 struct intel_sdvo_connector *intel_sdvo_connector; 2496 2497 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2498 2499 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); 2500 if (!intel_sdvo_connector) 2501 return false; 2502 2503 intel_connector = &intel_sdvo_connector->base; 2504 connector = &intel_connector->base; 2505 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2506 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2507 2508 intel_sdvo->controlled_output |= type; 2509 intel_sdvo_connector->output_flag = type; 2510 2511 intel_sdvo->is_tv = true; 2512 2513 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2514 kfree(intel_sdvo_connector); 2515 return false; 2516 } 2517 2518 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2519 goto err; 2520 2521 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2522 goto err; 2523 2524 return true; 2525 2526 err: 2527 drm_connector_unregister(connector); 2528 intel_sdvo_destroy(connector); 2529 return false; 2530 } 2531 2532 static bool 2533 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2534 { 2535 struct drm_encoder *encoder = &intel_sdvo->base.base; 2536 struct drm_connector *connector; 2537 struct intel_connector *intel_connector; 2538 struct intel_sdvo_connector *intel_sdvo_connector; 2539 2540 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2541 2542 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); 2543 if (!intel_sdvo_connector) 2544 return false; 2545 2546 intel_connector = &intel_sdvo_connector->base; 2547 connector = &intel_connector->base; 2548 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2549 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2550 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2551 2552 if (device == 0) { 2553 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2554 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2555 } else if (device == 1) { 2556 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2557 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2558 } 2559 2560 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2561 kfree(intel_sdvo_connector); 2562 return false; 2563 } 2564 2565 return true; 2566 } 2567 2568 static bool 2569 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2570 { 2571 struct drm_encoder *encoder = &intel_sdvo->base.base; 2572 struct drm_connector *connector; 2573 struct intel_connector *intel_connector; 2574 struct intel_sdvo_connector *intel_sdvo_connector; 2575 2576 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2577 2578 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); 2579 if (!intel_sdvo_connector) 2580 return false; 2581 2582 intel_connector = &intel_sdvo_connector->base; 2583 connector = &intel_connector->base; 2584 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2585 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2586 2587 if (device == 0) { 2588 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2589 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2590 } else if (device == 1) { 2591 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2592 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2593 } 2594 2595 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2596 kfree(intel_sdvo_connector); 2597 return false; 2598 } 2599 2600 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2601 goto err; 2602 2603 return true; 2604 2605 err: 2606 drm_connector_unregister(connector); 2607 intel_sdvo_destroy(connector); 2608 return false; 2609 } 2610 2611 static bool 2612 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2613 { 2614 intel_sdvo->is_tv = false; 2615 intel_sdvo->is_lvds = false; 2616 2617 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2618 2619 if (flags & SDVO_OUTPUT_TMDS0) 2620 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2621 return false; 2622 2623 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2624 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2625 return false; 2626 2627 /* TV has no XXX1 function block */ 2628 if (flags & SDVO_OUTPUT_SVID0) 2629 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2630 return false; 2631 2632 if (flags & SDVO_OUTPUT_CVBS0) 2633 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2634 return false; 2635 2636 if (flags & SDVO_OUTPUT_YPRPB0) 2637 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2638 return false; 2639 2640 if (flags & SDVO_OUTPUT_RGB0) 2641 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2642 return false; 2643 2644 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2645 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2646 return false; 2647 2648 if (flags & SDVO_OUTPUT_LVDS0) 2649 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2650 return false; 2651 2652 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2653 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2654 return false; 2655 2656 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2657 unsigned char bytes[2]; 2658 2659 intel_sdvo->controlled_output = 0; 2660 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2661 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2662 SDVO_NAME(intel_sdvo), 2663 bytes[0], bytes[1]); 2664 return false; 2665 } 2666 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2667 2668 return true; 2669 } 2670 2671 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2672 { 2673 struct drm_device *dev = intel_sdvo->base.base.dev; 2674 struct drm_connector *connector, *tmp; 2675 2676 list_for_each_entry_safe(connector, tmp, 2677 &dev->mode_config.connector_list, head) { 2678 if (intel_attached_encoder(connector) == &intel_sdvo->base) { 2679 drm_connector_unregister(connector); 2680 intel_sdvo_destroy(connector); 2681 } 2682 } 2683 } 2684 2685 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2686 struct intel_sdvo_connector *intel_sdvo_connector, 2687 int type) 2688 { 2689 struct drm_device *dev = intel_sdvo->base.base.dev; 2690 struct intel_sdvo_tv_format format; 2691 uint32_t format_map, i; 2692 2693 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2694 return false; 2695 2696 BUILD_BUG_ON(sizeof(format) != 6); 2697 if (!intel_sdvo_get_value(intel_sdvo, 2698 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2699 &format, sizeof(format))) 2700 return false; 2701 2702 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2703 2704 if (format_map == 0) 2705 return false; 2706 2707 intel_sdvo_connector->format_supported_num = 0; 2708 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2709 if (format_map & (1 << i)) 2710 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2711 2712 2713 intel_sdvo_connector->tv_format = 2714 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2715 "mode", intel_sdvo_connector->format_supported_num); 2716 if (!intel_sdvo_connector->tv_format) 2717 return false; 2718 2719 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2720 drm_property_add_enum( 2721 intel_sdvo_connector->tv_format, i, 2722 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2723 2724 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2725 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2726 intel_sdvo_connector->tv_format, 0); 2727 return true; 2728 2729 } 2730 2731 #define ENHANCEMENT(name, NAME) do { \ 2732 if (enhancements.name) { \ 2733 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2734 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2735 return false; \ 2736 intel_sdvo_connector->max_##name = data_value[0]; \ 2737 intel_sdvo_connector->cur_##name = response; \ 2738 intel_sdvo_connector->name = \ 2739 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2740 if (!intel_sdvo_connector->name) return false; \ 2741 drm_object_attach_property(&connector->base, \ 2742 intel_sdvo_connector->name, \ 2743 intel_sdvo_connector->cur_##name); \ 2744 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2745 data_value[0], data_value[1], response); \ 2746 } \ 2747 } while (0) 2748 2749 static bool 2750 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2751 struct intel_sdvo_connector *intel_sdvo_connector, 2752 struct intel_sdvo_enhancements_reply enhancements) 2753 { 2754 struct drm_device *dev = intel_sdvo->base.base.dev; 2755 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2756 uint16_t response, data_value[2]; 2757 2758 /* when horizontal overscan is supported, Add the left/right property */ 2759 if (enhancements.overscan_h) { 2760 if (!intel_sdvo_get_value(intel_sdvo, 2761 SDVO_CMD_GET_MAX_OVERSCAN_H, 2762 &data_value, 4)) 2763 return false; 2764 2765 if (!intel_sdvo_get_value(intel_sdvo, 2766 SDVO_CMD_GET_OVERSCAN_H, 2767 &response, 2)) 2768 return false; 2769 2770 intel_sdvo_connector->max_hscan = data_value[0]; 2771 intel_sdvo_connector->left_margin = data_value[0] - response; 2772 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2773 intel_sdvo_connector->left = 2774 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2775 if (!intel_sdvo_connector->left) 2776 return false; 2777 2778 drm_object_attach_property(&connector->base, 2779 intel_sdvo_connector->left, 2780 intel_sdvo_connector->left_margin); 2781 2782 intel_sdvo_connector->right = 2783 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2784 if (!intel_sdvo_connector->right) 2785 return false; 2786 2787 drm_object_attach_property(&connector->base, 2788 intel_sdvo_connector->right, 2789 intel_sdvo_connector->right_margin); 2790 DRM_DEBUG_KMS("h_overscan: max %d, " 2791 "default %d, current %d\n", 2792 data_value[0], data_value[1], response); 2793 } 2794 2795 if (enhancements.overscan_v) { 2796 if (!intel_sdvo_get_value(intel_sdvo, 2797 SDVO_CMD_GET_MAX_OVERSCAN_V, 2798 &data_value, 4)) 2799 return false; 2800 2801 if (!intel_sdvo_get_value(intel_sdvo, 2802 SDVO_CMD_GET_OVERSCAN_V, 2803 &response, 2)) 2804 return false; 2805 2806 intel_sdvo_connector->max_vscan = data_value[0]; 2807 intel_sdvo_connector->top_margin = data_value[0] - response; 2808 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2809 intel_sdvo_connector->top = 2810 drm_property_create_range(dev, 0, 2811 "top_margin", 0, data_value[0]); 2812 if (!intel_sdvo_connector->top) 2813 return false; 2814 2815 drm_object_attach_property(&connector->base, 2816 intel_sdvo_connector->top, 2817 intel_sdvo_connector->top_margin); 2818 2819 intel_sdvo_connector->bottom = 2820 drm_property_create_range(dev, 0, 2821 "bottom_margin", 0, data_value[0]); 2822 if (!intel_sdvo_connector->bottom) 2823 return false; 2824 2825 drm_object_attach_property(&connector->base, 2826 intel_sdvo_connector->bottom, 2827 intel_sdvo_connector->bottom_margin); 2828 DRM_DEBUG_KMS("v_overscan: max %d, " 2829 "default %d, current %d\n", 2830 data_value[0], data_value[1], response); 2831 } 2832 2833 ENHANCEMENT(hpos, HPOS); 2834 ENHANCEMENT(vpos, VPOS); 2835 ENHANCEMENT(saturation, SATURATION); 2836 ENHANCEMENT(contrast, CONTRAST); 2837 ENHANCEMENT(hue, HUE); 2838 ENHANCEMENT(sharpness, SHARPNESS); 2839 ENHANCEMENT(brightness, BRIGHTNESS); 2840 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2841 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2842 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2843 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2844 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2845 2846 if (enhancements.dot_crawl) { 2847 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2848 return false; 2849 2850 intel_sdvo_connector->max_dot_crawl = 1; 2851 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2852 intel_sdvo_connector->dot_crawl = 2853 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2854 if (!intel_sdvo_connector->dot_crawl) 2855 return false; 2856 2857 drm_object_attach_property(&connector->base, 2858 intel_sdvo_connector->dot_crawl, 2859 intel_sdvo_connector->cur_dot_crawl); 2860 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2861 } 2862 2863 return true; 2864 } 2865 2866 static bool 2867 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2868 struct intel_sdvo_connector *intel_sdvo_connector, 2869 struct intel_sdvo_enhancements_reply enhancements) 2870 { 2871 struct drm_device *dev = intel_sdvo->base.base.dev; 2872 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2873 uint16_t response, data_value[2]; 2874 2875 ENHANCEMENT(brightness, BRIGHTNESS); 2876 2877 return true; 2878 } 2879 #undef ENHANCEMENT 2880 2881 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2882 struct intel_sdvo_connector *intel_sdvo_connector) 2883 { 2884 union { 2885 struct intel_sdvo_enhancements_reply reply; 2886 uint16_t response; 2887 } enhancements; 2888 2889 BUILD_BUG_ON(sizeof(enhancements) != 2); 2890 2891 enhancements.response = 0; 2892 intel_sdvo_get_value(intel_sdvo, 2893 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2894 &enhancements, sizeof(enhancements)); 2895 if (enhancements.response == 0) { 2896 DRM_DEBUG_KMS("No enhancement is supported\n"); 2897 return true; 2898 } 2899 2900 if (IS_TV(intel_sdvo_connector)) 2901 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2902 else if (IS_LVDS(intel_sdvo_connector)) 2903 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2904 else 2905 return true; 2906 } 2907 2908 struct intel_sdvo_ddc_proxy_sc { 2909 struct intel_sdvo *intel_sdvo; 2910 device_t port; 2911 }; 2912 2913 static int 2914 intel_sdvo_ddc_proxy_probe(device_t idev) 2915 { 2916 2917 return (BUS_PROBE_DEFAULT); 2918 } 2919 2920 static int 2921 intel_sdvo_ddc_proxy_attach(device_t idev) 2922 { 2923 struct intel_sdvo_ddc_proxy_sc *sc; 2924 2925 sc = device_get_softc(idev); 2926 sc->port = device_add_child(idev, "iicbus", -1); 2927 if (sc->port == NULL) 2928 return (ENXIO); 2929 device_quiet(sc->port); 2930 bus_generic_attach(idev); 2931 return (0); 2932 } 2933 2934 static int 2935 intel_sdvo_ddc_proxy_detach(device_t idev) 2936 { 2937 struct intel_sdvo_ddc_proxy_sc *sc; 2938 device_t port; 2939 2940 sc = device_get_softc(idev); 2941 port = sc->port; 2942 bus_generic_detach(idev); 2943 if (port != NULL) 2944 device_delete_child(idev, port); 2945 return (0); 2946 } 2947 2948 static int 2949 intel_sdvo_ddc_proxy_reset(device_t idev, u_char speed, u_char addr, 2950 u_char *oldaddr) 2951 { 2952 struct intel_sdvo_ddc_proxy_sc *sc; 2953 struct intel_sdvo *sdvo; 2954 2955 sc = device_get_softc(idev); 2956 sdvo = sc->intel_sdvo; 2957 2958 return (IICBUS_RESET(device_get_parent(sdvo->i2c), speed, addr, 2959 oldaddr)); 2960 } 2961 2962 static int intel_sdvo_ddc_proxy_xfer(struct device *adapter, 2963 struct i2c_msg *msgs, 2964 int num) 2965 { 2966 struct intel_sdvo_ddc_proxy_sc *sc = device_get_softc(adapter); 2967 struct intel_sdvo *sdvo = sc->intel_sdvo; 2968 2969 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2970 return -EIO; 2971 2972 return (iicbus_transfer(sdvo->i2c, msgs, num)); 2973 } 2974 2975 static bool 2976 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, struct drm_device *dev, 2977 int sdvo_reg) 2978 { 2979 struct intel_sdvo_ddc_proxy_sc *sc; 2980 int ret; 2981 2982 sdvo->ddc_iic_bus = device_add_child(dev->dev, 2983 "intel_sdvo_ddc_proxy", sdvo_reg); 2984 if (sdvo->ddc_iic_bus == NULL) { 2985 DRM_ERROR("cannot create ddc proxy bus %d\n", sdvo_reg); 2986 return (false); 2987 } 2988 device_quiet(sdvo->ddc_iic_bus); 2989 ret = device_probe_and_attach(sdvo->ddc_iic_bus); 2990 if (ret != 0) { 2991 DRM_ERROR("cannot attach proxy bus %d error %d\n", 2992 sdvo_reg, ret); 2993 device_delete_child(dev->dev, sdvo->ddc_iic_bus); 2994 return (false); 2995 } 2996 sc = device_get_softc(sdvo->ddc_iic_bus); 2997 sc->intel_sdvo = sdvo; 2998 2999 sdvo->ddc = sc->port; 3000 return (true); 3001 } 3002 3003 static device_method_t intel_sdvo_ddc_proxy_methods[] = { 3004 DEVMETHOD(device_probe, intel_sdvo_ddc_proxy_probe), 3005 DEVMETHOD(device_attach, intel_sdvo_ddc_proxy_attach), 3006 DEVMETHOD(device_detach, intel_sdvo_ddc_proxy_detach), 3007 DEVMETHOD(iicbus_reset, intel_sdvo_ddc_proxy_reset), 3008 DEVMETHOD(iicbus_transfer, intel_sdvo_ddc_proxy_xfer), 3009 DEVMETHOD_END 3010 }; 3011 static driver_t intel_sdvo_ddc_proxy_driver = { 3012 "intel_sdvo_ddc_proxy", 3013 intel_sdvo_ddc_proxy_methods, 3014 sizeof(struct intel_sdvo_ddc_proxy_sc) 3015 }; 3016 static devclass_t intel_sdvo_devclass; 3017 DRIVER_MODULE_ORDERED(intel_sdvo_ddc_proxy, drm, intel_sdvo_ddc_proxy_driver, 3018 intel_sdvo_devclass, NULL, NULL, SI_ORDER_FIRST); 3019 3020 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) 3021 { 3022 struct drm_i915_private *dev_priv = dev->dev_private; 3023 struct intel_encoder *intel_encoder; 3024 struct intel_sdvo *intel_sdvo; 3025 int i; 3026 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3027 if (!intel_sdvo) 3028 return false; 3029 3030 intel_sdvo->sdvo_reg = sdvo_reg; 3031 intel_sdvo->is_sdvob = is_sdvob; 3032 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; 3033 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); 3034 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev, sdvo_reg)) 3035 goto err_i2c_bus; 3036 3037 /* encoder type will be decided later */ 3038 intel_encoder = &intel_sdvo->base; 3039 intel_encoder->type = INTEL_OUTPUT_SDVO; 3040 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); 3041 3042 /* Read the regs to test if we can talk to the device */ 3043 for (i = 0; i < 0x40; i++) { 3044 u8 byte; 3045 3046 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3047 DRM_DEBUG_KMS("No SDVO device found on %s\n", 3048 SDVO_NAME(intel_sdvo)); 3049 goto err; 3050 } 3051 } 3052 3053 intel_encoder->compute_config = intel_sdvo_compute_config; 3054 intel_encoder->disable = intel_disable_sdvo; 3055 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3056 intel_encoder->enable = intel_enable_sdvo; 3057 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3058 intel_encoder->get_config = intel_sdvo_get_config; 3059 3060 /* In default case sdvo lvds is false */ 3061 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3062 goto err; 3063 3064 if (intel_sdvo_output_setup(intel_sdvo, 3065 intel_sdvo->caps.output_flags) != true) { 3066 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 3067 SDVO_NAME(intel_sdvo)); 3068 /* Output_setup can leave behind connectors! */ 3069 goto err_output; 3070 } 3071 3072 /* Only enable the hotplug irq if we need it, to work around noisy 3073 * hotplug lines. 3074 */ 3075 if (intel_sdvo->hotplug_active) { 3076 intel_encoder->hpd_pin = 3077 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; 3078 } 3079 3080 /* 3081 * Cloning SDVO with anything is often impossible, since the SDVO 3082 * encoder can request a special input timing mode. And even if that's 3083 * not the case we have evidence that cloning a plain unscaled mode with 3084 * VGA doesn't really work. Furthermore the cloning flags are way too 3085 * simplistic anyway to express such constraints, so just give up on 3086 * cloning for SDVO encoders. 3087 */ 3088 intel_sdvo->base.cloneable = 0; 3089 3090 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 3091 3092 /* Set the input timing to the screen. Assume always input 0. */ 3093 if (!intel_sdvo_set_target_input(intel_sdvo)) 3094 goto err_output; 3095 3096 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3097 &intel_sdvo->pixel_clock_min, 3098 &intel_sdvo->pixel_clock_max)) 3099 goto err_output; 3100 3101 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3102 "clock range %dMHz - %dMHz, " 3103 "input 1: %c, input 2: %c, " 3104 "output 1: %c, output 2: %c\n", 3105 SDVO_NAME(intel_sdvo), 3106 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3107 intel_sdvo->caps.device_rev_id, 3108 intel_sdvo->pixel_clock_min / 1000, 3109 intel_sdvo->pixel_clock_max / 1000, 3110 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3111 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3112 /* check currently supported outputs */ 3113 intel_sdvo->caps.output_flags & 3114 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3115 intel_sdvo->caps.output_flags & 3116 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3117 return true; 3118 3119 err_output: 3120 intel_sdvo_output_cleanup(intel_sdvo); 3121 3122 err: 3123 drm_encoder_cleanup(&intel_encoder->base); 3124 err_i2c_bus: 3125 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3126 kfree(intel_sdvo); 3127 3128 return false; 3129 } 3130