1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 * $FreeBSD: src/sys/dev/drm2/i915/intel_sdvo_regs.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 27 */ 28 29 /** 30 * @file SDVO command definitions and structures. 31 */ 32 33 #define SDVO_OUTPUT_FIRST (0) 34 #define SDVO_OUTPUT_TMDS0 (1 << 0) 35 #define SDVO_OUTPUT_RGB0 (1 << 1) 36 #define SDVO_OUTPUT_CVBS0 (1 << 2) 37 #define SDVO_OUTPUT_SVID0 (1 << 3) 38 #define SDVO_OUTPUT_YPRPB0 (1 << 4) 39 #define SDVO_OUTPUT_SCART0 (1 << 5) 40 #define SDVO_OUTPUT_LVDS0 (1 << 6) 41 #define SDVO_OUTPUT_TMDS1 (1 << 8) 42 #define SDVO_OUTPUT_RGB1 (1 << 9) 43 #define SDVO_OUTPUT_CVBS1 (1 << 10) 44 #define SDVO_OUTPUT_SVID1 (1 << 11) 45 #define SDVO_OUTPUT_YPRPB1 (1 << 12) 46 #define SDVO_OUTPUT_SCART1 (1 << 13) 47 #define SDVO_OUTPUT_LVDS1 (1 << 14) 48 #define SDVO_OUTPUT_LAST (14) 49 50 struct intel_sdvo_caps { 51 u8 vendor_id; 52 u8 device_id; 53 u8 device_rev_id; 54 u8 sdvo_version_major; 55 u8 sdvo_version_minor; 56 unsigned int sdvo_inputs_mask:2; 57 unsigned int smooth_scaling:1; 58 unsigned int sharp_scaling:1; 59 unsigned int up_scaling:1; 60 unsigned int down_scaling:1; 61 unsigned int stall_support:1; 62 unsigned int pad:1; 63 u16 output_flags; 64 } __attribute__((packed)); 65 66 /** This matches the EDID DTD structure, more or less */ 67 struct intel_sdvo_dtd { 68 struct { 69 u16 clock; /**< pixel clock, in 10kHz units */ 70 u8 h_active; /**< lower 8 bits (pixels) */ 71 u8 h_blank; /**< lower 8 bits (pixels) */ 72 u8 h_high; /**< upper 4 bits each h_active, h_blank */ 73 u8 v_active; /**< lower 8 bits (lines) */ 74 u8 v_blank; /**< lower 8 bits (lines) */ 75 u8 v_high; /**< upper 4 bits each v_active, v_blank */ 76 } part1; 77 78 struct { 79 u8 h_sync_off; /**< lower 8 bits, from hblank start */ 80 u8 h_sync_width; /**< lower 8 bits (pixels) */ 81 /** lower 4 bits each vsync offset, vsync width */ 82 u8 v_sync_off_width; 83 /** 84 * 2 high bits of hsync offset, 2 high bits of hsync width, 85 * bits 4-5 of vsync offset, and 2 high bits of vsync width. 86 */ 87 u8 sync_off_width_high; 88 u8 dtd_flags; 89 u8 sdvo_flags; 90 /** bits 6-7 of vsync offset at bits 6-7 */ 91 u8 v_sync_off_high; 92 u8 reserved; 93 } part2; 94 } __attribute__((packed)); 95 96 struct intel_sdvo_pixel_clock_range { 97 u16 min; /**< pixel clock, in 10kHz units */ 98 u16 max; /**< pixel clock, in 10kHz units */ 99 } __attribute__((packed)); 100 101 struct intel_sdvo_preferred_input_timing_args { 102 u16 clock; 103 u16 width; 104 u16 height; 105 u8 interlace:1; 106 u8 scaled:1; 107 u8 pad:6; 108 } __attribute__((packed)); 109 110 /* I2C registers for SDVO */ 111 #define SDVO_I2C_ARG_0 0x07 112 #define SDVO_I2C_ARG_1 0x06 113 #define SDVO_I2C_ARG_2 0x05 114 #define SDVO_I2C_ARG_3 0x04 115 #define SDVO_I2C_ARG_4 0x03 116 #define SDVO_I2C_ARG_5 0x02 117 #define SDVO_I2C_ARG_6 0x01 118 #define SDVO_I2C_ARG_7 0x00 119 #define SDVO_I2C_OPCODE 0x08 120 #define SDVO_I2C_CMD_STATUS 0x09 121 #define SDVO_I2C_RETURN_0 0x0a 122 #define SDVO_I2C_RETURN_1 0x0b 123 #define SDVO_I2C_RETURN_2 0x0c 124 #define SDVO_I2C_RETURN_3 0x0d 125 #define SDVO_I2C_RETURN_4 0x0e 126 #define SDVO_I2C_RETURN_5 0x0f 127 #define SDVO_I2C_RETURN_6 0x10 128 #define SDVO_I2C_RETURN_7 0x11 129 #define SDVO_I2C_VENDOR_BEGIN 0x20 130 131 /* Status results */ 132 #define SDVO_CMD_STATUS_POWER_ON 0x0 133 #define SDVO_CMD_STATUS_SUCCESS 0x1 134 #define SDVO_CMD_STATUS_NOTSUPP 0x2 135 #define SDVO_CMD_STATUS_INVALID_ARG 0x3 136 #define SDVO_CMD_STATUS_PENDING 0x4 137 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5 138 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6 139 140 /* SDVO commands, argument/result registers */ 141 142 #define SDVO_CMD_RESET 0x01 143 144 /** Returns a struct intel_sdvo_caps */ 145 #define SDVO_CMD_GET_DEVICE_CAPS 0x02 146 147 #define SDVO_CMD_GET_FIRMWARE_REV 0x86 148 # define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0 149 # define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1 150 # define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2 151 152 /** 153 * Reports which inputs are trained (managed to sync). 154 * 155 * Devices must have trained within 2 vsyncs of a mode change. 156 */ 157 #define SDVO_CMD_GET_TRAINED_INPUTS 0x03 158 struct intel_sdvo_get_trained_inputs_response { 159 unsigned int input0_trained:1; 160 unsigned int input1_trained:1; 161 unsigned int pad:6; 162 } __attribute__((packed)); 163 164 /** Returns a struct intel_sdvo_output_flags of active outputs. */ 165 #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 166 167 /** 168 * Sets the current set of active outputs. 169 * 170 * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP 171 * on multi-output devices. 172 */ 173 #define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05 174 175 /** 176 * Returns the current mapping of SDVO inputs to outputs on the device. 177 * 178 * Returns two struct intel_sdvo_output_flags structures. 179 */ 180 #define SDVO_CMD_GET_IN_OUT_MAP 0x06 181 struct intel_sdvo_in_out_map { 182 u16 in0, in1; 183 }; 184 185 /** 186 * Sets the current mapping of SDVO inputs to outputs on the device. 187 * 188 * Takes two struct i380_sdvo_output_flags structures. 189 */ 190 #define SDVO_CMD_SET_IN_OUT_MAP 0x07 191 192 /** 193 * Returns a struct intel_sdvo_output_flags of attached displays. 194 */ 195 #define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b 196 197 /** 198 * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging. 199 */ 200 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c 201 202 /** 203 * Takes a struct intel_sdvo_output_flags. 204 */ 205 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d 206 207 /** 208 * Returns a struct intel_sdvo_output_flags of displays with hot plug 209 * interrupts enabled. 210 */ 211 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e 212 213 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f 214 struct intel_sdvo_get_interrupt_event_source_response { 215 u16 interrupt_status; 216 unsigned int ambient_light_interrupt:1; 217 unsigned int hdmi_audio_encrypt_change:1; 218 unsigned int pad:6; 219 } __attribute__((packed)); 220 221 /** 222 * Selects which input is affected by future input commands. 223 * 224 * Commands affected include SET_INPUT_TIMINGS_PART[12], 225 * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12], 226 * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS. 227 */ 228 #define SDVO_CMD_SET_TARGET_INPUT 0x10 229 struct intel_sdvo_set_target_input_args { 230 unsigned int target_1:1; 231 unsigned int pad:7; 232 } __attribute__((packed)); 233 234 /** 235 * Takes a struct intel_sdvo_output_flags of which outputs are targeted by 236 * future output commands. 237 * 238 * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], 239 * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. 240 */ 241 #define SDVO_CMD_SET_TARGET_OUTPUT 0x11 242 243 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12 244 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13 245 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14 246 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15 247 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16 248 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17 249 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18 250 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19 251 /* Part 1 */ 252 # define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0 253 # define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1 254 # define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2 255 # define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3 256 # define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4 257 # define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5 258 # define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6 259 # define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7 260 /* Part 2 */ 261 # define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0 262 # define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1 263 # define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2 264 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3 265 # define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4 266 # define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7) 267 # define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5) 268 # define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3) 269 # define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1) 270 # define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5 271 # define SDVO_DTD_SDVO_FLAG_STALL (1 << 7) 272 # define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6) 273 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6) 274 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4) 275 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4) 276 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4) 277 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4) 278 # define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6 279 280 /** 281 * Generates a DTD based on the given width, height, and flags. 282 * 283 * This will be supported by any device supporting scaling or interlaced 284 * modes. 285 */ 286 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a 287 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0 288 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1 289 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2 290 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3 291 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4 292 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5 293 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6 294 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0) 295 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1) 296 297 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b 298 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c 299 300 /** Returns a struct intel_sdvo_pixel_clock_range */ 301 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d 302 /** Returns a struct intel_sdvo_pixel_clock_range */ 303 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e 304 305 /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ 306 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f 307 308 /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 309 #define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20 310 /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ 311 #define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21 312 # define SDVO_CLOCK_RATE_MULT_1X (1 << 0) 313 # define SDVO_CLOCK_RATE_MULT_2X (1 << 1) 314 # define SDVO_CLOCK_RATE_MULT_4X (1 << 3) 315 316 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 317 /** 6 bytes of bit flags for TV formats shared by all TV format functions */ 318 struct intel_sdvo_tv_format { 319 unsigned int ntsc_m:1; 320 unsigned int ntsc_j:1; 321 unsigned int ntsc_443:1; 322 unsigned int pal_b:1; 323 unsigned int pal_d:1; 324 unsigned int pal_g:1; 325 unsigned int pal_h:1; 326 unsigned int pal_i:1; 327 328 unsigned int pal_m:1; 329 unsigned int pal_n:1; 330 unsigned int pal_nc:1; 331 unsigned int pal_60:1; 332 unsigned int secam_b:1; 333 unsigned int secam_d:1; 334 unsigned int secam_g:1; 335 unsigned int secam_k:1; 336 337 unsigned int secam_k1:1; 338 unsigned int secam_l:1; 339 unsigned int secam_60:1; 340 unsigned int hdtv_std_smpte_240m_1080i_59:1; 341 unsigned int hdtv_std_smpte_240m_1080i_60:1; 342 unsigned int hdtv_std_smpte_260m_1080i_59:1; 343 unsigned int hdtv_std_smpte_260m_1080i_60:1; 344 unsigned int hdtv_std_smpte_274m_1080i_50:1; 345 346 unsigned int hdtv_std_smpte_274m_1080i_59:1; 347 unsigned int hdtv_std_smpte_274m_1080i_60:1; 348 unsigned int hdtv_std_smpte_274m_1080p_23:1; 349 unsigned int hdtv_std_smpte_274m_1080p_24:1; 350 unsigned int hdtv_std_smpte_274m_1080p_25:1; 351 unsigned int hdtv_std_smpte_274m_1080p_29:1; 352 unsigned int hdtv_std_smpte_274m_1080p_30:1; 353 unsigned int hdtv_std_smpte_274m_1080p_50:1; 354 355 unsigned int hdtv_std_smpte_274m_1080p_59:1; 356 unsigned int hdtv_std_smpte_274m_1080p_60:1; 357 unsigned int hdtv_std_smpte_295m_1080i_50:1; 358 unsigned int hdtv_std_smpte_295m_1080p_50:1; 359 unsigned int hdtv_std_smpte_296m_720p_59:1; 360 unsigned int hdtv_std_smpte_296m_720p_60:1; 361 unsigned int hdtv_std_smpte_296m_720p_50:1; 362 unsigned int hdtv_std_smpte_293m_480p_59:1; 363 364 unsigned int hdtv_std_smpte_170m_480i_59:1; 365 unsigned int hdtv_std_iturbt601_576i_50:1; 366 unsigned int hdtv_std_iturbt601_576p_50:1; 367 unsigned int hdtv_std_eia_7702a_480i_60:1; 368 unsigned int hdtv_std_eia_7702a_480p_60:1; 369 unsigned int pad:3; 370 } __attribute__((packed)); 371 372 #define SDVO_CMD_GET_TV_FORMAT 0x28 373 374 #define SDVO_CMD_SET_TV_FORMAT 0x29 375 376 /** Returns the resolutiosn that can be used with the given TV format */ 377 #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83 378 struct intel_sdvo_sdtv_resolution_request { 379 unsigned int ntsc_m:1; 380 unsigned int ntsc_j:1; 381 unsigned int ntsc_443:1; 382 unsigned int pal_b:1; 383 unsigned int pal_d:1; 384 unsigned int pal_g:1; 385 unsigned int pal_h:1; 386 unsigned int pal_i:1; 387 388 unsigned int pal_m:1; 389 unsigned int pal_n:1; 390 unsigned int pal_nc:1; 391 unsigned int pal_60:1; 392 unsigned int secam_b:1; 393 unsigned int secam_d:1; 394 unsigned int secam_g:1; 395 unsigned int secam_k:1; 396 397 unsigned int secam_k1:1; 398 unsigned int secam_l:1; 399 unsigned int secam_60:1; 400 unsigned int pad:5; 401 } __attribute__((packed)); 402 403 struct intel_sdvo_sdtv_resolution_reply { 404 unsigned int res_320x200:1; 405 unsigned int res_320x240:1; 406 unsigned int res_400x300:1; 407 unsigned int res_640x350:1; 408 unsigned int res_640x400:1; 409 unsigned int res_640x480:1; 410 unsigned int res_704x480:1; 411 unsigned int res_704x576:1; 412 413 unsigned int res_720x350:1; 414 unsigned int res_720x400:1; 415 unsigned int res_720x480:1; 416 unsigned int res_720x540:1; 417 unsigned int res_720x576:1; 418 unsigned int res_768x576:1; 419 unsigned int res_800x600:1; 420 unsigned int res_832x624:1; 421 422 unsigned int res_920x766:1; 423 unsigned int res_1024x768:1; 424 unsigned int res_1280x1024:1; 425 unsigned int pad:5; 426 } __attribute__((packed)); 427 428 /* Get supported resolution with squire pixel aspect ratio that can be 429 scaled for the requested HDTV format */ 430 #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85 431 432 struct intel_sdvo_hdtv_resolution_request { 433 unsigned int hdtv_std_smpte_240m_1080i_59:1; 434 unsigned int hdtv_std_smpte_240m_1080i_60:1; 435 unsigned int hdtv_std_smpte_260m_1080i_59:1; 436 unsigned int hdtv_std_smpte_260m_1080i_60:1; 437 unsigned int hdtv_std_smpte_274m_1080i_50:1; 438 unsigned int hdtv_std_smpte_274m_1080i_59:1; 439 unsigned int hdtv_std_smpte_274m_1080i_60:1; 440 unsigned int hdtv_std_smpte_274m_1080p_23:1; 441 442 unsigned int hdtv_std_smpte_274m_1080p_24:1; 443 unsigned int hdtv_std_smpte_274m_1080p_25:1; 444 unsigned int hdtv_std_smpte_274m_1080p_29:1; 445 unsigned int hdtv_std_smpte_274m_1080p_30:1; 446 unsigned int hdtv_std_smpte_274m_1080p_50:1; 447 unsigned int hdtv_std_smpte_274m_1080p_59:1; 448 unsigned int hdtv_std_smpte_274m_1080p_60:1; 449 unsigned int hdtv_std_smpte_295m_1080i_50:1; 450 451 unsigned int hdtv_std_smpte_295m_1080p_50:1; 452 unsigned int hdtv_std_smpte_296m_720p_59:1; 453 unsigned int hdtv_std_smpte_296m_720p_60:1; 454 unsigned int hdtv_std_smpte_296m_720p_50:1; 455 unsigned int hdtv_std_smpte_293m_480p_59:1; 456 unsigned int hdtv_std_smpte_170m_480i_59:1; 457 unsigned int hdtv_std_iturbt601_576i_50:1; 458 unsigned int hdtv_std_iturbt601_576p_50:1; 459 460 unsigned int hdtv_std_eia_7702a_480i_60:1; 461 unsigned int hdtv_std_eia_7702a_480p_60:1; 462 unsigned int pad:6; 463 } __attribute__((packed)); 464 465 struct intel_sdvo_hdtv_resolution_reply { 466 unsigned int res_640x480:1; 467 unsigned int res_800x600:1; 468 unsigned int res_1024x768:1; 469 unsigned int res_1280x960:1; 470 unsigned int res_1400x1050:1; 471 unsigned int res_1600x1200:1; 472 unsigned int res_1920x1440:1; 473 unsigned int res_2048x1536:1; 474 475 unsigned int res_2560x1920:1; 476 unsigned int res_3200x2400:1; 477 unsigned int res_3840x2880:1; 478 unsigned int pad1:5; 479 480 unsigned int res_848x480:1; 481 unsigned int res_1064x600:1; 482 unsigned int res_1280x720:1; 483 unsigned int res_1360x768:1; 484 unsigned int res_1704x960:1; 485 unsigned int res_1864x1050:1; 486 unsigned int res_1920x1080:1; 487 unsigned int res_2128x1200:1; 488 489 unsigned int res_2560x1400:1; 490 unsigned int res_2728x1536:1; 491 unsigned int res_3408x1920:1; 492 unsigned int res_4264x2400:1; 493 unsigned int res_5120x2880:1; 494 unsigned int pad2:3; 495 496 unsigned int res_768x480:1; 497 unsigned int res_960x600:1; 498 unsigned int res_1152x720:1; 499 unsigned int res_1124x768:1; 500 unsigned int res_1536x960:1; 501 unsigned int res_1680x1050:1; 502 unsigned int res_1728x1080:1; 503 unsigned int res_1920x1200:1; 504 505 unsigned int res_2304x1440:1; 506 unsigned int res_2456x1536:1; 507 unsigned int res_3072x1920:1; 508 unsigned int res_3840x2400:1; 509 unsigned int res_4608x2880:1; 510 unsigned int pad3:3; 511 512 unsigned int res_1280x1024:1; 513 unsigned int pad4:7; 514 515 unsigned int res_1280x768:1; 516 unsigned int pad5:7; 517 } __attribute__((packed)); 518 519 /* Get supported power state returns info for encoder and monitor, rely on 520 last SetTargetInput and SetTargetOutput calls */ 521 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a 522 /* Get power state returns info for encoder and monitor, rely on last 523 SetTargetInput and SetTargetOutput calls */ 524 #define SDVO_CMD_GET_POWER_STATE 0x2b 525 #define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b 526 #define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c 527 # define SDVO_ENCODER_STATE_ON (1 << 0) 528 # define SDVO_ENCODER_STATE_STANDBY (1 << 1) 529 # define SDVO_ENCODER_STATE_SUSPEND (1 << 2) 530 # define SDVO_ENCODER_STATE_OFF (1 << 3) 531 # define SDVO_MONITOR_STATE_ON (1 << 4) 532 # define SDVO_MONITOR_STATE_STANDBY (1 << 5) 533 # define SDVO_MONITOR_STATE_SUSPEND (1 << 6) 534 # define SDVO_MONITOR_STATE_OFF (1 << 7) 535 536 #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d 537 #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e 538 #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f 539 /** 540 * The panel power sequencing parameters are in units of milliseconds. 541 * The high fields are bits 8:9 of the 10-bit values. 542 */ 543 struct sdvo_panel_power_sequencing { 544 u8 t0; 545 u8 t1; 546 u8 t2; 547 u8 t3; 548 u8 t4; 549 550 unsigned int t0_high:2; 551 unsigned int t1_high:2; 552 unsigned int t2_high:2; 553 unsigned int t3_high:2; 554 555 unsigned int t4_high:2; 556 unsigned int pad:6; 557 } __attribute__((packed)); 558 559 #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30 560 struct sdvo_max_backlight_reply { 561 u8 max_value; 562 u8 default_value; 563 } __attribute__((packed)); 564 565 #define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31 566 #define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32 567 568 #define SDVO_CMD_GET_AMBIENT_LIGHT 0x33 569 struct sdvo_get_ambient_light_reply { 570 u16 trip_low; 571 u16 trip_high; 572 u16 value; 573 } __attribute__((packed)); 574 #define SDVO_CMD_SET_AMBIENT_LIGHT 0x34 575 struct sdvo_set_ambient_light_reply { 576 u16 trip_low; 577 u16 trip_high; 578 unsigned int enable:1; 579 unsigned int pad:7; 580 } __attribute__((packed)); 581 582 /* Set display power state */ 583 #define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d 584 # define SDVO_DISPLAY_STATE_ON (1 << 0) 585 # define SDVO_DISPLAY_STATE_STANDBY (1 << 1) 586 # define SDVO_DISPLAY_STATE_SUSPEND (1 << 2) 587 # define SDVO_DISPLAY_STATE_OFF (1 << 3) 588 589 #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84 590 struct intel_sdvo_enhancements_reply { 591 unsigned int flicker_filter:1; 592 unsigned int flicker_filter_adaptive:1; 593 unsigned int flicker_filter_2d:1; 594 unsigned int saturation:1; 595 unsigned int hue:1; 596 unsigned int brightness:1; 597 unsigned int contrast:1; 598 unsigned int overscan_h:1; 599 600 unsigned int overscan_v:1; 601 unsigned int hpos:1; 602 unsigned int vpos:1; 603 unsigned int sharpness:1; 604 unsigned int dot_crawl:1; 605 unsigned int dither:1; 606 unsigned int tv_chroma_filter:1; 607 unsigned int tv_luma_filter:1; 608 } __attribute__((packed)); 609 610 /* Picture enhancement limits below are dependent on the current TV format, 611 * and thus need to be queried and set after it. 612 */ 613 #define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d 614 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b 615 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52 616 #define SDVO_CMD_GET_MAX_SATURATION 0x55 617 #define SDVO_CMD_GET_MAX_HUE 0x58 618 #define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b 619 #define SDVO_CMD_GET_MAX_CONTRAST 0x5e 620 #define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61 621 #define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64 622 #define SDVO_CMD_GET_MAX_HPOS 0x67 623 #define SDVO_CMD_GET_MAX_VPOS 0x6a 624 #define SDVO_CMD_GET_MAX_SHARPNESS 0x6d 625 #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74 626 #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77 627 struct intel_sdvo_enhancement_limits_reply { 628 u16 max_value; 629 u16 default_value; 630 } __attribute__((packed)); 631 632 #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f 633 #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80 634 # define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0) 635 # define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0) 636 # define SDVO_LVDS_CONNECTOR_SPWG (0 << 2) 637 # define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2) 638 # define SDVO_LVDS_SINGLE_CHANNEL (0 << 4) 639 # define SDVO_LVDS_DUAL_CHANNEL (1 << 4) 640 641 #define SDVO_CMD_GET_FLICKER_FILTER 0x4e 642 #define SDVO_CMD_SET_FLICKER_FILTER 0x4f 643 #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50 644 #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51 645 #define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53 646 #define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54 647 #define SDVO_CMD_GET_SATURATION 0x56 648 #define SDVO_CMD_SET_SATURATION 0x57 649 #define SDVO_CMD_GET_HUE 0x59 650 #define SDVO_CMD_SET_HUE 0x5a 651 #define SDVO_CMD_GET_BRIGHTNESS 0x5c 652 #define SDVO_CMD_SET_BRIGHTNESS 0x5d 653 #define SDVO_CMD_GET_CONTRAST 0x5f 654 #define SDVO_CMD_SET_CONTRAST 0x60 655 #define SDVO_CMD_GET_OVERSCAN_H 0x62 656 #define SDVO_CMD_SET_OVERSCAN_H 0x63 657 #define SDVO_CMD_GET_OVERSCAN_V 0x65 658 #define SDVO_CMD_SET_OVERSCAN_V 0x66 659 #define SDVO_CMD_GET_HPOS 0x68 660 #define SDVO_CMD_SET_HPOS 0x69 661 #define SDVO_CMD_GET_VPOS 0x6b 662 #define SDVO_CMD_SET_VPOS 0x6c 663 #define SDVO_CMD_GET_SHARPNESS 0x6e 664 #define SDVO_CMD_SET_SHARPNESS 0x6f 665 #define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75 666 #define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76 667 #define SDVO_CMD_GET_TV_LUMA_FILTER 0x78 668 #define SDVO_CMD_SET_TV_LUMA_FILTER 0x79 669 struct intel_sdvo_enhancements_arg { 670 u16 value; 671 } __attribute__((packed)); 672 673 #define SDVO_CMD_GET_DOT_CRAWL 0x70 674 #define SDVO_CMD_SET_DOT_CRAWL 0x71 675 # define SDVO_DOT_CRAWL_ON (1 << 0) 676 # define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1) 677 678 #define SDVO_CMD_GET_DITHER 0x72 679 #define SDVO_CMD_SET_DITHER 0x73 680 # define SDVO_DITHER_ON (1 << 0) 681 # define SDVO_DITHER_DEFAULT_ON (1 << 1) 682 683 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a 684 # define SDVO_CONTROL_BUS_PROM (1 << 0) 685 # define SDVO_CONTROL_BUS_DDC1 (1 << 1) 686 # define SDVO_CONTROL_BUS_DDC2 (1 << 2) 687 # define SDVO_CONTROL_BUS_DDC3 (1 << 3) 688 689 /* HDMI op codes */ 690 #define SDVO_CMD_GET_SUPP_ENCODE 0x9d 691 #define SDVO_CMD_GET_ENCODE 0x9e 692 #define SDVO_CMD_SET_ENCODE 0x9f 693 #define SDVO_ENCODE_DVI 0x0 694 #define SDVO_ENCODE_HDMI 0x1 695 #define SDVO_CMD_SET_PIXEL_REPLI 0x8b 696 #define SDVO_CMD_GET_PIXEL_REPLI 0x8c 697 #define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d 698 #define SDVO_CMD_SET_COLORIMETRY 0x8e 699 #define SDVO_COLORIMETRY_RGB256 0x0 700 #define SDVO_COLORIMETRY_RGB220 0x1 701 #define SDVO_COLORIMETRY_YCrCb422 0x3 702 #define SDVO_COLORIMETRY_YCrCb444 0x4 703 #define SDVO_CMD_GET_COLORIMETRY 0x8f 704 #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90 705 #define SDVO_CMD_SET_AUDIO_STAT 0x91 706 #define SDVO_CMD_GET_AUDIO_STAT 0x92 707 #define SDVO_CMD_SET_HBUF_INDEX 0x93 708 #define SDVO_CMD_GET_HBUF_INDEX 0x94 709 #define SDVO_CMD_GET_HBUF_INFO 0x95 710 #define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96 711 #define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97 712 #define SDVO_CMD_SET_HBUF_DATA 0x98 713 #define SDVO_CMD_GET_HBUF_DATA 0x99 714 #define SDVO_CMD_SET_HBUF_TXRATE 0x9a 715 #define SDVO_CMD_GET_HBUF_TXRATE 0x9b 716 #define SDVO_HBUF_TX_DISABLED (0 << 6) 717 #define SDVO_HBUF_TX_ONCE (2 << 6) 718 #define SDVO_HBUF_TX_VSYNC (3 << 6) 719 #define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c 720 #define SDVO_NEED_TO_STALL (1 << 7) 721 722 struct intel_sdvo_encode { 723 u8 dvi_rev; 724 u8 hdmi_rev; 725 } __attribute__ ((packed)); 726