1 /* 2 * Copyright (c) 2014-2016 François Tigeot 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef LINUX_PCI_H 28 #define LINUX_PCI_H 29 30 #define PCI_ANY_ID (~0u) 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/pciio.h> 35 #include <sys/rman.h> 36 #include <bus/pci/pcivar.h> 37 #include <bus/pci/pcireg.h> 38 39 #include <linux/types.h> 40 #include <linux/device.h> 41 #include <linux/io.h> 42 43 #include <linux/pci_ids.h> 44 45 struct pci_bus; 46 47 struct pci_device_id { 48 uint32_t vendor; 49 uint32_t device; 50 uint32_t subvendor; 51 uint32_t subdevice; 52 uint32_t class; 53 uint32_t class_mask; 54 unsigned long driver_data; 55 }; 56 57 struct pci_dev { 58 struct pci_bus *bus; /* bus device is nailed to */ 59 struct device *dev; /* NOTE the star */ 60 61 unsigned short vendor; /* vendor ID */ 62 unsigned short device; /* device ID */ 63 unsigned short subsystem_vendor; 64 unsigned short subsystem_device; 65 66 u8 revision; 67 68 unsigned int irq; 69 }; 70 71 struct pci_bus { 72 struct pci_dev *self; /* handle to pdev self */ 73 struct device *dev; /* handle to dev */ 74 75 unsigned char number; /* bus addr number */ 76 }; 77 78 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 79 80 #define PCI_DMA_BIDIRECTIONAL 0 81 82 /* extracted from radeon/si.c radeon/cik.c */ 83 #define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */ 84 #define PCI_EXP_LNKCTL2 48 85 #define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */ 86 #define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */ 87 #define PCI_EXP_DEVSTA_TRPND 0x0020 88 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 89 90 static inline int 91 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 92 { 93 *val = (u16)pci_read_config(pdev->dev, where, 1); 94 return 0; 95 } 96 97 static inline int 98 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 99 { 100 *val = (u16)pci_read_config(pdev->dev, where, 2); 101 return 0; 102 } 103 104 static inline int 105 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 106 { 107 *val = (u32)pci_read_config(pdev->dev, where, 4); 108 return 0; 109 } 110 111 static inline int 112 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 113 { 114 pci_write_config(pdev->dev, where, val, 1); 115 return 0; 116 } 117 118 static inline int 119 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 120 { 121 pci_write_config(pdev->dev, where, val, 2); 122 return 0; 123 } 124 125 static inline int 126 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 127 { 128 pci_write_config(pdev->dev, where, val, 4); 129 return 0; 130 } 131 132 /* extracted from drm/radeon/evergreen.c */ 133 static inline int 134 pcie_get_readrq(struct pci_dev *pdev) 135 { 136 u16 ctl; 137 int err, cap; 138 139 err = pci_find_extcap(pdev->dev, PCIY_EXPRESS, &cap); 140 WARN_ON(err); 141 142 cap += PCIER_DEVCTRL; 143 144 ctl = pci_read_config(pdev->dev, cap, 2); 145 146 return 128 << ((ctl & PCIEM_DEVCTL_MAX_READRQ_MASK) >> 12); 147 } 148 149 /* valid rq sizes: 128, 256, 512, 1024, 2048, 4096 (^2N) */ 150 static inline int 151 pcie_set_readrq(struct pci_dev *pdev, int rq) 152 { 153 u16 ctl; 154 int err, cap; 155 156 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 157 return -EINVAL; 158 159 err = pci_find_extcap(pdev->dev, PCIY_EXPRESS, &cap); 160 if (err) 161 return (-1); 162 163 cap += PCIER_DEVCTRL; 164 165 ctl = pci_read_config(pdev->dev, cap, 2); 166 ctl &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 167 ctl |= ((ffs(rq) - 8) << 12); 168 pci_write_config(pdev->dev, cap, ctl, 2); 169 return 0; 170 } 171 172 static inline struct pci_dev * 173 pci_dev_get(struct pci_dev *dev) 174 { 175 /* Linux increments a reference count here */ 176 return dev; 177 } 178 179 static inline struct pci_dev * 180 pci_dev_put(struct pci_dev *dev) 181 { 182 /* Linux decrements a reference count here */ 183 return dev; 184 } 185 186 187 static inline int 188 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 189 { 190 return -EIO; 191 } 192 193 static inline int 194 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 195 { 196 return -EIO; 197 } 198 199 typedef int pci_power_t; 200 201 #define PCI_D0 0 202 #define PCI_D1 1 203 #define PCI_D2 2 204 #define PCI_D3hot 3 205 #define PCI_D3cold 4 206 207 #include <asm/pci.h> 208 209 static inline struct resource_list_entry* 210 _pci_get_rle(struct pci_dev *pdev, int bar) 211 { 212 struct pci_devinfo *dinfo; 213 struct device *dev = pdev->dev; 214 struct resource_list_entry *rle; 215 216 dinfo = device_get_ivars(dev); 217 218 /* Some child devices don't have registered resources, they 219 * are only present in the parent */ 220 if (dinfo == NULL) { 221 kprintf("_pci_get_rle: dinfo was NULL, trying again with parent\n"); 222 dev = device_get_parent(dev); 223 } 224 dinfo = device_get_ivars(dev); 225 if (dinfo == NULL) 226 return NULL; 227 228 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, PCIR_BAR(bar)); 229 if (rle == NULL) { 230 rle = resource_list_find(&dinfo->resources, 231 SYS_RES_IOPORT, PCIR_BAR(bar)); 232 } 233 234 return rle; 235 } 236 237 /* 238 * Returns the first address (memory address or I/O port number) 239 * associated with one of the PCI I/O regions.The region is selected by 240 * the integer bar (the base address register), ranging from 0–5 (inclusive). 241 * The return value can be used by ioremap() 242 */ 243 static inline phys_addr_t 244 pci_resource_start(struct pci_dev *pdev, int bar) 245 { 246 struct resource_list_entry *rle; 247 248 rle = _pci_get_rle(pdev, bar); 249 if (rle == NULL) 250 return -1; 251 252 kprintf("pci_resource_start(0x%x, 0x%x) = 0x%lx\n", 253 pdev->device, PCIR_BAR(bar), rman_get_start(rle->res)); 254 255 return rman_get_start(rle->res); 256 } 257 258 static inline phys_addr_t 259 pci_resource_len(struct pci_dev *pdev, int bar) 260 { 261 struct resource_list_entry *rle; 262 263 rle = _pci_get_rle(pdev, bar); 264 if (rle == NULL) 265 return -1; 266 267 kprintf("pci_resource_len(0x%x, 0x%x) = 0x%lx\n", 268 pdev->device, PCIR_BAR(bar), rman_get_size(rle->res)); 269 270 return rman_get_size(rle->res); 271 } 272 273 static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 274 { 275 resource_size_t base, size; 276 277 base = pci_resource_start(dev, bar); 278 size = pci_resource_len(dev, bar); 279 280 if (base == 0) 281 return NULL; 282 283 if (maxlen && size > maxlen) 284 size = maxlen; 285 286 return ioremap(base, size); 287 } 288 289 #endif /* LINUX_PCI_H */ 290