1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/drm_fb_helper.h> 29 #include <drm/radeon_drm.h> 30 #include <drm/drm_fixed.h> 31 #include "radeon.h" 32 #include "atom.h" 33 #include "atom-bits.h" 34 35 static void atombios_overscan_setup(struct drm_crtc *crtc, 36 struct drm_display_mode *mode, 37 struct drm_display_mode *adjusted_mode) 38 { 39 struct drm_device *dev = crtc->dev; 40 struct radeon_device *rdev = dev->dev_private; 41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 43 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 44 int a1, a2; 45 46 memset(&args, 0, sizeof(args)); 47 48 args.ucCRTC = radeon_crtc->crtc_id; 49 50 switch (radeon_crtc->rmx_type) { 51 case RMX_CENTER: 52 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 53 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 56 break; 57 case RMX_ASPECT: 58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 60 61 if (a1 > a2) { 62 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 64 } else if (a2 > a1) { 65 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 67 } 68 break; 69 case RMX_FULL: 70 default: 71 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 72 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 73 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 74 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 75 break; 76 } 77 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 78 } 79 80 static void atombios_scaler_setup(struct drm_crtc *crtc) 81 { 82 struct drm_device *dev = crtc->dev; 83 struct radeon_device *rdev = dev->dev_private; 84 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 85 ENABLE_SCALER_PS_ALLOCATION args; 86 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 87 struct radeon_encoder *radeon_encoder = 88 to_radeon_encoder(radeon_crtc->encoder); 89 /* fixme - fill in enc_priv for atom dac */ 90 enum radeon_tv_std tv_std = TV_STD_NTSC; 91 bool is_tv = false, is_cv = false; 92 93 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 94 return; 95 96 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 97 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 98 tv_std = tv_dac->tv_std; 99 is_tv = true; 100 } 101 102 memset(&args, 0, sizeof(args)); 103 104 args.ucScaler = radeon_crtc->crtc_id; 105 106 if (is_tv) { 107 switch (tv_std) { 108 case TV_STD_NTSC: 109 default: 110 args.ucTVStandard = ATOM_TV_NTSC; 111 break; 112 case TV_STD_PAL: 113 args.ucTVStandard = ATOM_TV_PAL; 114 break; 115 case TV_STD_PAL_M: 116 args.ucTVStandard = ATOM_TV_PALM; 117 break; 118 case TV_STD_PAL_60: 119 args.ucTVStandard = ATOM_TV_PAL60; 120 break; 121 case TV_STD_NTSC_J: 122 args.ucTVStandard = ATOM_TV_NTSCJ; 123 break; 124 case TV_STD_SCART_PAL: 125 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 126 break; 127 case TV_STD_SECAM: 128 args.ucTVStandard = ATOM_TV_SECAM; 129 break; 130 case TV_STD_PAL_CN: 131 args.ucTVStandard = ATOM_TV_PALCN; 132 break; 133 } 134 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 135 } else if (is_cv) { 136 args.ucTVStandard = ATOM_TV_CV; 137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 138 } else { 139 switch (radeon_crtc->rmx_type) { 140 case RMX_FULL: 141 args.ucEnable = ATOM_SCALER_EXPANSION; 142 break; 143 case RMX_CENTER: 144 args.ucEnable = ATOM_SCALER_CENTER; 145 break; 146 case RMX_ASPECT: 147 args.ucEnable = ATOM_SCALER_EXPANSION; 148 break; 149 default: 150 if (ASIC_IS_AVIVO(rdev)) 151 args.ucEnable = ATOM_SCALER_DISABLE; 152 else 153 args.ucEnable = ATOM_SCALER_CENTER; 154 break; 155 } 156 } 157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 158 if ((is_tv || is_cv) 159 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 160 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 161 } 162 } 163 164 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 165 { 166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 167 struct drm_device *dev = crtc->dev; 168 struct radeon_device *rdev = dev->dev_private; 169 int index = 170 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 171 ENABLE_CRTC_PS_ALLOCATION args; 172 173 memset(&args, 0, sizeof(args)); 174 175 args.ucCRTC = radeon_crtc->crtc_id; 176 args.ucEnable = lock; 177 178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 179 } 180 181 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 182 { 183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 184 struct drm_device *dev = crtc->dev; 185 struct radeon_device *rdev = dev->dev_private; 186 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 187 ENABLE_CRTC_PS_ALLOCATION args; 188 189 memset(&args, 0, sizeof(args)); 190 191 args.ucCRTC = radeon_crtc->crtc_id; 192 args.ucEnable = state; 193 194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 195 } 196 197 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 198 { 199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 200 struct drm_device *dev = crtc->dev; 201 struct radeon_device *rdev = dev->dev_private; 202 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 203 ENABLE_CRTC_PS_ALLOCATION args; 204 205 memset(&args, 0, sizeof(args)); 206 207 args.ucCRTC = radeon_crtc->crtc_id; 208 args.ucEnable = state; 209 210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 211 } 212 213 static const u32 vga_control_regs[6] = 214 { 215 AVIVO_D1VGA_CONTROL, 216 AVIVO_D2VGA_CONTROL, 217 EVERGREEN_D3VGA_CONTROL, 218 EVERGREEN_D4VGA_CONTROL, 219 EVERGREEN_D5VGA_CONTROL, 220 EVERGREEN_D6VGA_CONTROL, 221 }; 222 223 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 224 { 225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 226 struct drm_device *dev = crtc->dev; 227 struct radeon_device *rdev = dev->dev_private; 228 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 229 BLANK_CRTC_PS_ALLOCATION args; 230 u32 vga_control = 0; 231 232 memset(&args, 0, sizeof(args)); 233 234 if (ASIC_IS_DCE8(rdev)) { 235 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); 236 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); 237 } 238 239 args.ucCRTC = radeon_crtc->crtc_id; 240 args.ucBlanking = state; 241 242 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 243 244 if (ASIC_IS_DCE8(rdev)) { 245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); 246 } 247 } 248 249 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 250 { 251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 252 struct drm_device *dev = crtc->dev; 253 struct radeon_device *rdev = dev->dev_private; 254 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 255 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 256 257 memset(&args, 0, sizeof(args)); 258 259 args.ucDispPipeId = radeon_crtc->crtc_id; 260 args.ucEnable = state; 261 262 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 263 } 264 265 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 266 { 267 struct drm_device *dev = crtc->dev; 268 struct radeon_device *rdev = dev->dev_private; 269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 270 271 switch (mode) { 272 case DRM_MODE_DPMS_ON: 273 radeon_crtc->enabled = true; 274 atombios_enable_crtc(crtc, ATOM_ENABLE); 275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 277 atombios_blank_crtc(crtc, ATOM_DISABLE); 278 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 279 radeon_crtc_load_lut(crtc); 280 break; 281 case DRM_MODE_DPMS_STANDBY: 282 case DRM_MODE_DPMS_SUSPEND: 283 case DRM_MODE_DPMS_OFF: 284 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 285 if (radeon_crtc->enabled) 286 atombios_blank_crtc(crtc, ATOM_ENABLE); 287 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 288 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 289 atombios_enable_crtc(crtc, ATOM_DISABLE); 290 radeon_crtc->enabled = false; 291 break; 292 } 293 /* adjust pm to dpms */ 294 radeon_pm_compute_clocks(rdev); 295 } 296 297 static void 298 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 299 struct drm_display_mode *mode) 300 { 301 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 302 struct drm_device *dev = crtc->dev; 303 struct radeon_device *rdev = dev->dev_private; 304 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 305 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 306 u16 misc = 0; 307 308 memset(&args, 0, sizeof(args)); 309 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 310 args.usH_Blanking_Time = 311 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 312 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 313 args.usV_Blanking_Time = 314 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 315 args.usH_SyncOffset = 316 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 317 args.usH_SyncWidth = 318 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 319 args.usV_SyncOffset = 320 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 321 args.usV_SyncWidth = 322 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 323 args.ucH_Border = radeon_crtc->h_border; 324 args.ucV_Border = radeon_crtc->v_border; 325 326 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 327 misc |= ATOM_VSYNC_POLARITY; 328 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 329 misc |= ATOM_HSYNC_POLARITY; 330 if (mode->flags & DRM_MODE_FLAG_CSYNC) 331 misc |= ATOM_COMPOSITESYNC; 332 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 333 misc |= ATOM_INTERLACE; 334 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 335 misc |= ATOM_DOUBLE_CLOCK_MODE; 336 337 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 338 args.ucCRTC = radeon_crtc->crtc_id; 339 340 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 341 } 342 343 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 344 struct drm_display_mode *mode) 345 { 346 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 347 struct drm_device *dev = crtc->dev; 348 struct radeon_device *rdev = dev->dev_private; 349 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 350 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 351 u16 misc = 0; 352 353 memset(&args, 0, sizeof(args)); 354 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 355 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 356 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 357 args.usH_SyncWidth = 358 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 359 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 360 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 361 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 362 args.usV_SyncWidth = 363 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 364 365 args.ucOverscanRight = radeon_crtc->h_border; 366 args.ucOverscanLeft = radeon_crtc->h_border; 367 args.ucOverscanBottom = radeon_crtc->v_border; 368 args.ucOverscanTop = radeon_crtc->v_border; 369 370 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 371 misc |= ATOM_VSYNC_POLARITY; 372 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 373 misc |= ATOM_HSYNC_POLARITY; 374 if (mode->flags & DRM_MODE_FLAG_CSYNC) 375 misc |= ATOM_COMPOSITESYNC; 376 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 377 misc |= ATOM_INTERLACE; 378 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 379 misc |= ATOM_DOUBLE_CLOCK_MODE; 380 381 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 382 args.ucCRTC = radeon_crtc->crtc_id; 383 384 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 385 } 386 387 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 388 { 389 u32 ss_cntl; 390 391 if (ASIC_IS_DCE4(rdev)) { 392 switch (pll_id) { 393 case ATOM_PPLL1: 394 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 395 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 396 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 397 break; 398 case ATOM_PPLL2: 399 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 400 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 401 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 402 break; 403 case ATOM_DCPLL: 404 case ATOM_PPLL_INVALID: 405 return; 406 } 407 } else if (ASIC_IS_AVIVO(rdev)) { 408 switch (pll_id) { 409 case ATOM_PPLL1: 410 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 411 ss_cntl &= ~1; 412 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 413 break; 414 case ATOM_PPLL2: 415 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 416 ss_cntl &= ~1; 417 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 418 break; 419 case ATOM_DCPLL: 420 case ATOM_PPLL_INVALID: 421 return; 422 } 423 } 424 } 425 426 427 union atom_enable_ss { 428 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 429 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 430 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 431 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 432 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 433 }; 434 435 static void atombios_crtc_program_ss(struct radeon_device *rdev, 436 int enable, 437 int pll_id, 438 int crtc_id, 439 struct radeon_atom_ss *ss) 440 { 441 unsigned i; 442 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 443 union atom_enable_ss args; 444 445 if (enable) { 446 /* Don't mess with SS if percentage is 0 or external ss. 447 * SS is already disabled previously, and disabling it 448 * again can cause display problems if the pll is already 449 * programmed. 450 */ 451 if (ss->percentage == 0) 452 return; 453 if (ss->type & ATOM_EXTERNAL_SS_MASK) 454 return; 455 } else { 456 for (i = 0; i < rdev->num_crtc; i++) { 457 if (rdev->mode_info.crtcs[i] && 458 rdev->mode_info.crtcs[i]->enabled && 459 i != crtc_id && 460 pll_id == rdev->mode_info.crtcs[i]->pll_id) { 461 /* one other crtc is using this pll don't turn 462 * off spread spectrum as it might turn off 463 * display on active crtc 464 */ 465 return; 466 } 467 } 468 } 469 470 memset(&args, 0, sizeof(args)); 471 472 if (ASIC_IS_DCE5(rdev)) { 473 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 474 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 475 switch (pll_id) { 476 case ATOM_PPLL1: 477 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 478 break; 479 case ATOM_PPLL2: 480 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 481 break; 482 case ATOM_DCPLL: 483 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 484 break; 485 case ATOM_PPLL_INVALID: 486 return; 487 } 488 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 489 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 490 args.v3.ucEnable = enable; 491 } else if (ASIC_IS_DCE4(rdev)) { 492 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 493 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 494 switch (pll_id) { 495 case ATOM_PPLL1: 496 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 497 break; 498 case ATOM_PPLL2: 499 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 500 break; 501 case ATOM_DCPLL: 502 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 503 break; 504 case ATOM_PPLL_INVALID: 505 return; 506 } 507 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 508 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 509 args.v2.ucEnable = enable; 510 } else if (ASIC_IS_DCE3(rdev)) { 511 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 512 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 513 args.v1.ucSpreadSpectrumStep = ss->step; 514 args.v1.ucSpreadSpectrumDelay = ss->delay; 515 args.v1.ucSpreadSpectrumRange = ss->range; 516 args.v1.ucPpll = pll_id; 517 args.v1.ucEnable = enable; 518 } else if (ASIC_IS_AVIVO(rdev)) { 519 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 520 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 521 atombios_disable_ss(rdev, pll_id); 522 return; 523 } 524 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 525 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 526 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 527 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 528 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 529 args.lvds_ss_2.ucEnable = enable; 530 } else { 531 if (enable == ATOM_DISABLE) { 532 atombios_disable_ss(rdev, pll_id); 533 return; 534 } 535 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 536 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 537 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 538 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 539 args.lvds_ss.ucEnable = enable; 540 } 541 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 542 } 543 544 union adjust_pixel_clock { 545 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 546 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 547 }; 548 549 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 550 struct drm_display_mode *mode) 551 { 552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 553 struct drm_device *dev = crtc->dev; 554 struct radeon_device *rdev = dev->dev_private; 555 struct drm_encoder *encoder = radeon_crtc->encoder; 556 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 557 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 558 u32 adjusted_clock = mode->clock; 559 int encoder_mode = atombios_get_encoder_mode(encoder); 560 u32 dp_clock = mode->clock; 561 u32 clock = mode->clock; 562 int bpc = radeon_crtc->bpc; 563 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 564 565 /* reset the pll flags */ 566 radeon_crtc->pll_flags = 0; 567 568 if (ASIC_IS_AVIVO(rdev)) { 569 if ((rdev->family == CHIP_RS600) || 570 (rdev->family == CHIP_RS690) || 571 (rdev->family == CHIP_RS740)) 572 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 573 RADEON_PLL_PREFER_CLOSEST_LOWER); 574 575 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 576 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 577 else 578 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 579 580 if (rdev->family < CHIP_RV770) 581 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 582 /* use frac fb div on APUs */ 583 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 584 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 585 /* use frac fb div on RS780/RS880 */ 586 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 587 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 588 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 589 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 590 } else { 591 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 592 593 if (mode->clock > 200000) /* range limits??? */ 594 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 595 else 596 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 597 } 598 599 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 600 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 601 if (connector) { 602 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 603 struct radeon_connector_atom_dig *dig_connector = 604 radeon_connector->con_priv; 605 606 dp_clock = dig_connector->dp_clock; 607 } 608 } 609 610 /* use recommended ref_div for ss */ 611 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 612 if (radeon_crtc->ss_enabled) { 613 if (radeon_crtc->ss.refdiv) { 614 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 615 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 616 if (ASIC_IS_AVIVO(rdev)) 617 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 618 } 619 } 620 } 621 622 if (ASIC_IS_AVIVO(rdev)) { 623 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 624 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 625 adjusted_clock = mode->clock * 2; 626 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 627 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 628 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 629 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 630 } else { 631 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 632 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 633 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 634 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 635 } 636 637 /* adjust pll for deep color modes */ 638 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 639 switch (bpc) { 640 case 8: 641 default: 642 break; 643 case 10: 644 clock = (clock * 5) / 4; 645 break; 646 case 12: 647 clock = (clock * 3) / 2; 648 break; 649 case 16: 650 clock = clock * 2; 651 break; 652 } 653 } 654 655 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 656 * accordingly based on the encoder/transmitter to work around 657 * special hw requirements. 658 */ 659 if (ASIC_IS_DCE3(rdev)) { 660 union adjust_pixel_clock args; 661 u8 frev, crev; 662 int index; 663 664 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 665 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 666 &crev)) 667 return adjusted_clock; 668 669 memset(&args, 0, sizeof(args)); 670 671 switch (frev) { 672 case 1: 673 switch (crev) { 674 case 1: 675 case 2: 676 args.v1.usPixelClock = cpu_to_le16(clock / 10); 677 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 678 args.v1.ucEncodeMode = encoder_mode; 679 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 680 args.v1.ucConfig |= 681 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 682 683 atom_execute_table(rdev->mode_info.atom_context, 684 index, (uint32_t *)&args); 685 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 686 break; 687 case 3: 688 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); 689 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 690 args.v3.sInput.ucEncodeMode = encoder_mode; 691 args.v3.sInput.ucDispPllConfig = 0; 692 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 693 args.v3.sInput.ucDispPllConfig |= 694 DISPPLL_CONFIG_SS_ENABLE; 695 if (ENCODER_MODE_IS_DP(encoder_mode)) { 696 args.v3.sInput.ucDispPllConfig |= 697 DISPPLL_CONFIG_COHERENT_MODE; 698 /* 16200 or 27000 */ 699 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 700 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 701 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 702 if (dig->coherent_mode) 703 args.v3.sInput.ucDispPllConfig |= 704 DISPPLL_CONFIG_COHERENT_MODE; 705 if (is_duallink) 706 args.v3.sInput.ucDispPllConfig |= 707 DISPPLL_CONFIG_DUAL_LINK; 708 } 709 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 710 ENCODER_OBJECT_ID_NONE) 711 args.v3.sInput.ucExtTransmitterID = 712 radeon_encoder_get_dp_bridge_encoder_id(encoder); 713 else 714 args.v3.sInput.ucExtTransmitterID = 0; 715 716 atom_execute_table(rdev->mode_info.atom_context, 717 index, (uint32_t *)&args); 718 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 719 if (args.v3.sOutput.ucRefDiv) { 720 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 721 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 722 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 723 } 724 if (args.v3.sOutput.ucPostDiv) { 725 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 726 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 727 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 728 } 729 break; 730 default: 731 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 732 return adjusted_clock; 733 } 734 break; 735 default: 736 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 737 return adjusted_clock; 738 } 739 } 740 return adjusted_clock; 741 } 742 743 union set_pixel_clock { 744 SET_PIXEL_CLOCK_PS_ALLOCATION base; 745 PIXEL_CLOCK_PARAMETERS v1; 746 PIXEL_CLOCK_PARAMETERS_V2 v2; 747 PIXEL_CLOCK_PARAMETERS_V3 v3; 748 PIXEL_CLOCK_PARAMETERS_V5 v5; 749 PIXEL_CLOCK_PARAMETERS_V6 v6; 750 }; 751 752 /* on DCE5, make sure the voltage is high enough to support the 753 * required disp clk. 754 */ 755 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 756 u32 dispclk) 757 { 758 u8 frev, crev; 759 int index; 760 union set_pixel_clock args; 761 762 memset(&args, 0, sizeof(args)); 763 764 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 765 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 766 &crev)) 767 return; 768 769 switch (frev) { 770 case 1: 771 switch (crev) { 772 case 5: 773 /* if the default dcpll clock is specified, 774 * SetPixelClock provides the dividers 775 */ 776 args.v5.ucCRTC = ATOM_CRTC_INVALID; 777 args.v5.usPixelClock = cpu_to_le16(dispclk); 778 args.v5.ucPpll = ATOM_DCPLL; 779 break; 780 case 6: 781 /* if the default dcpll clock is specified, 782 * SetPixelClock provides the dividers 783 */ 784 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 785 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 786 args.v6.ucPpll = ATOM_EXT_PLL1; 787 else if (ASIC_IS_DCE6(rdev)) 788 args.v6.ucPpll = ATOM_PPLL0; 789 else 790 args.v6.ucPpll = ATOM_DCPLL; 791 break; 792 default: 793 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 794 return; 795 } 796 break; 797 default: 798 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 799 return; 800 } 801 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 802 } 803 804 static void atombios_crtc_program_pll(struct drm_crtc *crtc, 805 u32 crtc_id, 806 int pll_id, 807 u32 encoder_mode, 808 u32 encoder_id, 809 u32 clock, 810 u32 ref_div, 811 u32 fb_div, 812 u32 frac_fb_div, 813 u32 post_div, 814 int bpc, 815 bool ss_enabled, 816 struct radeon_atom_ss *ss) 817 { 818 struct drm_device *dev = crtc->dev; 819 struct radeon_device *rdev = dev->dev_private; 820 u8 frev, crev; 821 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 822 union set_pixel_clock args; 823 824 memset(&args, 0, sizeof(args)); 825 826 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 827 &crev)) 828 return; 829 830 switch (frev) { 831 case 1: 832 switch (crev) { 833 case 1: 834 if (clock == ATOM_DISABLE) 835 return; 836 args.v1.usPixelClock = cpu_to_le16(clock / 10); 837 args.v1.usRefDiv = cpu_to_le16(ref_div); 838 args.v1.usFbDiv = cpu_to_le16(fb_div); 839 args.v1.ucFracFbDiv = frac_fb_div; 840 args.v1.ucPostDiv = post_div; 841 args.v1.ucPpll = pll_id; 842 args.v1.ucCRTC = crtc_id; 843 args.v1.ucRefDivSrc = 1; 844 break; 845 case 2: 846 args.v2.usPixelClock = cpu_to_le16(clock / 10); 847 args.v2.usRefDiv = cpu_to_le16(ref_div); 848 args.v2.usFbDiv = cpu_to_le16(fb_div); 849 args.v2.ucFracFbDiv = frac_fb_div; 850 args.v2.ucPostDiv = post_div; 851 args.v2.ucPpll = pll_id; 852 args.v2.ucCRTC = crtc_id; 853 args.v2.ucRefDivSrc = 1; 854 break; 855 case 3: 856 args.v3.usPixelClock = cpu_to_le16(clock / 10); 857 args.v3.usRefDiv = cpu_to_le16(ref_div); 858 args.v3.usFbDiv = cpu_to_le16(fb_div); 859 args.v3.ucFracFbDiv = frac_fb_div; 860 args.v3.ucPostDiv = post_div; 861 args.v3.ucPpll = pll_id; 862 if (crtc_id == ATOM_CRTC2) 863 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 864 else 865 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 866 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 867 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 868 args.v3.ucTransmitterId = encoder_id; 869 args.v3.ucEncoderMode = encoder_mode; 870 break; 871 case 5: 872 args.v5.ucCRTC = crtc_id; 873 args.v5.usPixelClock = cpu_to_le16(clock / 10); 874 args.v5.ucRefDiv = ref_div; 875 args.v5.usFbDiv = cpu_to_le16(fb_div); 876 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 877 args.v5.ucPostDiv = post_div; 878 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 879 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 880 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 881 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 882 switch (bpc) { 883 case 8: 884 default: 885 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 886 break; 887 case 10: 888 /* yes this is correct, the atom define is wrong */ 889 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; 890 break; 891 case 12: 892 /* yes this is correct, the atom define is wrong */ 893 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 894 break; 895 } 896 } 897 args.v5.ucTransmitterID = encoder_id; 898 args.v5.ucEncoderMode = encoder_mode; 899 args.v5.ucPpll = pll_id; 900 break; 901 case 6: 902 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 903 args.v6.ucRefDiv = ref_div; 904 args.v6.usFbDiv = cpu_to_le16(fb_div); 905 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 906 args.v6.ucPostDiv = post_div; 907 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 908 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 909 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 910 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 911 switch (bpc) { 912 case 8: 913 default: 914 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 915 break; 916 case 10: 917 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; 918 break; 919 case 12: 920 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; 921 break; 922 case 16: 923 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 924 break; 925 } 926 } 927 args.v6.ucTransmitterID = encoder_id; 928 args.v6.ucEncoderMode = encoder_mode; 929 args.v6.ucPpll = pll_id; 930 break; 931 default: 932 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 933 return; 934 } 935 break; 936 default: 937 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 938 return; 939 } 940 941 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 942 } 943 944 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 945 { 946 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 947 struct drm_device *dev = crtc->dev; 948 struct radeon_device *rdev = dev->dev_private; 949 struct radeon_encoder *radeon_encoder = 950 to_radeon_encoder(radeon_crtc->encoder); 951 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 952 953 radeon_crtc->bpc = 8; 954 radeon_crtc->ss_enabled = false; 955 956 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 957 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 958 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 959 struct drm_connector *connector = 960 radeon_get_connector_for_encoder(radeon_crtc->encoder); 961 struct radeon_connector *radeon_connector = 962 to_radeon_connector(connector); 963 struct radeon_connector_atom_dig *dig_connector = 964 radeon_connector->con_priv; 965 int dp_clock; 966 967 /* Assign mode clock for hdmi deep color max clock limit check */ 968 radeon_connector->pixelclock_for_modeset = mode->clock; 969 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 970 971 switch (encoder_mode) { 972 case ATOM_ENCODER_MODE_DP_MST: 973 case ATOM_ENCODER_MODE_DP: 974 /* DP/eDP */ 975 dp_clock = dig_connector->dp_clock / 10; 976 if (ASIC_IS_DCE4(rdev)) 977 radeon_crtc->ss_enabled = 978 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 979 ASIC_INTERNAL_SS_ON_DP, 980 dp_clock); 981 else { 982 if (dp_clock == 16200) { 983 radeon_crtc->ss_enabled = 984 radeon_atombios_get_ppll_ss_info(rdev, 985 &radeon_crtc->ss, 986 ATOM_DP_SS_ID2); 987 if (!radeon_crtc->ss_enabled) 988 radeon_crtc->ss_enabled = 989 radeon_atombios_get_ppll_ss_info(rdev, 990 &radeon_crtc->ss, 991 ATOM_DP_SS_ID1); 992 } else { 993 radeon_crtc->ss_enabled = 994 radeon_atombios_get_ppll_ss_info(rdev, 995 &radeon_crtc->ss, 996 ATOM_DP_SS_ID1); 997 } 998 /* disable spread spectrum on DCE3 DP */ 999 radeon_crtc->ss_enabled = false; 1000 } 1001 break; 1002 case ATOM_ENCODER_MODE_LVDS: 1003 if (ASIC_IS_DCE4(rdev)) 1004 radeon_crtc->ss_enabled = 1005 radeon_atombios_get_asic_ss_info(rdev, 1006 &radeon_crtc->ss, 1007 dig->lcd_ss_id, 1008 mode->clock / 10); 1009 else 1010 radeon_crtc->ss_enabled = 1011 radeon_atombios_get_ppll_ss_info(rdev, 1012 &radeon_crtc->ss, 1013 dig->lcd_ss_id); 1014 break; 1015 case ATOM_ENCODER_MODE_DVI: 1016 if (ASIC_IS_DCE4(rdev)) 1017 radeon_crtc->ss_enabled = 1018 radeon_atombios_get_asic_ss_info(rdev, 1019 &radeon_crtc->ss, 1020 ASIC_INTERNAL_SS_ON_TMDS, 1021 mode->clock / 10); 1022 break; 1023 case ATOM_ENCODER_MODE_HDMI: 1024 if (ASIC_IS_DCE4(rdev)) 1025 radeon_crtc->ss_enabled = 1026 radeon_atombios_get_asic_ss_info(rdev, 1027 &radeon_crtc->ss, 1028 ASIC_INTERNAL_SS_ON_HDMI, 1029 mode->clock / 10); 1030 break; 1031 default: 1032 break; 1033 } 1034 } 1035 1036 /* adjust pixel clock as needed */ 1037 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 1038 1039 return true; 1040 } 1041 1042 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 1043 { 1044 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1045 struct drm_device *dev = crtc->dev; 1046 struct radeon_device *rdev = dev->dev_private; 1047 struct radeon_encoder *radeon_encoder = 1048 to_radeon_encoder(radeon_crtc->encoder); 1049 u32 pll_clock = mode->clock; 1050 u32 clock = mode->clock; 1051 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 1052 struct radeon_pll *pll; 1053 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 1054 1055 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ 1056 if (ASIC_IS_DCE5(rdev) && 1057 (encoder_mode == ATOM_ENCODER_MODE_HDMI) && 1058 (radeon_crtc->bpc > 8)) 1059 clock = radeon_crtc->adjusted_clock; 1060 1061 switch (radeon_crtc->pll_id) { 1062 case ATOM_PPLL1: 1063 pll = &rdev->clock.p1pll; 1064 break; 1065 case ATOM_PPLL2: 1066 pll = &rdev->clock.p2pll; 1067 break; 1068 case ATOM_DCPLL: 1069 case ATOM_PPLL_INVALID: 1070 default: 1071 pll = &rdev->clock.dcpll; 1072 break; 1073 } 1074 1075 /* update pll params */ 1076 pll->flags = radeon_crtc->pll_flags; 1077 pll->reference_div = radeon_crtc->pll_reference_div; 1078 pll->post_div = radeon_crtc->pll_post_div; 1079 1080 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1081 /* TV seems to prefer the legacy algo on some boards */ 1082 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1083 &fb_div, &frac_fb_div, &ref_div, &post_div); 1084 else if (ASIC_IS_AVIVO(rdev)) 1085 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 1086 &fb_div, &frac_fb_div, &ref_div, &post_div); 1087 else 1088 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1089 &fb_div, &frac_fb_div, &ref_div, &post_div); 1090 1091 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 1092 radeon_crtc->crtc_id, &radeon_crtc->ss); 1093 1094 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1095 encoder_mode, radeon_encoder->encoder_id, clock, 1096 ref_div, fb_div, frac_fb_div, post_div, 1097 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1098 1099 if (radeon_crtc->ss_enabled) { 1100 /* calculate ss amount and step size */ 1101 if (ASIC_IS_DCE4(rdev)) { 1102 u32 step_size; 1103 u32 amount = (((fb_div * 10) + frac_fb_div) * 1104 (u32)radeon_crtc->ss.percentage) / 1105 (100 * (u32)radeon_crtc->ss.percentage_divider); 1106 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1107 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1108 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1109 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1110 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1111 (125 * 25 * pll->reference_freq / 100); 1112 else 1113 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1114 (125 * 25 * pll->reference_freq / 100); 1115 radeon_crtc->ss.step = step_size; 1116 } 1117 1118 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 1119 radeon_crtc->crtc_id, &radeon_crtc->ss); 1120 } 1121 } 1122 1123 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1124 struct drm_framebuffer *fb, 1125 int x, int y, int atomic) 1126 { 1127 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1128 struct drm_device *dev = crtc->dev; 1129 struct radeon_device *rdev = dev->dev_private; 1130 struct radeon_framebuffer *radeon_fb; 1131 struct drm_framebuffer *target_fb; 1132 struct drm_gem_object *obj; 1133 struct radeon_bo *rbo; 1134 uint64_t fb_location; 1135 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1136 unsigned bankw, bankh, mtaspect, tile_split; 1137 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1138 u32 tmp, viewport_w, viewport_h; 1139 int r; 1140 bool bypass_lut = false; 1141 1142 /* no fb bound */ 1143 if (!atomic && !crtc->primary->fb) { 1144 DRM_DEBUG_KMS("No FB bound\n"); 1145 return 0; 1146 } 1147 1148 if (atomic) { 1149 radeon_fb = to_radeon_framebuffer(fb); 1150 target_fb = fb; 1151 } 1152 else { 1153 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 1154 target_fb = crtc->primary->fb; 1155 } 1156 1157 /* If atomic, assume fb object is pinned & idle & fenced and 1158 * just update base pointers 1159 */ 1160 obj = radeon_fb->obj; 1161 rbo = gem_to_radeon_bo(obj); 1162 r = radeon_bo_reserve(rbo, false); 1163 if (unlikely(r != 0)) 1164 return r; 1165 1166 if (atomic) 1167 fb_location = radeon_bo_gpu_offset(rbo); 1168 else { 1169 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, (u64 *)&fb_location); 1170 if (unlikely(r != 0)) { 1171 radeon_bo_unreserve(rbo); 1172 return -EINVAL; 1173 } 1174 } 1175 1176 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1177 radeon_bo_unreserve(rbo); 1178 1179 switch (target_fb->pixel_format) { 1180 case DRM_FORMAT_C8: 1181 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1182 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1183 break; 1184 case DRM_FORMAT_XRGB4444: 1185 case DRM_FORMAT_ARGB4444: 1186 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1187 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); 1188 #ifdef __BIG_ENDIAN 1189 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1190 #endif 1191 break; 1192 case DRM_FORMAT_XRGB1555: 1193 case DRM_FORMAT_ARGB1555: 1194 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1195 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1196 #ifdef __BIG_ENDIAN 1197 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1198 #endif 1199 break; 1200 case DRM_FORMAT_BGRX5551: 1201 case DRM_FORMAT_BGRA5551: 1202 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1203 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); 1204 #ifdef __BIG_ENDIAN 1205 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1206 #endif 1207 break; 1208 case DRM_FORMAT_RGB565: 1209 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1210 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1211 #ifdef __BIG_ENDIAN 1212 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1213 #endif 1214 break; 1215 case DRM_FORMAT_XRGB8888: 1216 case DRM_FORMAT_ARGB8888: 1217 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1218 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1219 #ifdef __BIG_ENDIAN 1220 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1221 #endif 1222 break; 1223 case DRM_FORMAT_XRGB2101010: 1224 case DRM_FORMAT_ARGB2101010: 1225 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1226 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); 1227 #ifdef __BIG_ENDIAN 1228 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1229 #endif 1230 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1231 bypass_lut = true; 1232 break; 1233 case DRM_FORMAT_BGRX1010102: 1234 case DRM_FORMAT_BGRA1010102: 1235 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1236 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); 1237 #ifdef __BIG_ENDIAN 1238 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1239 #endif 1240 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1241 bypass_lut = true; 1242 break; 1243 default: 1244 DRM_ERROR("Unsupported screen format %s\n", 1245 drm_get_format_name(target_fb->pixel_format)); 1246 return -EINVAL; 1247 } 1248 1249 if (tiling_flags & RADEON_TILING_MACRO) { 1250 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1251 1252 /* Set NUM_BANKS. */ 1253 if (rdev->family >= CHIP_TAHITI) { 1254 unsigned index, num_banks; 1255 1256 if (rdev->family >= CHIP_BONAIRE) { 1257 unsigned tileb, tile_split_bytes; 1258 1259 /* Calculate the macrotile mode index. */ 1260 tile_split_bytes = 64 << tile_split; 1261 tileb = 8 * 8 * target_fb->bits_per_pixel / 8; 1262 tileb = min(tile_split_bytes, tileb); 1263 1264 for (index = 0; tileb > 64; index++) 1265 tileb >>= 1; 1266 1267 if (index >= 16) { 1268 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1269 target_fb->bits_per_pixel, tile_split); 1270 return -EINVAL; 1271 } 1272 1273 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1274 } else { 1275 switch (target_fb->bits_per_pixel) { 1276 case 8: 1277 index = 10; 1278 break; 1279 case 16: 1280 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; 1281 break; 1282 default: 1283 case 32: 1284 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; 1285 break; 1286 } 1287 1288 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; 1289 } 1290 1291 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1292 } else { 1293 /* NI and older. */ 1294 if (rdev->family >= CHIP_CAYMAN) 1295 tmp = rdev->config.cayman.tile_config; 1296 else 1297 tmp = rdev->config.evergreen.tile_config; 1298 1299 switch ((tmp & 0xf0) >> 4) { 1300 case 0: /* 4 banks */ 1301 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1302 break; 1303 case 1: /* 8 banks */ 1304 default: 1305 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1306 break; 1307 case 2: /* 16 banks */ 1308 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1309 break; 1310 } 1311 } 1312 1313 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1314 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1315 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1316 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1317 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1318 if (rdev->family >= CHIP_BONAIRE) { 1319 /* XXX need to know more about the surface tiling mode */ 1320 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); 1321 } 1322 } else if (tiling_flags & RADEON_TILING_MICRO) 1323 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1324 1325 if (rdev->family >= CHIP_BONAIRE) { 1326 /* Read the pipe config from the 2D TILED SCANOUT mode. 1327 * It should be the same for the other modes too, but not all 1328 * modes set the pipe config field. */ 1329 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; 1330 1331 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); 1332 } else if ((rdev->family == CHIP_TAHITI) || 1333 (rdev->family == CHIP_PITCAIRN)) 1334 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1335 else if ((rdev->family == CHIP_VERDE) || 1336 (rdev->family == CHIP_OLAND) || 1337 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ 1338 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1339 1340 switch (radeon_crtc->crtc_id) { 1341 case 0: 1342 WREG32(AVIVO_D1VGA_CONTROL, 0); 1343 break; 1344 case 1: 1345 WREG32(AVIVO_D2VGA_CONTROL, 0); 1346 break; 1347 case 2: 1348 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1349 break; 1350 case 3: 1351 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1352 break; 1353 case 4: 1354 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1355 break; 1356 case 5: 1357 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1358 break; 1359 default: 1360 break; 1361 } 1362 1363 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1364 upper_32_bits(fb_location)); 1365 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1366 upper_32_bits(fb_location)); 1367 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1368 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1369 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1370 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1371 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1372 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1373 1374 /* 1375 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1376 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1377 * retain the full precision throughout the pipeline. 1378 */ 1379 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, 1380 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), 1381 ~EVERGREEN_LUT_10BIT_BYPASS_EN); 1382 1383 if (bypass_lut) 1384 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1385 1386 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1387 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1388 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1389 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1390 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1391 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1392 1393 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1394 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1395 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1396 1397 if (rdev->family >= CHIP_BONAIRE) 1398 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1399 target_fb->height); 1400 else 1401 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1402 target_fb->height); 1403 x &= ~3; 1404 y &= ~1; 1405 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1406 (x << 16) | y); 1407 viewport_w = crtc->mode.hdisplay; 1408 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1409 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1410 (viewport_w << 16) | viewport_h); 1411 1412 /* pageflip setup */ 1413 /* make sure flip is at vb rather than hb */ 1414 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1415 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1416 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1417 1418 /* set pageflip to happen only at start of vblank interval (front porch) */ 1419 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1420 1421 if (!atomic && fb && fb != crtc->primary->fb) { 1422 radeon_fb = to_radeon_framebuffer(fb); 1423 rbo = gem_to_radeon_bo(radeon_fb->obj); 1424 r = radeon_bo_reserve(rbo, false); 1425 if (unlikely(r != 0)) 1426 return r; 1427 radeon_bo_unpin(rbo); 1428 radeon_bo_unreserve(rbo); 1429 } 1430 1431 /* Bytes per pixel may have changed */ 1432 radeon_bandwidth_update(rdev); 1433 1434 return 0; 1435 } 1436 1437 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1438 struct drm_framebuffer *fb, 1439 int x, int y, int atomic) 1440 { 1441 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1442 struct drm_device *dev = crtc->dev; 1443 struct radeon_device *rdev = dev->dev_private; 1444 struct radeon_framebuffer *radeon_fb; 1445 struct drm_gem_object *obj; 1446 struct radeon_bo *rbo; 1447 struct drm_framebuffer *target_fb; 1448 uint64_t fb_location; 1449 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1450 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1451 u32 tmp, viewport_w, viewport_h; 1452 int r; 1453 bool bypass_lut = false; 1454 1455 /* no fb bound */ 1456 if (!atomic && !crtc->primary->fb) { 1457 DRM_DEBUG_KMS("No FB bound\n"); 1458 return 0; 1459 } 1460 1461 if (atomic) { 1462 radeon_fb = to_radeon_framebuffer(fb); 1463 target_fb = fb; 1464 } 1465 else { 1466 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 1467 target_fb = crtc->primary->fb; 1468 } 1469 1470 obj = radeon_fb->obj; 1471 rbo = gem_to_radeon_bo(obj); 1472 r = radeon_bo_reserve(rbo, false); 1473 if (unlikely(r != 0)) 1474 return r; 1475 1476 /* If atomic, assume fb object is pinned & idle & fenced and 1477 * just update base pointers 1478 */ 1479 if (atomic) 1480 fb_location = radeon_bo_gpu_offset(rbo); 1481 else { 1482 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, (u64 *)&fb_location); 1483 if (unlikely(r != 0)) { 1484 radeon_bo_unreserve(rbo); 1485 return -EINVAL; 1486 } 1487 } 1488 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1489 radeon_bo_unreserve(rbo); 1490 1491 switch (target_fb->pixel_format) { 1492 case DRM_FORMAT_C8: 1493 fb_format = 1494 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1495 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1496 break; 1497 case DRM_FORMAT_XRGB4444: 1498 case DRM_FORMAT_ARGB4444: 1499 fb_format = 1500 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1501 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; 1502 #ifdef __BIG_ENDIAN 1503 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1504 #endif 1505 break; 1506 case DRM_FORMAT_XRGB1555: 1507 fb_format = 1508 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1509 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1510 #ifdef __BIG_ENDIAN 1511 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1512 #endif 1513 break; 1514 case DRM_FORMAT_RGB565: 1515 fb_format = 1516 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1517 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1518 #ifdef __BIG_ENDIAN 1519 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1520 #endif 1521 break; 1522 case DRM_FORMAT_XRGB8888: 1523 case DRM_FORMAT_ARGB8888: 1524 fb_format = 1525 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1526 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1527 #ifdef __BIG_ENDIAN 1528 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1529 #endif 1530 break; 1531 case DRM_FORMAT_XRGB2101010: 1532 case DRM_FORMAT_ARGB2101010: 1533 fb_format = 1534 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1535 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; 1536 #ifdef __BIG_ENDIAN 1537 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1538 #endif 1539 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1540 bypass_lut = true; 1541 break; 1542 default: 1543 DRM_ERROR("Unsupported screen format %s\n", 1544 drm_get_format_name(target_fb->pixel_format)); 1545 return -EINVAL; 1546 } 1547 1548 if (rdev->family >= CHIP_R600) { 1549 if (tiling_flags & RADEON_TILING_MACRO) 1550 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1551 else if (tiling_flags & RADEON_TILING_MICRO) 1552 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1553 } else { 1554 if (tiling_flags & RADEON_TILING_MACRO) 1555 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1556 1557 if (tiling_flags & RADEON_TILING_MICRO) 1558 fb_format |= AVIVO_D1GRPH_TILED; 1559 } 1560 1561 if (radeon_crtc->crtc_id == 0) 1562 WREG32(AVIVO_D1VGA_CONTROL, 0); 1563 else 1564 WREG32(AVIVO_D2VGA_CONTROL, 0); 1565 1566 if (rdev->family >= CHIP_RV770) { 1567 if (radeon_crtc->crtc_id) { 1568 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1569 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1570 } else { 1571 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1572 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1573 } 1574 } 1575 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1576 (u32) fb_location); 1577 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1578 radeon_crtc->crtc_offset, (u32) fb_location); 1579 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1580 if (rdev->family >= CHIP_R600) 1581 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1582 1583 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ 1584 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, 1585 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); 1586 1587 if (bypass_lut) 1588 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1589 1590 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1591 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1592 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1593 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1594 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1595 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1596 1597 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1598 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1599 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1600 1601 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1602 target_fb->height); 1603 x &= ~3; 1604 y &= ~1; 1605 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1606 (x << 16) | y); 1607 viewport_w = crtc->mode.hdisplay; 1608 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1609 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1610 (viewport_w << 16) | viewport_h); 1611 1612 /* pageflip setup */ 1613 /* make sure flip is at vb rather than hb */ 1614 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1615 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1616 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1617 1618 /* set pageflip to happen only at start of vblank interval (front porch) */ 1619 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1620 1621 if (!atomic && fb && fb != crtc->primary->fb) { 1622 radeon_fb = to_radeon_framebuffer(fb); 1623 rbo = gem_to_radeon_bo(radeon_fb->obj); 1624 r = radeon_bo_reserve(rbo, false); 1625 if (unlikely(r != 0)) 1626 return r; 1627 radeon_bo_unpin(rbo); 1628 radeon_bo_unreserve(rbo); 1629 } 1630 1631 /* Bytes per pixel may have changed */ 1632 radeon_bandwidth_update(rdev); 1633 1634 return 0; 1635 } 1636 1637 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1638 struct drm_framebuffer *old_fb) 1639 { 1640 struct drm_device *dev = crtc->dev; 1641 struct radeon_device *rdev = dev->dev_private; 1642 1643 if (ASIC_IS_DCE4(rdev)) 1644 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1645 else if (ASIC_IS_AVIVO(rdev)) 1646 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1647 else 1648 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1649 } 1650 1651 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1652 struct drm_framebuffer *fb, 1653 int x, int y, enum mode_set_atomic state) 1654 { 1655 struct drm_device *dev = crtc->dev; 1656 struct radeon_device *rdev = dev->dev_private; 1657 1658 if (ASIC_IS_DCE4(rdev)) 1659 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1660 else if (ASIC_IS_AVIVO(rdev)) 1661 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1662 else 1663 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1664 } 1665 1666 /* properly set additional regs when using atombios */ 1667 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1668 { 1669 struct drm_device *dev = crtc->dev; 1670 struct radeon_device *rdev = dev->dev_private; 1671 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1672 u32 disp_merge_cntl; 1673 1674 switch (radeon_crtc->crtc_id) { 1675 case 0: 1676 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1677 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1678 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1679 break; 1680 case 1: 1681 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1682 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1683 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1684 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1685 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1686 break; 1687 } 1688 } 1689 1690 /** 1691 * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1692 * 1693 * @crtc: drm crtc 1694 * 1695 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1696 */ 1697 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1698 { 1699 struct drm_device *dev = crtc->dev; 1700 struct drm_crtc *test_crtc; 1701 struct radeon_crtc *test_radeon_crtc; 1702 u32 pll_in_use = 0; 1703 1704 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1705 if (crtc == test_crtc) 1706 continue; 1707 1708 test_radeon_crtc = to_radeon_crtc(test_crtc); 1709 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1710 pll_in_use |= (1 << test_radeon_crtc->pll_id); 1711 } 1712 return pll_in_use; 1713 } 1714 1715 /** 1716 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1717 * 1718 * @crtc: drm crtc 1719 * 1720 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1721 * also in DP mode. For DP, a single PPLL can be used for all DP 1722 * crtcs/encoders. 1723 */ 1724 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1725 { 1726 struct drm_device *dev = crtc->dev; 1727 struct drm_crtc *test_crtc; 1728 struct radeon_crtc *test_radeon_crtc; 1729 1730 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1731 if (crtc == test_crtc) 1732 continue; 1733 test_radeon_crtc = to_radeon_crtc(test_crtc); 1734 if (test_radeon_crtc->encoder && 1735 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1736 /* for DP use the same PLL for all */ 1737 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1738 return test_radeon_crtc->pll_id; 1739 } 1740 } 1741 return ATOM_PPLL_INVALID; 1742 } 1743 1744 /** 1745 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 1746 * 1747 * @crtc: drm crtc 1748 * @encoder: drm encoder 1749 * 1750 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 1751 * be shared (i.e., same clock). 1752 */ 1753 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 1754 { 1755 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1756 struct drm_device *dev = crtc->dev; 1757 struct drm_crtc *test_crtc; 1758 struct radeon_crtc *test_radeon_crtc; 1759 u32 adjusted_clock, test_adjusted_clock; 1760 1761 adjusted_clock = radeon_crtc->adjusted_clock; 1762 1763 if (adjusted_clock == 0) 1764 return ATOM_PPLL_INVALID; 1765 1766 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1767 if (crtc == test_crtc) 1768 continue; 1769 test_radeon_crtc = to_radeon_crtc(test_crtc); 1770 if (test_radeon_crtc->encoder && 1771 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1772 /* check if we are already driving this connector with another crtc */ 1773 if (test_radeon_crtc->connector == radeon_crtc->connector) { 1774 /* if we are, return that pll */ 1775 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1776 return test_radeon_crtc->pll_id; 1777 } 1778 /* for non-DP check the clock */ 1779 test_adjusted_clock = test_radeon_crtc->adjusted_clock; 1780 if ((crtc->mode.clock == test_crtc->mode.clock) && 1781 (adjusted_clock == test_adjusted_clock) && 1782 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 1783 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 1784 return test_radeon_crtc->pll_id; 1785 } 1786 } 1787 return ATOM_PPLL_INVALID; 1788 } 1789 1790 /** 1791 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1792 * 1793 * @crtc: drm crtc 1794 * 1795 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1796 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1797 * monitors a dedicated PPLL must be used. If a particular board has 1798 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1799 * as there is no need to program the PLL itself. If we are not able to 1800 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1801 * avoid messing up an existing monitor. 1802 * 1803 * Asic specific PLL information 1804 * 1805 * DCE 8.x 1806 * KB/KV 1807 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 1808 * CI 1809 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1810 * 1811 * DCE 6.1 1812 * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1813 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1814 * 1815 * DCE 6.0 1816 * - PPLL0 is available to all UNIPHY (DP only) 1817 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1818 * 1819 * DCE 5.0 1820 * - DCPLL is available to all UNIPHY (DP only) 1821 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1822 * 1823 * DCE 3.0/4.0/4.1 1824 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1825 * 1826 */ 1827 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1828 { 1829 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1830 struct drm_device *dev = crtc->dev; 1831 struct radeon_device *rdev = dev->dev_private; 1832 struct radeon_encoder *radeon_encoder = 1833 to_radeon_encoder(radeon_crtc->encoder); 1834 u32 pll_in_use; 1835 int pll; 1836 1837 if (ASIC_IS_DCE8(rdev)) { 1838 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1839 if (rdev->clock.dp_extclk) 1840 /* skip PPLL programming if using ext clock */ 1841 return ATOM_PPLL_INVALID; 1842 else { 1843 /* use the same PPLL for all DP monitors */ 1844 pll = radeon_get_shared_dp_ppll(crtc); 1845 if (pll != ATOM_PPLL_INVALID) 1846 return pll; 1847 } 1848 } else { 1849 /* use the same PPLL for all monitors with the same clock */ 1850 pll = radeon_get_shared_nondp_ppll(crtc); 1851 if (pll != ATOM_PPLL_INVALID) 1852 return pll; 1853 } 1854 /* otherwise, pick one of the plls */ 1855 if ((rdev->family == CHIP_KAVERI) || 1856 (rdev->family == CHIP_KABINI) || 1857 (rdev->family == CHIP_MULLINS)) { 1858 /* KB/KV/ML has PPLL1 and PPLL2 */ 1859 pll_in_use = radeon_get_pll_use_mask(crtc); 1860 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1861 return ATOM_PPLL2; 1862 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1863 return ATOM_PPLL1; 1864 DRM_ERROR("unable to allocate a PPLL\n"); 1865 return ATOM_PPLL_INVALID; 1866 } else { 1867 /* CI has PPLL0, PPLL1, and PPLL2 */ 1868 pll_in_use = radeon_get_pll_use_mask(crtc); 1869 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1870 return ATOM_PPLL2; 1871 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1872 return ATOM_PPLL1; 1873 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1874 return ATOM_PPLL0; 1875 DRM_ERROR("unable to allocate a PPLL\n"); 1876 return ATOM_PPLL_INVALID; 1877 } 1878 } else if (ASIC_IS_DCE61(rdev)) { 1879 struct radeon_encoder_atom_dig *dig = 1880 radeon_encoder->enc_priv; 1881 1882 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1883 (dig->linkb == false)) 1884 /* UNIPHY A uses PPLL2 */ 1885 return ATOM_PPLL2; 1886 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1887 /* UNIPHY B/C/D/E/F */ 1888 if (rdev->clock.dp_extclk) 1889 /* skip PPLL programming if using ext clock */ 1890 return ATOM_PPLL_INVALID; 1891 else { 1892 /* use the same PPLL for all DP monitors */ 1893 pll = radeon_get_shared_dp_ppll(crtc); 1894 if (pll != ATOM_PPLL_INVALID) 1895 return pll; 1896 } 1897 } else { 1898 /* use the same PPLL for all monitors with the same clock */ 1899 pll = radeon_get_shared_nondp_ppll(crtc); 1900 if (pll != ATOM_PPLL_INVALID) 1901 return pll; 1902 } 1903 /* UNIPHY B/C/D/E/F */ 1904 pll_in_use = radeon_get_pll_use_mask(crtc); 1905 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1906 return ATOM_PPLL0; 1907 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1908 return ATOM_PPLL1; 1909 DRM_ERROR("unable to allocate a PPLL\n"); 1910 return ATOM_PPLL_INVALID; 1911 } else if (ASIC_IS_DCE41(rdev)) { 1912 /* Don't share PLLs on DCE4.1 chips */ 1913 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1914 if (rdev->clock.dp_extclk) 1915 /* skip PPLL programming if using ext clock */ 1916 return ATOM_PPLL_INVALID; 1917 } 1918 pll_in_use = radeon_get_pll_use_mask(crtc); 1919 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1920 return ATOM_PPLL1; 1921 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1922 return ATOM_PPLL2; 1923 DRM_ERROR("unable to allocate a PPLL\n"); 1924 return ATOM_PPLL_INVALID; 1925 } else if (ASIC_IS_DCE4(rdev)) { 1926 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1927 * depending on the asic: 1928 * DCE4: PPLL or ext clock 1929 * DCE5: PPLL, DCPLL, or ext clock 1930 * DCE6: PPLL, PPLL0, or ext clock 1931 * 1932 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1933 * PPLL/DCPLL programming and only program the DP DTO for the 1934 * crtc virtual pixel clock. 1935 */ 1936 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1937 if (rdev->clock.dp_extclk) 1938 /* skip PPLL programming if using ext clock */ 1939 return ATOM_PPLL_INVALID; 1940 else if (ASIC_IS_DCE6(rdev)) 1941 /* use PPLL0 for all DP */ 1942 return ATOM_PPLL0; 1943 else if (ASIC_IS_DCE5(rdev)) 1944 /* use DCPLL for all DP */ 1945 return ATOM_DCPLL; 1946 else { 1947 /* use the same PPLL for all DP monitors */ 1948 pll = radeon_get_shared_dp_ppll(crtc); 1949 if (pll != ATOM_PPLL_INVALID) 1950 return pll; 1951 } 1952 } else { 1953 /* use the same PPLL for all monitors with the same clock */ 1954 pll = radeon_get_shared_nondp_ppll(crtc); 1955 if (pll != ATOM_PPLL_INVALID) 1956 return pll; 1957 } 1958 /* all other cases */ 1959 pll_in_use = radeon_get_pll_use_mask(crtc); 1960 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1961 return ATOM_PPLL1; 1962 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1963 return ATOM_PPLL2; 1964 DRM_ERROR("unable to allocate a PPLL\n"); 1965 return ATOM_PPLL_INVALID; 1966 } else { 1967 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1968 /* some atombios (observed in some DCE2/DCE3) code have a bug, 1969 * the matching btw pll and crtc is done through 1970 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 1971 * pll (1 or 2) to select which register to write. ie if using 1972 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 1973 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 1974 * choose which value to write. Which is reverse order from 1975 * register logic. So only case that works is when pllid is 1976 * same as crtcid or when both pll and crtc are enabled and 1977 * both use same clock. 1978 * 1979 * So just return crtc id as if crtc and pll were hard linked 1980 * together even if they aren't 1981 */ 1982 return radeon_crtc->crtc_id; 1983 } 1984 } 1985 1986 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 1987 { 1988 /* always set DCPLL */ 1989 if (ASIC_IS_DCE6(rdev)) 1990 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1991 else if (ASIC_IS_DCE4(rdev)) { 1992 struct radeon_atom_ss ss; 1993 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 1994 ASIC_INTERNAL_SS_ON_DCPLL, 1995 rdev->clock.default_dispclk); 1996 if (ss_enabled) 1997 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 1998 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1999 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 2000 if (ss_enabled) 2001 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 2002 } 2003 2004 } 2005 2006 int atombios_crtc_mode_set(struct drm_crtc *crtc, 2007 struct drm_display_mode *mode, 2008 struct drm_display_mode *adjusted_mode, 2009 int x, int y, struct drm_framebuffer *old_fb) 2010 { 2011 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2012 struct drm_device *dev = crtc->dev; 2013 struct radeon_device *rdev = dev->dev_private; 2014 struct radeon_encoder *radeon_encoder = 2015 to_radeon_encoder(radeon_crtc->encoder); 2016 bool is_tvcv = false; 2017 2018 if (radeon_encoder->active_device & 2019 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2020 is_tvcv = true; 2021 2022 if (!radeon_crtc->adjusted_clock) 2023 return -EINVAL; 2024 2025 atombios_crtc_set_pll(crtc, adjusted_mode); 2026 2027 if (ASIC_IS_DCE4(rdev)) 2028 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2029 else if (ASIC_IS_AVIVO(rdev)) { 2030 if (is_tvcv) 2031 atombios_crtc_set_timing(crtc, adjusted_mode); 2032 else 2033 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2034 } else { 2035 atombios_crtc_set_timing(crtc, adjusted_mode); 2036 if (radeon_crtc->crtc_id == 0) 2037 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2038 radeon_legacy_atom_fixup(crtc); 2039 } 2040 atombios_crtc_set_base(crtc, x, y, old_fb); 2041 atombios_overscan_setup(crtc, mode, adjusted_mode); 2042 atombios_scaler_setup(crtc); 2043 /* update the hw version fpr dpm */ 2044 radeon_crtc->hw_mode = *adjusted_mode; 2045 2046 return 0; 2047 } 2048 2049 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 2050 const struct drm_display_mode *mode, 2051 struct drm_display_mode *adjusted_mode) 2052 { 2053 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2054 struct drm_device *dev = crtc->dev; 2055 struct drm_encoder *encoder; 2056 2057 /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 2058 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2059 if (encoder->crtc == crtc) { 2060 radeon_crtc->encoder = encoder; 2061 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 2062 break; 2063 } 2064 } 2065 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 2066 radeon_crtc->encoder = NULL; 2067 radeon_crtc->connector = NULL; 2068 return false; 2069 } 2070 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2071 return false; 2072 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2073 return false; 2074 /* pick pll */ 2075 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 2076 /* if we can't get a PPLL for a non-DP encoder, fail */ 2077 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 2078 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 2079 return false; 2080 2081 return true; 2082 } 2083 2084 static void atombios_crtc_prepare(struct drm_crtc *crtc) 2085 { 2086 struct drm_device *dev = crtc->dev; 2087 struct radeon_device *rdev = dev->dev_private; 2088 2089 /* disable crtc pair power gating before programming */ 2090 if (ASIC_IS_DCE6(rdev)) 2091 atombios_powergate_crtc(crtc, ATOM_DISABLE); 2092 2093 atombios_lock_crtc(crtc, ATOM_ENABLE); 2094 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2095 } 2096 2097 static void atombios_crtc_commit(struct drm_crtc *crtc) 2098 { 2099 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2100 atombios_lock_crtc(crtc, ATOM_DISABLE); 2101 } 2102 2103 static void atombios_crtc_disable(struct drm_crtc *crtc) 2104 { 2105 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2106 struct drm_device *dev = crtc->dev; 2107 struct radeon_device *rdev = dev->dev_private; 2108 struct radeon_atom_ss ss; 2109 int i; 2110 2111 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2112 if (crtc->primary->fb) { 2113 int r; 2114 struct radeon_framebuffer *radeon_fb; 2115 struct radeon_bo *rbo; 2116 2117 radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 2118 rbo = gem_to_radeon_bo(radeon_fb->obj); 2119 r = radeon_bo_reserve(rbo, false); 2120 if (unlikely(r)) 2121 DRM_ERROR("failed to reserve rbo before unpin\n"); 2122 else { 2123 radeon_bo_unpin(rbo); 2124 radeon_bo_unreserve(rbo); 2125 } 2126 } 2127 /* disable the GRPH */ 2128 if (ASIC_IS_DCE4(rdev)) 2129 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2130 else if (ASIC_IS_AVIVO(rdev)) 2131 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2132 2133 if (ASIC_IS_DCE6(rdev)) 2134 atombios_powergate_crtc(crtc, ATOM_ENABLE); 2135 2136 for (i = 0; i < rdev->num_crtc; i++) { 2137 if (rdev->mode_info.crtcs[i] && 2138 rdev->mode_info.crtcs[i]->enabled && 2139 i != radeon_crtc->crtc_id && 2140 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 2141 /* one other crtc is using this pll don't turn 2142 * off the pll 2143 */ 2144 goto done; 2145 } 2146 } 2147 2148 switch (radeon_crtc->pll_id) { 2149 case ATOM_PPLL1: 2150 case ATOM_PPLL2: 2151 /* disable the ppll */ 2152 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2153 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2154 break; 2155 case ATOM_PPLL0: 2156 /* disable the ppll */ 2157 if ((rdev->family == CHIP_ARUBA) || 2158 (rdev->family == CHIP_BONAIRE) || 2159 (rdev->family == CHIP_HAWAII)) 2160 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2161 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2162 break; 2163 default: 2164 break; 2165 } 2166 done: 2167 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2168 radeon_crtc->adjusted_clock = 0; 2169 radeon_crtc->encoder = NULL; 2170 radeon_crtc->connector = NULL; 2171 } 2172 2173 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 2174 .dpms = atombios_crtc_dpms, 2175 .mode_fixup = atombios_crtc_mode_fixup, 2176 .mode_set = atombios_crtc_mode_set, 2177 .mode_set_base = atombios_crtc_set_base, 2178 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 2179 .prepare = atombios_crtc_prepare, 2180 .commit = atombios_crtc_commit, 2181 .load_lut = radeon_crtc_load_lut, 2182 .disable = atombios_crtc_disable, 2183 }; 2184 2185 void radeon_atombios_init_crtc(struct drm_device *dev, 2186 struct radeon_crtc *radeon_crtc) 2187 { 2188 struct radeon_device *rdev = dev->dev_private; 2189 2190 if (ASIC_IS_DCE4(rdev)) { 2191 switch (radeon_crtc->crtc_id) { 2192 case 0: 2193 default: 2194 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 2195 break; 2196 case 1: 2197 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 2198 break; 2199 case 2: 2200 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 2201 break; 2202 case 3: 2203 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 2204 break; 2205 case 4: 2206 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 2207 break; 2208 case 5: 2209 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 2210 break; 2211 } 2212 } else { 2213 if (radeon_crtc->crtc_id == 1) 2214 radeon_crtc->crtc_offset = 2215 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 2216 else 2217 radeon_crtc->crtc_offset = 0; 2218 } 2219 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2220 radeon_crtc->adjusted_clock = 0; 2221 radeon_crtc->encoder = NULL; 2222 radeon_crtc->connector = NULL; 2223 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 2224 } 2225