1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include <drm/drmP.h> 28 #include <uapi_drm/radeon_drm.h> 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include <drm/drm_dp_helper.h> 34 35 /* move these to drm_dp_helper.c/h */ 36 #define DP_LINK_CONFIGURATION_SIZE 9 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 38 39 static char *voltage_names[] = { 40 "0.4V", "0.6V", "0.8V", "1.2V" 41 }; 42 static char *pre_emph_names[] = { 43 "0dB", "3.5dB", "6dB", "9.5dB" 44 }; 45 46 /***** radeon AUX functions *****/ 47 48 /* Atom needs data in little endian format 49 * so swap as appropriate when copying data to 50 * or from atom. Note that atom operates on 51 * dw units. 52 */ 53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 54 { 55 #ifdef __BIG_ENDIAN 56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 57 u32 *dst32, *src32; 58 int i; 59 60 memcpy(src_tmp, src, num_bytes); 61 src32 = (u32 *)src_tmp; 62 dst32 = (u32 *)dst_tmp; 63 if (to_le) { 64 for (i = 0; i < ((num_bytes + 3) / 4); i++) 65 dst32[i] = cpu_to_le32(src32[i]); 66 memcpy(dst, dst_tmp, num_bytes); 67 } else { 68 u8 dws = num_bytes & ~3; 69 for (i = 0; i < ((num_bytes + 3) / 4); i++) 70 dst32[i] = le32_to_cpu(src32[i]); 71 memcpy(dst, dst_tmp, dws); 72 if (num_bytes % 4) { 73 for (i = 0; i < (num_bytes % 4); i++) 74 dst[dws+i] = dst_tmp[dws+i]; 75 } 76 } 77 #else 78 memcpy(dst, src, num_bytes); 79 #endif 80 } 81 82 union aux_channel_transaction { 83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 85 }; 86 87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 88 u8 *send, int send_bytes, 89 u8 *recv, int recv_size, 90 u8 delay, u8 *ack) 91 { 92 struct drm_device *dev = chan->dev; 93 struct radeon_device *rdev = dev->dev_private; 94 union aux_channel_transaction args; 95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 96 unsigned char *base; 97 int recv_bytes; 98 int r = 0; 99 100 memset(&args, 0, sizeof(args)); 101 102 lockmgr(&chan->mutex, LK_EXCLUSIVE); 103 lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_EXCLUSIVE); 104 105 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 106 107 radeon_atom_copy_swap(base, send, send_bytes, true); 108 109 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 110 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); 111 args.v1.ucDataOutLen = 0; 112 args.v1.ucChannelID = chan->rec.i2c_id; 113 args.v1.ucDelay = delay / 10; 114 if (ASIC_IS_DCE4(rdev)) 115 args.v2.ucHPD_ID = chan->rec.hpd; 116 117 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); 118 119 *ack = args.v1.ucReplyStatus; 120 121 /* timeout */ 122 if (args.v1.ucReplyStatus == 1) { 123 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 124 r = -ETIMEDOUT; 125 goto done; 126 } 127 128 /* flags not zero */ 129 if (args.v1.ucReplyStatus == 2) { 130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 131 r = -EIO; 132 goto done; 133 } 134 135 /* error */ 136 if (args.v1.ucReplyStatus == 3) { 137 DRM_DEBUG_KMS("dp_aux_ch error\n"); 138 r = -EIO; 139 goto done; 140 } 141 142 recv_bytes = args.v1.ucDataOutLen; 143 if (recv_bytes > recv_size) 144 recv_bytes = recv_size; 145 146 if (recv && recv_size) 147 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); 148 149 r = recv_bytes; 150 done: 151 lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_RELEASE); 152 lockmgr(&chan->mutex, LK_RELEASE); 153 154 return r; 155 } 156 157 #define BARE_ADDRESS_SIZE 3 158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 159 160 static ssize_t 161 radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 162 { 163 struct radeon_i2c_chan *chan = 164 container_of(aux, struct radeon_i2c_chan, aux); 165 int ret; 166 u8 tx_buf[20]; 167 size_t tx_size; 168 u8 ack, delay = 0; 169 170 if (WARN_ON(msg->size > 16)) 171 return -E2BIG; 172 173 tx_buf[0] = msg->address & 0xff; 174 tx_buf[1] = msg->address >> 8; 175 tx_buf[2] = msg->request << 4; 176 tx_buf[3] = msg->size ? (msg->size - 1) : 0; 177 178 switch (msg->request & ~DP_AUX_I2C_MOT) { 179 case DP_AUX_NATIVE_WRITE: 180 case DP_AUX_I2C_WRITE: 181 /* tx_size needs to be 4 even for bare address packets since the atom 182 * table needs the info in tx_buf[3]. 183 */ 184 tx_size = HEADER_SIZE + msg->size; 185 if (msg->size == 0) 186 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 187 else 188 tx_buf[3] |= tx_size << 4; 189 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 190 ret = radeon_process_aux_ch(chan, 191 tx_buf, tx_size, NULL, 0, delay, &ack); 192 if (ret >= 0) 193 /* Return payload size. */ 194 ret = msg->size; 195 break; 196 case DP_AUX_NATIVE_READ: 197 case DP_AUX_I2C_READ: 198 /* tx_size needs to be 4 even for bare address packets since the atom 199 * table needs the info in tx_buf[3]. 200 */ 201 tx_size = HEADER_SIZE; 202 if (msg->size == 0) 203 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 204 else 205 tx_buf[3] |= tx_size << 4; 206 ret = radeon_process_aux_ch(chan, 207 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 208 break; 209 default: 210 ret = -EINVAL; 211 break; 212 } 213 214 if (ret >= 0) 215 msg->reply = ack >> 4; 216 217 return ret; 218 } 219 220 void radeon_dp_aux_init(struct radeon_connector *radeon_connector) 221 { 222 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 223 224 dig_connector->dp_i2c_bus->rec.hpd = radeon_connector->hpd.hpd; /* XXX check*/ 225 dig_connector->dp_i2c_bus->aux.dev = radeon_connector->base.kdev; 226 dig_connector->dp_i2c_bus->aux.transfer = radeon_dp_aux_transfer; 227 } 228 229 int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte) 230 { 231 struct i2c_algo_dp_aux_data *algo_data = device_get_softc(dev); 232 struct radeon_i2c_chan *auxch = algo_data->priv; 233 u16 address = algo_data->address; 234 u8 msg[5]; 235 u8 reply[2]; 236 unsigned retry; 237 int msg_bytes; 238 int reply_bytes = 1; 239 int ret; 240 u8 ack; 241 242 /* Set up the address */ 243 msg[0] = address; 244 msg[1] = address >> 8; 245 246 /* Set up the command byte */ 247 if (mode & MODE_I2C_READ) { 248 msg[2] = DP_AUX_I2C_READ << 4; 249 msg_bytes = 4; 250 msg[3] = msg_bytes << 4; 251 } else { 252 msg[2] = DP_AUX_I2C_WRITE << 4; 253 msg_bytes = 5; 254 msg[3] = msg_bytes << 4; 255 msg[4] = write_byte; 256 } 257 258 /* special handling for start/stop */ 259 if (mode & (MODE_I2C_START | MODE_I2C_STOP)) 260 msg[3] = 3 << 4; 261 262 /* Set MOT bit for all but stop */ 263 if ((mode & MODE_I2C_STOP) == 0) 264 msg[2] |= DP_AUX_I2C_MOT << 4; 265 266 for (retry = 0; retry < 7; retry++) { 267 ret = radeon_process_aux_ch(auxch, 268 msg, msg_bytes, reply, reply_bytes, 0, &ack); 269 if (ret == -EBUSY) 270 continue; 271 else if (ret < 0) { 272 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 273 return ret; 274 } 275 276 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) { 277 case DP_AUX_NATIVE_REPLY_ACK: 278 /* I2C-over-AUX Reply field is only valid 279 * when paired with AUX ACK. 280 */ 281 break; 282 case DP_AUX_NATIVE_REPLY_NACK: 283 DRM_DEBUG_KMS("aux_ch native nack\n"); 284 return -EREMOTEIO; 285 case DP_AUX_NATIVE_REPLY_DEFER: 286 DRM_DEBUG_KMS("aux_ch native defer\n"); 287 usleep_range(500, 600); 288 continue; 289 default: 290 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); 291 return -EREMOTEIO; 292 } 293 294 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) { 295 case DP_AUX_I2C_REPLY_ACK: 296 if (mode == MODE_I2C_READ) 297 *read_byte = reply[0]; 298 return (0); /* XXX: why 0 and not msg size? */ 299 case DP_AUX_I2C_REPLY_NACK: 300 DRM_DEBUG_KMS("aux_i2c nack\n"); 301 return -EREMOTEIO; 302 case DP_AUX_I2C_REPLY_DEFER: 303 DRM_DEBUG_KMS("aux_i2c defer\n"); 304 usleep_range(400, 500); 305 break; 306 default: 307 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); 308 return -EREMOTEIO; 309 } 310 } 311 312 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); 313 return -EREMOTEIO; 314 } 315 316 /***** general DP utility functions *****/ 317 318 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 319 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 320 321 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], 322 int lane_count, 323 u8 train_set[4]) 324 { 325 u8 v = 0; 326 u8 p = 0; 327 int lane; 328 329 for (lane = 0; lane < lane_count; lane++) { 330 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 331 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 332 333 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 334 lane, 335 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 336 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 337 338 if (this_v > v) 339 v = this_v; 340 if (this_p > p) 341 p = this_p; 342 } 343 344 if (v >= DP_VOLTAGE_MAX) 345 v |= DP_TRAIN_MAX_SWING_REACHED; 346 347 if (p >= DP_PRE_EMPHASIS_MAX) 348 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 349 350 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 351 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 352 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 353 354 for (lane = 0; lane < 4; lane++) 355 train_set[lane] = v | p; 356 } 357 358 /* convert bits per color to bits per pixel */ 359 /* get bpc from the EDID */ 360 static int convert_bpc_to_bpp(int bpc) 361 { 362 if (bpc == 0) 363 return 24; 364 else 365 return bpc * 3; 366 } 367 368 /* get the max pix clock supported by the link rate and lane num */ 369 static int dp_get_max_dp_pix_clock(int link_rate, 370 int lane_num, 371 int bpp) 372 { 373 return (link_rate * lane_num * 8) / bpp; 374 } 375 376 /***** radeon specific DP functions *****/ 377 378 static int radeon_dp_get_max_link_rate(struct drm_connector *connector, 379 u8 dpcd[DP_DPCD_SIZE]) 380 { 381 int max_link_rate; 382 383 if (radeon_connector_is_dp12_capable(connector)) 384 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); 385 else 386 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); 387 388 return max_link_rate; 389 } 390 391 /* First get the min lane# when low rate is used according to pixel clock 392 * (prefer low rate), second check max lane# supported by DP panel, 393 * if the max lane# < low rate lane# then use max lane# instead. 394 */ 395 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 396 u8 dpcd[DP_DPCD_SIZE], 397 int pix_clock) 398 { 399 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 400 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); 401 int max_lane_num = drm_dp_max_lane_count(dpcd); 402 int lane_num; 403 int max_dp_pix_clock; 404 405 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { 406 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); 407 if (pix_clock <= max_dp_pix_clock) 408 break; 409 } 410 411 return lane_num; 412 } 413 414 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, 415 u8 dpcd[DP_DPCD_SIZE], 416 int pix_clock) 417 { 418 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 419 int lane_num, max_pix_clock; 420 421 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 422 ENCODER_OBJECT_ID_NUTMEG) 423 return 270000; 424 425 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); 426 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); 427 if (pix_clock <= max_pix_clock) 428 return 162000; 429 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); 430 if (pix_clock <= max_pix_clock) 431 return 270000; 432 if (radeon_connector_is_dp12_capable(connector)) { 433 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); 434 if (pix_clock <= max_pix_clock) 435 return 540000; 436 } 437 438 return radeon_dp_get_max_link_rate(connector, dpcd); 439 } 440 441 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 442 int action, int dp_clock, 443 u8 ucconfig, u8 lane_num) 444 { 445 DP_ENCODER_SERVICE_PARAMETERS args; 446 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 447 448 memset(&args, 0, sizeof(args)); 449 args.ucLinkClock = dp_clock / 10; 450 args.ucConfig = ucconfig; 451 args.ucAction = action; 452 args.ucLaneNum = lane_num; 453 args.ucStatus = 0; 454 455 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 456 return args.ucStatus; 457 } 458 459 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 460 { 461 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 462 struct drm_device *dev = radeon_connector->base.dev; 463 struct radeon_device *rdev = dev->dev_private; 464 465 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 466 dig_connector->dp_i2c_bus->rec.i2c_id, 0); 467 } 468 469 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 470 { 471 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 472 u8 buf[3]; 473 474 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 475 return; 476 477 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_SINK_OUI, buf, 3) == 3) 478 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n", 479 buf[0], buf[1], buf[2]); 480 481 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 482 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n", 483 buf[0], buf[1], buf[2]); 484 } 485 486 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 487 { 488 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 489 u8 msg[DP_DPCD_SIZE]; 490 int ret; 491 492 char dpcd_hex_dump[DP_DPCD_SIZE * 3]; 493 494 ret = drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_DPCD_REV, msg, 495 DP_DPCD_SIZE); 496 if (ret > 0) { 497 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 498 DRM_DEBUG_KMS("DPCD: %s\n", hexncpy(dig_connector->dpcd, 499 sizeof(dig_connector->dpcd), 500 dpcd_hex_dump, sizeof(dpcd_hex_dump), " ")); 501 502 radeon_dp_probe_oui(radeon_connector); 503 504 return true; 505 } 506 dig_connector->dpcd[0] = 0; 507 return false; 508 } 509 510 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 511 struct drm_connector *connector) 512 { 513 struct drm_device *dev = encoder->dev; 514 struct radeon_device *rdev = dev->dev_private; 515 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 516 struct radeon_connector_atom_dig *dig_connector; 517 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 518 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 519 u8 tmp; 520 521 if (!ASIC_IS_DCE4(rdev)) 522 return panel_mode; 523 524 if (!radeon_connector->con_priv) 525 return panel_mode; 526 527 dig_connector = radeon_connector->con_priv; 528 529 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 530 /* DP bridge chips */ 531 if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, 532 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 533 if (tmp & 1) 534 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 535 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 536 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 537 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 538 else 539 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 540 } 541 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 542 /* eDP */ 543 if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, 544 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 545 if (tmp & 1) 546 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 547 } 548 } 549 550 return panel_mode; 551 } 552 553 void radeon_dp_set_link_config(struct drm_connector *connector, 554 const struct drm_display_mode *mode) 555 { 556 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 557 struct radeon_connector_atom_dig *dig_connector; 558 559 if (!radeon_connector->con_priv) 560 return; 561 dig_connector = radeon_connector->con_priv; 562 563 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 564 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 565 dig_connector->dp_clock = 566 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 567 dig_connector->dp_lane_count = 568 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); 569 } 570 } 571 572 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 573 struct drm_display_mode *mode) 574 { 575 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 576 struct radeon_connector_atom_dig *dig_connector; 577 int dp_clock; 578 579 if ((mode->clock > 340000) && 580 (!radeon_connector_is_dp12_capable(connector))) 581 return MODE_CLOCK_HIGH; 582 583 if (!radeon_connector->con_priv) 584 return MODE_CLOCK_HIGH; 585 dig_connector = radeon_connector->con_priv; 586 587 dp_clock = 588 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 589 590 if ((dp_clock == 540000) && 591 (!radeon_connector_is_dp12_capable(connector))) 592 return MODE_CLOCK_HIGH; 593 594 return MODE_OK; 595 } 596 597 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 598 { 599 u8 link_status[DP_LINK_STATUS_SIZE]; 600 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 601 602 if (drm_dp_dpcd_read_link_status(&dig->dp_i2c_bus->aux, link_status) <= 0) 603 return false; 604 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 605 return false; 606 return true; 607 } 608 609 void radeon_dp_set_rx_power_state(struct drm_connector *connector, 610 u8 power_state) 611 { 612 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 613 struct radeon_connector_atom_dig *dig_connector; 614 615 if (!radeon_connector->con_priv) 616 return; 617 618 dig_connector = radeon_connector->con_priv; 619 620 /* power up/down the sink */ 621 if (dig_connector->dpcd[0] >= 0x11) { 622 drm_dp_dpcd_writeb(&dig_connector->dp_i2c_bus->aux, 623 DP_SET_POWER, power_state); 624 usleep_range(1000, 2000); 625 } 626 } 627 628 629 struct radeon_dp_link_train_info { 630 struct radeon_device *rdev; 631 struct drm_encoder *encoder; 632 struct drm_connector *connector; 633 int enc_id; 634 int dp_clock; 635 int dp_lane_count; 636 bool tp3_supported; 637 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 638 u8 train_set[4]; 639 u8 link_status[DP_LINK_STATUS_SIZE]; 640 u8 tries; 641 bool use_dpencoder; 642 struct drm_dp_aux *aux; 643 }; 644 645 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 646 { 647 /* set the initial vs/emph on the source */ 648 atombios_dig_transmitter_setup(dp_info->encoder, 649 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 650 0, dp_info->train_set[0]); /* sets all lanes at once */ 651 652 /* set the vs/emph on the sink */ 653 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, 654 dp_info->train_set, dp_info->dp_lane_count); 655 } 656 657 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 658 { 659 int rtp = 0; 660 661 /* set training pattern on the source */ 662 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 663 switch (tp) { 664 case DP_TRAINING_PATTERN_1: 665 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 666 break; 667 case DP_TRAINING_PATTERN_2: 668 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 669 break; 670 case DP_TRAINING_PATTERN_3: 671 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 672 break; 673 } 674 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 675 } else { 676 switch (tp) { 677 case DP_TRAINING_PATTERN_1: 678 rtp = 0; 679 break; 680 case DP_TRAINING_PATTERN_2: 681 rtp = 1; 682 break; 683 } 684 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 685 dp_info->dp_clock, dp_info->enc_id, rtp); 686 } 687 688 /* enable training pattern on the sink */ 689 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); 690 } 691 692 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 693 { 694 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 695 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 696 u8 tmp; 697 698 /* power up the sink */ 699 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 700 701 /* possibly enable downspread on the sink */ 702 if (dp_info->dpcd[3] & 0x1) 703 drm_dp_dpcd_writeb(dp_info->aux, 704 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 705 else 706 drm_dp_dpcd_writeb(dp_info->aux, 707 DP_DOWNSPREAD_CTRL, 0); 708 709 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && 710 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { 711 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); 712 } 713 714 /* set the lane count on the sink */ 715 tmp = dp_info->dp_lane_count; 716 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 717 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 718 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); 719 720 /* set the link rate on the sink */ 721 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 722 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); 723 724 /* start training on the source */ 725 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 726 atombios_dig_encoder_setup(dp_info->encoder, 727 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 728 else 729 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 730 dp_info->dp_clock, dp_info->enc_id, 0); 731 732 /* disable the training pattern on the sink */ 733 drm_dp_dpcd_writeb(dp_info->aux, 734 DP_TRAINING_PATTERN_SET, 735 DP_TRAINING_PATTERN_DISABLE); 736 737 return 0; 738 } 739 740 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 741 { 742 udelay(400); 743 744 /* disable the training pattern on the sink */ 745 drm_dp_dpcd_writeb(dp_info->aux, 746 DP_TRAINING_PATTERN_SET, 747 DP_TRAINING_PATTERN_DISABLE); 748 749 /* disable the training pattern on the source */ 750 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 751 atombios_dig_encoder_setup(dp_info->encoder, 752 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 753 else 754 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 755 dp_info->dp_clock, dp_info->enc_id, 0); 756 757 return 0; 758 } 759 760 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 761 { 762 bool clock_recovery; 763 u8 voltage; 764 int i; 765 766 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 767 memset(dp_info->train_set, 0, 4); 768 radeon_dp_update_vs_emph(dp_info); 769 770 udelay(400); 771 772 /* clock recovery loop */ 773 clock_recovery = false; 774 dp_info->tries = 0; 775 voltage = 0xff; 776 while (1) { 777 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 778 779 if (drm_dp_dpcd_read_link_status(dp_info->aux, 780 dp_info->link_status) <= 0) { 781 DRM_ERROR("displayport link status failed\n"); 782 break; 783 } 784 785 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 786 clock_recovery = true; 787 break; 788 } 789 790 for (i = 0; i < dp_info->dp_lane_count; i++) { 791 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 792 break; 793 } 794 if (i == dp_info->dp_lane_count) { 795 DRM_ERROR("clock recovery reached max voltage\n"); 796 break; 797 } 798 799 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 800 ++dp_info->tries; 801 if (dp_info->tries == 5) { 802 DRM_ERROR("clock recovery tried 5 times\n"); 803 break; 804 } 805 } else 806 dp_info->tries = 0; 807 808 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 809 810 /* Compute new train_set as requested by sink */ 811 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 812 813 radeon_dp_update_vs_emph(dp_info); 814 } 815 if (!clock_recovery) { 816 DRM_ERROR("clock recovery failed\n"); 817 return -1; 818 } else { 819 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 820 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 821 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 822 DP_TRAIN_PRE_EMPHASIS_SHIFT); 823 return 0; 824 } 825 } 826 827 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 828 { 829 bool channel_eq; 830 831 if (dp_info->tp3_supported) 832 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 833 else 834 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 835 836 /* channel equalization loop */ 837 dp_info->tries = 0; 838 channel_eq = false; 839 while (1) { 840 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 841 842 if (drm_dp_dpcd_read_link_status(dp_info->aux, 843 dp_info->link_status) <= 0) { 844 DRM_ERROR("displayport link status failed\n"); 845 break; 846 } 847 848 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 849 channel_eq = true; 850 break; 851 } 852 853 /* Try 5 times */ 854 if (dp_info->tries > 5) { 855 DRM_ERROR("channel eq failed: 5 tries\n"); 856 break; 857 } 858 859 /* Compute new train_set as requested by sink */ 860 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 861 862 radeon_dp_update_vs_emph(dp_info); 863 dp_info->tries++; 864 } 865 866 if (!channel_eq) { 867 DRM_ERROR("channel eq failed\n"); 868 return -1; 869 } else { 870 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 871 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 872 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 873 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 874 return 0; 875 } 876 } 877 878 void radeon_dp_link_train(struct drm_encoder *encoder, 879 struct drm_connector *connector) 880 { 881 struct drm_device *dev = encoder->dev; 882 struct radeon_device *rdev = dev->dev_private; 883 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 884 struct radeon_encoder_atom_dig *dig; 885 struct radeon_connector *radeon_connector; 886 struct radeon_connector_atom_dig *dig_connector; 887 struct radeon_dp_link_train_info dp_info; 888 int index; 889 u8 tmp, frev, crev; 890 891 if (!radeon_encoder->enc_priv) 892 return; 893 dig = radeon_encoder->enc_priv; 894 895 radeon_connector = to_radeon_connector(connector); 896 if (!radeon_connector->con_priv) 897 return; 898 dig_connector = radeon_connector->con_priv; 899 900 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 901 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 902 return; 903 904 /* DPEncoderService newer than 1.1 can't program properly the 905 * training pattern. When facing such version use the 906 * DIGXEncoderControl (X== 1 | 2) 907 */ 908 dp_info.use_dpencoder = true; 909 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 910 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 911 if (crev > 1) { 912 dp_info.use_dpencoder = false; 913 } 914 } 915 916 dp_info.enc_id = 0; 917 if (dig->dig_encoder) 918 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 919 else 920 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 921 if (dig->linkb) 922 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 923 else 924 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 925 926 if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, DP_MAX_LANE_COUNT, &tmp) 927 == 1) { 928 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 929 dp_info.tp3_supported = true; 930 else 931 dp_info.tp3_supported = false; 932 } else { 933 dp_info.tp3_supported = false; 934 } 935 936 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 937 dp_info.rdev = rdev; 938 dp_info.encoder = encoder; 939 dp_info.connector = connector; 940 dp_info.dp_lane_count = dig_connector->dp_lane_count; 941 dp_info.dp_clock = dig_connector->dp_clock; 942 dp_info.aux = &dig_connector->dp_i2c_bus->aux; 943 944 if (radeon_dp_link_train_init(&dp_info)) 945 goto done; 946 if (radeon_dp_link_train_cr(&dp_info)) 947 goto done; 948 if (radeon_dp_link_train_ce(&dp_info)) 949 goto done; 950 done: 951 if (radeon_dp_link_train_finish(&dp_info)) 952 return; 953 } 954