1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include <drm/drmP.h> 28 #include <uapi_drm/radeon_drm.h> 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include <drm/drm_dp_helper.h> 34 35 /* move these to drm_dp_helper.c/h */ 36 #define DP_LINK_CONFIGURATION_SIZE 9 37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 38 39 static char *voltage_names[] = { 40 "0.4V", "0.6V", "0.8V", "1.2V" 41 }; 42 static char *pre_emph_names[] = { 43 "0dB", "3.5dB", "6dB", "9.5dB" 44 }; 45 46 /***** radeon AUX functions *****/ 47 48 /* Atom needs data in little endian format 49 * so swap as appropriate when copying data to 50 * or from atom. Note that atom operates on 51 * dw units. 52 */ 53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 54 { 55 #ifdef __BIG_ENDIAN 56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 57 u32 *dst32, *src32; 58 int i; 59 60 memcpy(src_tmp, src, num_bytes); 61 src32 = (u32 *)src_tmp; 62 dst32 = (u32 *)dst_tmp; 63 if (to_le) { 64 for (i = 0; i < ((num_bytes + 3) / 4); i++) 65 dst32[i] = cpu_to_le32(src32[i]); 66 memcpy(dst, dst_tmp, num_bytes); 67 } else { 68 u8 dws = num_bytes & ~3; 69 for (i = 0; i < ((num_bytes + 3) / 4); i++) 70 dst32[i] = le32_to_cpu(src32[i]); 71 memcpy(dst, dst_tmp, dws); 72 if (num_bytes % 4) { 73 for (i = 0; i < (num_bytes % 4); i++) 74 dst[dws+i] = dst_tmp[dws+i]; 75 } 76 } 77 #else 78 memcpy(dst, src, num_bytes); 79 #endif 80 } 81 82 union aux_channel_transaction { 83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 85 }; 86 87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 88 u8 *send, int send_bytes, 89 u8 *recv, int recv_size, 90 u8 delay, u8 *ack) 91 { 92 struct drm_device *dev = chan->dev; 93 struct radeon_device *rdev = dev->dev_private; 94 union aux_channel_transaction args; 95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 96 unsigned char *base; 97 int recv_bytes; 98 int r = 0; 99 100 memset(&args, 0, sizeof(args)); 101 102 lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_EXCLUSIVE); 103 104 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 105 106 radeon_atom_copy_swap(base, send, send_bytes, true); 107 108 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 109 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); 110 args.v1.ucDataOutLen = 0; 111 args.v1.ucChannelID = chan->rec.i2c_id; 112 args.v1.ucDelay = delay / 10; 113 if (ASIC_IS_DCE4(rdev)) 114 args.v2.ucHPD_ID = chan->rec.hpd; 115 116 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); 117 118 *ack = args.v1.ucReplyStatus; 119 120 /* timeout */ 121 if (args.v1.ucReplyStatus == 1) { 122 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 123 r = -ETIMEDOUT; 124 goto done; 125 } 126 127 /* flags not zero */ 128 if (args.v1.ucReplyStatus == 2) { 129 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 130 r = -EIO; 131 goto done; 132 } 133 134 /* error */ 135 if (args.v1.ucReplyStatus == 3) { 136 DRM_DEBUG_KMS("dp_aux_ch error\n"); 137 r = -EIO; 138 goto done; 139 } 140 141 recv_bytes = args.v1.ucDataOutLen; 142 if (recv_bytes > recv_size) 143 recv_bytes = recv_size; 144 145 if (recv && recv_size) 146 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); 147 148 r = recv_bytes; 149 done: 150 lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_RELEASE); 151 152 return r; 153 } 154 155 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, 156 u16 address, u8 *send, u8 send_bytes, u8 delay) 157 { 158 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 159 int ret; 160 u8 msg[20]; 161 int msg_bytes = send_bytes + 4; 162 u8 ack; 163 unsigned retry; 164 165 if (send_bytes > 16) 166 return -1; 167 168 msg[0] = address; 169 msg[1] = address >> 8; 170 msg[2] = DP_AUX_NATIVE_WRITE << 4; 171 msg[3] = (msg_bytes << 4) | (send_bytes - 1); 172 memcpy(&msg[4], send, send_bytes); 173 174 for (retry = 0; retry < 7; retry++) { 175 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 176 msg, msg_bytes, NULL, 0, delay, &ack); 177 if (ret == -EBUSY) 178 continue; 179 else if (ret < 0) 180 return ret; 181 ack >>= 4; 182 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 183 return send_bytes; 184 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 185 usleep_range(400, 500); 186 else 187 return -EIO; 188 } 189 190 return -EIO; 191 } 192 193 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, 194 u16 address, u8 *recv, int recv_bytes, u8 delay) 195 { 196 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 197 u8 msg[4]; 198 int msg_bytes = 4; 199 u8 ack; 200 int ret; 201 unsigned retry; 202 203 msg[0] = address; 204 msg[1] = address >> 8; 205 msg[2] = DP_AUX_NATIVE_READ << 4; 206 msg[3] = (msg_bytes << 4) | (recv_bytes - 1); 207 208 for (retry = 0; retry < 7; retry++) { 209 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 210 msg, msg_bytes, recv, recv_bytes, delay, &ack); 211 if (ret == -EBUSY) 212 continue; 213 else if (ret < 0) 214 return ret; 215 ack >>= 4; 216 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 217 return ret; 218 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 219 usleep_range(400, 500); 220 else if (ret == 0) 221 return -EPROTO; 222 else 223 return -EIO; 224 } 225 226 return -EIO; 227 } 228 229 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, 230 u16 reg, u8 val) 231 { 232 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); 233 } 234 235 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, 236 u16 reg) 237 { 238 u8 val = 0; 239 240 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); 241 242 return val; 243 } 244 245 int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte) 246 { 247 struct i2c_algo_dp_aux_data *algo_data = device_get_softc(dev); 248 struct radeon_i2c_chan *auxch = algo_data->priv; 249 u16 address = algo_data->address; 250 u8 msg[5]; 251 u8 reply[2]; 252 unsigned retry; 253 int msg_bytes; 254 int reply_bytes = 1; 255 int ret; 256 u8 ack; 257 258 /* Set up the address */ 259 msg[0] = address; 260 msg[1] = address >> 8; 261 262 /* Set up the command byte */ 263 if (mode & MODE_I2C_READ) { 264 msg[2] = DP_AUX_I2C_READ << 4; 265 msg_bytes = 4; 266 msg[3] = msg_bytes << 4; 267 } else { 268 msg[2] = DP_AUX_I2C_WRITE << 4; 269 msg_bytes = 5; 270 msg[3] = msg_bytes << 4; 271 msg[4] = write_byte; 272 } 273 274 /* special handling for start/stop */ 275 if (mode & (MODE_I2C_START | MODE_I2C_STOP)) 276 msg[3] = 3 << 4; 277 278 /* Set MOT bit for all but stop */ 279 if ((mode & MODE_I2C_STOP) == 0) 280 msg[2] |= DP_AUX_I2C_MOT << 4; 281 282 for (retry = 0; retry < 7; retry++) { 283 ret = radeon_process_aux_ch(auxch, 284 msg, msg_bytes, reply, reply_bytes, 0, &ack); 285 if (ret == -EBUSY) 286 continue; 287 else if (ret < 0) { 288 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 289 return ret; 290 } 291 292 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) { 293 case DP_AUX_NATIVE_REPLY_ACK: 294 /* I2C-over-AUX Reply field is only valid 295 * when paired with AUX ACK. 296 */ 297 break; 298 case DP_AUX_NATIVE_REPLY_NACK: 299 DRM_DEBUG_KMS("aux_ch native nack\n"); 300 return -EREMOTEIO; 301 case DP_AUX_NATIVE_REPLY_DEFER: 302 DRM_DEBUG_KMS("aux_ch native defer\n"); 303 usleep_range(500, 600); 304 continue; 305 default: 306 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); 307 return -EREMOTEIO; 308 } 309 310 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) { 311 case DP_AUX_I2C_REPLY_ACK: 312 if (mode == MODE_I2C_READ) 313 *read_byte = reply[0]; 314 return ret; 315 case DP_AUX_I2C_REPLY_NACK: 316 DRM_DEBUG_KMS("aux_i2c nack\n"); 317 return -EREMOTEIO; 318 case DP_AUX_I2C_REPLY_DEFER: 319 DRM_DEBUG_KMS("aux_i2c defer\n"); 320 usleep_range(400, 500); 321 break; 322 default: 323 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); 324 return -EREMOTEIO; 325 } 326 } 327 328 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); 329 return -EREMOTEIO; 330 } 331 332 /***** general DP utility functions *****/ 333 334 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 335 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 336 337 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], 338 int lane_count, 339 u8 train_set[4]) 340 { 341 u8 v = 0; 342 u8 p = 0; 343 int lane; 344 345 for (lane = 0; lane < lane_count; lane++) { 346 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 347 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 348 349 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 350 lane, 351 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 352 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 353 354 if (this_v > v) 355 v = this_v; 356 if (this_p > p) 357 p = this_p; 358 } 359 360 if (v >= DP_VOLTAGE_MAX) 361 v |= DP_TRAIN_MAX_SWING_REACHED; 362 363 if (p >= DP_PRE_EMPHASIS_MAX) 364 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 365 366 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 367 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 368 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 369 370 for (lane = 0; lane < 4; lane++) 371 train_set[lane] = v | p; 372 } 373 374 /* convert bits per color to bits per pixel */ 375 /* get bpc from the EDID */ 376 static int convert_bpc_to_bpp(int bpc) 377 { 378 if (bpc == 0) 379 return 24; 380 else 381 return bpc * 3; 382 } 383 384 /* get the max pix clock supported by the link rate and lane num */ 385 static int dp_get_max_dp_pix_clock(int link_rate, 386 int lane_num, 387 int bpp) 388 { 389 return (link_rate * lane_num * 8) / bpp; 390 } 391 392 /***** radeon specific DP functions *****/ 393 394 static int radeon_dp_get_max_link_rate(struct drm_connector *connector, 395 u8 dpcd[DP_DPCD_SIZE]) 396 { 397 int max_link_rate; 398 399 if (radeon_connector_is_dp12_capable(connector)) 400 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000); 401 else 402 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000); 403 404 return max_link_rate; 405 } 406 407 /* First get the min lane# when low rate is used according to pixel clock 408 * (prefer low rate), second check max lane# supported by DP panel, 409 * if the max lane# < low rate lane# then use max lane# instead. 410 */ 411 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 412 u8 dpcd[DP_DPCD_SIZE], 413 int pix_clock) 414 { 415 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 416 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd); 417 int max_lane_num = drm_dp_max_lane_count(dpcd); 418 int lane_num; 419 int max_dp_pix_clock; 420 421 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { 422 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); 423 if (pix_clock <= max_dp_pix_clock) 424 break; 425 } 426 427 return lane_num; 428 } 429 430 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, 431 u8 dpcd[DP_DPCD_SIZE], 432 int pix_clock) 433 { 434 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 435 int lane_num, max_pix_clock; 436 437 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 438 ENCODER_OBJECT_ID_NUTMEG) 439 return 270000; 440 441 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); 442 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); 443 if (pix_clock <= max_pix_clock) 444 return 162000; 445 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); 446 if (pix_clock <= max_pix_clock) 447 return 270000; 448 if (radeon_connector_is_dp12_capable(connector)) { 449 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); 450 if (pix_clock <= max_pix_clock) 451 return 540000; 452 } 453 454 return radeon_dp_get_max_link_rate(connector, dpcd); 455 } 456 457 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 458 int action, int dp_clock, 459 u8 ucconfig, u8 lane_num) 460 { 461 DP_ENCODER_SERVICE_PARAMETERS args; 462 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 463 464 memset(&args, 0, sizeof(args)); 465 args.ucLinkClock = dp_clock / 10; 466 args.ucConfig = ucconfig; 467 args.ucAction = action; 468 args.ucLaneNum = lane_num; 469 args.ucStatus = 0; 470 471 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 472 return args.ucStatus; 473 } 474 475 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 476 { 477 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 478 struct drm_device *dev = radeon_connector->base.dev; 479 struct radeon_device *rdev = dev->dev_private; 480 481 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 482 dig_connector->dp_i2c_bus->rec.i2c_id, 0); 483 } 484 485 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 486 { 487 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 488 u8 buf[3]; 489 490 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 491 return; 492 493 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) 494 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n", 495 buf[0], buf[1], buf[2]); 496 497 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) 498 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n", 499 buf[0], buf[1], buf[2]); 500 } 501 502 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 503 { 504 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 505 u8 msg[DP_DPCD_SIZE]; 506 int ret, i; 507 508 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 509 DP_DPCD_SIZE, 0); 510 if (ret > 0) { 511 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 512 DRM_DEBUG_KMS("DPCD: "); 513 for (i = 0; i < DP_DPCD_SIZE; i++) 514 DRM_DEBUG_KMS("%02x ", msg[i]); 515 DRM_DEBUG_KMS("\n"); 516 517 radeon_dp_probe_oui(radeon_connector); 518 519 return true; 520 } 521 dig_connector->dpcd[0] = 0; 522 return false; 523 } 524 525 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 526 struct drm_connector *connector) 527 { 528 struct drm_device *dev = encoder->dev; 529 struct radeon_device *rdev = dev->dev_private; 530 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 531 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 532 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 533 u8 tmp; 534 535 if (!ASIC_IS_DCE4(rdev)) 536 return panel_mode; 537 538 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 539 /* DP bridge chips */ 540 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 541 if (tmp & 1) 542 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 543 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 544 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 545 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 546 else 547 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 548 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 549 /* eDP */ 550 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 551 if (tmp & 1) 552 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 553 } 554 555 return panel_mode; 556 } 557 558 void radeon_dp_set_link_config(struct drm_connector *connector, 559 const struct drm_display_mode *mode) 560 { 561 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 562 struct radeon_connector_atom_dig *dig_connector; 563 564 if (!radeon_connector->con_priv) 565 return; 566 dig_connector = radeon_connector->con_priv; 567 568 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 569 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 570 dig_connector->dp_clock = 571 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 572 dig_connector->dp_lane_count = 573 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); 574 } 575 } 576 577 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 578 struct drm_display_mode *mode) 579 { 580 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 581 struct radeon_connector_atom_dig *dig_connector; 582 int dp_clock; 583 584 if (!radeon_connector->con_priv) 585 return MODE_CLOCK_HIGH; 586 dig_connector = radeon_connector->con_priv; 587 588 dp_clock = 589 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 590 591 if ((dp_clock == 540000) && 592 (!radeon_connector_is_dp12_capable(connector))) 593 return MODE_CLOCK_HIGH; 594 595 return MODE_OK; 596 } 597 598 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, 599 u8 link_status[DP_LINK_STATUS_SIZE]) 600 { 601 int ret; 602 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 603 link_status, DP_LINK_STATUS_SIZE, 100); 604 if (ret <= 0) { 605 return false; 606 } 607 608 DRM_DEBUG_KMS("link status %6ph\n", link_status); 609 return true; 610 } 611 612 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 613 { 614 u8 link_status[DP_LINK_STATUS_SIZE]; 615 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 616 617 if (!radeon_dp_get_link_status(radeon_connector, link_status)) 618 return false; 619 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 620 return false; 621 return true; 622 } 623 624 void radeon_dp_set_rx_power_state(struct drm_connector *connector, 625 u8 power_state) 626 { 627 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 628 struct radeon_connector_atom_dig *dig_connector; 629 630 if (!radeon_connector->con_priv) 631 return; 632 633 dig_connector = radeon_connector->con_priv; 634 635 /* power up/down the sink */ 636 if (dig_connector->dpcd[0] >= 0x11) { 637 radeon_write_dpcd_reg(radeon_connector, 638 DP_SET_POWER, power_state); 639 usleep_range(1000, 2000); 640 } 641 } 642 643 644 struct radeon_dp_link_train_info { 645 struct radeon_device *rdev; 646 struct drm_encoder *encoder; 647 struct drm_connector *connector; 648 struct radeon_connector *radeon_connector; 649 int enc_id; 650 int dp_clock; 651 int dp_lane_count; 652 bool tp3_supported; 653 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 654 u8 train_set[4]; 655 u8 link_status[DP_LINK_STATUS_SIZE]; 656 u8 tries; 657 bool use_dpencoder; 658 }; 659 660 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 661 { 662 /* set the initial vs/emph on the source */ 663 atombios_dig_transmitter_setup(dp_info->encoder, 664 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 665 0, dp_info->train_set[0]); /* sets all lanes at once */ 666 667 /* set the vs/emph on the sink */ 668 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, 669 dp_info->train_set, dp_info->dp_lane_count, 0); 670 } 671 672 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 673 { 674 int rtp = 0; 675 676 /* set training pattern on the source */ 677 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 678 switch (tp) { 679 case DP_TRAINING_PATTERN_1: 680 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 681 break; 682 case DP_TRAINING_PATTERN_2: 683 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 684 break; 685 case DP_TRAINING_PATTERN_3: 686 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 687 break; 688 } 689 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 690 } else { 691 switch (tp) { 692 case DP_TRAINING_PATTERN_1: 693 rtp = 0; 694 break; 695 case DP_TRAINING_PATTERN_2: 696 rtp = 1; 697 break; 698 } 699 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 700 dp_info->dp_clock, dp_info->enc_id, rtp); 701 } 702 703 /* enable training pattern on the sink */ 704 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); 705 } 706 707 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 708 { 709 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 710 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 711 u8 tmp; 712 713 /* power up the sink */ 714 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 715 716 /* possibly enable downspread on the sink */ 717 if (dp_info->dpcd[3] & 0x1) 718 radeon_write_dpcd_reg(dp_info->radeon_connector, 719 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 720 else 721 radeon_write_dpcd_reg(dp_info->radeon_connector, 722 DP_DOWNSPREAD_CTRL, 0); 723 724 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && 725 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { 726 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); 727 } 728 729 /* set the lane count on the sink */ 730 tmp = dp_info->dp_lane_count; 731 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 732 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 733 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); 734 735 /* set the link rate on the sink */ 736 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 737 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); 738 739 /* start training on the source */ 740 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 741 atombios_dig_encoder_setup(dp_info->encoder, 742 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 743 else 744 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 745 dp_info->dp_clock, dp_info->enc_id, 0); 746 747 /* disable the training pattern on the sink */ 748 radeon_write_dpcd_reg(dp_info->radeon_connector, 749 DP_TRAINING_PATTERN_SET, 750 DP_TRAINING_PATTERN_DISABLE); 751 752 return 0; 753 } 754 755 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 756 { 757 udelay(400); 758 759 /* disable the training pattern on the sink */ 760 radeon_write_dpcd_reg(dp_info->radeon_connector, 761 DP_TRAINING_PATTERN_SET, 762 DP_TRAINING_PATTERN_DISABLE); 763 764 /* disable the training pattern on the source */ 765 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 766 atombios_dig_encoder_setup(dp_info->encoder, 767 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 768 else 769 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 770 dp_info->dp_clock, dp_info->enc_id, 0); 771 772 return 0; 773 } 774 775 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 776 { 777 bool clock_recovery; 778 u8 voltage; 779 int i; 780 781 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 782 memset(dp_info->train_set, 0, 4); 783 radeon_dp_update_vs_emph(dp_info); 784 785 udelay(400); 786 787 /* clock recovery loop */ 788 clock_recovery = false; 789 dp_info->tries = 0; 790 voltage = 0xff; 791 while (1) { 792 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 793 794 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { 795 DRM_ERROR("displayport link status failed\n"); 796 break; 797 } 798 799 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 800 clock_recovery = true; 801 break; 802 } 803 804 for (i = 0; i < dp_info->dp_lane_count; i++) { 805 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 806 break; 807 } 808 if (i == dp_info->dp_lane_count) { 809 DRM_ERROR("clock recovery reached max voltage\n"); 810 break; 811 } 812 813 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 814 ++dp_info->tries; 815 if (dp_info->tries == 5) { 816 DRM_ERROR("clock recovery tried 5 times\n"); 817 break; 818 } 819 } else 820 dp_info->tries = 0; 821 822 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 823 824 /* Compute new train_set as requested by sink */ 825 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 826 827 radeon_dp_update_vs_emph(dp_info); 828 } 829 if (!clock_recovery) { 830 DRM_ERROR("clock recovery failed\n"); 831 return -1; 832 } else { 833 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 834 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 835 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 836 DP_TRAIN_PRE_EMPHASIS_SHIFT); 837 return 0; 838 } 839 } 840 841 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 842 { 843 bool channel_eq; 844 845 if (dp_info->tp3_supported) 846 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 847 else 848 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 849 850 /* channel equalization loop */ 851 dp_info->tries = 0; 852 channel_eq = false; 853 while (1) { 854 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 855 856 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { 857 DRM_ERROR("displayport link status failed\n"); 858 break; 859 } 860 861 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 862 channel_eq = true; 863 break; 864 } 865 866 /* Try 5 times */ 867 if (dp_info->tries > 5) { 868 DRM_ERROR("channel eq failed: 5 tries\n"); 869 break; 870 } 871 872 /* Compute new train_set as requested by sink */ 873 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 874 875 radeon_dp_update_vs_emph(dp_info); 876 dp_info->tries++; 877 } 878 879 if (!channel_eq) { 880 DRM_ERROR("channel eq failed\n"); 881 return -1; 882 } else { 883 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 884 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 885 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 886 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 887 return 0; 888 } 889 } 890 891 void radeon_dp_link_train(struct drm_encoder *encoder, 892 struct drm_connector *connector) 893 { 894 struct drm_device *dev = encoder->dev; 895 struct radeon_device *rdev = dev->dev_private; 896 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 897 struct radeon_encoder_atom_dig *dig; 898 struct radeon_connector *radeon_connector; 899 struct radeon_connector_atom_dig *dig_connector; 900 struct radeon_dp_link_train_info dp_info; 901 int index; 902 u8 tmp, frev, crev; 903 904 if (!radeon_encoder->enc_priv) 905 return; 906 dig = radeon_encoder->enc_priv; 907 908 radeon_connector = to_radeon_connector(connector); 909 if (!radeon_connector->con_priv) 910 return; 911 dig_connector = radeon_connector->con_priv; 912 913 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 914 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 915 return; 916 917 /* DPEncoderService newer than 1.1 can't program properly the 918 * training pattern. When facing such version use the 919 * DIGXEncoderControl (X== 1 | 2) 920 */ 921 dp_info.use_dpencoder = true; 922 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 923 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 924 if (crev > 1) { 925 dp_info.use_dpencoder = false; 926 } 927 } 928 929 dp_info.enc_id = 0; 930 if (dig->dig_encoder) 931 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 932 else 933 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 934 if (dig->linkb) 935 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 936 else 937 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 938 939 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); 940 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 941 dp_info.tp3_supported = true; 942 else 943 dp_info.tp3_supported = false; 944 945 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 946 dp_info.rdev = rdev; 947 dp_info.encoder = encoder; 948 dp_info.connector = connector; 949 dp_info.radeon_connector = radeon_connector; 950 dp_info.dp_lane_count = dig_connector->dp_lane_count; 951 dp_info.dp_clock = dig_connector->dp_clock; 952 953 if (radeon_dp_link_train_init(&dp_info)) 954 goto done; 955 if (radeon_dp_link_train_cr(&dp_info)) 956 goto done; 957 if (radeon_dp_link_train_ce(&dp_info)) 958 goto done; 959 done: 960 if (radeon_dp_link_train_finish(&dp_info)) 961 return; 962 } 963